diff options
| author | Krishnendra Nathella <krinat01@arm.com> | 2015-07-19 15:03:30 -0500 |
|---|---|---|
| committer | Krishnendra Nathella <krinat01@arm.com> | 2015-07-19 15:03:30 -0500 |
| commit | cabd4768c7186911fda91b9ea458df775b79486a (patch) | |
| tree | ded7b5edfa8d62f144258f9c8032744a86158d96 /tests/quick | |
| parent | c0d19391d423d16c5dc587c4946e8395b9c0db91 (diff) | |
| download | gem5-cabd4768c7186911fda91b9ea458df775b79486a.tar.xz | |
cpu: Fix LLSC atomic CPU wakeup
Writes to locked memory addresses (LLSC) did not wake up the locking
CPU. This can lead to deadlocks on multi-core runs. In AtomicSimpleCPU,
recvAtomicSnoop was checking if the incoming packet was an invalidation
(isInvalidate) and only then handled a locked snoop. But, writes are
seen instead of invalidates when running without caches (fast-forward
configurations). As as simple fix, now handleLockedSnoop is also called
even if the incoming snoop packet are from writes.
Diffstat (limited to 'tests/quick')
4 files changed, 3255 insertions, 3284 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 532d7e553..c94aa8f96 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -104,7 +104,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -146,7 +145,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -234,7 +232,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -276,7 +273,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -410,7 +406,6 @@ clk_domain=system.clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 @@ -447,7 +442,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -482,6 +476,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -615,6 +610,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 8c170a1b4..9ffda2705 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 13:49:21 -gem5 started Jan 21 2016 13:50:00 -gem5 executing on zizzer, pid 33973 +gem5 compiled Feb 29 2016 18:59:12 +gem5 started Feb 29 2016 18:59:20 +gem5 executing on redacted.arm.com, pid 18325 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second @@ -11,4 +11,4 @@ info: kernel located at: /dist/m5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 881785000 -Exiting @ tick 1982594146000 because m5_exit instruction encountered +Exiting @ tick 1982592736000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 965d378dd..3cac0b91e 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,79 +1,79 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.982593 # Number of seconds simulated -sim_ticks 1982593132000 # Number of ticks simulated -final_tick 1982593132000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1982592736000 # Number of ticks simulated +final_tick 1982592736000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1109655 # Simulator instruction rate (inst/s) -host_op_rate 1109654 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36063876778 # Simulator tick rate (ticks/s) -host_mem_usage 333984 # Number of bytes of host memory used -host_seconds 54.97 # Real time elapsed on the host -sim_insts 61002651 # Number of instructions simulated -sim_ops 61002651 # Number of ops (including micro ops) simulated +host_inst_rate 753764 # Simulator instruction rate (inst/s) +host_op_rate 753764 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24497172234 # Simulator tick rate (ticks/s) +host_mem_usage 320072 # Number of bytes of host memory used +host_seconds 80.93 # Real time elapsed on the host +sim_insts 61003209 # Number of instructions simulated +sim_ops 61003209 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 800256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24686464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 59392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 523264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 800192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24686016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 59328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 523328 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26070336 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 800256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 59392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 859648 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7739904 # Number of bytes written to this memory -system.physmem.bytes_written::total 7739904 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12504 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385726 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 928 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8176 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26069824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 800192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 59328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 859520 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7739392 # Number of bytes written to this memory +system.physmem.bytes_written::total 7739392 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12503 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385719 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 927 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8177 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 407349 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120936 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120936 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 403641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12451604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 29957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 263929 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 407341 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120928 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120928 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 403609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12451380 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 29924 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 263961 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13149615 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 403641 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 29957 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 433598 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3903930 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3903930 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3903930 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 403641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12451604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 29957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 263929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13149359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 403609 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 29924 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 433533 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3903672 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3903672 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3903672 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 403609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12451380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 29924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 263961 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17053544 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 407349 # Number of read requests accepted -system.physmem.writeReqs 120936 # Number of write requests accepted -system.physmem.readBursts 407349 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120936 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26062656 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue -system.physmem.bytesWritten 7738112 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26070336 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7739904 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17053031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 407341 # Number of read requests accepted +system.physmem.writeReqs 120928 # Number of write requests accepted +system.physmem.readBursts 407341 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120928 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26061824 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue +system.physmem.bytesWritten 7737600 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26069824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7739392 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25226 # Per bank write bursts system.physmem.perBankRdBursts::1 25379 # Per bank write bursts -system.physmem.perBankRdBursts::2 25428 # Per bank write bursts +system.physmem.perBankRdBursts::2 25423 # Per bank write bursts system.physmem.perBankRdBursts::3 24855 # Per bank write bursts system.physmem.perBankRdBursts::4 25157 # Per bank write bursts system.physmem.perBankRdBursts::5 25423 # Per bank write bursts -system.physmem.perBankRdBursts::6 25496 # Per bank write bursts -system.physmem.perBankRdBursts::7 25345 # Per bank write bursts +system.physmem.perBankRdBursts::6 25497 # Per bank write bursts +system.physmem.perBankRdBursts::7 25338 # Per bank write bursts system.physmem.perBankRdBursts::8 25239 # Per bank write bursts system.physmem.perBankRdBursts::9 25589 # Per bank write bursts system.physmem.perBankRdBursts::10 25733 # Per bank write bursts -system.physmem.perBankRdBursts::11 25919 # Per bank write bursts +system.physmem.perBankRdBursts::11 25917 # Per bank write bursts system.physmem.perBankRdBursts::12 25947 # Per bank write bursts system.physmem.perBankRdBursts::13 25572 # Per bank write bursts system.physmem.perBankRdBursts::14 25277 # Per bank write bursts @@ -84,34 +84,34 @@ system.physmem.perBankWrBursts::2 7471 # Pe system.physmem.perBankWrBursts::3 6886 # Per bank write bursts system.physmem.perBankWrBursts::4 7104 # Per bank write bursts system.physmem.perBankWrBursts::5 7345 # Per bank write bursts -system.physmem.perBankWrBursts::6 7430 # Per bank write bursts -system.physmem.perBankWrBursts::7 7151 # Per bank write bursts +system.physmem.perBankWrBursts::6 7431 # Per bank write bursts +system.physmem.perBankWrBursts::7 7144 # Per bank write bursts system.physmem.perBankWrBursts::8 7161 # Per bank write bursts system.physmem.perBankWrBursts::9 7315 # Per bank write bursts system.physmem.perBankWrBursts::10 7729 # Per bank write bursts -system.physmem.perBankWrBursts::11 8152 # Per bank write bursts +system.physmem.perBankWrBursts::11 8150 # Per bank write bursts system.physmem.perBankWrBursts::12 8256 # Per bank write bursts system.physmem.perBankWrBursts::13 7924 # Per bank write bursts system.physmem.perBankWrBursts::14 7541 # Per bank write bursts system.physmem.perBankWrBursts::15 7815 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1982585764500 # Total gap between requests +system.physmem.numWrRetry 9 # Number of times write queue was full causing retry +system.physmem.totGap 1982585344500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 407349 # Read request sizes (log2) +system.physmem.readPktSize::6 407341 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120936 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407149 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120928 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407136 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -158,112 +158,111 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1897 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 3334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7102 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67582 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 500.144536 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 302.732498 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 404.890859 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16271 24.08% 24.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12393 18.34% 42.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5170 7.65% 50.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3294 4.87% 54.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2518 3.73% 58.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4277 6.33% 64.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1487 2.20% 67.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2102 3.11% 70.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20070 29.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67582 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5413 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.229078 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2867.379606 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5410 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67562 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 500.272698 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 302.933598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 404.928891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16219 24.01% 24.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12429 18.40% 42.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5206 7.71% 50.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3267 4.84% 54.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2499 3.70% 58.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4251 6.29% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1505 2.23% 67.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2122 3.14% 70.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20064 29.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67562 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5401 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.393816 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2870.561720 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5398 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5413 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5413 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.336597 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.167195 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.176387 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4808 88.82% 88.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 29 0.54% 89.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 21 0.39% 89.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 46 0.85% 90.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 212 3.92% 94.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 15 0.28% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 14 0.26% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 26 0.48% 95.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 189 3.49% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.09% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 5 0.09% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.07% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 5 0.09% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 2 0.04% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 4 0.07% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.02% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 1 0.02% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 8 0.15% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 1 0.02% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 2 0.04% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 3 0.06% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 8 0.15% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5413 # Writes before turning the bus around for reads -system.physmem.totQLat 2790032750 # Total ticks spent queuing -system.physmem.totMemAccLat 10425576500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2036145000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6851.26 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5401 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5401 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.384744 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.196926 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.269218 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4796 88.80% 88.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 29 0.54% 89.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 16 0.30% 89.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 48 0.89% 90.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 211 3.91% 94.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 14 0.26% 94.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 16 0.30% 94.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 27 0.50% 95.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 197 3.65% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 3 0.06% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 2 0.04% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 4 0.07% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 6 0.11% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.06% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 3 0.06% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 4 0.07% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 5 0.09% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.04% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 9 0.17% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 3 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5401 # Writes before turning the bus around for reads +system.physmem.totQLat 2785960750 # Total ticks spent queuing +system.physmem.totMemAccLat 10421260750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2036080000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6841.48 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25601.26 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25591.48 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.15 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.90 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.15 # Average system read bandwidth in MiByte/s @@ -273,62 +272,62 @@ system.physmem.busUtil 0.13 # Da system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing -system.physmem.readRowHits 363813 # Number of row buffer hits during reads -system.physmem.writeRowHits 96742 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing +system.physmem.readRowHits 363789 # Number of row buffer hits during reads +system.physmem.writeRowHits 96765 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.99 # Row buffer hit rate for writes -system.physmem.avgGap 3752871.58 # Average gap between requests +system.physmem.writeRowHitRate 80.02 # Row buffer hit rate for writes +system.physmem.avgGap 3752984.45 # Average gap between requests system.physmem.pageHitRate 87.20 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 244006560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 133138500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1578010200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 382417200 # Energy for write commands per rank (pJ) +system.physmem_0.actEnergy 243704160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 132973500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577924400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 382378320 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 72939489120 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1125571835250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1330342003950 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.012251 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1872206783000 # Time in different power states +system.physmem_0.actBackEnergy 72905362650 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1125601770750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1330337220900 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.009839 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1872255893500 # Time in different power states system.physmem_0.memoryStateTime::REF 66203020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 44179949500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 44130839000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 266913360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 145637250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1598376000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 401066640 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 267064560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 145719750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1598360400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 401053680 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 73838725110 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1124783023500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1330526848980 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.105490 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1870895185000 # Time in different power states +system.physmem_1.actBackEnergy 73884851505 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1124742561750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1330532718765 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.108451 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1870830292750 # Time in different power states system.physmem_1.memoryStateTime::REF 66203020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 45491533750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 45556426000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7416541 # DTB read hits +system.cpu0.dtb.read_hits 7416468 # DTB read hits system.cpu0.dtb.read_misses 7442 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490672 # DTB read accesses -system.cpu0.dtb.write_hits 5004457 # DTB write hits +system.cpu0.dtb.write_hits 5004426 # DTB write hits system.cpu0.dtb.write_misses 812 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187451 # DTB write accesses -system.cpu0.dtb.data_hits 12420998 # DTB hits +system.cpu0.dtb.data_hits 12420894 # DTB hits system.cpu0.dtb.data_misses 8254 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678123 # DTB accesses -system.cpu0.itb.fetch_hits 3482402 # ITB hits +system.cpu0.itb.fetch_hits 3482357 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3486273 # ITB accesses +system.cpu0.itb.fetch_accesses 3486228 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -341,36 +340,36 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3964851877 # number of cpu cycles simulated +system.cpu0.numCycles 3964851876 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6803 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 162801 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 162795 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 55926 40.12% 40.12% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 133 0.10% 40.21% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1977 1.42% 41.63% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 435 0.31% 41.94% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 80941 58.06% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139412 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 80935 58.06% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 139406 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 55417 49.07% 49.07% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 133 0.12% 49.18% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1977 1.75% 50.93% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 435 0.39% 51.32% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 54983 48.68% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 112945 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1904793300500 96.08% 96.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 93813000 0.00% 96.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 790638500 0.04% 96.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1904797058500 96.08% 96.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 94101500 0.00% 96.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 790644500 0.04% 96.13% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 326474000 0.02% 96.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 76421682500 3.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1982425908500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 76417629500 3.85% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1982425908000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.990899 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.679297 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810153 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.679348 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810188 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -409,7 +408,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # nu system.cpu0.kern.callpal::swpctx 3024 2.05% 2.41% # number of callpals executed system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 132542 89.80% 92.24% # number of callpals executed +system.cpu0.kern.callpal::swpipl 132536 89.80% 92.24% # number of callpals executed system.cpu0.kern.callpal::rdps 6593 4.47% 96.71% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed @@ -418,44 +417,44 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.72% # nu system.cpu0.kern.callpal::rti 4325 2.93% 99.65% # number of callpals executed system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 147602 # number of callpals executed +system.cpu0.kern.callpal::total 147596 # number of callpals executed system.cpu0.kern.mode_switch::kernel 6863 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1282 -system.cpu0.kern.mode_good::user 1282 +system.cpu0.kern.mode_good::kernel 1283 +system.cpu0.kern.mode_good::user 1283 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186799 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186944 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.314794 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1977682087000 99.80% 99.80% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3901070000 0.20% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.315001 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1977682468000 99.80% 99.80% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3900182500 0.20% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3025 # number of times the context was actually changed -system.cpu0.committedInsts 47316172 # Number of instructions committed -system.cpu0.committedOps 47316172 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 43886449 # Number of integer alu accesses +system.cpu0.committedInsts 47316464 # Number of instructions committed +system.cpu0.committedOps 47316464 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 43886764 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 206939 # Number of float alu accesses -system.cpu0.num_func_calls 1185652 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5565345 # number of instructions that are conditional controls -system.cpu0.num_int_insts 43886449 # number of integer instructions +system.cpu0.num_func_calls 1185664 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5565449 # number of instructions that are conditional controls +system.cpu0.num_int_insts 43886764 # number of integer instructions system.cpu0.num_fp_insts 206939 # number of float instructions -system.cpu0.num_int_register_reads 60334275 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32718467 # number of times the integer registers were written +system.cpu0.num_int_register_reads 60334858 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32718698 # number of times the integer registers were written system.cpu0.num_fp_register_reads 100516 # number of times the floating registers were read system.cpu0.num_fp_register_writes 102286 # number of times the floating registers were written -system.cpu0.num_mem_refs 12460893 # number of memory refs -system.cpu0.num_load_insts 7443480 # Number of load instructions -system.cpu0.num_store_insts 5017413 # Number of store instructions -system.cpu0.num_idle_cycles 3699956428.707181 # Number of idle cycles -system.cpu0.num_busy_cycles 264895448.292820 # Number of busy cycles -system.cpu0.not_idle_fraction 0.066811 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.933189 # Percentage of idle cycles -system.cpu0.Branches 7133641 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2703037 5.71% 5.71% # Class of executed instruction -system.cpu0.op_class::IntAlu 31175022 65.87% 71.59% # Class of executed instruction -system.cpu0.op_class::IntMult 51696 0.11% 71.70% # Class of executed instruction +system.cpu0.num_mem_refs 12460790 # number of memory refs +system.cpu0.num_load_insts 7443408 # Number of load instructions +system.cpu0.num_store_insts 5017382 # Number of store instructions +system.cpu0.num_idle_cycles 3699967048.966084 # Number of idle cycles +system.cpu0.num_busy_cycles 264884827.033916 # Number of busy cycles +system.cpu0.not_idle_fraction 0.066808 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.933192 # Percentage of idle cycles +system.cpu0.Branches 7133745 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2703031 5.71% 5.71% # Class of executed instruction +system.cpu0.op_class::IntAlu 31175440 65.88% 71.59% # Class of executed instruction +system.cpu0.op_class::IntMult 51698 0.11% 71.70% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 71.70% # Class of executed instruction system.cpu0.op_class::FloatAdd 25566 0.05% 71.75% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 71.75% # Class of executed instruction @@ -483,98 +482,98 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.75% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 71.75% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.75% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::MemRead 7616572 16.09% 87.85% # Class of executed instruction -system.cpu0.op_class::MemWrite 5023515 10.61% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 727706 1.54% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 7616501 16.09% 87.85% # Class of executed instruction +system.cpu0.op_class::MemWrite 5023484 10.61% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 727686 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47324770 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1172753 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.332741 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11237004 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1173173 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.578301 # Average number of references to valid blocks. +system.cpu0.op_class::total 47325062 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1172723 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.333527 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11236927 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1173142 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.578488 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 144706500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.332741 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986978 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986978 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 420 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.333527 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986980 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986980 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 372 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.820312 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 50908772 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 50908772 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6342827 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6342827 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4601104 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4601104 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138127 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 138127 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145435 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 145435 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10943931 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10943931 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10943931 # number of overall hits -system.cpu0.dcache.overall_hits::total 10943931 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 934208 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 934208 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 249079 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 249079 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13580 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13580 # number of LoadLockedReq misses +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 371 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 50908342 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 50908342 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6342787 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6342787 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4601077 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4601077 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138129 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 138129 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145434 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 145434 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10943864 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10943864 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10943864 # number of overall hits +system.cpu0.dcache.overall_hits::total 10943864 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 934179 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 934179 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 249076 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 249076 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13578 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13578 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5739 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 5739 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1183287 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1183287 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1183287 # number of overall misses -system.cpu0.dcache.overall_misses::total 1183287 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42886334500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 42886334500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16793569500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 16793569500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 151760500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 151760500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 94775500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 94775500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 59679904000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 59679904000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 59679904000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 59679904000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7277035 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7277035 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4850183 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4850183 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 1183255 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1183255 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1183255 # number of overall misses +system.cpu0.dcache.overall_misses::total 1183255 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42885164500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 42885164500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16793601000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 16793601000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 151515500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 151515500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 94785500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 94785500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 59678765500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 59678765500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 59678765500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 59678765500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7276966 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7276966 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4850153 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4850153 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151707 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 151707 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151174 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 151174 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12127218 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12127218 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12127218 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12127218 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128378 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.128378 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051355 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051355 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089515 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089515 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151173 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 151173 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12127119 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12127119 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12127119 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12127119 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128375 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.128375 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051354 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051354 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089501 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089501 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037963 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037963 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097573 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097573 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097573 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097573 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45906.623043 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 45906.623043 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67422.663091 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 67422.663091 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11175.294551 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11175.294551 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16514.288204 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16514.288204 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50435.696496 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50435.696496 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50435.696496 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50435.696496 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097571 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097571 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097571 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097571 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45906.795700 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 45906.795700 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67423.601632 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 67423.601632 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11158.896745 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11158.896745 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16516.030667 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16516.030667 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50436.098305 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50436.098305 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50436.098305 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50436.098305 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -583,126 +582,126 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 672821 # number of writebacks -system.cpu0.dcache.writebacks::total 672821 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934208 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 934208 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249079 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 249079 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13580 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13580 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 672790 # number of writebacks +system.cpu0.dcache.writebacks::total 672790 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934179 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 934179 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249076 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249076 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13578 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13578 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5739 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 5739 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1183287 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1183287 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1183287 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1183287 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7086 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7086 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10784 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10784 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17870 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17870 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41952126500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41952126500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 16544490500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 16544490500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 138180500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 138180500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 89036500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 89036500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58496617000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 58496617000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58496617000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 58496617000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1567540500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1567540500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2452068500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2452068500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4019609000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4019609000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128378 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128378 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051355 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051355 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089515 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089515 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1183255 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1183255 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1183255 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1183255 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7083 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7083 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10783 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10783 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17866 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17866 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41950985500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41950985500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 16544525000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 16544525000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 137937500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137937500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 89046500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 89046500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58495510500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 58495510500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58495510500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 58495510500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1566902000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1566902000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2451870500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2451870500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4018772500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4018772500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128375 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128375 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051354 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051354 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089501 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089501 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037963 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037963 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097573 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097573 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097573 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097573 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44906.623043 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44906.623043 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66422.663091 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66422.663091 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10175.294551 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10175.294551 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15514.288204 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15514.288204 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49435.696496 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49435.696496 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49435.696496 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49435.696496 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221216.553768 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221216.553768 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227380.239243 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227380.239243 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224936.149972 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224936.149972 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097571 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097571 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097571 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097571 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44906.795700 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44906.795700 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66423.601632 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66423.601632 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10158.896745 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10158.896745 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15516.030667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15516.030667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49436.098305 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49436.098305 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49436.098305 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49436.098305 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221220.104476 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221220.104476 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227382.963925 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227382.963925 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224939.689914 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224939.689914 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 686592 # number of replacements -system.cpu0.icache.tags.tagsinuse 506.490691 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 46637544 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 687104 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.875524 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 686545 # number of replacements +system.cpu0.icache.tags.tagsinuse 506.490868 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 46637883 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 687057 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.880661 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 58998281500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.490691 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.490868 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989240 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.989240 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 417 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48011996 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48011996 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 46637544 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 46637544 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 46637544 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 46637544 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 46637544 # number of overall hits -system.cpu0.icache.overall_hits::total 46637544 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 687226 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 687226 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 687226 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 687226 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 687226 # number of overall misses -system.cpu0.icache.overall_misses::total 687226 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10626395500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10626395500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10626395500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10626395500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10626395500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10626395500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47324770 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47324770 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47324770 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47324770 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47324770 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47324770 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014521 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014521 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014521 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014521 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014521 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014521 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15462.737877 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15462.737877 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15462.737877 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15462.737877 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15462.737877 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15462.737877 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48012241 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48012241 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 46637883 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 46637883 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 46637883 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 46637883 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 46637883 # number of overall hits +system.cpu0.icache.overall_hits::total 46637883 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 687179 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 687179 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 687179 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 687179 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 687179 # number of overall misses +system.cpu0.icache.overall_misses::total 687179 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10623000500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10623000500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10623000500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10623000500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10623000500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10623000500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47325062 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47325062 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47325062 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47325062 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47325062 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47325062 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014520 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014520 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014520 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014520 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014520 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014520 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15458.854971 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15458.854971 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15458.854971 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15458.854971 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15458.854971 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15458.854971 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -711,53 +710,53 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 686592 # number of writebacks -system.cpu0.icache.writebacks::total 686592 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687226 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 687226 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 687226 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 687226 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 687226 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 687226 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9939169500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9939169500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9939169500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9939169500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9939169500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9939169500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014521 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014521 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14462.737877 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14462.737877 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14462.737877 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 14462.737877 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14462.737877 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 14462.737877 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 686545 # number of writebacks +system.cpu0.icache.writebacks::total 686545 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687179 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 687179 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 687179 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 687179 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 687179 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 687179 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9935821500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9935821500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9935821500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9935821500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9935821500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9935821500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014520 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014520 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014520 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14458.854971 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14458.854971 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14458.854971 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2511145 # DTB read hits +system.cpu1.dtb.read_hits 2511191 # DTB read hits system.cpu1.dtb.read_misses 2993 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239364 # DTB read accesses -system.cpu1.dtb.write_hits 1829996 # DTB write hits +system.cpu1.dtb.write_hits 1830032 # DTB write hits system.cpu1.dtb.write_misses 342 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105248 # DTB write accesses -system.cpu1.dtb.data_hits 4341141 # DTB hits +system.cpu1.dtb.data_hits 4341223 # DTB hits system.cpu1.dtb.data_misses 3335 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344612 # DTB accesses -system.cpu1.itb.fetch_hits 1990273 # ITB hits +system.cpu1.itb.fetch_hits 1990291 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1991489 # ITB accesses +system.cpu1.itb.fetch_accesses 1991507 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -770,32 +769,32 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3965186264 # number of cpu cycles simulated +system.cpu1.numCycles 3965185472 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2869 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 81047 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27546 38.52% 38.52% # number of times we switched to this ipl +system.cpu1.kern.inst.hwrei 81049 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 27547 38.53% 38.53% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1971 2.76% 41.28% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 524 0.73% 42.01% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 41461 57.99% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 71502 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26678 48.22% 48.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 41462 57.99% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 71504 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 26679 48.22% 48.22% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1971 3.56% 51.78% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 524 0.95% 52.73% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 26154 47.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 55327 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1912240588500 96.45% 96.45% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 731240000 0.04% 96.49% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_good::31 26155 47.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 55329 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1912239584500 96.45% 96.45% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 731206500 0.04% 96.49% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::30 374509500 0.02% 96.51% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 69246057000 3.49% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1982592395000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968489 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_ticks::31 69246698500 3.49% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1982591999000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968490 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.630810 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.773783 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.630819 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.773789 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -817,7 +816,7 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # nu system.cpu1.kern.callpal::swpctx 2066 2.79% 3.39% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed -system.cpu1.kern.callpal::swpipl 65180 88.12% 91.52% # number of callpals executed +system.cpu1.kern.callpal::swpipl 65182 88.12% 91.52% # number of callpals executed system.cpu1.kern.callpal::rdps 2261 3.06% 94.57% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 94.57% # number of callpals executed system.cpu1.kern.callpal::wrusp 4 0.01% 94.58% # number of callpals executed @@ -826,7 +825,7 @@ system.cpu1.kern.callpal::rti 3826 5.17% 99.76% # nu system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 73970 # number of callpals executed +system.cpu1.kern.callpal::total 73972 # number of callpals executed system.cpu1.kern.mode_switch::kernel 2115 # number of protection mode switches system.cpu1.kern.mode_switch::user 464 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2921 # number of protection mode switches @@ -837,33 +836,33 @@ system.cpu1.kern.mode_switch_good::kernel 0.431206 # f system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.153372 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total 0.331636 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 19470103000 0.98% 0.98% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1729907500 0.09% 1.07% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1961392382500 98.93% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::kernel 19469811000 0.98% 0.98% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1729387000 0.09% 1.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1961392799000 98.93% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2067 # number of times the context was actually changed -system.cpu1.committedInsts 13686479 # Number of instructions committed -system.cpu1.committedOps 13686479 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12624111 # Number of integer alu accesses +system.cpu1.committedInsts 13686745 # Number of instructions committed +system.cpu1.committedOps 13686745 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12624358 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 178612 # Number of float alu accesses -system.cpu1.num_func_calls 430158 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1359705 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12624111 # number of integer instructions +system.cpu1.num_func_calls 430170 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1359717 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12624358 # number of integer instructions system.cpu1.num_fp_insts 178612 # number of float instructions -system.cpu1.num_int_register_reads 17383206 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9260208 # number of times the integer registers were written +system.cpu1.num_int_register_reads 17383561 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9260404 # number of times the integer registers were written system.cpu1.num_fp_register_reads 93246 # number of times the floating registers were read system.cpu1.num_fp_register_writes 95234 # number of times the floating registers were written -system.cpu1.num_mem_refs 4365297 # number of memory refs -system.cpu1.num_load_insts 2525800 # Number of load instructions -system.cpu1.num_store_insts 1839497 # Number of store instructions -system.cpu1.num_idle_cycles 3912233484.998027 # Number of idle cycles -system.cpu1.num_busy_cycles 52952779.001973 # Number of busy cycles +system.cpu1.num_mem_refs 4365379 # number of memory refs +system.cpu1.num_load_insts 2525846 # Number of load instructions +system.cpu1.num_store_insts 1839533 # Number of store instructions +system.cpu1.num_idle_cycles 3912234287.998026 # Number of idle cycles +system.cpu1.num_busy_cycles 52951184.001973 # Number of busy cycles system.cpu1.not_idle_fraction 0.013354 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.986646 # Percentage of idle cycles -system.cpu1.Branches 1950120 # Number of branches fetched -system.cpu1.op_class::No_OpClass 733810 5.36% 5.36% # Class of executed instruction -system.cpu1.op_class::IntAlu 8101284 59.18% 64.54% # Class of executed instruction -system.cpu1.op_class::IntMult 23184 0.17% 64.71% # Class of executed instruction +system.cpu1.Branches 1950147 # Number of branches fetched +system.cpu1.op_class::No_OpClass 733822 5.36% 5.36% # Class of executed instruction +system.cpu1.op_class::IntAlu 8101444 59.18% 64.54% # Class of executed instruction +system.cpu1.op_class::IntMult 23186 0.17% 64.71% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 64.71% # Class of executed instruction system.cpu1.op_class::FloatAdd 14372 0.10% 64.81% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 64.81% # Class of executed instruction @@ -891,99 +890,99 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.83% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 64.83% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.83% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::MemRead 2600475 19.00% 83.82% # Class of executed instruction -system.cpu1.op_class::MemWrite 1840521 13.44% 97.27% # Class of executed instruction -system.cpu1.op_class::IprAccess 374211 2.73% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 2600523 19.00% 83.82% # Class of executed instruction +system.cpu1.op_class::MemWrite 1840557 13.44% 97.27% # Class of executed instruction +system.cpu1.op_class::IprAccess 374219 2.73% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13689843 # Class of executed instruction -system.cpu1.dcache.tags.replacements 173686 # number of replacements -system.cpu1.dcache.tags.tagsinuse 481.983606 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4164884 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 174198 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.908908 # Average number of references to valid blocks. +system.cpu1.op_class::total 13690109 # Class of executed instruction +system.cpu1.dcache.tags.replacements 173692 # number of replacements +system.cpu1.dcache.tags.tagsinuse 481.984896 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4164965 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 174204 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.908550 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 90321767000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.983606 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.941374 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.941374 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.984896 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.941377 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.941377 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 17608316 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 17608316 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2339523 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2339523 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1707175 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1707175 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50425 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 50425 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 53078 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 53078 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4046698 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4046698 # 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number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050136 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050136 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036998 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036998 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155091 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155091 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103215 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103215 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 789482500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 789482500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 814533500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 814533500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050137 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050137 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036996 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036996 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155072 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155072 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103212 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103212 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044637 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.044637 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044637 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.044637 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11600.433251 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11600.433251 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27523.151748 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27523.151748 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8191.335350 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8191.335350 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14870.928139 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14870.928139 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17123.959402 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17123.959402 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17123.959402 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17123.959402 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11596.760088 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11596.760088 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27534.679657 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27534.679657 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8167.477039 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8167.477039 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14872.565068 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14872.565068 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17125.218826 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17125.218826 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17125.218826 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17125.218826 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 212296.610169 # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212296.610169 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.048984 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.048984 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235006.635892 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235006.635892 # average overall mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.198327 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.198327 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235006.780150 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235006.780150 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 331505 # number of replacements -system.cpu1.icache.tags.tagsinuse 442.932847 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 13357787 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 332017 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.232238 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 331529 # number of replacements +system.cpu1.icache.tags.tagsinuse 442.932822 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 13358029 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 332041 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.230059 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 1975288394500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.932847 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.932822 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865103 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.865103 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 405 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 403 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 14021901 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 14021901 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 13357787 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13357787 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13357787 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13357787 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13357787 # number of overall hits -system.cpu1.icache.overall_hits::total 13357787 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 332057 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 332057 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 332057 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 332057 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 332057 # number of overall misses -system.cpu1.icache.overall_misses::total 332057 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4541544500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4541544500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4541544500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4541544500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4541544500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4541544500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13689844 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13689844 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13689844 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13689844 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13689844 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13689844 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024256 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024256 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024256 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024256 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024256 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024256 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13677.002744 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13677.002744 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13677.002744 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13677.002744 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13677.002744 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13677.002744 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 14022191 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 14022191 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 13358029 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13358029 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13358029 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13358029 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13358029 # number of overall hits +system.cpu1.icache.overall_hits::total 13358029 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 332081 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 332081 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 332081 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 332081 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 332081 # number of overall misses +system.cpu1.icache.overall_misses::total 332081 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4540351000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4540351000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4540351000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4540351000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4540351000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4540351000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13690110 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13690110 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13690110 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13690110 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13690110 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13690110 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024257 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024257 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024257 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024257 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024257 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024257 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13672.420283 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13672.420283 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13672.420283 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13672.420283 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13672.420283 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13672.420283 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1122,32 +1121,32 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 331505 # number of writebacks -system.cpu1.icache.writebacks::total 331505 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 332057 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 332057 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 332057 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 332057 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 332057 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 332057 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4209487500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4209487500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4209487500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4209487500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4209487500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4209487500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024256 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024256 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024256 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024256 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024256 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024256 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12677.002744 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12677.002744 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12677.002744 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12677.002744 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12677.002744 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12677.002744 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 331529 # number of writebacks +system.cpu1.icache.writebacks::total 331529 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 332081 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 332081 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 332081 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 332081 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 332081 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 332081 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4208270000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4208270000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4208270000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4208270000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4208270000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4208270000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024257 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024257 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024257 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12672.420283 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1161,37 +1160,37 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7379 # Transaction distribution -system.iobus.trans_dist::ReadResp 7379 # Transaction distribution -system.iobus.trans_dist::WriteReq 55684 # Transaction distribution -system.iobus.trans_dist::WriteResp 55684 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14066 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7376 # Transaction distribution +system.iobus.trans_dist::ReadResp 7376 # Transaction distribution +system.iobus.trans_dist::WriteReq 55683 # Transaction distribution +system.iobus.trans_dist::WriteResp 55683 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14050 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 188 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18150 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42664 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 126118 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56200 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 171 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9075 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 82507 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 82454 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2744131 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 15127500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2744078 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 15116500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1199,31 +1198,31 @@ system.iobus.reqLayer2.occupancy 9500 # La system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 175000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 183000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15843000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15844000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2460000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6055000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6055500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 83000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215669663 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215674412 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28540000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28533000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.566874 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.566860 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 1775103309000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.566874 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035430 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035430 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::tsunami.ide 0.566860 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035429 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035429 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1239,8 +1238,8 @@ system.iocache.overall_misses::tsunami.ide 175 # system.iocache.overall_misses::total 175 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21956883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21956883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245212780 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5245212780 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245146529 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5245146529 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21956883 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21956883 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21956883 # number of overall miss cycles @@ -1263,8 +1262,8 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125467.902857 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 125467.902857 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126232.498556 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126232.498556 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.904144 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126230.904144 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency system.iocache.demand_avg_miss_latency::total 125467.902857 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency @@ -1289,8 +1288,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 175 system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13206883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 13206883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165805993 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3165805993 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165739741 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3165739741 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 13206883 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 13206883 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 13206883 # number of overall MSHR miss cycles @@ -1305,197 +1304,197 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 75467.902857 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76189.016004 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76189.016004 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.421568 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.421568 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 342144 # number of replacements -system.l2c.tags.tagsinuse 65164.214079 # Cycle average of tags in use -system.l2c.tags.total_refs 3686310 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407150 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.053936 # Average number of references to valid blocks. +system.l2c.tags.replacements 342136 # number of replacements +system.l2c.tags.tagsinuse 65163.366749 # Cycle average of tags in use +system.l2c.tags.total_refs 3685387 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 407142 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.051847 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 12928623000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54851.914684 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4798.806705 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5354.570072 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 119.591740 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 39.330879 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.836974 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073224 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.081704 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.001825 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 54851.977847 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4799.733629 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5353.675533 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 118.645951 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 39.333789 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.836975 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073238 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.081691 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.001810 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000600 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994327 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994314 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65006 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 517 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5381 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6294 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5377 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6298 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 52712 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.991913 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 35907872 # Number of tag accesses -system.l2c.tags.data_accesses 35907872 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 792557 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 792557 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 746952 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 746952 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 186 # number of UpgradeReq hits +system.l2c.tags.tag_accesses 35906899 # Number of tag accesses +system.l2c.tags.data_accesses 35906899 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 792516 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 792516 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 746948 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 746948 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 183 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 548 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 734 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 40 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 63 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 124117 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 48557 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172674 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 674696 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 331117 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1005813 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 659477 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 113729 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 773206 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 674696 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 783594 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 331117 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 162286 # number of demand (read+write) hits -system.l2c.demand_hits::total 1951693 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 674696 # number of overall hits -system.l2c.overall_hits::cpu0.data 783594 # number of overall hits -system.l2c.overall_hits::cpu1.inst 331117 # number of overall hits -system.l2c.overall_hits::cpu1.data 162286 # number of overall hits -system.l2c.overall_hits::total 1951693 # number of overall hits +system.l2c.UpgradeReq_hits::total 731 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 41 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 65 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 124124 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 48553 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 172677 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 674650 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 331142 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1005792 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 659425 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 113738 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 773163 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 674650 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 783549 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 331142 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 162291 # number of demand (read+write) hits +system.l2c.demand_hits::total 1951632 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 674650 # number of overall hits +system.l2c.overall_hits::cpu0.data 783549 # number of overall hits +system.l2c.overall_hits::cpu1.inst 331142 # number of overall hits +system.l2c.overall_hits::cpu1.data 162291 # number of overall hits +system.l2c.overall_hits::total 1951632 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 2972 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1811 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4783 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1812 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4784 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 926 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 930 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1856 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114977 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 114970 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 7877 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122854 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 12504 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 939 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13443 # number of ReadCleanReq misses +system.l2c.ReadExReq_misses::total 122847 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 12503 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 938 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 13441 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121368.002239 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114930.755419 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122773.707974 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121492.147553 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 115277.837125 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208711.191081 # average ReadReq mshr uncacheable latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117149.547708 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121705.725657 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117441.691706 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121152.163481 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121352.751888 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121166.009010 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113991.494713 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 115926.035503 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113993.899770 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121152.163481 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114930.886116 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121352.751888 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121467.924650 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 115267.622116 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121152.163481 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114930.886116 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121352.751888 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121467.924650 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 115267.622116 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208714.810109 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199792.372881 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208565.102721 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215871.939911 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.166069 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217869.374469 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213032.484611 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223468.695903 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 214727.830896 # average overall mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208568.601583 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215874.478438 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.315412 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217871.488288 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213036.018191 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223468.840162 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 214731.131680 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 7204 # Transaction distribution -system.membus.trans_dist::ReadResp 292685 # Transaction distribution -system.membus.trans_dist::WriteReq 14132 # Transaction distribution -system.membus.trans_dist::WriteResp 14132 # Transaction distribution -system.membus.trans_dist::WritebackDirty 120936 # Transaction distribution +system.membus.trans_dist::ReadReq 7201 # Transaction distribution +system.membus.trans_dist::ReadResp 292681 # Transaction distribution +system.membus.trans_dist::WriteReq 14131 # Transaction distribution +system.membus.trans_dist::WriteResp 14131 # Transaction distribution +system.membus.trans_dist::WritebackDirty 120928 # Transaction distribution system.membus.trans_dist::CleanEvict 262098 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16894 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11785 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16893 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11783 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 123162 # Transaction distribution -system.membus.trans_dist::ReadExResp 122291 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285481 # Transaction distribution +system.membus.trans_dist::ReadExReq 123156 # Transaction distribution +system.membus.trans_dist::ReadExResp 122284 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285480 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42672 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1185820 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1228492 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42664 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1185794 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1228458 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83437 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83437 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1311929 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82507 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31152000 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31234507 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1311895 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82454 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31150976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31233430 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33892747 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22774 # Total snoops (count) -system.membus.snoop_fanout::samples 883255 # Request fanout histogram +system.membus.pkt_size::total 33891670 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 22771 # Total snoops (count) +system.membus.snoop_fanout::samples 883231 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 883255 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 883231 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 883255 # Request fanout histogram -system.membus.reqLayer0.occupancy 40521000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 883231 # Request fanout histogram +system.membus.reqLayer0.occupancy 40519500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1327609723 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1327558723 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2178253250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2178214500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 898617 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4790864 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2395593 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 361656 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 4790762 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2395545 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 361654 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 1242 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 1182 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 7204 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2107176 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14132 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14132 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 913504 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1018097 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 816785 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 17065 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 7201 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2107124 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14131 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14131 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 913453 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1018074 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 816802 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 17061 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 11848 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28913 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297603 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297603 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1019283 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1080704 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28909 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297601 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297601 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1019260 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1080678 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2061018 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3585479 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 995618 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 558881 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7200996 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 87922688 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118013949 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 42467904 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18601358 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 267005899 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 484765 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2873241 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.136986 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.344076 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2060877 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3585353 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 995690 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 558897 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7200817 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 87916672 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118008584 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 42470976 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18601102 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 266997334 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 484769 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2873172 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.136988 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.344078 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2479885 86.31% 86.31% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 393120 13.68% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2479819 86.31% 86.31% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 393117 13.68% 99.99% # Request fanout histogram system.toL2Bus.snoop_fanout::2 234 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2873241 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4223821996 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2873172 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4223704496 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 297883 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1031213250 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1031139756 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1802267282 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1802215285 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 499176813 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 499214310 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 293823888 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 293827886 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 13b640b18..b7a9648fc 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,158 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.871782 # Number of seconds simulated -sim_ticks 2871782342000 # Number of ticks simulated -final_tick 2871782342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.871806 # Number of seconds simulated +sim_ticks 2871806231000 # Number of ticks simulated +final_tick 2871806231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 937604 # Simulator instruction rate (inst/s) host_op_rate 1134083 # Simulator op (including micro ops) rate (op/s) host_tick_rate 20478123685 # Simulator tick rate (ticks/s) host_mem_usage 614632 # Number of bytes of host memory used host_seconds 140.24 # Real time elapsed on the host -sim_insts 131486349 # Number of instructions simulated -sim_ops 159039994 # Number of ops (including micro ops) simulated +sim_insts 131483712 # Number of instructions simulated +sim_ops 159036662 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1156004 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1264932 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8602496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 151508 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 548500 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 349120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1158756 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1268260 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8634112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 151380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 543380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 351296 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12074032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1156004 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 151508 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1307512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8524352 # Number of bytes written to this memory +system.physmem.bytes_read::total 12108656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1158756 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 151380 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1310136 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8536192 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8541916 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8553756 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26516 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20284 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134414 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2522 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8591 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5455 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26559 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20336 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134908 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2520 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8511 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5489 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 197805 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 133193 # Number of write requests responded to by this memory +system.physmem.num_reads::total 198346 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 133378 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 137584 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 111 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 137769 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 402539 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 440469 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2995525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52757 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 190996 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 121569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 403494 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 441625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3006509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 189212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 122326 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4204369 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 402539 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52757 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 455296 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2968314 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4216390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 403494 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 456206 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2972412 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6102 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2974430 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2968314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2978528 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2972412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 402539 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 446571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2995525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52757 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 191010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 121569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 403494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 447727 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3006509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 189226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 122326 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7178799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 197805 # Number of read requests accepted -system.physmem.writeReqs 137584 # Number of write requests accepted -system.physmem.readBursts 197805 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 137584 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12650304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue -system.physmem.bytesWritten 8554240 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12074032 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8541916 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7194919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198346 # Number of read requests accepted +system.physmem.writeReqs 137769 # Number of write requests accepted +system.physmem.readBursts 198346 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 137769 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12684736 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue +system.physmem.bytesWritten 8566272 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12108656 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8553756 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11699 # Per bank write bursts -system.physmem.perBankRdBursts::1 11843 # Per bank write bursts -system.physmem.perBankRdBursts::2 11790 # Per bank write bursts -system.physmem.perBankRdBursts::3 11735 # Per bank write bursts -system.physmem.perBankRdBursts::4 20524 # Per bank write bursts -system.physmem.perBankRdBursts::5 11797 # Per bank write bursts -system.physmem.perBankRdBursts::6 12442 # Per bank write bursts -system.physmem.perBankRdBursts::7 12572 # Per bank write bursts -system.physmem.perBankRdBursts::8 12187 # Per bank write bursts -system.physmem.perBankRdBursts::9 12631 # Per bank write bursts -system.physmem.perBankRdBursts::10 11774 # Per bank write bursts -system.physmem.perBankRdBursts::11 11306 # Per bank write bursts -system.physmem.perBankRdBursts::12 11587 # Per bank write bursts -system.physmem.perBankRdBursts::13 11723 # Per bank write bursts -system.physmem.perBankRdBursts::14 11020 # Per bank write bursts -system.physmem.perBankRdBursts::15 11031 # Per bank write bursts -system.physmem.perBankWrBursts::0 8350 # Per bank write bursts -system.physmem.perBankWrBursts::1 8610 # Per bank write bursts -system.physmem.perBankWrBursts::2 8670 # Per bank write bursts -system.physmem.perBankWrBursts::3 8312 # Per bank write bursts -system.physmem.perBankWrBursts::4 8160 # Per bank write bursts -system.physmem.perBankWrBursts::5 8304 # Per bank write bursts -system.physmem.perBankWrBursts::6 8940 # Per bank write bursts -system.physmem.perBankWrBursts::7 8786 # Per bank write bursts -system.physmem.perBankWrBursts::8 8636 # Per bank write bursts -system.physmem.perBankWrBursts::9 9040 # Per bank write bursts -system.physmem.perBankWrBursts::10 8341 # Per bank write bursts -system.physmem.perBankWrBursts::11 8261 # Per bank write bursts -system.physmem.perBankWrBursts::12 8330 # Per bank write bursts -system.physmem.perBankWrBursts::13 7860 # Per bank write bursts -system.physmem.perBankWrBursts::14 7712 # Per bank write bursts -system.physmem.perBankWrBursts::15 7348 # Per bank write bursts +system.physmem.perBankRdBursts::0 11680 # Per bank write bursts +system.physmem.perBankRdBursts::1 11729 # Per bank write bursts +system.physmem.perBankRdBursts::2 12020 # Per bank write bursts +system.physmem.perBankRdBursts::3 11779 # Per bank write bursts +system.physmem.perBankRdBursts::4 20245 # Per bank write bursts +system.physmem.perBankRdBursts::5 11824 # Per bank write bursts +system.physmem.perBankRdBursts::6 12521 # Per bank write bursts +system.physmem.perBankRdBursts::7 12818 # Per bank write bursts +system.physmem.perBankRdBursts::8 12201 # Per bank write bursts +system.physmem.perBankRdBursts::9 12749 # Per bank write bursts +system.physmem.perBankRdBursts::10 11883 # Per bank write bursts +system.physmem.perBankRdBursts::11 11375 # Per bank write bursts +system.physmem.perBankRdBursts::12 11512 # Per bank write bursts +system.physmem.perBankRdBursts::13 11780 # Per bank write bursts +system.physmem.perBankRdBursts::14 10986 # Per bank write bursts +system.physmem.perBankRdBursts::15 11097 # Per bank write bursts +system.physmem.perBankWrBursts::0 8306 # Per bank write bursts +system.physmem.perBankWrBursts::1 8598 # Per bank write bursts +system.physmem.perBankWrBursts::2 8866 # Per bank write bursts +system.physmem.perBankWrBursts::3 8386 # Per bank write bursts +system.physmem.perBankWrBursts::4 7973 # Per bank write bursts +system.physmem.perBankWrBursts::5 8273 # Per bank write bursts +system.physmem.perBankWrBursts::6 8936 # Per bank write bursts +system.physmem.perBankWrBursts::7 8926 # Per bank write bursts +system.physmem.perBankWrBursts::8 8615 # Per bank write bursts +system.physmem.perBankWrBursts::9 9047 # Per bank write bursts +system.physmem.perBankWrBursts::10 8395 # Per bank write bursts +system.physmem.perBankWrBursts::11 8237 # Per bank write bursts +system.physmem.perBankWrBursts::12 8245 # Per bank write bursts +system.physmem.perBankWrBursts::13 7999 # Per bank write bursts +system.physmem.perBankWrBursts::14 7661 # Per bank write bursts +system.physmem.perBankWrBursts::15 7385 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 27 # Number of times write queue was full causing retry -system.physmem.totGap 2871781902000 # Total gap between requests +system.physmem.numWrRetry 23 # Number of times write queue was full causing retry +system.physmem.totGap 2871805791000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9732 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 188045 # Read request sizes (log2) +system.physmem.readPktSize::6 188586 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 133193 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138723 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15603 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6977 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4557 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 91 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 133378 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 139268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8733 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3807 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -184,163 +180,159 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 107 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 87582 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 242.110023 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 136.595388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 304.444001 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46635 53.25% 53.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17297 19.75% 73.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6011 6.86% 79.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3421 3.91% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2493 2.85% 86.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1531 1.75% 88.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 857 0.98% 89.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 971 1.11% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8366 9.55% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 87582 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6415 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.812159 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 590.882305 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6413 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1075 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 81 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 87931 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 241.677497 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 136.342742 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 304.582310 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46815 53.24% 53.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17415 19.81% 73.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6112 6.95% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3386 3.85% 83.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2470 2.81% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1473 1.68% 88.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 853 0.97% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 929 1.06% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8478 9.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 87931 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6424 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.852584 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 590.448326 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6422 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6415 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6415 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.835542 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.951972 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.109397 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5337 83.20% 83.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 463 7.22% 90.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 65 1.01% 91.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 41 0.64% 92.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 43 0.67% 92.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 15 0.23% 92.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 61 0.95% 93.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 12 0.19% 94.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 120 1.87% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 12 0.19% 96.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.12% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 12 0.19% 96.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 75 1.17% 97.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 9 0.14% 97.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 97.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 25 0.39% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 75 1.17% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.03% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.05% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.02% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.17% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.05% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 5 0.08% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6415 # Writes before turning the bus around for reads -system.physmem.totQLat 4510532456 # Total ticks spent queuing -system.physmem.totMemAccLat 8216676206 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 988305000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22819.54 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6424 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6424 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.835616 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.963518 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.817635 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5349 83.27% 83.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 441 6.86% 90.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 73 1.14% 91.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 47 0.73% 92.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 38 0.59% 92.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 25 0.39% 92.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 52 0.81% 93.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 19 0.30% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 115 1.79% 95.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 11 0.17% 96.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 10 0.16% 96.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 10 0.16% 96.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 81 1.26% 97.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 9 0.14% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 97.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 28 0.44% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 75 1.17% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 5 0.08% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.05% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.05% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.16% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 7 0.11% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6424 # Writes before turning the bus around for reads +system.physmem.totQLat 4482627455 # Total ticks spent queuing +system.physmem.totMemAccLat 8198858705 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 990995000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22616.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41569.54 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 41366.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.97 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.88 # Average write queue length when enqueuing -system.physmem.readRowHits 165067 # Number of row buffer hits during reads -system.physmem.writeRowHits 78671 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.85 # Row buffer hit rate for writes -system.physmem.avgGap 8562540.52 # Average gap between requests -system.physmem.pageHitRate 73.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 341273520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 186210750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 814335600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 441495360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187570659120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 86023351485 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647608604750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1922985930585 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.614762 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2740794855198 # Time in different power states -system.physmem_0.memoryStateTime::REF 95895020000 # Time in different power states +system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing +system.physmem.readRowHits 165480 # Number of row buffer hits during reads +system.physmem.writeRowHits 78635 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.49 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.74 # Row buffer hit rate for writes +system.physmem.avgGap 8544116.72 # Average gap between requests +system.physmem.pageHitRate 73.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 342929160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 187114125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 816004800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 442350720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187572184800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 85984866225 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647656379000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1923001828830 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.614852 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2740877422516 # Time in different power states +system.physmem_0.memoryStateTime::REF 95895800000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35089613552 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35029624984 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 320846400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 175065000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 727412400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 424621440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187570659120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 84787415640 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1648692759000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1922698779000 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.514771 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2742610583350 # Time in different power states -system.physmem_1.memoryStateTime::REF 95895020000 # Time in different power states +system.physmem_1.actEnergy 321829200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 175601250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 729939600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 424984320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187572184800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85018582845 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648503996000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1922747118015 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.526158 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2742296701194 # Time in different power states +system.physmem_1.memoryStateTime::REF 95895800000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33276576650 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33613567806 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -396,59 +388,56 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 8793 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 8793 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1631 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7162 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 8793 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 8793 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 8793 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 7275 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12044.604811 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11100.960867 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5725.376750 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6764 92.98% 92.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 475 6.53% 99.51% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 28 0.38% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-147455 2 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 7275 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 8733 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 8733 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1652 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7081 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 8733 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 8733 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 8733 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 7215 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12160.221760 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11349.326630 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6137.175819 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 7184 99.57% 99.57% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 27 0.37% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 7215 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 1809726500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 1809726500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 1809726500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5691 78.23% 78.23% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1584 21.77% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 7275 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8793 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5610 77.75% 77.75% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1605 22.25% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 7215 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8733 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8793 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7275 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8733 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7215 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7275 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 16068 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7215 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 15948 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25747110 # DTB read hits -system.cpu0.dtb.read_misses 7587 # DTB read misses -system.cpu0.dtb.write_hits 19248161 # DTB write hits -system.cpu0.dtb.write_misses 1206 # DTB write misses +system.cpu0.dtb.read_hits 25746594 # DTB read hits +system.cpu0.dtb.read_misses 7520 # DTB read misses +system.cpu0.dtb.write_hits 19247313 # DTB write hits +system.cpu0.dtb.write_misses 1213 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3752 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3753 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1822 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1863 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 321 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25754697 # DTB read accesses -system.cpu0.dtb.write_accesses 19249367 # DTB write accesses +system.cpu0.dtb.read_accesses 25754114 # DTB read accesses +system.cpu0.dtb.write_accesses 19248526 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 44995271 # DTB hits -system.cpu0.dtb.misses 8793 # DTB misses -system.cpu0.dtb.accesses 45004064 # DTB accesses +system.cpu0.dtb.hits 44993907 # DTB hits +system.cpu0.dtb.misses 8733 # DTB misses +system.cpu0.dtb.accesses 45002640 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -486,13 +475,15 @@ system.cpu0.itb.walker.walkWaitTime::samples 3674 system.cpu0.itb.walker.walkWaitTime::0 3674 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 3674 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 2576 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12540.566770 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11604.890292 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 7309.377161 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 2541 98.64% 98.64% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 33 1.28% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12667.119565 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11857.484982 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6117.849264 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 2266 87.97% 87.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 279 10.83% 98.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 28 1.09% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.04% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 2576 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 1809154500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 1809154500 100.00% 100.00% # Table walker pending requests distribution @@ -507,7 +498,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2576 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2576 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 6250 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 121581439 # ITB inst hits +system.cpu0.itb.inst_hits 121577578 # ITB inst hits system.cpu0.itb.inst_misses 3674 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -524,40 +515,40 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 121585113 # ITB inst accesses -system.cpu0.itb.hits 121581439 # DTB hits +system.cpu0.itb.inst_accesses 121581252 # ITB inst accesses +system.cpu0.itb.hits 121577578 # DTB hits system.cpu0.itb.misses 3674 # DTB misses -system.cpu0.itb.accesses 121585113 # DTB accesses -system.cpu0.numCycles 5743564684 # number of cpu cycles simulated +system.cpu0.itb.accesses 121581252 # DTB accesses +system.cpu0.numCycles 5743612462 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1899 # number of quiesce instructions executed -system.cpu0.committedInsts 117764996 # Number of instructions committed -system.cpu0.committedOps 142323546 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 125936873 # Number of integer alu accesses +system.cpu0.kern.inst.quiesce 1891 # number of quiesce instructions executed +system.cpu0.committedInsts 117761026 # Number of instructions committed +system.cpu0.committedOps 142319020 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 125932364 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 11483 # Number of float alu accesses -system.cpu0.num_func_calls 12772448 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 16008688 # number of instructions that are conditional controls -system.cpu0.num_int_insts 125936873 # number of integer instructions +system.cpu0.num_func_calls 12772321 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 16008283 # number of instructions that are conditional controls +system.cpu0.num_int_insts 125932364 # number of integer instructions system.cpu0.num_fp_insts 11483 # number of float instructions -system.cpu0.num_int_register_reads 231719006 # number of times the integer registers were read -system.cpu0.num_int_register_writes 87450436 # number of times the integer registers were written +system.cpu0.num_int_register_reads 231711074 # number of times the integer registers were read +system.cpu0.num_int_register_writes 87448067 # number of times the integer registers were written system.cpu0.num_fp_register_reads 8771 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 515468589 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 53496392 # number of times the CC registers were written -system.cpu0.num_mem_refs 46152180 # number of memory refs -system.cpu0.num_load_insts 26006060 # Number of load instructions -system.cpu0.num_store_insts 20146120 # Number of store instructions -system.cpu0.num_idle_cycles 5455990176.452100 # Number of idle cycles -system.cpu0.num_busy_cycles 287574507.547900 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050069 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949931 # Percentage of idle cycles -system.cpu0.Branches 29546529 # Number of branches fetched +system.cpu0.num_cc_register_reads 515452324 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 53494266 # number of times the CC registers were written +system.cpu0.num_mem_refs 46150372 # number of memory refs +system.cpu0.num_load_insts 26005626 # Number of load instructions +system.cpu0.num_store_insts 20144746 # Number of store instructions +system.cpu0.num_idle_cycles 5456042423.958100 # Number of idle cycles +system.cpu0.num_busy_cycles 287570038.041900 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050068 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949932 # Percentage of idle cycles +system.cpu0.Branches 29545974 # Number of branches fetched system.cpu0.op_class::No_OpClass 2315 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 99842345 68.33% 68.33% # Class of executed instruction -system.cpu0.op_class::IntMult 112141 0.08% 68.41% # Class of executed instruction +system.cpu0.op_class::IntAlu 99839256 68.33% 68.33% # Class of executed instruction +system.cpu0.op_class::IntMult 112113 0.08% 68.41% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.41% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.41% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 68.41% # Class of executed instruction @@ -581,115 +572,115 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.41% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.41% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.41% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8311 0.01% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8315 0.01% 68.41% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.41% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.41% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::MemRead 26006060 17.80% 86.21% # Class of executed instruction -system.cpu0.op_class::MemWrite 20146120 13.79% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 26005626 17.80% 86.21% # Class of executed instruction +system.cpu0.op_class::MemWrite 20144746 13.79% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 146117292 # Class of executed instruction -system.cpu0.dcache.tags.replacements 732778 # number of replacements -system.cpu0.dcache.tags.tagsinuse 487.345221 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 44083181 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 733290 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 60.116981 # Average number of references to valid blocks. +system.cpu0.op_class::total 146112371 # Class of executed instruction +system.cpu0.dcache.tags.replacements 733230 # number of replacements +system.cpu0.dcache.tags.tagsinuse 488.702331 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 44081285 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 733742 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 60.077364 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1836359000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 487.345221 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.951846 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.951846 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 488.702331 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.954497 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.954497 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 90667478 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 90667478 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 24441740 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 24441740 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 18494582 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18494582 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 326232 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 326232 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374079 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 374079 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 371656 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 371656 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 42936322 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 42936322 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 43262554 # number of overall hits -system.cpu0.dcache.overall_hits::total 43262554 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 418013 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 418013 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 337667 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 337667 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 133440 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 133440 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22337 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22337 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19808 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19808 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 755680 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 755680 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 889120 # number of overall misses -system.cpu0.dcache.overall_misses::total 889120 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5665137000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5665137000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6926542000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6926542000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 343483500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 343483500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 502731000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 502731000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1840500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1840500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 12591679000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 12591679000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 12591679000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 12591679000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 24859753 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 24859753 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 18832249 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 18832249 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 459672 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 459672 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396416 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 396416 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391464 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 391464 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 43692002 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 43692002 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 44151674 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 44151674 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016815 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.016815 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017930 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017930 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.290294 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.290294 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056347 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056347 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.050600 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.050600 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.017296 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.017296 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.020138 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.020138 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13552.537840 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13552.537840 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20512.937302 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20512.937302 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15377.333572 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15377.333572 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25380.199919 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25380.199919 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 90665231 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 90665231 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 24440591 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 24440591 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 18493820 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18493820 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 326163 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 326163 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374037 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 374037 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 371586 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 371586 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 42934411 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 42934411 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 43260574 # number of overall hits +system.cpu0.dcache.overall_hits::total 43260574 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 418663 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 418663 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 337563 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 337563 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 133473 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 133473 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22401 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22401 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19896 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19896 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 756226 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 756226 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 889699 # number of overall misses +system.cpu0.dcache.overall_misses::total 889699 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5670544000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5670544000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6922080500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6922080500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 345375500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 345375500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 506120500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 506120500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1857000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1857000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 12592624500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 12592624500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 12592624500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 12592624500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24859254 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24859254 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18831383 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18831383 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 459636 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 459636 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396438 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 396438 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391482 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 391482 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 43690637 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 43690637 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 44150273 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 44150273 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016841 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.016841 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017926 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017926 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.290388 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.290388 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056506 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056506 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.050822 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.050822 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.017309 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.017309 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.020152 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.020152 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13544.411615 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13544.411615 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20506.040354 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20506.040354 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15417.860810 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15417.860810 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25438.304182 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25438.304182 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16662.713053 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16662.713053 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14161.956766 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14161.956766 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16651.932756 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16651.932756 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14153.803140 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14153.803140 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -698,149 +689,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 732778 # number of writebacks -system.cpu0.dcache.writebacks::total 732778 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25286 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25286 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15664 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15664 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25288 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25288 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25288 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25288 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 392727 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 392727 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337665 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 337665 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106338 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 106338 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6673 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6673 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19808 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 19808 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 730392 # 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number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15695 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25286 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25286 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25286 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25286 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 393378 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 393378 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337562 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 337562 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106333 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 106333 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6706 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6706 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19896 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19896 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 730940 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 730940 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 837273 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 837273 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31817 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31817 # number of ReadReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60319 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60319 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4843447000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4843447000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6588824500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6588824500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1737105000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1737105000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102846500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102846500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 482970000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 482970000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1793500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1793500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11432271500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11432271500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13169376500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13169376500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6629050000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6629050000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5400878000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5400878000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12029928000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12029928000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015798 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015798 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017930 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017930 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231335 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.231335 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016833 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016833 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.050600 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.050600 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016717 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016717 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018951 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018951 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12332.859722 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12332.859722 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19512.903321 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19512.903321 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16335.693731 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16335.693731 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15412.333283 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15412.333283 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24382.572698 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24382.572698 # average StoreCondReq mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60316 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60316 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4848200000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4848200000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6584514000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6584514000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1737943000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1737943000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 103994500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103994500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 486281500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 486281500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1800000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1800000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11432714000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11432714000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13170657000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13170657000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628843000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628843000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5400920500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5400920500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12029763500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12029763500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015824 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015824 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017926 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017926 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231342 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.231342 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016916 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016916 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.050822 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.050822 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016730 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016730 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018964 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018964 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12324.532638 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12324.532638 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19506.087771 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19506.087771 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16344.342772 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16344.342772 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15507.679690 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15507.679690 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24441.169079 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24441.169079 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15652.240851 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15652.240851 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15739.099232 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15739.099232 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208329.666876 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208329.666876 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189511.140742 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189511.140742 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199438.452229 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199438.452229 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15641.111446 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15641.111446 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15730.421260 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15730.421260 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208342.804161 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208342.804161 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189512.632022 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189512.632022 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199445.644605 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199445.644605 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1147265 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.321425 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 120433653 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1147777 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 104.927746 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1147026 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.321434 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 120430031 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1147538 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 104.946443 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 14862010000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321425 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321434 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998675 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998675 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 244310664 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 244310664 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 120433653 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 120433653 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 120433653 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 120433653 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 120433653 # number of overall hits -system.cpu0.icache.overall_hits::total 120433653 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1147786 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1147786 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1147786 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1147786 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1147786 # number of overall misses -system.cpu0.icache.overall_misses::total 1147786 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12247651500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12247651500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12247651500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12247651500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12247651500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12247651500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 121581439 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 121581439 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 121581439 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 121581439 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 121581439 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 121581439 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009440 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.009440 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009440 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.009440 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009440 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.009440 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10670.675108 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10670.675108 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10670.675108 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10670.675108 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10670.675108 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10670.675108 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 244302703 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 244302703 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 120430031 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 120430031 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 120430031 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 120430031 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 120430031 # number of overall hits +system.cpu0.icache.overall_hits::total 120430031 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1147547 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1147547 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1147547 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1147547 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1147547 # number of overall misses +system.cpu0.icache.overall_misses::total 1147547 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12241983500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12241983500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12241983500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12241983500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12241983500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12241983500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 121577578 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 121577578 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 121577578 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 121577578 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 121577578 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 121577578 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009439 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009439 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009439 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.009439 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009439 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.009439 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10667.958262 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10667.958262 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10667.958262 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10667.958262 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10667.958262 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10667.958262 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -849,238 +840,240 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 1147265 # number of writebacks -system.cpu0.icache.writebacks::total 1147265 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1147786 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1147786 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1147786 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1147786 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1147786 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1147786 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1147026 # number of writebacks +system.cpu0.icache.writebacks::total 1147026 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1147547 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1147547 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1147547 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1147547 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1147547 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1147547 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11673758500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11673758500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11673758500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11673758500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11673758500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11673758500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11668210000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11668210000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11668210000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11668210000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11668210000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11668210000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1253876500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1253876500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009440 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009440 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009440 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009440 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009440 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009440 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10170.675108 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10170.675108 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10170.675108 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10170.675108 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10170.675108 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10170.675108 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009439 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009439 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009439 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009439 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009439 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009439 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10167.958262 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10167.958262 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10167.958262 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10167.958262 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10167.958262 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10167.958262 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1935691 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1935756 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 57 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1935584 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1935659 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 66 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 245684 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 272679 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16060.422672 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3064880 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 288783 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 10.613090 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 246453 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 273594 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16077.204583 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3064483 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 289692 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 10.578418 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14559.127845 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.514376 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.125186 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1500.655266 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.888619 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000031 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.091593 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.980250 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1021 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15080 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 262 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 312 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 434 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 14597.123435 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.512757 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.144663 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1477.423728 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.890938 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000153 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000009 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.090175 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.981275 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1029 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15061 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 254 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 333 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 432 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3313 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7651 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3839 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062317 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.920410 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 62824015 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 62824015 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10929 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4820 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 15749 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 500939 # 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number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 650364 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1767687 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10929 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4820 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1101574 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 650364 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1767687 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 174 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 78 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 252 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55084 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 55084 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19799 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19799 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 9 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43776 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 43776 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 46212 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 46212 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94179 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 94179 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 174 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 78 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 46212 # 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average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63547.816252 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.228797 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21548.076923 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21006.666667 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21372.294372 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77179.151703 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 77179.151703 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25500.788172 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25500.788172 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16968.067988 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16968.067988 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 137049.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 137049.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56538.614908 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56538.614908 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 65605.366449 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65605.366449 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28270.224035 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28270.224035 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21548.076923 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21006.666667 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 65605.366449 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36920.891101 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44123.948519 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21548.076923 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21006.666667 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65605.366449 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36920.891101 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77179.151703 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63704.390920 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200316.687618 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185110.633661 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182006.877434 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182006.877434 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200329.807964 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185119.738485 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182008.368715 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182008.368715 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191665.826688 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183834.996611 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191673.022084 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183840.916958 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 3905249 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1969182 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28911 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 320342 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 316677 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3665 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 63843 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1765873 # Transaction distribution +system.cpu0.toL2Bus.snoop_filter.tot_requests 3905427 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1969134 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28903 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 319838 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 316964 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2874 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 63699 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1766064 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 28499 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 28499 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 732965 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1379104 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 189043 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 312150 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 85708 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41941 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112560 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 301555 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 298207 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1147786 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 575214 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3299 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3460881 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2681738 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11926 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27058 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6181603 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 146919352 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 101652834 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 19592 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 44412 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 248636190 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 986669 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2981108 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.123159 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.332339 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::WritebackDirty 734457 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1378164 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 189732 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 311664 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 85807 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41981 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112714 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 301438 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 298033 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1147547 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 575765 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3263 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3460164 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2683424 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12059 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27146 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6182793 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 146888760 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 101708758 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 20124 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 45328 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 248662970 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 986506 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2981817 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.122538 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.330833 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2617624 87.81% 87.81% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 359819 12.07% 99.88% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 3665 0.12% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2619305 87.84% 87.84% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 359638 12.06% 99.90% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 2874 0.10% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2981108 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 3885976496 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2981817 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 3886437494 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115188451 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115091926 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1730701000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1730342500 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1266054481 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1266858980 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 7028000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 15961487 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 15821984 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1323,57 +1316,65 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 2346 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 2346 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 473 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1873 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 2346 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 2346 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 2346 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1700 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11761.764706 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11073.675458 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5957.546231 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 1554 91.41% 91.41% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 135 7.94% 99.35% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-49151 5 0.29% 99.65% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-65535 5 0.29% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1700 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 2347 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 2347 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 475 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1872 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 2347 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 2347 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 2347 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1701 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11647.854203 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11021.395784 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 4763.004778 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-4095 3 0.18% 0.18% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-8191 360 21.16% 21.34% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-12287 989 58.14% 79.48% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-16383 206 12.11% 91.59% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-20479 34 2.00% 93.59% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::20480-24575 60 3.53% 97.12% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-28671 28 1.65% 98.77% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::28672-32767 11 0.65% 99.41% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-36863 1 0.06% 99.47% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::36864-40959 2 0.12% 99.59% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.18% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-53247 3 0.18% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1701 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples -1207257828 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 -1207257828 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total -1207257828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1227 72.18% 72.18% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 473 27.82% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1700 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2346 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1226 72.08% 72.08% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 475 27.92% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1701 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2347 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2346 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1700 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2347 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1701 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1700 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 4046 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1701 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 4048 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3334779 # DTB read hits -system.cpu1.dtb.read_misses 1954 # DTB read misses -system.cpu1.dtb.write_hits 2915242 # DTB write hits -system.cpu1.dtb.write_misses 392 # DTB write misses +system.cpu1.dtb.read_hits 3334777 # DTB read hits +system.cpu1.dtb.read_misses 1951 # DTB read misses +system.cpu1.dtb.write_hits 2915290 # DTB write hits +system.cpu1.dtb.write_misses 396 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1652 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 260 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 124 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3336733 # DTB read accesses -system.cpu1.dtb.write_accesses 2915634 # DTB write accesses +system.cpu1.dtb.read_accesses 3336728 # DTB read accesses +system.cpu1.dtb.write_accesses 2915686 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6250021 # DTB hits -system.cpu1.dtb.misses 2346 # DTB misses -system.cpu1.dtb.accesses 6252367 # DTB accesses +system.cpu1.dtb.hits 6250067 # DTB hits +system.cpu1.dtb.misses 2347 # DTB misses +system.cpu1.dtb.accesses 6252414 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1412,19 +1413,19 @@ system.cpu1.itb.walker.walkWaitTime::0 1376 100.00% 100.00% # Ta system.cpu1.itb.walker.walkWaitTime::total 1376 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 819 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::mean 11933.455433 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11288.127256 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5150.797327 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 116 14.16% 14.16% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 577 70.45% 84.62% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 76 9.28% 93.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 8 0.98% 94.87% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.24% 95.12% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 22 2.69% 97.80% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.98% 98.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 98.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.61% 99.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11302.540712 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5121.103483 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 113 13.80% 13.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 572 69.84% 83.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 87 10.62% 94.26% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 7 0.85% 95.12% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.12% 95.24% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 23 2.81% 98.05% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.98% 99.02% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 4 0.49% 99.51% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.24% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.24% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.12% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.12% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 819 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples -1208095828 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 -1208095828 100.00% 100.00% # Table walker pending requests distribution @@ -1439,7 +1440,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 819 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 819 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2195 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 13920333 # ITB inst hits +system.cpu1.itb.inst_hits 13921759 # ITB inst hits system.cpu1.itb.inst_misses 1376 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1456,40 +1457,40 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 13921709 # ITB inst accesses -system.cpu1.itb.hits 13920333 # DTB hits +system.cpu1.itb.inst_accesses 13923135 # ITB inst accesses +system.cpu1.itb.hits 13921759 # DTB hits system.cpu1.itb.misses 1376 # DTB misses -system.cpu1.itb.accesses 13921709 # DTB accesses -system.cpu1.numCycles 5742623362 # number of cpu cycles simulated +system.cpu1.itb.accesses 13923135 # DTB accesses +system.cpu1.numCycles 5742672703 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2722 # number of quiesce instructions executed -system.cpu1.committedInsts 13721353 # Number of instructions committed -system.cpu1.committedOps 16716448 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 15155011 # Number of integer alu accesses +system.cpu1.kern.inst.quiesce 2702 # number of quiesce instructions executed +system.cpu1.committedInsts 13722686 # Number of instructions committed +system.cpu1.committedOps 16717642 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 15156242 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 915079 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1497955 # number of instructions that are conditional controls -system.cpu1.num_int_insts 15155011 # number of integer instructions +system.cpu1.num_func_calls 915130 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1497977 # number of instructions that are conditional controls +system.cpu1.num_int_insts 15156242 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 27537464 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10698089 # number of times the integer registers were written +system.cpu1.num_int_register_reads 27539507 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10698774 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 61338598 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 5194112 # number of times the CC registers were written -system.cpu1.num_mem_refs 6464162 # number of memory refs -system.cpu1.num_load_insts 3439477 # Number of load instructions -system.cpu1.num_store_insts 3024685 # Number of store instructions -system.cpu1.num_idle_cycles 5696031009.438875 # Number of idle cycles -system.cpu1.num_busy_cycles 46592352.561125 # Number of busy cycles -system.cpu1.not_idle_fraction 0.008113 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.991887 # Percentage of idle cycles -system.cpu1.Branches 2464329 # Number of branches fetched +system.cpu1.num_cc_register_reads 61342237 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 5194989 # number of times the CC registers were written +system.cpu1.num_mem_refs 6464220 # number of memory refs +system.cpu1.num_load_insts 3439445 # Number of load instructions +system.cpu1.num_store_insts 3024775 # Number of store instructions +system.cpu1.num_idle_cycles 5696078911.641530 # Number of idle cycles +system.cpu1.num_busy_cycles 46593791.358469 # Number of busy cycles +system.cpu1.not_idle_fraction 0.008114 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.991886 # Percentage of idle cycles +system.cpu1.Branches 2464409 # Number of branches fetched system.cpu1.op_class::No_OpClass 24 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 10543721 61.89% 61.89% # Class of executed instruction -system.cpu1.op_class::IntMult 24250 0.14% 62.04% # Class of executed instruction +system.cpu1.op_class::IntAlu 10544854 61.90% 61.90% # Class of executed instruction +system.cpu1.op_class::IntMult 24300 0.14% 62.04% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 62.04% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 62.04% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 62.04% # Class of executed instruction @@ -1513,114 +1514,114 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.04% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.04% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.04% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3188 0.02% 62.05% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 62.05% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.05% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.05% # Class of executed instruction -system.cpu1.op_class::MemRead 3439477 20.19% 82.24% # Class of executed instruction -system.cpu1.op_class::MemWrite 3024685 17.76% 100.00% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3186 0.02% 62.06% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.06% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.06% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.06% # Class of executed instruction +system.cpu1.op_class::MemRead 3439445 20.19% 82.25% # Class of executed instruction +system.cpu1.op_class::MemWrite 3024775 17.75% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 17035345 # Class of executed instruction -system.cpu1.dcache.tags.replacements 148314 # number of replacements -system.cpu1.dcache.tags.tagsinuse 469.091453 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6019898 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 148666 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 40.492769 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 106291978000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.091453 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916194 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.916194 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 352 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 33 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 12680697 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 12680697 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3066133 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3066133 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2748576 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2748576 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41842 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 41842 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69851 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 69851 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61610 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 61610 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5814709 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5814709 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 5856551 # number of overall hits -system.cpu1.dcache.overall_hits::total 5856551 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 112800 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 112800 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 79377 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 79377 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24461 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 24461 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16636 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16636 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23088 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23088 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 192177 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 192177 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 216638 # number of overall misses -system.cpu1.dcache.overall_misses::total 216638 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1758096000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1758096000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2710284000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2710284000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320294000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 320294000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 628163500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 628163500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3848000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3848000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4468380000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4468380000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4468380000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4468380000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3178933 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3178933 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2827953 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2827953 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66303 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 66303 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86487 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 86487 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84698 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 84698 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 6006886 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 6006886 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 6073189 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 6073189 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035484 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035484 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028069 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.028069 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.368927 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.368927 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.192353 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.192353 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.272592 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.272592 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031993 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031993 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035671 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035671 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15585.957447 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15585.957447 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34144.449904 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34144.449904 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19253.065641 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19253.065641 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27207.358801 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27207.358801 # average StoreCondReq miss latency +system.cpu1.op_class::total 17036584 # Class of executed instruction +system.cpu1.dcache.tags.replacements 148452 # number of replacements +system.cpu1.dcache.tags.tagsinuse 468.602887 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6022671 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 148794 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 40.476572 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 106290860000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.602887 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.915240 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.915240 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 36 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.667969 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 12680857 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 12680857 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3066042 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3066042 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2748534 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2748534 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41898 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 41898 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69885 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 69885 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61599 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 61599 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 5814576 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 5814576 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 5856474 # number of overall hits +system.cpu1.dcache.overall_hits::total 5856474 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 112908 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 112908 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 79472 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 79472 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24389 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 24389 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16600 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16600 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23097 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23097 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 192380 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 192380 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 216769 # number of overall misses +system.cpu1.dcache.overall_misses::total 216769 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1761858500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1761858500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2707072000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2707072000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 321180000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 321180000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 626224500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 626224500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5032000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5032000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4468930500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4468930500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4468930500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4468930500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3178950 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3178950 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2828006 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2828006 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66287 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 66287 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86485 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 86485 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84696 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 84696 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 6006956 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 6006956 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 6073243 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 6073243 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035517 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035517 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028102 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.028102 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.367930 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.367930 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.191941 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.191941 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.272705 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.272705 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.032026 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.032026 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035692 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035692 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15604.372587 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15604.372587 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34063.217234 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34063.217234 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19348.192771 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19348.192771 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27112.806858 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27112.806858 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23251.377636 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23251.377636 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20626.021289 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20626.021289 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23229.704231 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23229.704231 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20616.095936 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20616.095936 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1629,147 +1630,147 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 148314 # number of writebacks -system.cpu1.dcache.writebacks::total 148314 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 199 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 199 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11732 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11732 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 199 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 199 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 199 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 199 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 112601 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 112601 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79377 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 79377 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 24003 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 24003 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4904 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4904 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23088 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23088 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 191978 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 191978 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 215981 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 215981 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3083 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3083 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2425 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2425 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5508 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5508 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1635811500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1635811500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2630907000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2630907000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 431572500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 431572500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89921000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89921000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 605110500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 605110500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3813000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3813000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4266718500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4266718500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4698291000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4698291000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 439541500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 439541500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 303268000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 303268000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742809500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742809500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035421 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035421 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028069 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028069 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.362020 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.362020 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056702 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056702 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.272592 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.272592 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031960 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031960 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035563 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035563 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14527.504196 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14527.504196 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33144.449904 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33144.449904 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17979.940007 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17979.940007 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18336.256117 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18336.256117 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26208.874740 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26208.874740 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 148452 # number of writebacks +system.cpu1.dcache.writebacks::total 148452 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 223 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11671 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11671 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 223 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 223 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 223 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 112685 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 112685 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79472 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 79472 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23925 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 23925 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4929 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4929 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23097 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23097 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 192157 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 192157 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 216082 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 216082 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3082 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3082 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2423 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2423 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5505 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5505 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1634927500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1634927500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2627600000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2627600000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 437401500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 437401500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91610500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91610500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 603174500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 603174500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4985000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4985000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4262527500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4262527500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4699929000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4699929000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 439527500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 439527500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 303136500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 303136500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742664000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742664000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035447 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035447 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028102 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028102 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.360930 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.360930 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056993 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056993 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.272705 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.272705 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031989 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031989 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035579 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035579 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14508.829924 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14508.829924 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33063.217234 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33063.217234 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18282.194357 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18282.194357 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18586.021505 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18586.021505 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26114.841754 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26114.841754 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22225.038807 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22225.038807 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21753.260703 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21753.260703 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142569.412910 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142569.412910 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125058.969072 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125058.969072 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134860.112564 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134860.112564 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22182.525227 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22182.525227 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21750.673355 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21750.673355 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142611.129137 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142611.129137 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125107.924061 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125107.924061 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134907.175295 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134907.175295 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 463432 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.310833 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 13456384 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 463944 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 29.004328 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 106360036500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.310833 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973263 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973263 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 463484 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.310914 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 13457758 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 463996 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 29.004039 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 106358922000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.310914 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973264 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973264 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 28304600 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 28304600 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 13456384 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13456384 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13456384 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13456384 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13456384 # number of overall hits -system.cpu1.icache.overall_hits::total 13456384 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 463944 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 463944 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 463944 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 463944 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 463944 # number of overall misses -system.cpu1.icache.overall_misses::total 463944 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4214272500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4214272500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4214272500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4214272500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4214272500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4214272500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13920328 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13920328 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13920328 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13920328 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13920328 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13920328 # number of overall (read+write) accesses +system.cpu1.icache.tags.tag_accesses 28307504 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 28307504 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 13457758 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13457758 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13457758 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13457758 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13457758 # number of overall hits +system.cpu1.icache.overall_hits::total 13457758 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 463996 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 463996 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 463996 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 463996 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 463996 # number of overall misses +system.cpu1.icache.overall_misses::total 463996 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4214067500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4214067500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4214067500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4214067500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4214067500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4214067500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13921754 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13921754 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13921754 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13921754 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13921754 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13921754 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033329 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.033329 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033329 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total 0.033329 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033329 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.033329 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9083.580130 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9083.580130 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9083.580130 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9083.580130 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9083.580130 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9083.580130 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9082.120320 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9082.120320 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9082.120320 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9082.120320 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9082.120320 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9082.120320 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1778,24 +1779,24 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # 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number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 463996 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 463996 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 463996 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 463996 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 463996 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3982300500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3982300500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3982300500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3982300500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3982300500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3982300500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3982069500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3982069500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3982069500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3982069500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3982069500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3982069500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 23546500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 23546500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 23546500 # number of overall MSHR uncacheable cycles @@ -1806,298 +1807,298 @@ system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.033329 system.cpu1.icache.demand_mshr_miss_rate::total 0.033329 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.033329 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8583.580130 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8583.580130 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8583.580130 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8583.580130 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8583.580130 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8583.580130 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8582.120320 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8582.120320 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8582.120320 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8582.120320 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8582.120320 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8582.120320 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 118303 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 118321 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.num_hwpf_issued 117918 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 117936 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 16 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # 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number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 927478543 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 3906024043 # number of overall MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22219000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 414529000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 436748000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 285072000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 285072000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 414523000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 436742000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 284955500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 284955500 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22219000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 699601000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 721820000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.124153 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.169109 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.141577 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 699478500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 721697500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.124642 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.166480 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.140986 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses @@ -2106,113 +2107,113 @@ system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.637826 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.637826 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019198 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.019198 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.451423 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451423 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.124153 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.169109 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.019198 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.500380 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159871 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.124153 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.169109 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.019198 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.500380 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.635821 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.635821 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018914 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018914 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.451105 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451105 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.124642 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.166480 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018914 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.499625 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159462 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.124642 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.166480 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018914 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.499625 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191827 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14162.808642 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44272.218526 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44272.218526 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19901.166603 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19901.166603 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18706.436523 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18706.436523 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 3550000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 3550000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44810.382905 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44810.382905 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 53553.834063 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 53553.834063 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16480.612085 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16480.612085 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 53553.834063 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25964.974122 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28219.919685 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 53553.834063 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25964.974122 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44272.218526 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30894.056879 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191241 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14073.275862 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14013.931889 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44184.581154 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44184.581154 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19905.624978 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19905.624978 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18619.565217 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18619.565217 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 926400 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 926400 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44732.064878 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44732.064878 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54263.616682 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54263.616682 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16588.591834 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16588.591834 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14073.275862 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54263.616682 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25996.256868 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28277.957107 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14073.275862 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54263.616682 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25996.256868 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44184.581154 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30921.170050 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134456.373662 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133971.779141 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117555.463918 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117555.463918 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134498.053212 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134011.046333 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117604.416013 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117604.416013 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127015.432099 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126969.217238 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127062.397820 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127014.695530 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 1324645 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 668824 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10099 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 169409 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 166956 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2453 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 10097 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 652790 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2425 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2425 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 119017 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 519745 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 86537 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 25449 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 70337 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40896 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 84740 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 57665 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 55147 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 463944 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 215084 # Transaction distribution +system.cpu1.toL2Bus.snoop_filter.tot_requests 1324952 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 669028 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10089 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 168501 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 166697 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1804 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 10096 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 652859 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2423 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2423 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 119114 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 519969 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 86535 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 25223 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 70168 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40922 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 84814 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 57641 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 55180 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 463996 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 214635 # Transaction distribution system.cpu1.toL2Bus.trans_dist::InvalidateReq 32 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1391674 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 722021 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4392 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7022 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2125109 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 59352772 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24485096 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7096 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11212 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 83856176 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 356096 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 999531 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.187033 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.396182 # Request fanout histogram +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1391830 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 722434 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4408 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7011 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2125683 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 59359428 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24498524 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7160 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11168 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 83876280 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 355270 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 998881 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.185518 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.393336 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 815039 81.54% 81.54% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 182039 18.21% 99.75% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 2453 0.25% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 815375 81.63% 81.63% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 181702 18.19% 99.82% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1804 0.18% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 999531 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1279051999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 998881 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1279425500 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79434008 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79453408 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 696093000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 696171000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 318231000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 318356500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 2618000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) @@ -2268,17 +2269,17 @@ system.iobus.pkt_size_system.bridge.master::total 162814 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48746500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 48736000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 32500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 93500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 93000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 609000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) @@ -2302,25 +2303,25 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6162500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6160500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 32045500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 32043500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187117449 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187096722 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36461 # number of replacements -system.iocache.tags.tagsinuse 14.380044 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.380038 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 290746348000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.380044 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.898753 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.898753 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 290749964000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.380038 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.898752 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.898752 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2334,14 +2335,14 @@ system.iocache.demand_misses::realview.ide 255 # system.iocache.demand_misses::total 255 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 255 # number of overall misses system.iocache.overall_misses::total 255 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32874877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32874877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4582462572 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4582462572 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32874877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32874877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32874877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32874877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32883377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32883377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4577110345 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4577110345 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32883377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32883377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32883377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32883377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2358,19 +2359,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128921.086275 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128921.086275 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126503.494148 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126503.494148 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128921.086275 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128921.086275 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128921.086275 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128921.086275 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 19 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128954.419608 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128954.419608 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126355.740531 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126355.740531 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128954.419608 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128954.419608 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128954.419608 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128954.419608 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.333333 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2384,14 +2385,14 @@ system.iocache.demand_mshr_misses::realview.ide 255 system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 20124877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 20124877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2769551646 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2769551646 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 20124877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 20124877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 20124877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 20124877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 20133377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 20133377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764215832 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2764215832 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 20133377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 20133377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 20133377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 20133377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2400,303 +2401,290 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78921.086275 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 78921.086275 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76456.262312 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76456.262312 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 78921.086275 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 78921.086275 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 78921.086275 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 78921.086275 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78954.419608 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 78954.419608 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76308.961793 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76308.961793 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 78954.419608 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 78954.419608 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 78954.419608 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 78954.419608 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 123661 # number of replacements -system.l2c.tags.tagsinuse 63058.402721 # Cycle average of tags in use -system.l2c.tags.total_refs 421257 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 187718 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.244095 # Average number of references to valid blocks. +system.l2c.tags.replacements 124374 # number of replacements +system.l2c.tags.tagsinuse 62971.222447 # Cycle average of tags in use +system.l2c.tags.total_refs 421293 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 188431 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.235795 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13491.325958 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.985555 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.052859 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7361.006580 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2805.566875 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35728.682862 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954518 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1443.499308 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 410.819619 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1814.508588 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.205861 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.112320 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042810 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.545176 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.022026 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.006269 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027687 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.962195 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 32044 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 32009 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 306 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5120 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 26618 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 402 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2325 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 29253 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.488953 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.488419 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5830329 # Number of tag accesses -system.l2c.tags.data_accesses 5830329 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 257370 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 257370 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 32263 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1924 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 34187 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2044 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 899 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2943 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4115 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1385 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5500 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 95 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 72 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 28709 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 46783 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47559 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 20 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 13 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 6543 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 5065 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3419 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 138278 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 95 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 72 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 28709 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 50898 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 47559 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 20 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 13 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 6543 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 6450 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 3419 # number of demand (read+write) hits -system.l2c.demand_hits::total 143778 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 95 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 72 # number of overall hits -system.l2c.overall_hits::cpu0.inst 28709 # number of overall hits -system.l2c.overall_hits::cpu0.data 50898 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 47559 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 20 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 13 # number of overall hits -system.l2c.overall_hits::cpu1.inst 6543 # number of overall hits -system.l2c.overall_hits::cpu1.data 6450 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 3419 # number of overall hits -system.l2c.overall_hits::total 143778 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9386 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2249 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11635 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 587 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1308 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1895 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11114 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7777 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 18891 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 5 # number of ReadSharedReq misses +system.l2c.tags.occ_blocks::writebacks 13456.936548 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.884029 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.161578 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7408.035333 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2772.307356 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35669.502662 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1440.723489 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 421.652649 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1798.018803 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.205337 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000059 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.113038 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.042302 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.544273 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.021984 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.006434 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027436 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.960865 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 32172 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 31879 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 296 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5261 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 26614 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 368 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2433 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 29060 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.490906 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.486435 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5838028 # Number of tag accesses +system.l2c.tags.data_accesses 5838028 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 257920 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 257920 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 32259 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1955 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 34214 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2096 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 941 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 3037 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4136 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1368 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5504 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 86 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 68 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 28311 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 47114 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47400 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 25 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 16 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 6412 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 5086 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3327 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 137845 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 86 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 28311 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 51250 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 47400 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 25 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 16 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 6412 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 6454 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 3327 # number of demand (read+write) hits +system.l2c.demand_hits::total 143349 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 86 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 68 # number of overall hits +system.l2c.overall_hits::cpu0.inst 28311 # number of overall hits +system.l2c.overall_hits::cpu0.data 51250 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 47400 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 25 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 16 # number of overall hits +system.l2c.overall_hits::cpu1.inst 6412 # number of overall hits +system.l2c.overall_hits::cpu1.data 6454 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 3327 # number of overall hits +system.l2c.overall_hits::total 143349 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 9332 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2240 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11572 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 606 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1282 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1888 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11165 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 7705 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 18870 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 6 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 17503 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 8876 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134571 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 17548 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 8846 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 135065 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.inst 2364 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 804 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5455 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 169581 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses +system.l2c.ReadSharedReq_misses::cpu1.data 796 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5489 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 170116 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 6 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 17503 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 19990 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 134571 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 17548 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 20011 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 135065 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 2364 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8581 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 5455 # number of demand (read+write) misses -system.l2c.demand_misses::total 188472 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses +system.l2c.demand_misses::cpu1.data 8501 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 5489 # number of demand (read+write) misses +system.l2c.demand_misses::total 188986 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 6 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 17503 # number of overall misses -system.l2c.overall_misses::cpu0.data 19990 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 134571 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu0.inst 17548 # number of overall misses +system.l2c.overall_misses::cpu0.data 20011 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 135065 # number of overall misses system.l2c.overall_misses::cpu1.inst 2364 # number of overall misses -system.l2c.overall_misses::cpu1.data 8581 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 5455 # number of overall misses -system.l2c.overall_misses::total 188472 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 30248000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 5203000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 35451000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3836500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2726000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 6562500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 1620087000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1017624500 # 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mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.552352 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.065217 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.028571 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.382564 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.280813 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740224 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.268345 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.568439 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.622618 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.568622 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.065217 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.028571 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.382564 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.280813 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740224 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.268345 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.568439 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.622618 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.568622 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72734.033433 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72331.696429 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72656.152783 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74575.082508 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73932.527301 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74138.771186 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135700.046305 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121478.197794 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 129892.979915 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 124916.666667 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121559.878933 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126142.550983 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135080.747196 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123628.455626 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 140210.435930 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145140.941337 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133411.035014 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 124916.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121559.878933 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131475.089851 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135080.747196 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123628.455626 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123232.210446 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145140.941337 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 133059.737740 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 124916.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121559.878933 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131475.089851 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135080.747196 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123628.455626 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123232.210446 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145140.941337 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 133059.737740 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182316.341923 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182329.650847 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116572.727273 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163341.515681 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165006.368645 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100538.350928 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159950.911945 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116613.998376 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163353.770314 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165007.403804 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100578.208832 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159958.831932 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174137.875296 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174144.978148 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109509.446140 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 161943.930541 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109552.072156 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 161954.377048 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 44099 # Transaction distribution -system.membus.trans_dist::ReadResp 213926 # Transaction distribution -system.membus.trans_dist::WriteReq 30924 # Transaction distribution -system.membus.trans_dist::WriteResp 30924 # Transaction distribution -system.membus.trans_dist::WritebackDirty 133193 # Transaction distribution -system.membus.trans_dist::CleanEvict 14771 # Transaction distribution -system.membus.trans_dist::UpgradeReq 73670 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 39871 # Transaction distribution +system.membus.trans_dist::ReadReq 44095 # Transaction distribution +system.membus.trans_dist::ReadResp 214453 # Transaction distribution +system.membus.trans_dist::WriteReq 30922 # Transaction distribution +system.membus.trans_dist::WriteResp 30922 # Transaction distribution +system.membus.trans_dist::WritebackDirty 133378 # Transaction distribution +system.membus.trans_dist::CleanEvict 14958 # Transaction distribution +system.membus.trans_dist::UpgradeReq 73332 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 39852 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 39385 # Transaction distribution -system.membus.trans_dist::ReadExResp 18791 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 169827 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.membus.trans_dist::ReadExReq 39426 # Transaction distribution +system.membus.trans_dist::ReadExResp 18801 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 170358 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 650336 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 772080 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13764 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 651465 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 773197 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72955 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72955 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 845035 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 846152 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27552 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18297804 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18488238 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18344268 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18534678 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20806382 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 121083 # Total snoops (count) -system.membus.snoop_fanout::samples 581994 # Request fanout histogram +system.membus.pkt_size::total 20852822 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 120859 # Total snoops (count) +system.membus.snoop_fanout::samples 582572 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 581994 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 582572 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 581994 # Request fanout histogram -system.membus.reqLayer0.occupancy 88286500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 582572 # Request fanout histogram +system.membus.reqLayer0.occupancy 88269500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11391000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11360500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 968108262 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 969988933 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1106274782 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1109172490 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1388877 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1385877 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3011,52 +2987,52 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 960339 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 518534 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 139328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 20435 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 19626 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 809 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 44102 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 468032 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30924 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30924 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 390589 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 105128 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 107757 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 42814 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 150571 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 82 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50426 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50426 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 423945 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 961097 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 519247 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 138785 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 20683 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 19864 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 819 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 44098 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 467805 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30922 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30922 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 391320 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 106223 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 107477 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 42889 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 150366 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 104 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50473 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50473 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 423722 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1240075 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 253445 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1493520 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34222158 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3776032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 37998190 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 438746 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 896439 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.337268 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.474682 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1241271 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 253131 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1494402 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34264962 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3773844 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 38038806 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 438960 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 896783 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.336520 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.474448 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 594908 66.36% 66.36% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 300722 33.55% 99.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 809 0.09% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 595817 66.44% 66.44% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 300147 33.47% 99.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 819 0.09% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 896439 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 863728414 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 896783 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 864823852 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 360123 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 645946273 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 645977888 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 202615858 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 202227821 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |