diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-03-21 10:36:45 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-03-21 10:36:45 -0500 |
| commit | 3c666083c6f5fecc38699a6f0c5f4f25b23e18c9 (patch) | |
| tree | e554e37e76714f9ae9c9faa07ef645db0f9a6d93 /tests/quick | |
| parent | 8e2a8fbb7e4751260c88fccd19ebe8d1138d0695 (diff) | |
| download | gem5-3c666083c6f5fecc38699a6f0c5f4f25b23e18c9.tar.xz | |
ARM: Update stats for IT and conditional branch changes
Diffstat (limited to 'tests/quick')
27 files changed, 1234 insertions, 1234 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index ebd663d39..78c29faa1 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -306,7 +306,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] @@ -400,7 +400,7 @@ port=system.membus.master[2] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -640,13 +640,16 @@ proc_id1=201327138 system=system pio=system.iobus.master[1] -[system.realview.rtc_fake] -type=AmbaFake -amba_id=266289 -ignore_access=false +[system.realview.rtc] +type=PL031 +amba_id=3412017 +gic=system.realview.gic +int_delay=100000 +int_num=42 pio_addr=268529664 pio_latency=1000 system=system +time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[23] [system.realview.sci_fake] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index c5cc2bafe..8b688fa3a 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,13 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 08:32:03 -gem5 started Mar 9 2012 08:33:32 +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 16:34:57 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -The currently selected ARM platforms doesn't support - the amount of DRAM you've selected. Please try - another platform +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index f60d68e94..f44938962 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,13 +4,13 @@ sim_seconds 2.411694 # Nu sim_ticks 2411694099500 # Number of ticks simulated final_tick 2411694099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2022463 # Simulator instruction rate (inst/s) -host_op_rate 2614492 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79249307765 # Simulator tick rate (ticks/s) -host_mem_usage 379912 # Number of bytes of host memory used -host_seconds 30.43 # Real time elapsed on the host -sim_insts 61546998 # Number of instructions simulated -sim_ops 79563488 # Number of ops (including micro ops) simulated +host_inst_rate 2019241 # Simulator instruction rate (inst/s) +host_op_rate 2610327 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79123006525 # Simulator tick rate (ticks/s) +host_mem_usage 377328 # Number of bytes of host memory used +host_seconds 30.48 # Real time elapsed on the host +sim_insts 61547057 # Number of instructions simulated +sim_ops 79563547 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -31,20 +31,20 @@ system.physmem.bw_inst_read 419370 # In system.physmem.bw_write 4223269 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total 55336844 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 127720 # number of replacements -system.l2c.tagsinuse 25547.920863 # Cycle average of tags in use -system.l2c.total_refs 1498989 # Total number of references to valid blocks. +system.l2c.tagsinuse 25547.920882 # Cycle average of tags in use +system.l2c.total_refs 1498993 # Total number of references to valid blocks. system.l2c.sampled_refs 156132 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.600780 # Average number of references to valid blocks. +system.l2c.avg_refs 9.600806 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 14919.913596 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 14919.913613 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 1.146267 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.046172 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3116.154269 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 1287.935030 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3116.154275 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 1287.935036 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.dtb.walker 4.789000 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.itb.walker 0.017808 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2080.961375 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4136.957345 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2080.961372 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4136.957340 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.227660 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000017 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy @@ -61,11 +61,11 @@ system.l2c.ReadReq_hits::cpu0.inst 493019 # nu system.l2c.ReadReq_hits::cpu0.data 213171 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 4123 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 1590 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 368109 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 131706 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1218925 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 580461 # number of Writeback hits -system.l2c.Writeback_hits::total 580461 # number of Writeback hits +system.l2c.ReadReq_hits::cpu1.inst 368111 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 131707 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1218928 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 580462 # number of Writeback hits +system.l2c.Writeback_hits::total 580462 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 776 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 523 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 1299 # number of UpgradeReq hits @@ -81,18 +81,18 @@ system.l2c.demand_hits::cpu0.inst 493019 # nu system.l2c.demand_hits::cpu0.data 278002 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 4123 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 1590 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 368109 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 169503 # number of demand (read+write) hits -system.l2c.demand_hits::total 1321553 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 368111 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 169504 # number of demand (read+write) hits +system.l2c.demand_hits::total 1321556 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 5051 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 2156 # number of overall hits system.l2c.overall_hits::cpu0.inst 493019 # number of overall hits system.l2c.overall_hits::cpu0.data 278002 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 4123 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 1590 # number of overall hits -system.l2c.overall_hits::cpu1.inst 368109 # number of overall hits -system.l2c.overall_hits::cpu1.data 169503 # number of overall hits -system.l2c.overall_hits::total 1321553 # number of overall hits +system.l2c.overall_hits::cpu1.inst 368111 # number of overall hits +system.l2c.overall_hits::cpu1.data 169504 # number of overall hits +system.l2c.overall_hits::total 1321556 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 7 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.inst 10289 # number of ReadReq misses @@ -135,11 +135,11 @@ system.l2c.ReadReq_accesses::cpu0.inst 503308 # nu system.l2c.ReadReq_accesses::cpu0.data 222557 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 4144 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 1603 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 373203 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 141836 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1253876 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 580461 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 580461 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 373205 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 141837 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1253879 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 580462 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 580462 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 7125 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 4015 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 11140 # number of UpgradeReq accesses(hits+misses) @@ -155,18 +155,18 @@ system.l2c.demand_accesses::cpu0.inst 503308 # nu system.l2c.demand_accesses::cpu0.data 386436 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 4144 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 1603 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 373203 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 228418 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1504337 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 373205 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 228419 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1504340 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 5062 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 2163 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 503308 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 386436 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 4144 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 1603 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 373203 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 228418 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1504337 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 373205 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 228419 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1504340 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.002173 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.003236 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.020443 # miss rate for ReadReq accesses @@ -174,7 +174,7 @@ system.l2c.ReadReq_miss_rate::cpu0.data 0.042173 # mi system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.005068 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.008110 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.013649 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.071421 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.071420 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.891088 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.869738 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843284 # miss rate for SCUpgradeReq accesses @@ -188,7 +188,7 @@ system.l2c.demand_miss_rate::cpu0.data 0.280600 # mi system.l2c.demand_miss_rate::cpu1.dtb.walker 0.005068 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.itb.walker 0.008110 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.013649 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.257926 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.257925 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002173 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.003236 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.020443 # miss rate for overall accesses @@ -196,7 +196,7 @@ system.l2c.overall_miss_rate::cpu0.data 0.280600 # mi system.l2c.overall_miss_rate::cpu1.dtb.walker 0.005068 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.itb.walker 0.008110 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.013649 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.257926 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.257925 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -216,9 +216,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9339288 # DTB read hits +system.cpu0.dtb.read_hits 9339290 # DTB read hits system.cpu0.dtb.read_misses 5153 # DTB read misses -system.cpu0.dtb.write_hits 6907876 # DTB write hits +system.cpu0.dtb.write_hits 6907877 # DTB write hits system.cpu0.dtb.write_misses 1048 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -229,13 +229,13 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9344441 # DTB read accesses -system.cpu0.dtb.write_accesses 6908924 # DTB write accesses +system.cpu0.dtb.read_accesses 9344443 # DTB read accesses +system.cpu0.dtb.write_accesses 6908925 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 16247164 # DTB hits +system.cpu0.dtb.hits 16247167 # DTB hits system.cpu0.dtb.misses 6201 # DTB misses -system.cpu0.dtb.accesses 16253365 # DTB accesses -system.cpu0.itb.inst_hits 34822552 # ITB inst hits +system.cpu0.dtb.accesses 16253368 # DTB accesses +system.cpu0.itb.inst_hits 34822572 # ITB inst hits system.cpu0.itb.inst_misses 2978 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -252,61 +252,61 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 34825530 # ITB inst accesses -system.cpu0.itb.hits 34822552 # DTB hits +system.cpu0.itb.inst_accesses 34825550 # ITB inst accesses +system.cpu0.itb.hits 34822572 # DTB hits system.cpu0.itb.misses 2978 # DTB misses -system.cpu0.itb.accesses 34825530 # DTB accesses +system.cpu0.itb.accesses 34825550 # DTB accesses system.cpu0.numCycles 4823340800 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 34068103 # Number of instructions committed -system.cpu0.committedOps 44975797 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 39858123 # Number of integer alu accesses +system.cpu0.committedInsts 34068123 # Number of instructions committed +system.cpu0.committedOps 44975817 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 39858141 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4945 # Number of float alu accesses system.cpu0.num_func_calls 1311755 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4652122 # number of instructions that are conditional controls -system.cpu0.num_int_insts 39858123 # number of integer instructions +system.cpu0.num_conditional_control_insts 4519198 # number of instructions that are conditional controls +system.cpu0.num_int_insts 39858141 # number of integer instructions system.cpu0.num_fp_insts 4945 # number of float instructions -system.cpu0.num_int_register_reads 202125744 # number of times the integer registers were read -system.cpu0.num_int_register_writes 42204131 # number of times the integer registers were written +system.cpu0.num_int_register_reads 202125837 # number of times the integer registers were read +system.cpu0.num_int_register_writes 42204153 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3641 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1308 # number of times the floating registers were written -system.cpu0.num_mem_refs 17030946 # number of memory refs -system.cpu0.num_load_insts 9786549 # Number of load instructions -system.cpu0.num_store_insts 7244397 # Number of store instructions -system.cpu0.num_idle_cycles 4777543068.852608 # Number of idle cycles -system.cpu0.num_busy_cycles 45797731.147393 # Number of busy cycles +system.cpu0.num_mem_refs 17030949 # number of memory refs +system.cpu0.num_load_insts 9786551 # Number of load instructions +system.cpu0.num_store_insts 7244398 # Number of store instructions +system.cpu0.num_idle_cycles 4777543048.852804 # Number of idle cycles +system.cpu0.num_busy_cycles 45797751.147196 # Number of busy cycles system.cpu0.not_idle_fraction 0.009495 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.990505 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 59311 # number of quiesce instructions executed system.cpu0.icache.replacements 504460 # number of replacements system.cpu0.icache.tagsinuse 511.627588 # Cycle average of tags in use -system.cpu0.icache.total_refs 34319155 # Total number of references to valid blocks. +system.cpu0.icache.total_refs 34319175 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 504972 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.962491 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 67.962531 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 64519524000 # Cycle when the warmup percentage was hit. system.cpu0.icache.occ_blocks::cpu0.inst 511.627588 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.999273 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.999273 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 34319155 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 34319155 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 34319155 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 34319155 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 34319155 # number of overall hits -system.cpu0.icache.overall_hits::total 34319155 # number of overall hits +system.cpu0.icache.ReadReq_hits::cpu0.inst 34319175 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 34319175 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 34319175 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 34319175 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 34319175 # number of overall hits +system.cpu0.icache.overall_hits::total 34319175 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 504973 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 504973 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 504973 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 504973 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 504973 # number of overall misses system.cpu0.icache.overall_misses::total 504973 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 34824128 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 34824128 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 34824128 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 34824128 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 34824128 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 34824128 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 34824148 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 34824148 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 34824148 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 34824148 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 34824148 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 34824148 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014501 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014501 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014501 # miss rate for overall accesses @@ -323,25 +323,25 @@ system.cpu0.icache.writebacks::total 24728 # nu system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 380107 # number of replacements system.cpu0.dcache.tagsinuse 479.716402 # Cycle average of tags in use -system.cpu0.dcache.total_refs 14708286 # Total number of references to valid blocks. +system.cpu0.dcache.total_refs 14708289 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 380619 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 38.643068 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 38.643076 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.occ_blocks::cpu0.data 479.716402 # Average occupied blocks per requestor system.cpu0.dcache.occ_percent::cpu0.data 0.936946 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.936946 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7803296 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7803296 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 6534059 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 6534059 # number of WriteReq hits +system.cpu0.dcache.ReadReq_hits::cpu0.data 7803298 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7803298 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 6534060 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 6534060 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172314 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 172314 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 174866 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 174866 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 14337355 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 14337355 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 14337355 # number of overall hits -system.cpu0.dcache.overall_hits::total 14337355 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 14337358 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 14337358 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 14337358 # number of overall hits +system.cpu0.dcache.overall_hits::total 14337358 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 237350 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 237350 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 183580 # number of WriteReq misses @@ -354,18 +354,18 @@ system.cpu0.dcache.demand_misses::cpu0.data 420930 # system.cpu0.dcache.demand_misses::total 420930 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 420930 # number of overall misses system.cpu0.dcache.overall_misses::total 420930 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8040646 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8040646 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6717639 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6717639 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8040648 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8040648 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6717640 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6717640 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182192 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 182192 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182159 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 182159 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14758285 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14758285 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14758285 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14758285 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 14758288 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14758288 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14758288 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14758288 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029519 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027328 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054218 # miss rate for LoadLockedReq accesses @@ -385,9 +385,9 @@ system.cpu0.dcache.writebacks::total 339627 # nu system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6258230 # DTB read hits +system.cpu1.dtb.read_hits 6258240 # DTB read hits system.cpu1.dtb.read_misses 2159 # DTB read misses -system.cpu1.dtb.write_hits 4713962 # DTB write hits +system.cpu1.dtb.write_hits 4713968 # DTB write hits system.cpu1.dtb.write_misses 1181 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -398,13 +398,13 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 92 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6260389 # DTB read accesses -system.cpu1.dtb.write_accesses 4715143 # DTB write accesses +system.cpu1.dtb.read_accesses 6260399 # DTB read accesses +system.cpu1.dtb.write_accesses 4715149 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 10972192 # DTB hits +system.cpu1.dtb.hits 10972208 # DTB hits system.cpu1.dtb.misses 3340 # DTB misses -system.cpu1.dtb.accesses 10975532 # DTB accesses -system.cpu1.itb.inst_hits 27739434 # ITB inst hits +system.cpu1.dtb.accesses 10975548 # DTB accesses +system.cpu1.itb.inst_hits 27739473 # ITB inst hits system.cpu1.itb.inst_misses 1388 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -421,61 +421,61 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 27740822 # ITB inst accesses -system.cpu1.itb.hits 27739434 # DTB hits +system.cpu1.itb.inst_accesses 27740861 # ITB inst accesses +system.cpu1.itb.hits 27739473 # DTB hits system.cpu1.itb.misses 1388 # DTB misses -system.cpu1.itb.accesses 27740822 # DTB accesses +system.cpu1.itb.accesses 27740861 # DTB accesses system.cpu1.numCycles 4822838236 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 27478895 # Number of instructions committed -system.cpu1.committedOps 34587691 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 30998246 # Number of integer alu accesses +system.cpu1.committedInsts 27478934 # Number of instructions committed +system.cpu1.committedOps 34587730 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 30998282 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5772 # Number of float alu accesses system.cpu1.num_func_calls 758024 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3438794 # number of instructions that are conditional controls -system.cpu1.num_int_insts 30998246 # number of integer instructions +system.cpu1.num_conditional_control_insts 3403316 # number of instructions that are conditional controls +system.cpu1.num_int_insts 30998282 # number of integer instructions system.cpu1.num_fp_insts 5772 # number of float instructions -system.cpu1.num_int_register_reads 156835040 # number of times the integer registers were read -system.cpu1.num_int_register_writes 33469179 # number of times the integer registers were written +system.cpu1.num_int_register_reads 156835224 # number of times the integer registers were read +system.cpu1.num_int_register_writes 33469234 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3980 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1792 # number of times the floating registers were written -system.cpu1.num_mem_refs 11415835 # number of memory refs -system.cpu1.num_load_insts 6478994 # Number of load instructions -system.cpu1.num_store_insts 4936841 # Number of store instructions -system.cpu1.num_idle_cycles 4787960178.177661 # Number of idle cycles -system.cpu1.num_busy_cycles 34878057.822339 # Number of busy cycles +system.cpu1.num_mem_refs 11415851 # number of memory refs +system.cpu1.num_load_insts 6479004 # Number of load instructions +system.cpu1.num_store_insts 4936847 # Number of store instructions +system.cpu1.num_idle_cycles 4787960139.182108 # Number of idle cycles +system.cpu1.num_busy_cycles 34878096.817892 # Number of busy cycles system.cpu1.not_idle_fraction 0.007232 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.992768 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 33011 # number of quiesce instructions executed -system.cpu1.icache.replacements 374406 # number of replacements +system.cpu1.icache.replacements 374408 # number of replacements system.cpu1.icache.tagsinuse 498.143079 # Cycle average of tags in use -system.cpu1.icache.total_refs 27365572 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 374918 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 72.990819 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 69956143000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.total_refs 27365609 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 374920 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 72.990529 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 69956153000 # Cycle when the warmup percentage was hit. system.cpu1.icache.occ_blocks::cpu1.inst 498.143079 # Average occupied blocks per requestor system.cpu1.icache.occ_percent::cpu1.inst 0.972936 # Average percentage of cache occupancy system.cpu1.icache.occ_percent::total 0.972936 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 27365572 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 27365572 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 27365572 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 27365572 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 27365572 # number of overall hits -system.cpu1.icache.overall_hits::total 27365572 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 374920 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 374920 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 374920 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 374920 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 374920 # number of overall misses -system.cpu1.icache.overall_misses::total 374920 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 27740492 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 27740492 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 27740492 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 27740492 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 27740492 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 27740492 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 27365609 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 27365609 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 27365609 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 27365609 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 27365609 # number of overall hits +system.cpu1.icache.overall_hits::total 27365609 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 374922 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 374922 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 374922 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 374922 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 374922 # number of overall misses +system.cpu1.icache.overall_misses::total 374922 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 27740531 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 27740531 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 27740531 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 27740531 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 27740531 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 27740531 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013515 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013515 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013515 # miss rate for overall accesses @@ -490,52 +490,52 @@ system.cpu1.icache.cache_copies 0 # nu system.cpu1.icache.writebacks::writebacks 13905 # number of writebacks system.cpu1.icache.writebacks::total 13905 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 247434 # number of replacements -system.cpu1.dcache.tagsinuse 444.903488 # Cycle average of tags in use -system.cpu1.dcache.total_refs 9876826 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 247805 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 39.857251 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 69253206000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 444.903488 # Average occupied blocks per requestor +system.cpu1.dcache.replacements 247435 # number of replacements +system.cpu1.dcache.tagsinuse 444.903487 # Cycle average of tags in use +system.cpu1.dcache.total_refs 9876841 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 247806 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 39.857150 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 69253216000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 444.903487 # Average occupied blocks per requestor system.cpu1.dcache.occ_percent::cpu1.data 0.868952 # Average percentage of cache occupancy system.cpu1.dcache.occ_percent::total 0.868952 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 5955973 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 5955973 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3777038 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3777038 # number of WriteReq hits +system.cpu1.dcache.ReadReq_hits::cpu1.data 5955982 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 5955982 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3777044 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3777044 # number of WriteReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 59593 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 59593 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 60090 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 60090 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 9733011 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 9733011 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 9733011 # number of overall hits -system.cpu1.dcache.overall_hits::total 9733011 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 165799 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 165799 # number of ReadReq misses +system.cpu1.dcache.demand_hits::cpu1.data 9733026 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 9733026 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 9733026 # number of overall hits +system.cpu1.dcache.overall_hits::total 9733026 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 165800 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 165800 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 111467 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 111467 # number of WriteReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10725 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 10725 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10198 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 10198 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 277266 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 277266 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 277266 # number of overall misses -system.cpu1.dcache.overall_misses::total 277266 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 6121772 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 6121772 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3888505 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3888505 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.demand_misses::cpu1.data 277267 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 277267 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 277267 # number of overall misses +system.cpu1.dcache.overall_misses::total 277267 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 6121782 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 6121782 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3888511 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3888511 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 70318 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 70318 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 70288 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 70288 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 10010277 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 10010277 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 10010277 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 10010277 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027083 # miss rate for ReadReq accesses +system.cpu1.dcache.demand_accesses::cpu1.data 10010293 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 10010293 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 10010293 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 10010293 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027084 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028666 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152521 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.145089 # miss rate for StoreCondReq accesses @@ -549,8 +549,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 202201 # number of writebacks -system.cpu1.dcache.writebacks::total 202201 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 202202 # number of writebacks +system.cpu1.dcache.writebacks::total 202202 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 6cc3c2484..81760af9f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -192,7 +192,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] @@ -286,7 +286,7 @@ port=system.membus.master[2] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -526,13 +526,16 @@ proc_id1=201327138 system=system pio=system.iobus.master[1] -[system.realview.rtc_fake] -type=AmbaFake -amba_id=266289 -ignore_access=false +[system.realview.rtc] +type=PL031 +amba_id=3412017 +gic=system.realview.gic +int_delay=100000 +int_num=42 pio_addr=268529664 pio_latency=1000 system=system +time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[23] [system.realview.sci_fake] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index 32fe1f3d3..60dab884c 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,13 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 08:32:03 -gem5 started Mar 9 2012 08:33:32 +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 16:34:16 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -The currently selected ARM platforms doesn't support - the amount of DRAM you've selected. Please try - another platform +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 86fb980a7..c2b68c5b8 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,13 +4,13 @@ sim_seconds 2.332317 # Nu sim_ticks 2332316587000 # Number of ticks simulated final_tick 2332316587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1979884 # Simulator instruction rate (inst/s) -host_op_rate 2556849 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 77919104565 # Simulator tick rate (ticks/s) -host_mem_usage 379864 # Number of bytes of host memory used -host_seconds 29.93 # Real time elapsed on the host -sim_insts 59262876 # Number of instructions simulated -sim_ops 76532931 # Number of ops (including micro ops) simulated +host_inst_rate 1994377 # Simulator instruction rate (inst/s) +host_op_rate 2575566 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78489486028 # Simulator tick rate (ticks/s) +host_mem_usage 377288 # Number of bytes of host memory used +host_seconds 29.72 # Real time elapsed on the host +sim_insts 59262896 # Number of instructions simulated +sim_ops 76532951 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -31,16 +31,16 @@ system.physmem.bw_inst_read 403582 # In system.physmem.bw_write 4106561 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total 56699565 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 116822 # number of replacements -system.l2c.tagsinuse 24240.388378 # Cycle average of tags in use +system.l2c.tagsinuse 24240.388395 # Cycle average of tags in use system.l2c.total_refs 1520830 # Total number of references to valid blocks. system.l2c.sampled_refs 146847 # Sample count of references to valid blocks. system.l2c.avg_refs 10.356562 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 13639.466210 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 13639.466229 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.dtb.walker 7.864412 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.itb.walker 1.966419 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.inst 5246.411267 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5344.680069 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 5344.680068 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.208122 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.dtb.walker 0.000120 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000030 # Average percentage of cache occupancy @@ -141,9 +141,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14940566 # DTB read hits +system.cpu.dtb.read_hits 14940568 # DTB read hits system.cpu.dtb.read_misses 7288 # DTB read misses -system.cpu.dtb.write_hits 11198205 # DTB write hits +system.cpu.dtb.write_hits 11198206 # DTB write hits system.cpu.dtb.write_misses 2199 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -154,13 +154,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 14947854 # DTB read accesses -system.cpu.dtb.write_accesses 11200404 # DTB write accesses +system.cpu.dtb.read_accesses 14947856 # DTB read accesses +system.cpu.dtb.write_accesses 11200405 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26138771 # DTB hits +system.cpu.dtb.hits 26138774 # DTB hits system.cpu.dtb.misses 9487 # DTB misses -system.cpu.dtb.accesses 26148258 # DTB accesses -system.cpu.itb.inst_hits 60273889 # ITB inst hits +system.cpu.dtb.accesses 26148261 # DTB accesses +system.cpu.itb.inst_hits 60273909 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -177,61 +177,61 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 60278360 # ITB inst accesses -system.cpu.itb.hits 60273889 # DTB hits +system.cpu.itb.inst_accesses 60278380 # ITB inst accesses +system.cpu.itb.hits 60273909 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 60278360 # DTB accesses +system.cpu.itb.accesses 60278380 # DTB accesses system.cpu.numCycles 4664556206 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 59262876 # Number of instructions committed -system.cpu.committedOps 76532931 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68161177 # Number of integer alu accesses +system.cpu.committedInsts 59262896 # Number of instructions committed +system.cpu.committedOps 76532951 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68161195 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses system.cpu.num_func_calls 1971944 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7793824 # number of instructions that are conditional controls -system.cpu.num_int_insts 68161177 # number of integer instructions +system.cpu.num_conditional_control_insts 7636089 # number of instructions that are conditional controls +system.cpu.num_int_insts 68161195 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 345365607 # number of times the integer registers were read -system.cpu.num_int_register_writes 72877692 # number of times the integer registers were written +system.cpu.num_int_register_reads 345365700 # number of times the integer registers were read +system.cpu.num_int_register_writes 72877714 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27310784 # number of memory refs -system.cpu.num_load_insts 15607074 # Number of load instructions -system.cpu.num_store_insts 11703710 # Number of store instructions -system.cpu.num_idle_cycles 4586920150.977920 # Number of idle cycles -system.cpu.num_busy_cycles 77636055.022080 # Number of busy cycles +system.cpu.num_mem_refs 27310787 # number of memory refs +system.cpu.num_load_insts 15607076 # Number of load instructions +system.cpu.num_store_insts 11703711 # Number of store instructions +system.cpu.num_idle_cycles 4586920130.978250 # Number of idle cycles +system.cpu.num_busy_cycles 77636075.021750 # Number of busy cycles system.cpu.not_idle_fraction 0.016644 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983356 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 82751 # number of quiesce instructions executed system.cpu.icache.replacements 847054 # number of replacements system.cpu.icache.tagsinuse 511.678552 # Cycle average of tags in use -system.cpu.icache.total_refs 59429083 # Total number of references to valid blocks. +system.cpu.icache.total_refs 59429103 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 847566 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.117351 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 5705452000 # Cycle when the warmup percentage was hit. +system.cpu.icache.avg_refs 70.117375 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 5705462000 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 511.678552 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 59429083 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59429083 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59429083 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59429083 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59429083 # number of overall hits -system.cpu.icache.overall_hits::total 59429083 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 59429103 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59429103 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59429103 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59429103 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59429103 # number of overall hits +system.cpu.icache.overall_hits::total 59429103 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 847566 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 847566 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 847566 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 847566 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 847566 # number of overall misses system.cpu.icache.overall_misses::total 847566 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 60276649 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60276649 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60276649 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60276649 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60276649 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60276649 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 60276669 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60276669 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60276669 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60276669 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60276669 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60276669 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014061 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.014061 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.014061 # miss rate for overall accesses @@ -248,25 +248,25 @@ system.cpu.icache.writebacks::total 44721 # nu system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 622134 # number of replacements system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use -system.cpu.dcache.total_refs 23580069 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 23580072 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 622646 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.870747 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 37.870752 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13150366 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13150366 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9943631 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9943631 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 13150368 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13150368 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9943632 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9943632 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 235999 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 235999 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247136 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247136 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23093997 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23093997 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23093997 # number of overall hits -system.cpu.dcache.overall_hits::total 23093997 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 23094000 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23094000 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23094000 # number of overall hits +system.cpu.dcache.overall_hits::total 23094000 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 364548 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 364548 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 249897 # number of WriteReq misses @@ -277,18 +277,18 @@ system.cpu.dcache.demand_misses::cpu.data 614445 # n system.cpu.dcache.demand_misses::total 614445 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 614445 # number of overall misses system.cpu.dcache.overall_misses::total 614445 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13514914 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13514914 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10193528 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10193528 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 13514916 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13514916 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10193529 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10193529 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247137 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247137 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247136 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247136 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23708442 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23708442 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23708442 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23708442 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 23708445 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23708445 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23708445 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23708445 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026974 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024515 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045068 # miss rate for LoadLockedReq accesses diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 266856004..d4b7d32fd 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -300,7 +300,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] @@ -394,7 +394,7 @@ port=system.membus.master[2] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -634,13 +634,16 @@ proc_id1=201327138 system=system pio=system.iobus.master[1] -[system.realview.rtc_fake] -type=AmbaFake -amba_id=266289 -ignore_access=false +[system.realview.rtc] +type=PL031 +amba_id=3412017 +gic=system.realview.gic +int_delay=100000 +int_num=42 pio_addr=268529664 pio_latency=1000 system=system +time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[23] [system.realview.sci_fake] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index cdc402d36..79a5c7d79 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,13 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 08:32:03 -gem5 started Mar 9 2012 08:33:32 +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 16:36:56 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -The currently selected ARM platforms doesn't support - the amount of DRAM you've selected. Please try - another platform +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index a94cfdfbd..ed51beca1 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -4,13 +4,13 @@ sim_seconds 2.669611 # Nu sim_ticks 2669611225000 # Number of ticks simulated final_tick 2669611225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 888599 # Simulator instruction rate (inst/s) -host_op_rate 1136769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38701401221 # Simulator tick rate (ticks/s) -host_mem_usage 381720 # Number of bytes of host memory used -host_seconds 68.98 # Real time elapsed on the host -sim_insts 61295262 # Number of instructions simulated -sim_ops 78413959 # Number of ops (including micro ops) simulated +host_inst_rate 887100 # Simulator instruction rate (inst/s) +host_op_rate 1134851 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38636092154 # Simulator tick rate (ticks/s) +host_mem_usage 379132 # Number of bytes of host memory used +host_seconds 69.10 # Real time elapsed on the host +sim_insts 61295282 # Number of instructions simulated +sim_ops 78413979 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -31,20 +31,20 @@ system.physmem.bw_inst_read 375905 # In system.physmem.bw_write 3818629 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total 54138623 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 127749 # number of replacements -system.l2c.tagsinuse 26172.513439 # Cycle average of tags in use -system.l2c.total_refs 1540412 # Total number of references to valid blocks. +system.l2c.tagsinuse 26172.513447 # Cycle average of tags in use +system.l2c.total_refs 1540413 # Total number of references to valid blocks. system.l2c.sampled_refs 157158 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.801677 # Average number of references to valid blocks. +system.l2c.avg_refs 9.801684 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 15197.869059 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 15197.869082 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 8.069070 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.114155 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2680.486069 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3670.979885 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 2680.486070 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3670.979881 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.dtb.walker 0.091092 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.itb.walker 0.000002 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2441.904066 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2173.000042 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2441.904061 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2173.000034 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.231901 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000123 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy @@ -57,13 +57,13 @@ system.l2c.occ_percent::cpu1.data 0.033157 # Av system.l2c.occ_percent::total 0.399361 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.dtb.walker 4237 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 1502 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 371106 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 371107 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 191753 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 4185 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 1874 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 499097 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 157046 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1230800 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1230801 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 589400 # number of Writeback hits system.l2c.Writeback_hits::total 589400 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 1143 # number of UpgradeReq hits @@ -77,22 +77,22 @@ system.l2c.ReadExReq_hits::cpu1.data 58554 # nu system.l2c.ReadExReq_hits::total 101060 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 4237 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 1502 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 371106 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 371107 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 234259 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 4185 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 1874 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 499097 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 215600 # number of demand (read+write) hits -system.l2c.demand_hits::total 1331860 # number of demand (read+write) hits +system.l2c.demand_hits::total 1331861 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 4237 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 1502 # number of overall hits -system.l2c.overall_hits::cpu0.inst 371106 # number of overall hits +system.l2c.overall_hits::cpu0.inst 371107 # number of overall hits system.l2c.overall_hits::cpu0.data 234259 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 4185 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 1874 # number of overall hits system.l2c.overall_hits::cpu1.inst 499097 # number of overall hits system.l2c.overall_hits::cpu1.data 215600 # number of overall hits -system.l2c.overall_hits::total 1331860 # number of overall hits +system.l2c.overall_hits::total 1331861 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 24 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 14 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.inst 7728 # number of ReadReq misses @@ -167,13 +167,13 @@ system.l2c.overall_miss_latency::cpu1.data 3132782000 # system.l2c.overall_miss_latency::total 9564047500 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 4261 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 1516 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 378834 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 378835 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 202680 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 4193 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 1878 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 506630 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 165547 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1265539 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1265540 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 589400 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 589400 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 4658 # number of UpgradeReq accesses(hits+misses) @@ -187,22 +187,22 @@ system.l2c.ReadExReq_accesses::cpu1.data 110078 # nu system.l2c.ReadExReq_accesses::total 249908 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 4261 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 1516 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 378834 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 378835 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 342510 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 4193 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 1878 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 506630 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 275625 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1515447 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1515448 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 4261 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 1516 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 378834 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 378835 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 342510 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 4193 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 1878 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 506630 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 275625 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1515447 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1515448 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.005632 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.009235 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.020399 # miss rate for ReadReq accesses @@ -494,7 +494,7 @@ system.cpu0.committedOps 43969024 # Nu system.cpu0.num_int_alu_accesses 39881498 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4107 # Number of float alu accesses system.cpu0.num_func_calls 977479 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4566516 # number of instructions that are conditional controls +system.cpu0.num_conditional_control_insts 4455595 # number of instructions that are conditional controls system.cpu0.num_int_insts 39881498 # number of integer instructions system.cpu0.num_fp_insts 4107 # number of float instructions system.cpu0.num_int_register_reads 225043856 # number of times the integer registers were read @@ -504,39 +504,39 @@ system.cpu0.num_fp_register_writes 256 # nu system.cpu0.num_mem_refs 14677999 # number of memory refs system.cpu0.num_load_insts 8148547 # Number of load instructions system.cpu0.num_store_insts 6529452 # Number of store instructions -system.cpu0.num_idle_cycles 5107410781.564784 # Number of idle cycles -system.cpu0.num_busy_cycles 230394434.435216 # Number of busy cycles +system.cpu0.num_idle_cycles 5107410767.568501 # Number of idle cycles +system.cpu0.num_busy_cycles 230394448.431500 # Number of busy cycles system.cpu0.not_idle_fraction 0.043163 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.956837 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 38525 # number of quiesce instructions executed -system.cpu0.icache.replacements 380069 # number of replacements +system.cpu0.icache.replacements 380070 # number of replacements system.cpu0.icache.tagsinuse 510.849663 # Cycle average of tags in use -system.cpu0.icache.total_refs 35367311 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 380581 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 92.929786 # Average number of references to valid blocks. +system.cpu0.icache.total_refs 35367310 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 380582 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 92.929539 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 74921716000 # Cycle when the warmup percentage was hit. system.cpu0.icache.occ_blocks::cpu0.inst 510.849663 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.997753 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.997753 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 35367311 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 35367311 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 35367311 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 35367311 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 35367311 # number of overall hits -system.cpu0.icache.overall_hits::total 35367311 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 380583 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 380583 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 380583 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 380583 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 380583 # number of overall misses -system.cpu0.icache.overall_misses::total 380583 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5651439000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5651439000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5651439000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5651439000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5651439000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5651439000 # number of overall miss cycles +system.cpu0.icache.ReadReq_hits::cpu0.inst 35367310 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 35367310 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 35367310 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 35367310 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 35367310 # number of overall hits +system.cpu0.icache.overall_hits::total 35367310 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 380584 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 380584 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 380584 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 380584 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 380584 # number of overall misses +system.cpu0.icache.overall_misses::total 380584 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5651447000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5651447000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5651447000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5651447000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5651447000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5651447000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 35747894 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 35747894 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 35747894 # number of demand (read+write) accesses @@ -546,9 +546,9 @@ system.cpu0.icache.overall_accesses::total 35747894 # system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010646 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010646 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010646 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14849.425749 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14849.425749 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14849.425749 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14849.407752 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14849.407752 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14849.407752 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -559,18 +559,18 @@ system.cpu0.icache.fast_writes 0 # nu system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 12960 # number of writebacks system.cpu0.icache.writebacks::total 12960 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 380583 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 380583 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 380583 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 380583 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 380583 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 380583 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4509188500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4509188500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4509188500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4509188500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4509188500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4509188500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 380584 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 380584 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 380584 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 380584 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 380584 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 380584 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4509193500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4509193500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4509193500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4509193500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4509193500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4509193500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles @@ -578,19 +578,19 @@ system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11848.108034 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11848.108034 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11848.108034 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11848.090041 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11848.090041 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11848.090041 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 334596 # number of replacements -system.cpu0.dcache.tagsinuse 450.118381 # Cycle average of tags in use +system.cpu0.dcache.tagsinuse 450.118379 # Cycle average of tags in use system.cpu0.dcache.total_refs 12875674 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 335004 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 38.434389 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 450.118381 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu0.data 450.118379 # Average occupied blocks per requestor system.cpu0.dcache.occ_percent::cpu0.data 0.879137 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.879137 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 7428609 # number of ReadReq hits @@ -714,9 +714,9 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7762496 # DTB read hits +system.cpu1.dtb.read_hits 7762498 # DTB read hits system.cpu1.dtb.read_misses 5432 # DTB read misses -system.cpu1.dtb.write_hits 5411648 # DTB write hits +system.cpu1.dtb.write_hits 5411649 # DTB write hits system.cpu1.dtb.write_misses 1096 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -727,13 +727,13 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 166 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 261 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7767928 # DTB read accesses -system.cpu1.dtb.write_accesses 5412744 # DTB write accesses +system.cpu1.dtb.read_accesses 7767930 # DTB read accesses +system.cpu1.dtb.write_accesses 5412745 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13174144 # DTB hits +system.cpu1.dtb.hits 13174147 # DTB hits system.cpu1.dtb.misses 6528 # DTB misses -system.cpu1.dtb.accesses 13180672 # DTB accesses -system.cpu1.itb.inst_hits 26848280 # ITB inst hits +system.cpu1.dtb.accesses 13180675 # DTB accesses +system.cpu1.itb.inst_hits 26848300 # ITB inst hits system.cpu1.itb.inst_misses 3154 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -750,73 +750,73 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 26851434 # ITB inst accesses -system.cpu1.itb.hits 26848280 # DTB hits +system.cpu1.itb.inst_accesses 26851454 # ITB inst accesses +system.cpu1.itb.hits 26848300 # DTB hits system.cpu1.itb.misses 3154 # DTB misses -system.cpu1.itb.accesses 26851434 # DTB accesses +system.cpu1.itb.accesses 26851454 # DTB accesses system.cpu1.numCycles 5339222450 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 25921760 # Number of instructions committed -system.cpu1.committedOps 34444935 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 31033253 # Number of integer alu accesses +system.cpu1.committedInsts 25921780 # Number of instructions committed +system.cpu1.committedOps 34444955 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 31033271 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5714 # Number of float alu accesses system.cpu1.num_func_calls 1093852 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3529915 # number of instructions that are conditional controls -system.cpu1.num_int_insts 31033253 # number of integer instructions +system.cpu1.num_conditional_control_insts 3472619 # number of instructions that are conditional controls +system.cpu1.num_int_insts 31033271 # number of integer instructions system.cpu1.num_fp_insts 5714 # number of float instructions -system.cpu1.num_int_register_reads 181157193 # number of times the integer registers were read -system.cpu1.num_int_register_writes 32585304 # number of times the integer registers were written +system.cpu1.num_int_register_reads 181157292 # number of times the integer registers were read +system.cpu1.num_int_register_writes 32585326 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3770 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1948 # number of times the floating registers were written -system.cpu1.num_mem_refs 13796843 # number of memory refs -system.cpu1.num_load_insts 8139019 # Number of load instructions -system.cpu1.num_store_insts 5657824 # Number of store instructions -system.cpu1.num_idle_cycles 4950307250.068146 # Number of idle cycles -system.cpu1.num_busy_cycles 388915199.931854 # Number of busy cycles +system.cpu1.num_mem_refs 13796846 # number of memory refs +system.cpu1.num_load_insts 8139021 # Number of load instructions +system.cpu1.num_store_insts 5657825 # Number of store instructions +system.cpu1.num_idle_cycles 4950307196.068146 # Number of idle cycles +system.cpu1.num_busy_cycles 388915253.931854 # Number of busy cycles system.cpu1.not_idle_fraction 0.072841 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.927159 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 53838 # number of quiesce instructions executed system.cpu1.icache.replacements 508221 # number of replacements system.cpu1.icache.tagsinuse 497.375159 # Cycle average of tags in use -system.cpu1.icache.total_refs 26339543 # Total number of references to valid blocks. +system.cpu1.icache.total_refs 26339563 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 508733 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 51.774788 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 51.774827 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 191336880000 # Cycle when the warmup percentage was hit. system.cpu1.icache.occ_blocks::cpu1.inst 497.375159 # Average occupied blocks per requestor system.cpu1.icache.occ_percent::cpu1.inst 0.971436 # Average percentage of cache occupancy system.cpu1.icache.occ_percent::total 0.971436 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 26339543 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 26339543 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 26339543 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 26339543 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 26339543 # number of overall hits -system.cpu1.icache.overall_hits::total 26339543 # number of overall hits +system.cpu1.icache.ReadReq_hits::cpu1.inst 26339563 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 26339563 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 26339563 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 26339563 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 26339563 # number of overall hits +system.cpu1.icache.overall_hits::total 26339563 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 508733 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 508733 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 508733 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 508733 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 508733 # number of overall misses system.cpu1.icache.overall_misses::total 508733 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7436442000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7436442000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7436442000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7436442000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7436442000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7436442000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 26848276 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 26848276 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 26848276 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 26848276 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 26848276 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 26848276 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7436443000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7436443000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7436443000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7436443000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7436443000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7436443000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 26848296 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 26848296 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 26848296 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 26848296 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 26848296 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 26848296 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018948 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018948 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018948 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14617.573462 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14617.573462 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14617.573462 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14617.575428 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14617.575428 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14617.575428 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -833,12 +833,12 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 508733 system.cpu1.icache.demand_mshr_misses::total 508733 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 508733 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 508733 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5908060000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5908060000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5908060000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5908060000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5908060000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5908060000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5908061000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5908061000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5908061000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5908061000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5908061000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5908061000 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles @@ -846,33 +846,33 @@ system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11613.282409 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11613.282409 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11613.282409 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11613.284375 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11613.284375 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11613.284375 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 295754 # number of replacements -system.cpu1.dcache.tagsinuse 467.166427 # Cycle average of tags in use -system.cpu1.dcache.total_refs 11737107 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 467.166428 # Cycle average of tags in use +system.cpu1.dcache.total_refs 11737110 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 296266 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 39.616787 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 39.616797 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 75924171000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 467.166427 # Average occupied blocks per requestor +system.cpu1.dcache.occ_blocks::cpu1.data 467.166428 # Average occupied blocks per requestor system.cpu1.dcache.occ_percent::cpu1.data 0.912434 # Average percentage of cache occupancy system.cpu1.dcache.occ_percent::total 0.912434 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 6345290 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6345290 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 5152610 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 5152610 # number of WriteReq hits +system.cpu1.dcache.ReadReq_hits::cpu1.data 6345292 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6345292 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 5152611 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 5152611 # number of WriteReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 104795 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 104795 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 106403 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 106403 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11497900 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11497900 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11497900 # number of overall hits -system.cpu1.dcache.overall_hits::total 11497900 # number of overall hits +system.cpu1.dcache.demand_hits::cpu1.data 11497903 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11497903 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11497903 # number of overall hits +system.cpu1.dcache.overall_hits::total 11497903 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 188245 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 188245 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 137493 # number of WriteReq misses @@ -885,42 +885,42 @@ system.cpu1.dcache.demand_misses::cpu1.data 325738 # system.cpu1.dcache.demand_misses::total 325738 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 325738 # number of overall misses system.cpu1.dcache.overall_misses::total 325738 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2729023500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2729023500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2729025500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2729025500 # number of ReadReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4123985000 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 4123985000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131721000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 131721000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131720000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 131720000 # number of LoadLockedReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 82493000 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::total 82493000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6853008500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6853008500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6853008500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6853008500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 6533535 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 6533535 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5290103 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5290103 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.demand_miss_latency::cpu1.data 6853010500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6853010500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6853010500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6853010500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 6533537 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 6533537 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5290104 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5290104 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 116352 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 116352 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 116309 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 116309 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 11823638 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11823638 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 11823638 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11823638 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 11823641 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11823641 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 11823641 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 11823641 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.028812 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025991 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099328 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085170 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027550 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027550 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14497.189832 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14497.200457 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 29994.145156 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11397.508004 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11397.421476 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8327.579245 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21038.406634 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21038.406634 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21038.412773 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21038.412773 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -943,36 +943,36 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 325738 system.cpu1.dcache.demand_mshr_misses::total 325738 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 325738 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 325738 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2164153000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2164153000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2164155000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2164155000 # number of ReadReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3711466500 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3711466500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 97050000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 97050000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 97049000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 97049000 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52793000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52793000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5875619500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5875619500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5875619500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5875619500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137931975000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137931975000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 470526000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 470526000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 138402501000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 138402501000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5875621500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5875621500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5875621500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5875621500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137931976000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137931976000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 470527000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 470527000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 138402503000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 138402503000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028812 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025991 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099328 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085118 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027550 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027550 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11496.470026 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11496.480650 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26993.857869 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8397.508004 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8397.421476 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5332.626263 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18037.869392 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18037.869392 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18037.875532 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18037.875532 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 064eb9907..cb6ee4aa9 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -189,7 +189,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] @@ -283,7 +283,7 @@ port=system.membus.master[2] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -523,13 +523,16 @@ proc_id1=201327138 system=system pio=system.iobus.master[1] -[system.realview.rtc_fake] -type=AmbaFake -amba_id=266289 -ignore_access=false +[system.realview.rtc] +type=PL031 +amba_id=3412017 +gic=system.realview.gic +int_delay=100000 +int_num=42 pio_addr=268529664 pio_latency=1000 system=system +time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[23] [system.realview.sci_fake] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index c88a5bef6..1758a0df6 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,13 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 08:32:03 -gem5 started Mar 9 2012 08:33:32 +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 16:35:38 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -The currently selected ARM platforms doesn't support - the amount of DRAM you've selected. Please try - another platform +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index e62e718fc..2c94df23b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,13 +4,13 @@ sim_seconds 2.591442 # Nu sim_ticks 2591441692000 # Number of ticks simulated final_tick 2591441692000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 886915 # Simulator instruction rate (inst/s) -host_op_rate 1133159 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38905818967 # Simulator tick rate (ticks/s) -host_mem_usage 380156 # Number of bytes of host memory used -host_seconds 66.61 # Real time elapsed on the host -sim_insts 59075683 # Number of instructions simulated -sim_ops 75477515 # Number of ops (including micro ops) simulated +host_inst_rate 879685 # Simulator instruction rate (inst/s) +host_op_rate 1123921 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38588641896 # Simulator tick rate (ticks/s) +host_mem_usage 377580 # Number of bytes of host memory used +host_seconds 67.16 # Real time elapsed on the host +sim_insts 59075703 # Number of instructions simulated +sim_ops 75477535 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -31,22 +31,22 @@ system.physmem.bw_inst_read 366560 # In system.physmem.bw_write 3717742 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total 55293438 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 117809 # number of replacements -system.l2c.tagsinuse 24928.376904 # Cycle average of tags in use -system.l2c.total_refs 1535240 # Total number of references to valid blocks. +system.l2c.tagsinuse 24929.234619 # Cycle average of tags in use +system.l2c.total_refs 1535239 # Total number of references to valid blocks. system.l2c.sampled_refs 146709 # Sample count of references to valid blocks. -system.l2c.avg_refs 10.464525 # Average number of references to valid blocks. +system.l2c.avg_refs 10.464518 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 14588.908220 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 14588.908290 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.dtb.walker 6.963925 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.itb.walker 0.970411 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 5158.445831 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5173.088517 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 5159.303507 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 5173.088486 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.222609 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.dtb.walker 0.000106 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.078712 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.078725 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.data 0.078935 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.380377 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.380390 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu.dtb.walker 8825 # number of ReadReq hits system.l2c.ReadReq_hits::cpu.itb.walker 3670 # number of ReadReq hits system.l2c.ReadReq_hits::cpu.inst 837469 # number of ReadReq hits @@ -253,9 +253,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14970647 # DTB read hits +system.cpu.dtb.read_hits 14970649 # DTB read hits system.cpu.dtb.read_misses 7343 # DTB read misses -system.cpu.dtb.write_hits 11215605 # DTB write hits +system.cpu.dtb.write_hits 11215606 # DTB write hits system.cpu.dtb.write_misses 2208 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -266,13 +266,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 183 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 14977990 # DTB read accesses -system.cpu.dtb.write_accesses 11217813 # DTB write accesses +system.cpu.dtb.read_accesses 14977992 # DTB read accesses +system.cpu.dtb.write_accesses 11217814 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26186252 # DTB hits +system.cpu.dtb.hits 26186255 # DTB hits system.cpu.dtb.misses 9551 # DTB misses -system.cpu.dtb.accesses 26195803 # DTB accesses -system.cpu.itb.inst_hits 60357722 # ITB inst hits +system.cpu.dtb.accesses 26195806 # DTB accesses +system.cpu.itb.inst_hits 60357742 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -289,49 +289,49 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 60362193 # ITB inst accesses -system.cpu.itb.hits 60357722 # DTB hits +system.cpu.itb.inst_accesses 60362213 # ITB inst accesses +system.cpu.itb.hits 60357742 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 60362193 # DTB accesses +system.cpu.itb.accesses 60362213 # DTB accesses system.cpu.numCycles 5182883384 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 59075683 # Number of instructions committed -system.cpu.committedOps 75477515 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68255270 # Number of integer alu accesses +system.cpu.committedInsts 59075703 # Number of instructions committed +system.cpu.committedOps 75477535 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68255288 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses system.cpu.num_func_calls 1975579 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7801778 # number of instructions that are conditional controls -system.cpu.num_int_insts 68255270 # number of integer instructions +system.cpu.num_conditional_control_insts 7643992 # number of instructions that are conditional controls +system.cpu.num_int_insts 68255288 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 390835391 # number of times the integer registers were read -system.cpu.num_int_register_writes 72984158 # number of times the integer registers were written +system.cpu.num_int_register_reads 390835490 # number of times the integer registers were read +system.cpu.num_int_register_writes 72984180 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27351734 # number of memory refs -system.cpu.num_load_insts 15632521 # Number of load instructions -system.cpu.num_store_insts 11719213 # Number of store instructions -system.cpu.num_idle_cycles 4574345772.482235 # Number of idle cycles -system.cpu.num_busy_cycles 608537611.517765 # Number of busy cycles +system.cpu.num_mem_refs 27351737 # number of memory refs +system.cpu.num_load_insts 15632523 # Number of load instructions +system.cpu.num_store_insts 11719214 # Number of store instructions +system.cpu.num_idle_cycles 4574345726.482235 # Number of idle cycles +system.cpu.num_busy_cycles 608537657.517765 # Number of busy cycles system.cpu.not_idle_fraction 0.117413 # Percentage of non-idle cycles system.cpu.idle_fraction 0.882587 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 82953 # number of quiesce instructions executed system.cpu.icache.replacements 852971 # number of replacements system.cpu.icache.tagsinuse 510.943281 # Cycle average of tags in use -system.cpu.icache.total_refs 59504239 # Total number of references to valid blocks. +system.cpu.icache.total_refs 59504259 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 853483 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 69.719302 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18512998000 # Cycle when the warmup percentage was hit. +system.cpu.icache.avg_refs 69.719325 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 18513021000 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 510.943281 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.997936 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.997936 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 59504239 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59504239 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59504239 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59504239 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59504239 # number of overall hits -system.cpu.icache.overall_hits::total 59504239 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 59504259 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59504259 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59504259 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59504259 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59504259 # number of overall hits +system.cpu.icache.overall_hits::total 59504259 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 853483 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 853483 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 853483 # number of demand (read+write) misses @@ -344,12 +344,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 12547128000 system.cpu.icache.demand_miss_latency::total 12547128000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 12547128000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 12547128000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 60357722 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60357722 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60357722 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60357722 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60357722 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60357722 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 60357742 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60357742 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60357742 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60357742 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60357742 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60357742 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014140 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.014140 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.014140 # miss rate for overall accesses @@ -393,25 +393,25 @@ system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 626903 # number of replacements system.cpu.dcache.tagsinuse 511.875592 # Cycle average of tags in use -system.cpu.dcache.total_refs 23615096 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 23615099 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 627415 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.638718 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 37.638722 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 660309000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.875592 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999757 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13170367 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13170367 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9958094 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9958094 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 13170369 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13170369 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9958095 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9958095 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 236142 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 236142 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247592 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247592 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23128461 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23128461 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23128461 # number of overall hits -system.cpu.dcache.overall_hits::total 23128461 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 23128464 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23128464 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23128464 # number of overall hits +system.cpu.dcache.overall_hits::total 23128464 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 368563 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 368563 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 250302 # number of WriteReq misses @@ -432,18 +432,18 @@ system.cpu.dcache.demand_miss_latency::cpu.data 15398067500 system.cpu.dcache.demand_miss_latency::total 15398067500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 15398067500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 15398067500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13538930 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13538930 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10208396 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10208396 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 13538932 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13538932 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10208397 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10208397 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247593 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247593 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247592 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247592 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23747326 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23747326 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23747326 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23747326 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 23747329 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23747329 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23747329 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23747329 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027222 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024519 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046249 # miss rate for LoadLockedReq accesses diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index e76d62054..5d5098bd1 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -573,7 +573,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index 762733a64..d9b6fdd69 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:17:15 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 16:33:35 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10389500 because target called exit() +Exiting @ tick 10303500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 3a90ce183..2d5ac9cf2 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10389500 # Number of ticks simulated -final_tick 10389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 10303500 # Number of ticks simulated +final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 29724 # Simulator instruction rate (inst/s) -host_op_rate 37079 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67113828 # Simulator tick rate (ticks/s) -host_mem_usage 225376 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 46836 # Simulator instruction rate (inst/s) +host_op_rate 58425 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 104878029 # Simulator tick rate (ticks/s) +host_mem_usage 222544 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 25600 # Number of bytes read from this memory +system.physmem.bytes_read 25664 # Number of bytes read from this memory system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 400 # Number of read requests responded to by this memory +system.physmem.num_reads 401 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2464026180 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1700178064 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2464026180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2490804096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1714368904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2490804096 # Total bandwidth to/from this memory (bytes/s) system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -108,102 +108,102 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 20780 # number of cpu cycles simulated +system.cpu.numCycles 20608 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2550 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1890 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 477 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1987 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 688 # Number of BTB hits +system.cpu.BPredUnit.lookups 2552 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1875 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 474 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2008 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 693 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 244 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6285 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13028 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2550 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 932 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2849 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1782 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1735 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 237 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6263 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13044 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2552 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 930 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2846 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1780 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1715 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2028 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 296 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12124 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.372402 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.762919 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2031 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12075 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.376812 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.767860 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9275 76.50% 76.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 244 2.01% 78.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 198 1.63% 80.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.86% 82.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 226 1.86% 83.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 278 2.29% 86.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 125 1.03% 87.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 139 1.15% 88.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1413 11.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9229 76.43% 76.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 246 2.04% 78.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 197 1.63% 80.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 227 1.88% 81.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 225 1.86% 83.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 278 2.30% 86.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 120 0.99% 87.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 130 1.08% 88.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1423 11.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12124 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122714 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.626949 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6488 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1902 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2634 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 56 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1044 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 12075 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.123835 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.632958 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6461 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1883 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2624 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1046 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 175 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14514 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 580 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1044 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6777 # Number of cycles rename is idle +system.cpu.decode.BranchMispred 174 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14512 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 583 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1046 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6744 # Number of cycles rename is idle system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1438 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2397 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 194 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13625 # Number of instructions processed by rename +system.cpu.rename.serializeStallCycles 1422 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2398 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 191 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13646 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 154 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 13271 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 62674 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 61282 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 155 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 13298 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 62745 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 61353 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7587 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 646 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2866 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1785 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 16 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11782 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9138 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5710 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16685 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12124 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.753712 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.440468 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 7614 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 44 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 614 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2865 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11802 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9165 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5733 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16704 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12075 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.759006 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.446143 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8489 70.02% 70.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1331 10.98% 81.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 789 6.51% 87.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 561 4.63% 92.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 477 3.93% 96.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 294 2.42% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 126 1.04% 99.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 44 0.36% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 13 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8430 69.81% 69.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1334 11.05% 80.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 801 6.63% 87.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 552 4.57% 92.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 480 3.98% 96.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 289 2.39% 98.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 130 1.08% 99.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 44 0.36% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12075 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available @@ -239,115 +239,115 @@ system.cpu.iq.fu_full::MemWrite 63 29.30% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5491 60.09% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2383 26.08% 86.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1254 13.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5502 60.03% 60.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2395 26.13% 86.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1258 13.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9138 # Type of FU issued -system.cpu.iq.rate 0.439750 # Inst issue rate +system.cpu.iq.FU_type_0::total 9165 # Type of FU issued +system.cpu.iq.rate 0.444730 # Inst issue rate system.cpu.iq.fu_busy_cnt 215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023528 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30688 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 17549 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8140 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.023459 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30696 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 17588 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9333 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9360 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1665 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1664 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 847 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 865 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1044 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1046 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11839 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2866 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1785 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 11855 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 180 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2865 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 100 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 326 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 426 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8635 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 503 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 104 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 425 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8667 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2152 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 498 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 1 # number of nop insts executed -system.cpu.iew.exec_refs 3325 # number of memory reference insts executed -system.cpu.iew.exec_branches 1404 # Number of branches executed -system.cpu.iew.exec_stores 1195 # Number of stores executed -system.cpu.iew.exec_rate 0.415544 # Inst execution rate -system.cpu.iew.wb_sent 8328 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8156 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3863 # num instructions producing a value -system.cpu.iew.wb_consumers 7813 # num instructions consuming a value +system.cpu.iew.exec_refs 3351 # number of memory reference insts executed +system.cpu.iew.exec_branches 1406 # Number of branches executed +system.cpu.iew.exec_stores 1199 # Number of stores executed +system.cpu.iew.exec_rate 0.420565 # Inst execution rate +system.cpu.iew.wb_sent 8349 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8167 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3874 # num instructions producing a value +system.cpu.iew.wb_consumers 7832 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.392493 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.494432 # average fanout of values written-back +system.cpu.iew.wb_rate 0.396302 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.494637 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6099 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6115 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11081 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.517914 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.332416 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 378 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11030 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.520308 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.336045 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8736 78.84% 78.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1106 9.98% 88.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 431 3.89% 92.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 257 2.32% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 182 1.64% 96.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 177 1.60% 98.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 55 0.50% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.35% 99.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98 0.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8688 78.77% 78.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1103 10.00% 88.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 433 3.93% 92.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 253 2.29% 94.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 182 1.65% 96.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 178 1.61% 98.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 56 0.51% 98.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.35% 99.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 98 0.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11081 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11030 # Number of insts commited each cycle system.cpu.commit.committedInsts 4600 # Number of instructions committed system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -360,61 +360,61 @@ system.cpu.commit.int_insts 4985 # Nu system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22664 # The number of ROB reads -system.cpu.rob.rob_writes 24737 # The number of ROB writes -system.cpu.timesIdled 179 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8656 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22629 # The number of ROB reads +system.cpu.rob.rob_writes 24771 # The number of ROB writes +system.cpu.timesIdled 177 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8533 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4600 # Number of Instructions Simulated system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4600 # Number of Instructions Simulated -system.cpu.cpi 4.517391 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.517391 # CPI: Total CPI of All Threads -system.cpu.ipc 0.221367 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.221367 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39570 # number of integer regfile reads -system.cpu.int_regfile_writes 8020 # number of integer regfile writes +system.cpu.cpi 4.480000 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.480000 # CPI: Total CPI of All Threads +system.cpu.ipc 0.223214 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.223214 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39716 # number of integer regfile reads +system.cpu.int_regfile_writes 8038 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 16023 # number of misc regfile reads +system.cpu.misc_regfile_reads 16043 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 152.513802 # Cycle average of tags in use -system.cpu.icache.total_refs 1663 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 151.737773 # Cycle average of tags in use +system.cpu.icache.total_refs 1665 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.618243 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.625000 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 152.513802 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.074470 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.074470 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1663 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1663 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1663 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1663 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1663 # number of overall hits -system.cpu.icache.overall_hits::total 1663 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses -system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12618000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12618000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12618000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12618000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12618000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12618000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2028 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2028 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2028 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2028 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179980 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.179980 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.179980 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34569.863014 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 151.737773 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.074091 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.074091 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1665 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1665 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1665 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1665 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1665 # number of overall hits +system.cpu.icache.overall_hits::total 1665 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses +system.cpu.icache.overall_misses::total 366 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12617500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12617500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12617500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12617500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12617500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12617500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2031 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2031 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2031 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2031 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -423,52 +423,52 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9837000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9837000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9837000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9837000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9837000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9837000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33233.108108 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9833500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9833500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9833500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9833500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.512831 # Cycle average of tags in use -system.cpu.dcache.total_refs 2409 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use +system.cpu.dcache.total_refs 2425 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.167785 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.275168 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.512831 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021365 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021365 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1780 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1780 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 87.257006 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021303 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021303 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1796 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1796 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2389 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2389 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2389 # number of overall hits -system.cpu.dcache.overall_hits::total 2389 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits +system.cpu.dcache.overall_hits::total 2405 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses @@ -479,38 +479,38 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5506000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5506000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5541500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5541500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16350000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16350000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16350000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16350000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1950 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 16385500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16385500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16385500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16385500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1966 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1966 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087179 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2879 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2879 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.165561 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.165561 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32388.235294 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -537,65 +537,65 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 149 system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3156500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3156500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3192000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3192000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4658000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4658000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4658000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4658000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054872 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4693500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4693500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29500 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 189.446862 # Cycle average of tags in use -system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.114525 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use +system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.111421 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 142.892597 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.554265 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004361 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001421 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005781 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 142.150350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.638961 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004338 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001423 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005761 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 41 # 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number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) @@ -608,19 +608,19 @@ system.cpu.l2cache.overall_accesses::cpu.inst 296 system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.803738 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.859060 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # 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number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 358 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 124 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 400 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 124 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2580000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11170500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11202500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3895000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12485500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3927000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12517500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3895000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12485500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.766355 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31463.414634 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 29d0ee1dd..e584370ea 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -514,7 +514,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index cdeb6fd62..9bfa3671c 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:17:15 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 16:33:24 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10389500 because target called exit() +Exiting @ tick 10303500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index b762714e2..c4c9274ca 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10389500 # Number of ticks simulated -final_tick 10389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 10303500 # Number of ticks simulated +final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31505 # Simulator instruction rate (inst/s) -host_op_rate 39300 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71135954 # Simulator tick rate (ticks/s) -host_mem_usage 225060 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 48410 # Simulator instruction rate (inst/s) +host_op_rate 60388 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 108401694 # Simulator tick rate (ticks/s) +host_mem_usage 222284 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 25600 # Number of bytes read from this memory +system.physmem.bytes_read 25664 # Number of bytes read from this memory system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 400 # Number of read requests responded to by this memory +system.physmem.num_reads 401 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2464026180 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1700178064 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2464026180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2490804096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1714368904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2490804096 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -63,102 +63,102 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 20780 # number of cpu cycles simulated +system.cpu.numCycles 20608 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2550 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1890 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 477 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1987 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 688 # Number of BTB hits +system.cpu.BPredUnit.lookups 2552 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1875 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 474 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2008 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 693 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 244 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6285 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13028 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2550 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 932 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2849 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1782 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1735 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 237 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6263 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13044 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2552 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 930 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2846 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1780 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1715 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2028 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 296 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12124 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.372402 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.762919 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2031 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12075 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.376812 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.767860 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9275 76.50% 76.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 244 2.01% 78.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 198 1.63% 80.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.86% 82.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 226 1.86% 83.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 278 2.29% 86.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 125 1.03% 87.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 139 1.15% 88.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1413 11.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9229 76.43% 76.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 246 2.04% 78.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 197 1.63% 80.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 227 1.88% 81.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 225 1.86% 83.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 278 2.30% 86.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 120 0.99% 87.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 130 1.08% 88.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1423 11.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12124 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122714 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.626949 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6488 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1902 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2634 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 56 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1044 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 12075 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.123835 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.632958 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6461 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1883 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2624 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1046 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 175 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14514 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 580 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1044 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6777 # Number of cycles rename is idle +system.cpu.decode.BranchMispred 174 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14512 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 583 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1046 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6744 # Number of cycles rename is idle system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1438 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2397 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 194 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13625 # Number of instructions processed by rename +system.cpu.rename.serializeStallCycles 1422 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2398 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 191 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13646 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 154 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 13271 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 62674 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 61282 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 155 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 13298 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 62745 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 61353 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7587 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 646 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2866 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1785 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 16 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11782 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9138 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5710 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16685 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12124 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.753712 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.440468 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 7614 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 44 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 614 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2865 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11802 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9165 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5733 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16704 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12075 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.759006 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.446143 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8489 70.02% 70.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1331 10.98% 81.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 789 6.51% 87.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 561 4.63% 92.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 477 3.93% 96.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 294 2.42% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 126 1.04% 99.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 44 0.36% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 13 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8430 69.81% 69.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1334 11.05% 80.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 801 6.63% 87.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 552 4.57% 92.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 480 3.98% 96.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 289 2.39% 98.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 130 1.08% 99.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 44 0.36% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12075 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available @@ -194,115 +194,115 @@ system.cpu.iq.fu_full::MemWrite 63 29.30% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5491 60.09% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2383 26.08% 86.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1254 13.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5502 60.03% 60.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2395 26.13% 86.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1258 13.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9138 # Type of FU issued -system.cpu.iq.rate 0.439750 # Inst issue rate +system.cpu.iq.FU_type_0::total 9165 # Type of FU issued +system.cpu.iq.rate 0.444730 # Inst issue rate system.cpu.iq.fu_busy_cnt 215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023528 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30688 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 17549 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8140 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.023459 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30696 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 17588 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9333 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9360 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1665 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1664 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 847 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 865 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1044 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1046 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11839 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2866 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1785 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 11855 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 180 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2865 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 100 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 326 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 426 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8635 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 503 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 104 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 425 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8667 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2152 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 498 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 1 # number of nop insts executed -system.cpu.iew.exec_refs 3325 # number of memory reference insts executed -system.cpu.iew.exec_branches 1404 # Number of branches executed -system.cpu.iew.exec_stores 1195 # Number of stores executed -system.cpu.iew.exec_rate 0.415544 # Inst execution rate -system.cpu.iew.wb_sent 8328 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8156 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3863 # num instructions producing a value -system.cpu.iew.wb_consumers 7813 # num instructions consuming a value +system.cpu.iew.exec_refs 3351 # number of memory reference insts executed +system.cpu.iew.exec_branches 1406 # Number of branches executed +system.cpu.iew.exec_stores 1199 # Number of stores executed +system.cpu.iew.exec_rate 0.420565 # Inst execution rate +system.cpu.iew.wb_sent 8349 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8167 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3874 # num instructions producing a value +system.cpu.iew.wb_consumers 7832 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.392493 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.494432 # average fanout of values written-back +system.cpu.iew.wb_rate 0.396302 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.494637 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6099 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6115 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11081 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.517914 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.332416 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 378 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11030 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.520308 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.336045 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8736 78.84% 78.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1106 9.98% 88.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 431 3.89% 92.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 257 2.32% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 182 1.64% 96.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 177 1.60% 98.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 55 0.50% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.35% 99.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98 0.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8688 78.77% 78.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1103 10.00% 88.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 433 3.93% 92.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 253 2.29% 94.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 182 1.65% 96.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 178 1.61% 98.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 56 0.51% 98.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.35% 99.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 98 0.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11081 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11030 # Number of insts commited each cycle system.cpu.commit.committedInsts 4600 # Number of instructions committed system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -315,61 +315,61 @@ system.cpu.commit.int_insts 4985 # Nu system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22664 # The number of ROB reads -system.cpu.rob.rob_writes 24737 # The number of ROB writes -system.cpu.timesIdled 179 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8656 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22629 # The number of ROB reads +system.cpu.rob.rob_writes 24771 # The number of ROB writes +system.cpu.timesIdled 177 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8533 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4600 # Number of Instructions Simulated system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4600 # Number of Instructions Simulated -system.cpu.cpi 4.517391 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.517391 # CPI: Total CPI of All Threads -system.cpu.ipc 0.221367 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.221367 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39570 # number of integer regfile reads -system.cpu.int_regfile_writes 8020 # number of integer regfile writes +system.cpu.cpi 4.480000 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.480000 # CPI: Total CPI of All Threads +system.cpu.ipc 0.223214 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.223214 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39716 # number of integer regfile reads +system.cpu.int_regfile_writes 8038 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 16023 # number of misc regfile reads +system.cpu.misc_regfile_reads 16043 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 152.513802 # Cycle average of tags in use -system.cpu.icache.total_refs 1663 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 151.737773 # Cycle average of tags in use +system.cpu.icache.total_refs 1665 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.618243 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.625000 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 152.513802 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.074470 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.074470 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1663 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1663 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1663 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1663 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1663 # number of overall hits -system.cpu.icache.overall_hits::total 1663 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses -system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12618000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12618000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12618000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12618000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12618000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12618000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2028 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2028 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2028 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2028 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179980 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.179980 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.179980 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34569.863014 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 151.737773 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.074091 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.074091 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1665 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1665 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1665 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1665 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1665 # number of overall hits +system.cpu.icache.overall_hits::total 1665 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses +system.cpu.icache.overall_misses::total 366 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12617500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12617500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12617500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12617500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12617500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12617500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2031 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2031 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2031 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2031 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -378,52 +378,52 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9837000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9837000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9837000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9837000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9837000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9837000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33233.108108 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9833500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9833500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9833500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9833500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.512831 # Cycle average of tags in use -system.cpu.dcache.total_refs 2409 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use +system.cpu.dcache.total_refs 2425 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.167785 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.275168 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.512831 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021365 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021365 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1780 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1780 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 87.257006 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021303 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021303 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1796 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1796 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2389 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2389 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2389 # number of overall hits -system.cpu.dcache.overall_hits::total 2389 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits +system.cpu.dcache.overall_hits::total 2405 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses @@ -434,38 +434,38 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5506000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5506000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5541500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5541500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16350000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16350000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16350000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16350000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1950 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 16385500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16385500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16385500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16385500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1966 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1966 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087179 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2879 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2879 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.165561 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.165561 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32388.235294 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -492,65 +492,65 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 149 system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 149 # 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number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054872 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4693500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4693500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29500 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 189.446862 # Cycle average of tags in use -system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.114525 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use +system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.111421 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 142.892597 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.554265 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004361 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001421 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005781 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 142.150350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.638961 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004338 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001423 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005761 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits -system.cpu.l2cache.overall_hits::total 41 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits +system.cpu.l2cache.overall_hits::total 40 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 362 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 128 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 129 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 128 # number of overall misses -system.cpu.l2cache.overall_misses::total 404 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9478000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2963500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12441500 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.data 129 # number of overall misses +system.cpu.l2cache.overall_misses::total 405 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9475500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2999000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12474500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1446500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1446500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9478000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4410000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13888000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9478000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4410000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13888000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9475500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4445500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13921000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9475500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4445500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13921000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) @@ -563,19 +563,19 @@ system.cpu.l2cache.overall_accesses::cpu.inst 296 system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.803738 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.859060 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.859060 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34340.579710 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34459.302326 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,41 +591,41 @@ system.cpu.l2cache.demand_mshr_hits::total 4 # system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 358 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 124 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 400 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 124 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2580000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11170500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11202500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3895000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12485500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3927000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12517500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3895000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12485500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.766355 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31463.414634 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini index 1bb97fb57..305feda00 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini @@ -154,7 +154,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index 708e8b4cb..38e35b911 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:17:15 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 16:33:56 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 047a13c77..693c12922 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2875500 # Number of ticks simulated final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25080 # Simulator instruction rate (inst/s) -host_op_rate 31285 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15673750 # Simulator tick rate (ticks/s) -host_mem_usage 214860 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 95261 # Simulator instruction rate (inst/s) +host_op_rate 118814 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59514762 # Simulator tick rate (ticks/s) +host_mem_usage 212272 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated system.physmem.bytes_read 22944 # Number of bytes read from this memory @@ -117,7 +117,7 @@ system.cpu.committedOps 5739 # Nu system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 185 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls system.cpu.num_int_insts 4985 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 25237 # number of times the integer registers were read diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini index 85d2a6f4f..a6e23776e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -100,7 +100,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index a7a548730..af4cba8f6 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:17:15 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 16:33:45 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index b76299081..ed3ee4578 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2875500 # Number of ticks simulated final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24562 # Simulator instruction rate (inst/s) -host_op_rate 30640 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15350765 # Simulator tick rate (ticks/s) -host_mem_usage 214764 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 126142 # Simulator instruction rate (inst/s) +host_op_rate 157316 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78793699 # Simulator tick rate (ticks/s) +host_mem_usage 212180 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated system.physmem.bytes_read 22944 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 5739 # Nu system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 185 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls system.cpu.num_int_insts 4985 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 25237 # number of times the integer registers were read diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index 50ec8fd07..92e235eb9 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -183,7 +183,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index 25b5aeda6..976d6a78b 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:17:15 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 16:34:06 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 4b008ff5c..2c4a7f677 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 26361000 # Number of ticks simulated final_tick 26361000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 29458 # Simulator instruction rate (inst/s) -host_op_rate 36586 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 169706423 # Simulator tick rate (ticks/s) -host_mem_usage 223936 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 140316 # Simulator instruction rate (inst/s) +host_op_rate 174230 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 807994403 # Simulator tick rate (ticks/s) +host_mem_usage 221092 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 4574 # Number of instructions simulated sim_ops 5682 # Number of ops (including micro ops) simulated system.physmem.bytes_read 22400 # Number of bytes read from this memory @@ -71,7 +71,7 @@ system.cpu.committedOps 5682 # Nu system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 185 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls system.cpu.num_int_insts 4985 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 28701 # number of times the integer registers were read |