diff options
| author | Steve Reinhardt <stever@gmail.com> | 2009-04-22 01:55:52 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2009-04-22 01:55:52 -0400 |
| commit | 7b40c36fbd1c348e5ef43231325923aae1cd0809 (patch) | |
| tree | b1d142d10229a7ca68eff864aa9aae672230e41a /tests/quick | |
| parent | 6629d9b2bc58a885bfebce1517fd12483497b6e4 (diff) | |
| download | gem5-7b40c36fbd1c348e5ef43231325923aae1cd0809.tar.xz | |
Update stats for new single bad-address responder.
Mostly just config.ini updates, though the different response
latency for bad addresses caused very minor timing changes
in the O3 Linux boot tests.
Diffstat (limited to 'tests/quick')
83 files changed, 426 insertions, 608 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index be9b35776..9978c29e9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -104,11 +104,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -277,11 +276,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -313,11 +311,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -361,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 7b43e6682..a47274398 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 14 2009 16:03:56 -M5 revision 5716400b2110+ 6033+ default qtip tip new-thread-status-stats-update -M5 started Apr 14 2009 16:03:59 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:57:23 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 59870a0d4..d9c15b30b 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 100618 # Simulator instruction rate (inst/s) -host_mem_usage 204352 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 195881226 # Simulator tick rate (ticks/s) +host_inst_rate 118345 # Simulator instruction rate (inst/s) +host_mem_usage 200916 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 230331062 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout index da206d16c..52c0469fb 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:37:48 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:57:23 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt index a6c36497f..3077042e9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 130449 # Simulator instruction rate (inst/s) -host_mem_usage 194292 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 65193146 # Simulator tick rate (ticks/s) +host_inst_rate 272186 # Simulator instruction rate (inst/s) +host_mem_usage 192556 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 135226078 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 988a9a0ce..c0449a709 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout index fd7224cc6..15dc4382a 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:30:03 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:52:32 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt index 14eb9b58a..1153fe460 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 14499 # Simulator instruction rate (inst/s) -host_mem_usage 201828 # Number of bytes of host memory used -host_seconds 0.44 # Real time elapsed on the host -host_tick_rate 76395737 # Simulator tick rate (ticks/s) +host_inst_rate 457919 # Simulator instruction rate (inst/s) +host_mem_usage 200100 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 2381009446 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000034 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 477ca365f..f6582aa5c 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -104,11 +104,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -277,11 +276,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -313,11 +311,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -361,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 0ffb13f0d..63832f049 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 14 2009 16:03:56 -M5 revision 5716400b2110+ 6033+ default qtip tip new-thread-status-stats-update -M5 started Apr 14 2009 16:03:59 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:39:11 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 220cf8ff6..98d731942 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 72174 # Simulator instruction rate (inst/s) -host_mem_usage 203356 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 215783466 # Simulator tick rate (ticks/s) +host_inst_rate 48067 # Simulator instruction rate (inst/s) +host_mem_usage 199912 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 143884460 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout index fd4dcc4fc..0cca599d2 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:30:03 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:39:03 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index fc21ca705..8610ea2cd 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 7782 # Simulator instruction rate (inst/s) -host_mem_usage 193364 # Number of bytes of host memory used -host_seconds 0.33 # Real time elapsed on the host -host_tick_rate 3915244 # Simulator tick rate (ticks/s) +host_inst_rate 312515 # Simulator instruction rate (inst/s) +host_mem_usage 191632 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 151541696 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index be492f6c5..b2b4a540c 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout index ac591190c..82648883e 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:30:03 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:59:01 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt index da1cac32f..d6291acb4 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 6492 # Simulator instruction rate (inst/s) -host_mem_usage 200880 # Number of bytes of host memory used -host_seconds 0.40 # Real time elapsed on the host -host_tick_rate 43734802 # Simulator tick rate (ticks/s) +host_inst_rate 164528 # Simulator instruction rate (inst/s) +host_mem_usage 199264 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1091811726 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000017 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini index d64731634..9e32dcc7f 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini @@ -158,11 +158,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -331,11 +330,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -367,11 +365,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -415,7 +412,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index 09c4684d8..4849c504d 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 18 2009 10:32:20 -M5 revision dfe15f43c57e 6039 default qtip tip o3-mips-hello-regress -M5 started Apr 18 2009 10:37:22 -M5 executing on zooks +M5 compiled Apr 21 2009 18:01:16 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:01:42 +M5 executing on zizzer command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index f4a13baba..abebc01ef 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 49036 # Simulator instruction rate (inst/s) -host_mem_usage 153428 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 135151055 # Simulator tick rate (ticks/s) +host_inst_rate 62820 # Simulator instruction rate (inst/s) +host_mem_usage 202152 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 173066613 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5024 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated @@ -19,23 +19,23 @@ system.cpu.BPredUnit.usedRAS 384 # Nu system.cpu.commit.COM:branches 879 # Number of branches committed system.cpu.commit.COM:bw_lim_events 63 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 14165 -system.cpu.commit.COM:committed_per_cycle::min_value 0 -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% -system.cpu.commit.COM:committed_per_cycle::0-1 11701 82.61% -system.cpu.commit.COM:committed_per_cycle::1-2 1166 8.23% -system.cpu.commit.COM:committed_per_cycle::2-3 493 3.48% -system.cpu.commit.COM:committed_per_cycle::3-4 279 1.97% -system.cpu.commit.COM:committed_per_cycle::4-5 290 2.05% -system.cpu.commit.COM:committed_per_cycle::5-6 74 0.52% -system.cpu.commit.COM:committed_per_cycle::6-7 61 0.43% -system.cpu.commit.COM:committed_per_cycle::7-8 38 0.27% -system.cpu.commit.COM:committed_per_cycle::8 63 0.44% -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% -system.cpu.commit.COM:committed_per_cycle::total 14165 -system.cpu.commit.COM:committed_per_cycle::max_value 8 -system.cpu.commit.COM:committed_per_cycle::mean 0.399223 -system.cpu.commit.COM:committed_per_cycle::stdev 1.126414 +system.cpu.commit.COM:committed_per_cycle::samples 14165 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 11701 82.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 1166 8.23% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 493 3.48% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 279 1.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 290 2.05% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 74 0.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 61 0.43% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 38 0.27% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 63 0.44% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 14165 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.399223 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.126414 # Number of insts commited each cycle system.cpu.commit.COM:count 5655 # Number of instructions committed system.cpu.commit.COM:loads 1130 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -141,23 +141,23 @@ system.cpu.fetch.branchRate 0.084246 # Nu system.cpu.fetch.icacheStallCycles 2162 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 0.549669 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 15217 -system.cpu.fetch.rateDist::min_value 0 -system.cpu.fetch.rateDist::underflows 0 0.00% -system.cpu.fetch.rateDist::0-1 11225 73.77% -system.cpu.fetch.rateDist::1-2 1766 11.61% -system.cpu.fetch.rateDist::2-3 196 1.29% -system.cpu.fetch.rateDist::3-4 137 0.90% -system.cpu.fetch.rateDist::4-5 314 2.06% -system.cpu.fetch.rateDist::5-6 113 0.74% -system.cpu.fetch.rateDist::6-7 304 2.00% -system.cpu.fetch.rateDist::7-8 249 1.64% -system.cpu.fetch.rateDist::8 913 6.00% -system.cpu.fetch.rateDist::overflows 0 0.00% -system.cpu.fetch.rateDist::total 15217 -system.cpu.fetch.rateDist::max_value 8 -system.cpu.fetch.rateDist::mean 1.002892 -system.cpu.fetch.rateDist::stdev 2.262712 +system.cpu.fetch.rateDist::samples 15217 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 11225 73.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 1766 11.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 196 1.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 137 0.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 314 2.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 113 0.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 304 2.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 249 1.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 913 6.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 15217 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.002892 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.262712 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 2162 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 35500 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34915.151515 # average ReadReq mshr miss latency diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout index 4fee53c4d..b140ca5f4 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:01 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:33:27 -M5 executing on maize +M5 compiled Apr 21 2009 18:01:16 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:01:42 +M5 executing on zizzer command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt index a50f65423..60efc35e1 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 113529 # Simulator instruction rate (inst/s) -host_mem_usage 195572 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 56492209 # Simulator tick rate (ticks/s) +host_inst_rate 525065 # Simulator instruction rate (inst/s) +host_mem_usage 193736 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 257090909 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5656 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index ac73fcc0d..9f3729e92 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -94,11 +94,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -130,11 +129,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -166,11 +164,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout index 77ad52898..f10279373 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:01 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:30:04 -M5 executing on maize +M5 compiled Apr 21 2009 18:01:16 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:01:42 +M5 executing on zizzer command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt index c7fdc027e..caa6f8c7b 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 6063 # Simulator instruction rate (inst/s) -host_mem_usage 203244 # Number of bytes of host memory used -host_seconds 0.93 # Real time elapsed on the host -host_tick_rate 34635885 # Simulator tick rate (ticks/s) +host_inst_rate 35646 # Simulator instruction rate (inst/s) +host_mem_usage 201368 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host +host_tick_rate 203367436 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5656 # Number of instructions simulated sim_seconds 0.000032 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout index c66e3090a..4273b735d 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:32:53 -M5 executing on maize +M5 compiled Apr 21 2009 18:04:32 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:05:07 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt index 90590228c..e9a2222d7 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 179147 # Simulator instruction rate (inst/s) -host_mem_usage 195464 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 89901478 # Simulator tick rate (ticks/s) +host_inst_rate 314858 # Simulator instruction rate (inst/s) +host_mem_usage 193720 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 157107957 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index 2bb5be9ae..928e1a6a9 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout index b434e54e7..156edd943 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:30:32 -M5 executing on maize +M5 compiled Apr 21 2009 18:04:32 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:14:35 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt index 011b7eb96..185c6fd8b 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 18112 # Simulator instruction rate (inst/s) -host_mem_usage 202936 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host -host_tick_rate 98375821 # Simulator tick rate (ticks/s) +host_inst_rate 333292 # Simulator instruction rate (inst/s) +host_mem_usage 201348 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1783998034 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout index 3efb926df..dbaa3b09e 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 12 2009 13:26:17 -M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch -M5 started Apr 12 2009 13:27:47 -M5 executing on tater +M5 compiled Apr 21 2009 19:00:07 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 19:57:53 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt index 36a339c2e..f96fa3e66 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 114267 # Simulator instruction rate (inst/s) -host_mem_usage 193116 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 65956833 # Simulator tick rate (ticks/s) +host_inst_rate 544881 # Simulator instruction rate (inst/s) +host_mem_usage 193800 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 311186037 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9494 # Number of instructions simulated sim_seconds 0.000005 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini index ff74f91e4..5db260ab9 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index 337fad398..b776401d1 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 12 2009 13:26:17 -M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch -M5 started Apr 12 2009 13:32:19 -M5 executing on tater +M5 compiled Apr 21 2009 19:00:07 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 19:57:54 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index a3cf444c8..fa5ab8e26 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 99388 # Simulator instruction rate (inst/s) -host_mem_usage 200700 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 310581132 # Simulator tick rate (ticks/s) +host_inst_rate 426927 # Simulator instruction rate (inst/s) +host_mem_usage 201388 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1322141682 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9494 # Number of instructions simulated sim_seconds 0.000030 # Number of seconds simulated diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index f89bcb443..4e95f234f 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -104,11 +104,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -277,11 +276,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -313,11 +311,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -361,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -380,7 +377,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 187715811..a796d7912 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 14 2009 16:03:56 -M5 revision 5716400b2110+ 6033+ default qtip tip new-thread-status-stats-update -M5 started Apr 14 2009 16:03:57 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:39:11 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index d738dd02e..06def78dc 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 12362 # Simulator instruction rate (inst/s) -host_mem_usage 204880 # Number of bytes of host memory used -host_seconds 1.03 # Real time elapsed on the host -host_tick_rate 13784522 # Simulator tick rate (ticks/s) +host_inst_rate 75551 # Simulator instruction rate (inst/s) +host_mem_usage 201440 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host +host_tick_rate 84168035 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 12773 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index 95ee672cf..e7d27f8d6 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -104,11 +104,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -277,11 +276,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -313,11 +311,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -361,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/insttest/bin/sparc/linux/insttest +executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index 974c1f458..34998e971 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 14 2009 16:03:50 -M5 revision 5716400b2110+ 6033+ default qtip tip new-thread-status-stats-update -M5 started Apr 14 2009 16:03:52 -M5 executing on phenom -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing +M5 compiled Apr 21 2009 18:04:32 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:05:07 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 3faf1f835..3e04b78ab 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 9495 # Simulator instruction rate (inst/s) -host_mem_usage 208836 # Number of bytes of host memory used -host_seconds 1.52 # Real time elapsed on the host -host_tick_rate 18237542 # Simulator tick rate (ticks/s) +host_inst_rate 47616 # Simulator instruction rate (inst/s) +host_mem_usage 201812 # Number of bytes of host memory used +host_seconds 0.30 # Real time elapsed on the host +host_tick_rate 91393866 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated sim_seconds 0.000028 # Number of seconds simulated diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout index 645f97a41..3b6aca04c 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:30:34 -M5 executing on maize +M5 compiled Apr 21 2009 18:04:32 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:05:08 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index 1ac975e6b..bb032e871 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 387939 # Simulator instruction rate (inst/s) -host_mem_usage 195268 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 193638166 # Simulator tick rate (ticks/s) +host_inst_rate 587404 # Simulator instruction rate (inst/s) +host_mem_usage 193520 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 292299724 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 15175 # Number of instructions simulated sim_seconds 0.000008 # Number of seconds simulated diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index 2a3a9cb21..ab1742f70 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout index 788bf8fe4..4ea7967d3 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:30:40 -M5 executing on maize +M5 compiled Apr 21 2009 18:04:32 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:15:57 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 81d91e476..43fac0d7a 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 11404 # Simulator instruction rate (inst/s) -host_mem_usage 202820 # Number of bytes of host memory used -host_seconds 1.33 # Real time elapsed on the host -host_tick_rate 32108089 # Simulator tick rate (ticks/s) +host_inst_rate 347867 # Simulator instruction rate (inst/s) +host_mem_usage 201056 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 973883913 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 15175 # Number of instructions simulated sim_seconds 0.000043 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index ef33d965f..40be52d31 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -69,11 +69,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -105,11 +104,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -178,11 +176,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -214,11 +211,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -308,14 +304,13 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst [system.iocache] type=BaseCache -addr_range=0:18446744073709551615 +addr_range=0:8589934591 assoc=8 block_size=64 -cpu_side_filter_ranges=549755813888:18446744073709551615 +forward_snoops=false hash_delay=1 latency=50000 max_miss_count=0 -mem_side_filter_ranges=0:18446744073709551615 mshrs=20 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -343,11 +338,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=8 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=92 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -372,20 +366,20 @@ mem_side=system.membus.port[3] [system.membus] type=Bus -children=responder +children=badaddr_responder block_size=64 bus_id=1 clock=1000 header_cycles=1 responder_set=false width=64 -default=system.membus.responder.pio +default=system.membus.badaddr_responder.pio port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side -[system.membus.responder] +[system.membus.badaddr_responder] type=IsaFake pio_addr=0 -pio_latency=1 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -428,32 +422,14 @@ port=3456 [system.toL2Bus] type=Bus -children=responder block_size=64 bus_id=0 clock=1000 header_cycles=1 responder_set=false width=64 -default=system.toL2Bus.responder.pio port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side -[system.toL2Bus.responder] -type=IsaFake -pio_addr=0 -pio_latency=1 -pio_size=8 -platform=system.tsunami -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.toL2Bus.default - [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index a95a79ffc..1c7915c5e 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:30:04 -M5 executing on maize +M5 compiled Apr 21 2009 17:45:48 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 17:54:58 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index a781e9d48..7757176f7 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4473904 # Simulator instruction rate (inst/s) -host_mem_usage 294520 # Number of bytes of host memory used -host_seconds 14.12 # Real time elapsed on the host -host_tick_rate 132494065933 # Simulator tick rate (ticks/s) +host_inst_rate 2919011 # Simulator instruction rate (inst/s) +host_mem_usage 293452 # Number of bytes of host memory used +host_seconds 21.64 # Real time elapsed on the host +host_tick_rate 86446798213 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63154034 # Number of instructions simulated sim_seconds 1.870336 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 511baadf2..d098a0440 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -69,11 +69,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -105,11 +104,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -199,14 +197,13 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst [system.iocache] type=BaseCache -addr_range=0:18446744073709551615 +addr_range=0:8589934591 assoc=8 block_size=64 -cpu_side_filter_ranges=549755813888:18446744073709551615 +forward_snoops=false hash_delay=1 latency=50000 max_miss_count=0 -mem_side_filter_ranges=0:18446744073709551615 mshrs=20 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -234,11 +231,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=8 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=92 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -263,20 +259,20 @@ mem_side=system.membus.port[3] [system.membus] type=Bus -children=responder +children=badaddr_responder block_size=64 bus_id=1 clock=1000 header_cycles=1 responder_set=false width=64 -default=system.membus.responder.pio +default=system.membus.badaddr_responder.pio port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side -[system.membus.responder] +[system.membus.badaddr_responder] type=IsaFake pio_addr=0 -pio_latency=1 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -319,32 +315,14 @@ port=3456 [system.toL2Bus] type=Bus -children=responder block_size=64 bus_id=0 clock=1000 header_cycles=1 responder_set=false width=64 -default=system.toL2Bus.responder.pio port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side -[system.toL2Bus.responder] -type=IsaFake -pio_addr=0 -pio_latency=1 -pio_size=8 -platform=system.tsunami -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.toL2Bus.default - [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index b5820599c..6085e3c17 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:30:05 -M5 executing on maize +M5 compiled Apr 21 2009 17:45:48 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 17:54:37 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 9c2b9013b..2f7905f66 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4520875 # Simulator instruction rate (inst/s) -host_mem_usage 293196 # Number of bytes of host memory used -host_seconds 13.28 # Real time elapsed on the host -host_tick_rate 137745560508 # Simulator tick rate (ticks/s) +host_inst_rate 2944628 # Simulator instruction rate (inst/s) +host_mem_usage 292076 # Number of bytes of host memory used +host_seconds 20.39 # Real time elapsed on the host +host_tick_rate 89719993414 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60038305 # Number of instructions simulated sim_seconds 1.829332 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 97b65b05c..85ee22259 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -66,11 +66,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -102,11 +101,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -172,11 +170,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -208,11 +205,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -302,14 +298,13 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst [system.iocache] type=BaseCache -addr_range=0:18446744073709551615 +addr_range=0:8589934591 assoc=8 block_size=64 -cpu_side_filter_ranges=549755813888:18446744073709551615 +forward_snoops=false hash_delay=1 latency=50000 max_miss_count=0 -mem_side_filter_ranges=0:18446744073709551615 mshrs=20 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -337,11 +332,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=8 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=92 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -366,20 +360,20 @@ mem_side=system.membus.port[3] [system.membus] type=Bus -children=responder +children=badaddr_responder block_size=64 bus_id=1 clock=1000 header_cycles=1 responder_set=false width=64 -default=system.membus.responder.pio +default=system.membus.badaddr_responder.pio port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side -[system.membus.responder] +[system.membus.badaddr_responder] type=IsaFake pio_addr=0 -pio_latency=1 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -422,32 +416,14 @@ port=3456 [system.toL2Bus] type=Bus -children=responder block_size=64 bus_id=0 clock=1000 header_cycles=1 responder_set=false width=64 -default=system.toL2Bus.responder.pio port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side -[system.toL2Bus.responder] -type=IsaFake -pio_addr=0 -pio_latency=1 -pio_size=8 -platform=system.tsunami -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.toL2Bus.default - [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 3ba004aee..28d9dc74d 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:30:05 -M5 executing on maize +M5 compiled Apr 21 2009 17:45:48 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 17:56:00 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index fa370386c..6292a0ccf 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2075727 # Simulator instruction rate (inst/s) -host_mem_usage 291612 # Number of bytes of host memory used -host_seconds 28.63 # Real time elapsed on the host -host_tick_rate 68891569254 # Simulator tick rate (ticks/s) +host_inst_rate 1283961 # Simulator instruction rate (inst/s) +host_mem_usage 290228 # Number of bytes of host memory used +host_seconds 46.28 # Real time elapsed on the host +host_tick_rate 42613693899 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 59420593 # Number of instructions simulated sim_seconds 1.972135 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index a7d96b196..64bcede47 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -66,11 +66,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -102,11 +101,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -196,14 +194,13 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst [system.iocache] type=BaseCache -addr_range=0:18446744073709551615 +addr_range=0:8589934591 assoc=8 block_size=64 -cpu_side_filter_ranges=549755813888:18446744073709551615 +forward_snoops=false hash_delay=1 latency=50000 max_miss_count=0 -mem_side_filter_ranges=0:18446744073709551615 mshrs=20 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -231,11 +228,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=8 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=92 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -260,20 +256,20 @@ mem_side=system.membus.port[3] [system.membus] type=Bus -children=responder +children=badaddr_responder block_size=64 bus_id=1 clock=1000 header_cycles=1 responder_set=false width=64 -default=system.membus.responder.pio +default=system.membus.badaddr_responder.pio port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side -[system.membus.responder] +[system.membus.badaddr_responder] type=IsaFake pio_addr=0 -pio_latency=1 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -316,32 +312,14 @@ port=3456 [system.toL2Bus] type=Bus -children=responder block_size=64 bus_id=0 clock=1000 header_cycles=1 responder_set=false width=64 -default=system.toL2Bus.responder.pio port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side -[system.toL2Bus.responder] -type=IsaFake -pio_addr=0 -pio_latency=1 -pio_size=8 -platform=system.tsunami -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.toL2Bus.default - [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index 0edc8e974..b6e01de39 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:30:04 -M5 executing on maize +M5 compiled Apr 21 2009 17:45:48 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 17:55:21 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 7b42fa0e8..589cc1a34 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2046881 # Simulator instruction rate (inst/s) -host_mem_usage 290296 # Number of bytes of host memory used -host_seconds 27.46 # Real time elapsed on the host -host_tick_rate 70291420604 # Simulator tick rate (ticks/s) +host_inst_rate 1437585 # Simulator instruction rate (inst/s) +host_mem_usage 288848 # Number of bytes of host memory used +host_seconds 39.10 # Real time elapsed on the host +host_tick_rate 49367876331 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56205703 # Number of instructions simulated sim_seconds 1.930165 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout index b2ea6d6e3..06ee016b8 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:38:04 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:57:23 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt index ca25b214e..b870c6458 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4651388 # Simulator instruction rate (inst/s) -host_mem_usage 193356 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -host_tick_rate 2320975678 # Simulator tick rate (ticks/s) +host_inst_rate 3016706 # Simulator instruction rate (inst/s) +host_mem_usage 191632 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host +host_tick_rate 1506280802 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index c3b0ede0c..5fbeffed0 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout index a040a467d..ad2ad5770 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:34:29 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:59:01 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt index a1d2c7b35..74765736f 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2409922 # Simulator instruction rate (inst/s) -host_mem_usage 200896 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host -host_tick_rate 3549730180 # Simulator tick rate (ticks/s) +host_inst_rate 1514764 # Simulator instruction rate (inst/s) +host_mem_usage 199328 # Number of bytes of host memory used +host_seconds 0.33 # Real time elapsed on the host +host_tick_rate 2232178480 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated sim_seconds 0.000737 # Number of seconds simulated diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini index 97cda243a..b801b4825 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini @@ -43,11 +43,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -79,11 +78,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -157,11 +155,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -193,11 +190,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -271,11 +267,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -307,11 +302,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -385,11 +379,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -421,11 +414,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -470,11 +462,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=8 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=92 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout index 6504ffb9c..7c058e100 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:38:03 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:39:02 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt index 9d21b6bf4..2a786c1d0 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4748415 # Simulator instruction rate (inst/s) -host_mem_usage 1125700 # Number of bytes of host memory used -host_seconds 0.42 # Real time elapsed on the host -host_tick_rate 593193174 # Simulator tick rate (ticks/s) +host_inst_rate 2806031 # Simulator instruction rate (inst/s) +host_mem_usage 1124224 # Number of bytes of host memory used +host_seconds 0.71 # Real time elapsed on the host +host_tick_rate 350627795 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2000004 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini index e871dcaff..02b245760 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -151,11 +149,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -187,11 +184,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -262,11 +258,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -298,11 +293,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -373,11 +367,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -409,11 +402,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -458,11 +450,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=8 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=92 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout index 974e2e1d0..4f024f577 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:44:10 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:39:10 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt index 78b7525ed..cb27727f8 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2309817 # Simulator instruction rate (inst/s) -host_mem_usage 208124 # Number of bytes of host memory used -host_seconds 0.87 # Real time elapsed on the host -host_tick_rate 852520777 # Simulator tick rate (ticks/s) +host_inst_rate 1377736 # Simulator instruction rate (inst/s) +host_mem_usage 206716 # Number of bytes of host memory used +host_seconds 1.45 # Real time elapsed on the host +host_tick_rate 508569870 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1999941 # Number of instructions simulated sim_seconds 0.000738 # Number of seconds simulated diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index b1c2caacb..28f0771b6 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -104,11 +104,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -277,11 +276,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -425,11 +423,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -598,11 +595,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -727,11 +723,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -900,11 +895,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -1029,11 +1023,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -1202,11 +1195,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -1241,11 +1233,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=8 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=92 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index fca385548..3245c7a36 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 17 2009 00:22:56 -M5 revision 35b1dc26772f 6041 default qtip tip m5threads-base-regressions.diff -M5 started Apr 17 2009 00:29:37 +M5 compiled Apr 21 2009 18:04:32 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:04:58 M5 executing on zizzer -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 0689a00e0..df75bec2d 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 28911 # Simulator instruction rate (inst/s) -host_mem_usage 217084 # Number of bytes of host memory used -host_seconds 15.18 # Real time elapsed on the host -host_tick_rate 14522493 # Simulator tick rate (ticks/s) +host_inst_rate 52497 # Simulator instruction rate (inst/s) +host_mem_usage 211604 # Number of bytes of host memory used +host_seconds 8.36 # Real time elapsed on the host +host_tick_rate 26370227 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 438923 # Number of instructions simulated sim_seconds 0.000220 # Number of seconds simulated diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini index 7be5f22d7..1a2a2ab9f 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini @@ -43,11 +43,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -79,11 +78,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -166,11 +164,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -202,11 +199,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -270,11 +266,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -306,11 +301,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -374,11 +368,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -410,11 +403,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -449,11 +441,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=8 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=92 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index 26493f774..2507950f0 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 17 2009 00:22:56 -M5 revision 35b1dc26772f 6041 default qtip tip m5threads-base-regressions.diff -M5 started Apr 17 2009 00:29:53 +M5 compiled Apr 21 2009 18:04:32 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:14:35 M5 executing on zizzer -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 167b992ee..6e706304f 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 774669 # Simulator instruction rate (inst/s) -host_mem_usage 1132460 # Number of bytes of host memory used -host_seconds 0.87 # Real time elapsed on the host -host_tick_rate 100270242 # Simulator tick rate (ticks/s) +host_inst_rate 1148641 # Simulator instruction rate (inst/s) +host_mem_usage 1126984 # Number of bytes of host memory used +host_seconds 0.59 # Real time elapsed on the host +host_tick_rate 148677785 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 677340 # Number of instructions simulated sim_seconds 0.000088 # Number of seconds simulated diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index 3cb5f4680..c778c454d 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -160,11 +158,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -196,11 +193,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -261,11 +257,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -297,11 +292,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -362,11 +356,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -398,11 +391,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -437,11 +429,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=8 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=92 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index dd09f9142..fc28b1d81 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 17 2009 00:22:56 -M5 revision 35b1dc26772f 6041 default qtip tip m5threads-base-regressions.diff -M5 started Apr 17 2009 00:29:54 +M5 compiled Apr 21 2009 18:04:32 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:04:57 M5 executing on zizzer -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 1e2146668..36df0b10e 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 675702 # Simulator instruction rate (inst/s) -host_mem_usage 214956 # Number of bytes of host memory used -host_seconds 0.96 # Real time elapsed on the host -host_tick_rate 273465785 # Simulator tick rate (ticks/s) +host_inst_rate 700731 # Simulator instruction rate (inst/s) +host_mem_usage 209476 # Number of bytes of host memory used +host_seconds 0.93 # Real time elapsed on the host +host_tick_rate 283592249 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 650423 # Number of instructions simulated sim_seconds 0.000263 # Number of seconds simulated diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index f9dfac7de..bb5089d27 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -30,11 +30,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=12 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -78,11 +77,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=12 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -126,11 +124,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=12 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -174,11 +171,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=12 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -222,11 +218,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=12 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -270,11 +265,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=12 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -318,11 +312,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=12 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -366,11 +359,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=12 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -408,11 +400,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=8 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=92 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout index 84934c75f..0a2232d19 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:34:30 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 17:07:10 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt index 2fa4194ff..451bddd68 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 328212 # Number of bytes of host memory used -host_seconds 135.65 # Real time elapsed on the host -host_tick_rate 1982429 # Simulator tick rate (ticks/s) +host_mem_usage 326608 # Number of bytes of host memory used +host_seconds 197.86 # Real time elapsed on the host +host_tick_rate 1359114 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000269 # Number of seconds simulated sim_ticks 268915439 # Number of ticks simulated diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index 42e1d38a7..6c3647fa4 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/n/blue/z/binkert/work/m5/work/configs/boot/netperf-server.rcS +readfile=/z/stever/hg/m5/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -135,20 +135,20 @@ port=drivesys.bridge.side_a drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pi [drivesys.membus] type=Bus -children=responder +children=badaddr_responder block_size=64 bus_id=1 clock=1000 header_cycles=1 responder_set=false width=64 -default=drivesys.membus.responder.pio +default=drivesys.membus.badaddr_responder.pio port=drivesys.bridge.side_b drivesys.physmem.port[0] drivesys.cpu.icache_port drivesys.cpu.dcache_port -[drivesys.membus.responder] +[drivesys.membus.badaddr_responder] type=IsaFake pio_addr=0 -pio_latency=1 +pio_latency=1000 pio_size=8 platform=drivesys.tsunami ret_bad_addr=true @@ -718,7 +718,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/n/blue/z/binkert/work/m5/work/configs/boot/netperf-stream-client.rcS +readfile=/z/stever/hg/m5/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 @@ -839,20 +839,20 @@ port=testsys.bridge.side_a testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio t [testsys.membus] type=Bus -children=responder +children=badaddr_responder block_size=64 bus_id=1 clock=1000 header_cycles=1 responder_set=false width=64 -default=testsys.membus.responder.pio +default=testsys.membus.badaddr_responder.pio port=testsys.bridge.side_b testsys.physmem.port[0] testsys.cpu.icache_port testsys.cpu.dcache_port -[testsys.membus.responder] +[testsys.membus.badaddr_responder] type=IsaFake pio_addr=0 -pio_latency=1 +pio_latency=1000 pio_size=8 platform=testsys.tsunami ret_bad_addr=true diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout index 69dfeb8ac..28985f265 100755 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:30:05 -M5 executing on maize +M5 compiled Apr 21 2009 17:45:48 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 17:56:47 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index f97003767..ff3dc00d0 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -155,10 +155,10 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 239279638 # Simulator instruction rate (inst/s) -host_mem_usage 480276 # Number of bytes of host memory used -host_seconds 1.14 # Real time elapsed on the host -host_tick_rate 175028279617 # Simulator tick rate (ticks/s) +host_inst_rate 160898071 # Simulator instruction rate (inst/s) +host_mem_usage 480604 # Number of bytes of host memory used +host_seconds 1.70 # Real time elapsed on the host +host_tick_rate 117699865039 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273374833 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated @@ -429,10 +429,10 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 135334075743 # Simulator instruction rate (inst/s) -host_mem_usage 480276 # Number of bytes of host memory used +host_inst_rate 125057105672 # Simulator instruction rate (inst/s) +host_mem_usage 480604 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 369524213 # Simulator tick rate (ticks/s) +host_tick_rate 342026980 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273374833 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated |