X86: Update stats for the updated auxilliary vectors.

6 files changed, 102 insertions, 102 deletions

diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
index 49018d812..911046b97 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -57,7 +57,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
index d7f9758f3..8d015897b 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 25 2010 03:41:05
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 04:11:29
-M5 executing on SC2B0619
+M5 compiled May  2 2010 23:23:01
+M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
+M5 started May  2 2010 23:23:02
+M5 executing on burrito
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 5504000 because target called exit()
+Exiting @ tick 5526500 because target called exit()
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
index 8b2e120b0..296e494c2 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -1,18 +1,18 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 940985                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 185436                       # Number of bytes of host memory used
+host_inst_rate                                 940026                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 213000                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              530148334                       # Simulator tick rate (ticks/s)
+host_tick_rate                              529916579                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                        9519                       # Number of instructions simulated
+sim_insts                                        9561                       # Number of instructions simulated
 sim_seconds                                  0.000006                       # Number of seconds simulated
-sim_ticks                                     5504000                       # Number of ticks simulated
+sim_ticks                                     5526500                       # Number of ticks simulated
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                            11009                       # number of cpu cycles simulated
-system.cpu.num_insts                             9519                       # Number of instructions executed
-system.cpu.num_refs                              1987                       # Number of memory references
+system.cpu.numCycles                            11054                       # number of cpu cycles simulated
+system.cpu.num_insts                             9561                       # Number of instructions executed
+system.cpu.num_refs                              1990                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
index 64e4a7561..db5e719f3 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
index de395dbab..2a02cd35e 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 25 2010 03:41:05
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 04:11:30
-M5 executing on SC2B0619
+M5 compiled May  2 2010 23:23:01
+M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
+M5 started May  2 2010 23:23:02
+M5 executing on burrito
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 29731000 because target called exit()
+Exiting @ tick 29813000 because target called exit()
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
index a1830d00b..cc8de12ad 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -1,23 +1,23 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 605496                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 193040                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                             1857026858                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 734670                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 220588                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
+host_tick_rate                             2255655595                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                        9519                       # Number of instructions simulated
+sim_insts                                        9561                       # Number of instructions simulated
 sim_seconds                                  0.000030                       # Number of seconds simulated
-sim_ticks                                    29731000                       # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses               1053                       # number of ReadReq accesses(hits+misses)
+sim_ticks                                    29813000                       # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses               1056                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits                    999                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency        3024000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.051282                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                   54                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      2862000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.051282                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses              54                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_hits                   1001                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency        3080000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.052083                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses                   55                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency      2915000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.052083                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses              55                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses               934                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
@@ -30,102 +30,102 @@ system.cpu.dcache.WriteReq_mshr_miss_rate     0.104925                       # m
 system.cpu.dcache.WriteReq_mshr_misses             98                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  13.939850                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  13.850746                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses                1987                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses                1990                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                    1835                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency         8512000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.076497                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                   152                       # number of demand (read+write) misses
+system.cpu.dcache.demand_hits                    1837                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency         8568000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.076884                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                   153                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency      8056000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.076497                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses              152                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency      8109000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.076884                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses              153                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.019744                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0             80.872189                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses               1987                       # number of overall (read+write) accesses
+system.cpu.dcache.occ_%::0                   0.019841                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0             81.267134                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses               1990                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits                   1835                       # number of overall hits
-system.cpu.dcache.overall_miss_latency        8512000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.076497                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                  152                       # number of overall misses
+system.cpu.dcache.overall_hits                   1837                       # number of overall hits
+system.cpu.dcache.overall_miss_latency        8568000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.076884                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses                  153                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency      8056000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.076497                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses             152                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency      8109000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.076884                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses             153                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.sampled_refs                    133                       # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs                    134                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                 80.872189                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     1854                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 81.267134                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     1856                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_accesses               6887                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses               6911                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 55815.789474                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits                   6659                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits                   6683                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency       12726000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.033106                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate          0.032991                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  228                       # number of ReadReq misses
 system.cpu.icache.ReadReq_mshr_miss_latency     12042000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.033106                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate     0.032991                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             228                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                  29.206140                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                  29.311404                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses                6887                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses                6911                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency 55815.789474                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                    6659                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits                    6683                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency        12726000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.033106                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate           0.032991                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   228                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
 system.cpu.icache.demand_mshr_miss_latency     12042000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.033106                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate      0.032991                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses              228                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.052069                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            106.638328                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses               6887                       # number of overall (read+write) accesses
+system.cpu.icache.occ_%::0                   0.052030                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            106.557747                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses               6911                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 55815.789474                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits                   6659                       # number of overall hits
+system.cpu.icache.overall_hits                   6683                       # number of overall hits
 system.cpu.icache.overall_miss_latency       12726000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.033106                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate          0.032991                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  228                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_miss_latency     12042000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.033106                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate     0.032991                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses             228                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.icache.replacements                      0                       # number of replacements
 system.cpu.icache.sampled_refs                    228                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                106.638328                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     6659                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                106.557747                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     6683                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
@@ -138,16 +138,16 @@ system.cpu.l2cache.ReadExReq_misses                79                       # nu
 system.cpu.l2cache.ReadExReq_mshr_miss_latency      3160000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses           79                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses               282                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses               283                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                     1                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency      14612000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.996454                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                 281                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     11240000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.996454                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses            281                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_miss_latency      14664000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.996466                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses                 282                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency     11280000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.996466                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses            282                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_accesses             19                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_avg_miss_latency        52000                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
@@ -159,53 +159,53 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1
 system.cpu.l2cache.UpgradeReq_mshr_misses           19                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.003817                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.003802                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses                361                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses                362                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                      1                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency       18720000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.997230                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                  360                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_miss_latency       18772000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.997238                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                  361                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency     14400000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.997230                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses             360                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency     14440000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.997238                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses             361                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.003910                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0           128.120518                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses               361                       # number of overall (read+write) accesses
+system.cpu.l2cache.occ_%::0                  0.003920                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0           128.459536                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses               362                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                     1                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency      18720000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.997230                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                 360                       # number of overall misses
+system.cpu.l2cache.overall_miss_latency      18772000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.997238                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                 361                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency     14400000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.997230                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses            360                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency     14440000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.997238                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses            361                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                   262                       # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   263                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               128.120518                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               128.459536                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                            59462                       # number of cpu cycles simulated
-system.cpu.num_insts                             9519                       # Number of instructions executed
-system.cpu.num_refs                              1987                       # Number of memory references
+system.cpu.numCycles                            59626                       # number of cpu cycles simulated
+system.cpu.num_insts                             9561                       # Number of instructions executed
+system.cpu.num_refs                              1990                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------