diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-04 10:43:47 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-04 10:43:47 -0500 |
| commit | 9954eb74df98c4749651eb78098595f78d642105 (patch) | |
| tree | 74766341f05f999e2ad00626284e09dc6d0a2c58 /tests/quick | |
| parent | 67925a833445a8b2ddce0fae4c86677ce0f4298d (diff) | |
| download | gem5-9954eb74df98c4749651eb78098595f78d642105.tar.xz | |
stats: update stale config.ini files, eio and few other stats.
Diffstat (limited to 'tests/quick')
17 files changed, 899 insertions, 901 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini index 4f89807d5..4494621d8 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -87,7 +87,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -98,7 +98,6 @@ size=262144 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -128,7 +127,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -139,7 +138,6 @@ size=131072 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -178,7 +176,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -189,7 +187,6 @@ size=2097152 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini index b89f21c49..58c25e2f3 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini @@ -109,7 +109,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.branchPred] -type=BranchPredictor +type=TournamentBP BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -123,7 +123,6 @@ localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 -predType=tournament [system.cpu.dcache] type=BaseCache @@ -135,7 +134,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -146,7 +145,6 @@ size=262144 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -559,7 +557,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -570,7 +568,6 @@ size=131072 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -609,7 +606,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -620,7 +617,6 @@ size=2097152 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index 51b805140..09a1c4524 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -159,7 +159,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -170,7 +170,6 @@ size=262144 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -206,9 +205,9 @@ opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntAlu opLat=1 +pipelined=true [system.cpu.fuPool.FUList1] type=FUDesc @@ -220,16 +219,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntMult opLat=3 +pipelined=true [system.cpu.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=19 opClass=IntDiv opLat=20 +pipelined=false [system.cpu.fuPool.FUList2] type=FUDesc @@ -241,23 +240,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste [system.cpu.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatAdd opLat=2 +pipelined=true [system.cpu.fuPool.FUList2.opList1] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCmp opLat=2 +pipelined=true [system.cpu.fuPool.FUList2.opList2] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCvt opLat=2 +pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc @@ -269,23 +268,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste [system.cpu.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatMult opLat=4 +pipelined=true [system.cpu.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 -issueLat=12 opClass=FloatDiv opLat=12 +pipelined=false [system.cpu.fuPool.FUList3.opList2] type=OpDesc eventq_index=0 -issueLat=24 opClass=FloatSqrt opLat=24 +pipelined=false [system.cpu.fuPool.FUList4] type=FUDesc @@ -297,9 +296,9 @@ opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=1 +pipelined=true [system.cpu.fuPool.FUList5] type=FUDesc @@ -311,142 +310,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys [system.cpu.fuPool.FUList5.opList00] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAdd opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList01] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAddAcc opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList02] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAlu opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList03] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCmp opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList04] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCvt opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList05] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMisc opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList06] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMult opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList07] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMultAcc opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList08] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShift opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList09] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShiftAcc opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList10] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdSqrt opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList11] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAdd opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList12] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAlu opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList13] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCmp opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList14] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCvt opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList15] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatDiv opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList16] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMisc opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList17] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMult opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList18] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMultAcc opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList19] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatSqrt opLat=1 +pipelined=true [system.cpu.fuPool.FUList6] type=FUDesc @@ -458,9 +457,9 @@ opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=1 +pipelined=true [system.cpu.fuPool.FUList7] type=FUDesc @@ -472,16 +471,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=1 +pipelined=true [system.cpu.fuPool.FUList7.opList1] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=1 +pipelined=true [system.cpu.fuPool.FUList8] type=FUDesc @@ -493,9 +492,9 @@ opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc eventq_index=0 -issueLat=3 opClass=IprAccess opLat=3 +pipelined=false [system.cpu.icache] type=BaseCache @@ -507,7 +506,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -518,7 +517,6 @@ size=131072 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -557,7 +555,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -568,7 +566,6 @@ size=2097152 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini index 60f2b3295..7319a71af 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -87,7 +87,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -98,7 +98,6 @@ size=262144 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -128,7 +127,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -139,7 +138,6 @@ size=131072 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -177,7 +175,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -188,7 +186,6 @@ size=2097152 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 9d4907542..998b24edb 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -159,7 +159,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -170,7 +170,6 @@ size=262144 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -206,9 +205,9 @@ opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntAlu opLat=1 +pipelined=true [system.cpu.fuPool.FUList1] type=FUDesc @@ -220,16 +219,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntMult opLat=3 +pipelined=true [system.cpu.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=19 opClass=IntDiv opLat=20 +pipelined=false [system.cpu.fuPool.FUList2] type=FUDesc @@ -241,23 +240,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste [system.cpu.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatAdd opLat=2 +pipelined=true [system.cpu.fuPool.FUList2.opList1] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCmp opLat=2 +pipelined=true [system.cpu.fuPool.FUList2.opList2] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCvt opLat=2 +pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc @@ -269,23 +268,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste [system.cpu.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatMult opLat=4 +pipelined=true [system.cpu.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 -issueLat=12 opClass=FloatDiv opLat=12 +pipelined=false [system.cpu.fuPool.FUList3.opList2] type=OpDesc eventq_index=0 -issueLat=24 opClass=FloatSqrt opLat=24 +pipelined=false [system.cpu.fuPool.FUList4] type=FUDesc @@ -297,9 +296,9 @@ opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=1 +pipelined=true [system.cpu.fuPool.FUList5] type=FUDesc @@ -311,142 +310,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys [system.cpu.fuPool.FUList5.opList00] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAdd opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList01] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAddAcc opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList02] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAlu opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList03] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCmp opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList04] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCvt opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList05] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMisc opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList06] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMult opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList07] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMultAcc opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList08] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShift opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList09] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShiftAcc opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList10] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdSqrt opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList11] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAdd opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList12] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAlu opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList13] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCmp opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList14] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCvt opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList15] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatDiv opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList16] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMisc opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList17] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMult opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList18] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMultAcc opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList19] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatSqrt opLat=1 +pipelined=true [system.cpu.fuPool.FUList6] type=FUDesc @@ -458,9 +457,9 @@ opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=1 +pipelined=true [system.cpu.fuPool.FUList7] type=FUDesc @@ -472,16 +471,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=1 +pipelined=true [system.cpu.fuPool.FUList7.opList1] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=1 +pipelined=true [system.cpu.fuPool.FUList8] type=FUDesc @@ -493,9 +492,9 @@ opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc eventq_index=0 -issueLat=3 opClass=IprAccess opLat=3 +pipelined=false [system.cpu.icache] type=BaseCache @@ -507,7 +506,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -518,7 +517,6 @@ size=131072 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -562,7 +560,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -573,7 +571,6 @@ size=2097152 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini index 392920ac8..9da046447 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -87,6 +88,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu.dtb [system.cpu.dstage2_mmu.stage2_tlb] @@ -104,7 +106,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.membus.slave[6] [system.cpu.dtb] type=ArmTLB @@ -154,6 +155,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -161,6 +163,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu.itb [system.cpu.istage2_mmu.stage2_tlb] @@ -178,7 +181,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB @@ -204,7 +206,8 @@ eventq_index=0 [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic +cwd=build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic +drivers= egid=100 env= errout=cerr @@ -213,6 +216,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -242,13 +246,16 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt index 7d45c36b9..bc136f4c7 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000727 # Nu sim_ticks 727072500 # Number of ticks simulated final_tick 727072500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 639322 # Simulator instruction rate (inst/s) -host_op_rate 639300 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 929601467 # Simulator tick rate (ticks/s) -host_mem_usage 223596 # Number of bytes of host memory used -host_seconds 0.78 # Real time elapsed on the host +host_inst_rate 1010970 # Simulator instruction rate (inst/s) +host_op_rate 1010933 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1469988465 # Simulator tick rate (ticks/s) +host_mem_usage 285244 # Number of bytes of host memory used +host_seconds 0.49 # Real time elapsed on the host sim_insts 500001 # Number of instructions simulated sim_ops 500001 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -122,14 +122,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 500019 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 287.258890 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 287.258578 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 454 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 397.182819 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 287.258890 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.070132 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 287.258578 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.070131 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.070131 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 454 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id @@ -201,14 +201,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 454 system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16852500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16852500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7436500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7436500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24289000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24289000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24289000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24289000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17010000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17010000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7506000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7506000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24516000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24516000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24516000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24516000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002531 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses @@ -217,22 +217,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 system.cpu.dcache.demand_mshr_miss_rate::total 0.002511 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002511 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 265.012564 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 265.012287 # Cycle average of tags in use system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 403 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1239.744417 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 265.012564 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 265.012287 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.129401 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.129401 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 403 # Occupied blocks per task id @@ -290,33 +290,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 403 system.cpu.icache.demand_mshr_misses::total 403 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 403 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21561000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21561000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21561000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21561000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21561000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21561000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21762500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21762500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21762500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21762500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21762500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21762500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000806 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000806 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000806 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53501.240695 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53501.240695 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53501.240695 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53501.240695 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53501.240695 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53501.240695 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54001.240695 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54001.240695 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54001.240695 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54001.240695 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54001.240695 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54001.240695 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 481.541188 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 481.539213 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 718 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 265.019216 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 216.521972 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 265.018107 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 216.521106 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008088 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006608 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.014695 # Average percentage of cache occupancy @@ -327,55 +327,60 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 714 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021912 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 7713 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 7713 # Number of data accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 315 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 718 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 139 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 139 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 403 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 403 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 315 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 315 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 403 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 454 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 857 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 403 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 454 # number of overall misses system.cpu.l2cache.overall_misses::total 857 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21158000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16537500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 37695500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7297500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 7297500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21158000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 21158000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 16537500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 16537500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 21158000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 23835000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 44993000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 21158000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 23835000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 44993000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 403 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 315 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 139 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 139 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 403 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 403 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 315 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 315 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 403 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 454 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 857 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 403 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 454 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 857 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.240695 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.696379 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.240695 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.240695 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.240695 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52500.583431 # average overall miss latency @@ -390,55 +395,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 718 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 139 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 139 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 403 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 403 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 315 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 315 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 857 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 857 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16321500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12757500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 29079000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5629500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5629500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16321500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18387000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 34708500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16321500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18387000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 34708500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5907500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5907500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17128000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17128000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13387500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13387500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17128000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19295000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 36423000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17128000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19295000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 36423000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.240695 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.240695 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.240695 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.583431 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.240695 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.583431 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 718 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 718 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 139 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 139 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 403 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 315 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 806 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 908 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 1714 # Packet count per connected master and slave (bytes) @@ -463,10 +473,10 @@ system.cpu.toL2Bus.respLayer0.occupancy 604500 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 681000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 718 # Transaction distribution system.membus.trans_dist::ReadResp 718 # Transaction distribution system.membus.trans_dist::ReadExReq 139 # Transaction distribution system.membus.trans_dist::ReadExResp 139 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 718 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54848 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini index 8ea14a565..ee3422841 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini @@ -91,7 +91,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -102,7 +102,6 @@ size=32768 system=system tags=system.cpu0.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] @@ -132,7 +131,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -143,7 +142,6 @@ size=32768 system=system tags=system.cpu0.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] @@ -236,7 +234,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -247,7 +245,6 @@ size=32768 system=system tags=system.cpu1.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.slave[3] @@ -277,7 +274,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -288,7 +285,6 @@ size=32768 system=system tags=system.cpu1.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.slave[2] @@ -381,7 +377,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -392,7 +388,6 @@ size=32768 system=system tags=system.cpu2.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu2.dcache_port mem_side=system.toL2Bus.slave[5] @@ -422,7 +417,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -433,7 +428,6 @@ size=32768 system=system tags=system.cpu2.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu2.icache_port mem_side=system.toL2Bus.slave[4] @@ -526,7 +520,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -537,7 +531,6 @@ size=32768 system=system tags=system.cpu3.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu3.dcache_port mem_side=system.toL2Bus.slave[7] @@ -567,7 +560,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -578,7 +571,6 @@ size=32768 system=system tags=system.cpu3.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu3.icache_port mem_side=system.toL2Bus.slave[6] @@ -650,7 +642,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -661,7 +653,6 @@ size=4194304 system=system tags=system.l2c.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[1] diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt index 7a94e3207..8a18a4d03 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000250 # Nu sim_ticks 250015500 # Number of ticks simulated final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1548972 # Simulator instruction rate (inst/s) -host_op_rate 1548948 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 193626740 # Simulator tick rate (ticks/s) -host_mem_usage 235568 # Number of bytes of host memory used -host_seconds 1.29 # Real time elapsed on the host +host_inst_rate 2352807 # Simulator instruction rate (inst/s) +host_op_rate 2352743 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 294103962 # Simulator tick rate (ticks/s) +host_mem_usage 298060 # Number of bytes of host memory used +host_seconds 0.85 # Real time elapsed on the host sim_insts 2000004 # Number of instructions simulated sim_ops 2000004 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -854,9 +854,9 @@ system.cpu3.icache.cache_copies 0 # nu system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.tagsinuse 1962.780232 # Cycle average of tags in use -system.l2c.tags.total_refs 332 # Total number of references to valid blocks. +system.l2c.tags.total_refs 1068 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 0.364256 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 17.466765 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 267.152061 # Average occupied blocks per requestor @@ -882,19 +882,20 @@ system.l2c.tags.age_task_id_blocks_1024::0 8 # system.l2c.tags.age_task_id_blocks_1024::1 1088 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 1836 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 34048 # Number of tag accesses -system.l2c.tags.data_accesses 34048 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::total 276 # number of ReadReq hits +system.l2c.tags.tag_accesses 39936 # Number of tag accesses +system.l2c.tags.data_accesses 39936 # Number of data accesses system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits system.l2c.Writeback_hits::total 116 # number of Writeback hits +system.l2c.ReadCleanReq_hits::cpu0.inst 60 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 60 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 60 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 60 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 240 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 36 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits @@ -913,20 +914,21 @@ system.l2c.overall_hits::cpu2.data 9 # nu system.l2c.overall_hits::cpu3.inst 60 # number of overall hits system.l2c.overall_hits::cpu3.data 9 # number of overall hits system.l2c.overall_hits::total 276 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 403 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 403 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 403 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 403 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 1612 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 315 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 315 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 315 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3.data 315 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 1260 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses @@ -945,15 +947,6 @@ system.l2c.overall_misses::cpu2.data 454 # nu system.l2c.overall_misses::cpu3.inst 403 # number of overall misses system.l2c.overall_misses::cpu3.data 454 # number of overall misses system.l2c.overall_misses::total 3428 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 116 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses) @@ -961,6 +954,16 @@ system.l2c.ReadExReq_accesses::cpu1.data 139 # nu system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 463 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 463 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 463 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu3.inst 463 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1852 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 324 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 324 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 324 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3.data 324 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1296 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses @@ -979,20 +982,21 @@ system.l2c.overall_accesses::cpu2.data 463 # nu system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.912325 # miss rate for ReadReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.870410 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.972222 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses @@ -1020,10 +1024,10 @@ system.l2c.avg_blocked_cycles::no_targets nan # a system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 2872 # Transaction distribution system.membus.trans_dist::ReadResp 2872 # Transaction distribution system.membus.trans_dist::ReadExReq 556 # Transaction distribution system.membus.trans_dist::ReadExResp 556 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2872 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes) @@ -1039,20 +1043,22 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3428 # Request fanout histogram -system.toL2Bus.trans_dist::ReadReq 3148 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution system.toL2Bus.trans_dist::Writeback 116 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 736 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7524 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadCleanReq 1852 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1296 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8260 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes) @@ -1063,7 +1069,7 @@ system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 244480 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 0 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3820 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 4556 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -1074,11 +1080,11 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 3820 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 4556 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3820 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 4556 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini index 098ebf393..7b3ac07e0 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini @@ -87,7 +87,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -98,7 +98,6 @@ size=32768 system=system tags=system.cpu0.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] @@ -128,7 +127,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -139,7 +138,6 @@ size=32768 system=system tags=system.cpu0.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] @@ -228,7 +226,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -239,7 +237,6 @@ size=32768 system=system tags=system.cpu1.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.slave[3] @@ -269,7 +266,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -280,7 +277,6 @@ size=32768 system=system tags=system.cpu1.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.slave[2] @@ -369,7 +365,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -380,7 +376,6 @@ size=32768 system=system tags=system.cpu2.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu2.dcache_port mem_side=system.toL2Bus.slave[5] @@ -410,7 +405,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -421,7 +416,6 @@ size=32768 system=system tags=system.cpu2.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu2.icache_port mem_side=system.toL2Bus.slave[4] @@ -510,7 +504,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -521,7 +515,6 @@ size=32768 system=system tags=system.cpu3.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu3.dcache_port mem_side=system.toL2Bus.slave[7] @@ -551,7 +544,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -562,7 +555,6 @@ size=32768 system=system tags=system.cpu3.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu3.icache_port mem_side=system.toL2Bus.slave[6] @@ -634,7 +626,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -645,7 +637,6 @@ size=4194304 system=system tags=system.l2c.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[1] diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt index 42278656d..640568869 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000728 # Number of seconds simulated -sim_ticks 727903500 # Number of ticks simulated -final_tick 727903500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 727902500 # Number of ticks simulated +final_tick 727902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 639540 # Simulator instruction rate (inst/s) -host_op_rate 639535 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 232760737 # Simulator tick rate (ticks/s) -host_mem_usage 235576 # Number of bytes of host memory used -host_seconds 3.13 # Real time elapsed on the host +host_inst_rate 969116 # Simulator instruction rate (inst/s) +host_op_rate 969107 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 352708611 # Simulator tick rate (ticks/s) +host_mem_usage 298060 # Number of bytes of host memory used +host_seconds 2.06 # Real time elapsed on the host sim_insts 1999978 # Number of instructions simulated sim_ops 1999978 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,29 +36,29 @@ system.physmem.num_reads::cpu2.data 454 # Nu system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 35433268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 39917379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35433268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 39917379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 35433268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 39917379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 35433268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 39917379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 301402590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 35433268 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35433268 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 35433268 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 35433268 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 141733073 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 35433268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 39917379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35433268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 39917379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 35433268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 39917379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 35433268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 39917379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 301402590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 35433317 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 39917434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35433317 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 39917434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 35433317 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 39917434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 35433317 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 39917434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 301403004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 35433317 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35433317 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 35433317 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 35433317 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 141733268 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 35433317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 39917434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 35433317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 39917434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 35433317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 39917434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 35433317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 39917434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 301403004 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses @@ -93,7 +93,7 @@ system.cpu0.itb.data_misses 0 # DT system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.workload.num_syscalls 18 # Number of system calls -system.cpu0.numCycles 1455807 # number of cpu cycles simulated +system.cpu0.numCycles 1455805 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 500001 # Number of instructions committed @@ -112,7 +112,7 @@ system.cpu0.num_mem_refs 180793 # nu system.cpu0.num_load_insts 124443 # Number of load instructions system.cpu0.num_store_insts 56350 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 1455807 # Number of busy cycles +system.cpu0.num_busy_cycles 1455805 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.Branches 59023 # Number of branches fetched @@ -152,14 +152,14 @@ system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 500019 # Class of executed instruction system.cpu0.dcache.tags.replacements 61 # number of replacements -system.cpu0.dcache.tags.tagsinuse 273.598283 # Cycle average of tags in use +system.cpu0.dcache.tags.tagsinuse 273.597897 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 273.598283 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.534372 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.534372 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 273.597897 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.534371 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.534371 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id @@ -183,14 +183,14 @@ system.cpu0.dcache.demand_misses::cpu0.data 463 # system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses system.cpu0.dcache.overall_misses::total 463 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17443000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 17443000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17442000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 17442000 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7645000 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 25088000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 25088000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 25088000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 25088000 # number of overall miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 25087000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 25087000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 25087000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 25087000 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses) @@ -207,14 +207,14 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 53836.419753 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 53836.419753 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 53833.333333 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 53833.333333 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 55000 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 54185.745140 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 54185.745140 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 54185.745140 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 54185.745140 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 54183.585313 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 54183.585313 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 54183.585313 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 54183.585313 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -233,14 +233,14 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 463 system.cpu0.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 463 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 16957000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 16957000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7436500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7436500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24393500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 24393500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24393500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 24393500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 17118000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 17118000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7506000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7506000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24624000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 24624000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24624000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 24624000 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002604 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002467 # mshr miss rate for WriteReq accesses @@ -249,24 +249,24 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002561 system.cpu0.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 52336.419753 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 52336.419753 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 53500 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 52685.745140 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 52685.745140 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52685.745140 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 52685.745140 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 52833.333333 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 52833.333333 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 54000 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 53183.585313 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 53183.585313 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 53183.585313 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 53183.585313 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 152 # number of replacements -system.cpu0.icache.tags.tagsinuse 216.437634 # Cycle average of tags in use +system.cpu0.icache.tags.tagsinuse 216.437309 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 1078.956803 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 216.437634 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.422730 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.422730 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 216.437309 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.422729 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.422729 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id @@ -322,24 +322,24 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 463 system.cpu0.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 463 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22253000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 22253000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22253000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 22253000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22253000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 22253000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22484500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 22484500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22484500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 22484500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22484500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 22484500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 48062.634989 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 48062.634989 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 48062.634989 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 48062.634989 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 48062.634989 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 48062.634989 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 48562.634989 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 48562.634989 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 48562.634989 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 48562.634989 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 48562.634989 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 48562.634989 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses @@ -374,7 +374,7 @@ system.cpu1.itb.data_misses 0 # DT system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.workload.num_syscalls 18 # Number of system calls -system.cpu1.numCycles 1455807 # number of cpu cycles simulated +system.cpu1.numCycles 1455805 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 499997 # Number of instructions committed @@ -393,7 +393,7 @@ system.cpu1.num_mem_refs 180792 # nu system.cpu1.num_load_insts 124443 # Number of load instructions system.cpu1.num_store_insts 56349 # Number of store instructions system.cpu1.num_idle_cycles 0 # Number of idle cycles -system.cpu1.num_busy_cycles 1455807 # Number of busy cycles +system.cpu1.num_busy_cycles 1455805 # Number of busy cycles system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu1.idle_fraction 0 # Percentage of idle cycles system.cpu1.Branches 59022 # Number of branches fetched @@ -433,14 +433,14 @@ system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 500015 # Class of executed instruction system.cpu1.dcache.tags.replacements 61 # number of replacements -system.cpu1.dcache.tags.tagsinuse 273.595522 # Cycle average of tags in use +system.cpu1.dcache.tags.tagsinuse 273.595136 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 180311 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 273.595522 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.534366 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.534366 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 273.595136 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.534365 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.534365 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id @@ -464,14 +464,14 @@ system.cpu1.dcache.demand_misses::cpu1.data 463 # system.cpu1.dcache.demand_misses::total 463 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 463 # number of overall misses system.cpu1.dcache.overall_misses::total 463 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 17443000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 17443000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 17442000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 17442000 # number of ReadReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7645000 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 25088000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 25088000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 25088000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 25088000 # number of overall miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 25087000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 25087000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 25087000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 25087000 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 124435 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 56339 # number of WriteReq accesses(hits+misses) @@ -488,14 +488,14 @@ system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 53836.419753 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 53836.419753 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 53833.333333 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 53833.333333 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 55000 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 54185.745140 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 54185.745140 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 54185.745140 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 54185.745140 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 54183.585313 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 54183.585313 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 54183.585313 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 54183.585313 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -514,14 +514,14 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 463 system.cpu1.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 463 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 16957000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 16957000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7436500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7436500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 24393500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 24393500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 24393500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 24393500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 17118000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 17118000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7506000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7506000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 24624000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 24624000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 24624000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 24624000 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002604 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002467 # mshr miss rate for WriteReq accesses @@ -530,24 +530,24 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002561 system.cpu1.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 52336.419753 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 52336.419753 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 53500 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 52685.745140 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 52685.745140 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 52685.745140 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 52685.745140 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 52833.333333 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 52833.333333 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54000 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 53183.585313 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 53183.585313 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 53183.585313 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 53183.585313 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 152 # number of replacements -system.cpu1.icache.tags.tagsinuse 216.435498 # Cycle average of tags in use +system.cpu1.icache.tags.tagsinuse 216.435172 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 499553 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 1078.948164 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 216.435498 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.422726 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.422726 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 216.435172 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.422725 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.422725 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id @@ -603,24 +603,24 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 463 system.cpu1.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 463 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 22258000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 22258000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 22258000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 22258000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 22258000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 22258000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 22489500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 22489500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 22489500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 22489500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 22489500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 22489500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 48073.434125 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 48073.434125 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 48073.434125 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 48073.434125 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 48073.434125 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 48073.434125 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 48573.434125 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 48573.434125 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 48573.434125 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 48573.434125 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 48573.434125 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 48573.434125 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses @@ -655,7 +655,7 @@ system.cpu2.itb.data_misses 0 # DT system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses system.cpu2.workload.num_syscalls 18 # Number of system calls -system.cpu2.numCycles 1455807 # number of cpu cycles simulated +system.cpu2.numCycles 1455805 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu2.committedInsts 499992 # Number of instructions committed @@ -674,7 +674,7 @@ system.cpu2.num_mem_refs 180792 # nu system.cpu2.num_load_insts 124443 # Number of load instructions system.cpu2.num_store_insts 56349 # Number of store instructions system.cpu2.num_idle_cycles 0 # Number of idle cycles -system.cpu2.num_busy_cycles 1455807 # Number of busy cycles +system.cpu2.num_busy_cycles 1455805 # Number of busy cycles system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu2.idle_fraction 0 # Percentage of idle cycles system.cpu2.Branches 59022 # Number of branches fetched @@ -714,14 +714,14 @@ system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::total 500010 # Class of executed instruction system.cpu2.dcache.tags.replacements 61 # number of replacements -system.cpu2.dcache.tags.tagsinuse 273.592761 # Cycle average of tags in use +system.cpu2.dcache.tags.tagsinuse 273.592374 # Cycle average of tags in use system.cpu2.dcache.tags.total_refs 180311 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. system.cpu2.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 273.592761 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.534361 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.534361 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_blocks::cpu2.data 273.592374 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.534360 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.534360 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id @@ -745,14 +745,14 @@ system.cpu2.dcache.demand_misses::cpu2.data 463 # system.cpu2.dcache.demand_misses::total 463 # number of demand (read+write) misses system.cpu2.dcache.overall_misses::cpu2.data 463 # number of overall misses system.cpu2.dcache.overall_misses::total 463 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 17443000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 17443000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 17442000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 17442000 # number of ReadReq miss cycles system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 7645000 # number of WriteReq miss cycles system.cpu2.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 25088000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 25088000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 25088000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 25088000 # number of overall miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 25087000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 25087000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 25087000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 25087000 # number of overall miss cycles system.cpu2.dcache.ReadReq_accesses::cpu2.data 124435 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::cpu2.data 56339 # number of WriteReq accesses(hits+misses) @@ -769,14 +769,14 @@ system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 53836.419753 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 53836.419753 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 53833.333333 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 53833.333333 # average ReadReq miss latency system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 55000 # average WriteReq miss latency system.cpu2.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 54185.745140 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 54185.745140 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 54185.745140 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 54185.745140 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 54183.585313 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 54183.585313 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 54183.585313 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 54183.585313 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -795,14 +795,14 @@ system.cpu2.dcache.demand_mshr_misses::cpu2.data 463 system.cpu2.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu2.dcache.overall_mshr_misses::cpu2.data 463 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 16957000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 16957000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 7436500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 7436500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 24393500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 24393500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 24393500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 24393500 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 17118000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 17118000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 7506000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 7506000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 24624000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 24624000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 24624000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 24624000 # number of overall MSHR miss cycles system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002604 # mshr miss rate for ReadReq accesses system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002467 # mshr miss rate for WriteReq accesses @@ -811,22 +811,22 @@ system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002561 system.cpu2.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for overall accesses system.cpu2.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 52336.419753 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 52336.419753 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53500 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 52685.745140 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 52685.745140 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 52685.745140 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 52685.745140 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 52833.333333 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 52833.333333 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 54000 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 53183.585313 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 53183.585313 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 53183.585313 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 53183.585313 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 152 # number of replacements -system.cpu2.icache.tags.tagsinuse 216.433362 # Cycle average of tags in use +system.cpu2.icache.tags.tagsinuse 216.433036 # Cycle average of tags in use system.cpu2.icache.tags.total_refs 499548 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. system.cpu2.icache.tags.avg_refs 1078.937365 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 216.433362 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_blocks::cpu2.inst 216.433036 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.422721 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_percent::total 0.422721 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id @@ -884,24 +884,24 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 463 system.cpu2.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 463 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 22263000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 22263000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 22263000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 22263000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 22263000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 22263000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 22494500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 22494500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 22494500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 22494500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 22494500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 22494500 # number of overall MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for ReadReq accesses system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for demand accesses system.cpu2.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for overall accesses system.cpu2.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 48084.233261 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 48084.233261 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 48084.233261 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 48084.233261 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 48084.233261 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 48084.233261 # average overall mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 48584.233261 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 48584.233261 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 48584.233261 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 48584.233261 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 48584.233261 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 48584.233261 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dtb.fetch_hits 0 # ITB hits system.cpu3.dtb.fetch_misses 0 # ITB misses @@ -936,7 +936,7 @@ system.cpu3.itb.data_misses 0 # DT system.cpu3.itb.data_acv 0 # DTB access violations system.cpu3.itb.data_accesses 0 # DTB accesses system.cpu3.workload.num_syscalls 18 # Number of system calls -system.cpu3.numCycles 1455807 # number of cpu cycles simulated +system.cpu3.numCycles 1455805 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu3.committedInsts 499988 # Number of instructions committed @@ -955,7 +955,7 @@ system.cpu3.num_mem_refs 180790 # nu system.cpu3.num_load_insts 124441 # Number of load instructions system.cpu3.num_store_insts 56349 # Number of store instructions system.cpu3.num_idle_cycles 0 # Number of idle cycles -system.cpu3.num_busy_cycles 1455807 # Number of busy cycles +system.cpu3.num_busy_cycles 1455805 # Number of busy cycles system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu3.idle_fraction 0 # Percentage of idle cycles system.cpu3.Branches 59022 # Number of branches fetched @@ -995,12 +995,12 @@ system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::total 500006 # Class of executed instruction system.cpu3.dcache.tags.replacements 61 # number of replacements -system.cpu3.dcache.tags.tagsinuse 273.589931 # Cycle average of tags in use +system.cpu3.dcache.tags.tagsinuse 273.589530 # Cycle average of tags in use system.cpu3.dcache.tags.total_refs 180309 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. system.cpu3.dcache.tags.avg_refs 389.436285 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 273.589931 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_blocks::cpu3.data 273.589530 # Average occupied blocks per requestor system.cpu3.dcache.tags.occ_percent::cpu3.data 0.534355 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_percent::total 0.534355 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id @@ -1026,14 +1026,14 @@ system.cpu3.dcache.demand_misses::cpu3.data 463 # system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses system.cpu3.dcache.overall_misses::cpu3.data 463 # number of overall misses system.cpu3.dcache.overall_misses::total 463 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 17443500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 17443500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 7645500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 7645500 # number of WriteReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 25089000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 25089000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 25089000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 25089000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 17442500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 17442500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 7645000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 25087500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 25087500 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 25087500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 25087500 # number of overall miss cycles system.cpu3.dcache.ReadReq_accesses::cpu3.data 124433 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.ReadReq_accesses::total 124433 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.WriteReq_accesses::cpu3.data 56339 # number of WriteReq accesses(hits+misses) @@ -1050,14 +1050,14 @@ system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561 system.cpu3.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 53837.962963 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 53837.962963 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 55003.597122 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 55003.597122 # average WriteReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 54187.904968 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 54187.904968 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 54187.904968 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 54187.904968 # average overall miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 53834.876543 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 53834.876543 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 55000 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 54184.665227 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 54184.665227 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 54184.665227 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 54184.665227 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1076,14 +1076,14 @@ system.cpu3.dcache.demand_mshr_misses::cpu3.data 463 system.cpu3.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu3.dcache.overall_mshr_misses::cpu3.data 463 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 16957500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 16957500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 7437000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 7437000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 24394500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 24394500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 24394500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 24394500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 17118500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 17118500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 7506000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 7506000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 24624500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 24624500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 24624500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 24624500 # number of overall MSHR miss cycles system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002604 # mshr miss rate for ReadReq accesses system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002467 # mshr miss rate for WriteReq accesses @@ -1092,24 +1092,24 @@ system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002561 system.cpu3.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002561 # mshr miss rate for overall accesses system.cpu3.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 52337.962963 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 52337.962963 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 53503.597122 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 53503.597122 # average WriteReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 52687.904968 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 52687.904968 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52687.904968 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 52687.904968 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 52834.876543 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 52834.876543 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 54000 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 53184.665227 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 53184.665227 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 53184.665227 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 53184.665227 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 152 # number of replacements -system.cpu3.icache.tags.tagsinuse 216.431169 # Cycle average of tags in use +system.cpu3.icache.tags.tagsinuse 216.430826 # Cycle average of tags in use system.cpu3.icache.tags.total_refs 499544 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. system.cpu3.icache.tags.avg_refs 1078.928726 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 216.431169 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.422717 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.422717 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 216.430826 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.422716 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.422716 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id @@ -1127,12 +1127,12 @@ system.cpu3.icache.demand_misses::cpu3.inst 463 # system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses system.cpu3.icache.overall_misses::total 463 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 22962500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 22962500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 22962500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 22962500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 22962500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 22962500 # number of overall miss cycles +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 22963000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 22963000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 22963000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 22963000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 22963000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 22963000 # number of overall miss cycles system.cpu3.icache.ReadReq_accesses::cpu3.inst 500007 # number of ReadReq accesses(hits+misses) system.cpu3.icache.ReadReq_accesses::total 500007 # number of ReadReq accesses(hits+misses) system.cpu3.icache.demand_accesses::cpu3.inst 500007 # number of demand (read+write) accesses @@ -1145,12 +1145,12 @@ system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 49595.032397 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 49595.032397 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 49595.032397 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 49595.032397 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 49595.032397 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 49595.032397 # average overall miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 49596.112311 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 49596.112311 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 49596.112311 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 49596.112311 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 49596.112311 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 49596.112311 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1165,40 +1165,40 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 463 system.cpu3.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 463 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 22268000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 22268000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 22268000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 22268000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 22268000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 22268000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 22500000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 22500000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 22500000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 22500000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 22500000 # number of overall MSHR miss cycles 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latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 48095.032397 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 48095.032397 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 48095.032397 # average overall mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 48596.112311 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 48596.112311 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 48596.112311 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 48596.112311 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 48596.112311 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 48596.112311 # average overall mshr miss latency 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occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 265.087863 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 216.562658 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 265.085095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 216.560494 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 265.082241 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 216.558304 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 17.239740 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 265.089371 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 216.563852 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 265.086602 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 216.561689 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 265.083834 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 216.559525 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 265.080948 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 216.557319 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.004045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.003305 # Average percentage of cache occupancy @@ -1208,25 +1208,26 @@ system.l2c.tags.occ_percent::cpu2.inst 0.004045 # Av system.l2c.tags.occ_percent::cpu2.data 0.003304 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.inst 0.004045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.003304 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.029661 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.029660 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 2932 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 2904 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 34048 # Number of tag accesses -system.l2c.tags.data_accesses 34048 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::total 276 # number of ReadReq hits +system.l2c.tags.tag_accesses 39936 # Number of tag accesses +system.l2c.tags.data_accesses 39936 # Number of data accesses system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits system.l2c.Writeback_hits::total 116 # number of Writeback hits +system.l2c.ReadCleanReq_hits::cpu0.inst 60 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 60 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 60 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 60 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 240 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 36 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits @@ -1245,20 +1246,21 @@ system.l2c.overall_hits::cpu2.data 9 # nu system.l2c.overall_hits::cpu3.inst 60 # number of overall hits system.l2c.overall_hits::cpu3.data 9 # number of overall hits system.l2c.overall_hits::total 276 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses -system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 403 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 403 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 403 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 403 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 1612 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 315 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 315 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 315 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3.data 315 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 1260 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses @@ -1277,47 +1279,39 @@ system.l2c.overall_misses::cpu2.data 454 # nu system.l2c.overall_misses::cpu3.inst 403 # number of overall misses system.l2c.overall_misses::cpu3.data 454 # number of overall misses system.l2c.overall_misses::total 3428 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 21158500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 16537500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 21164500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 16537500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 21169000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 16538500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 21172000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 16539000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 150816500 # number of ReadReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 7297500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 7297500 # number of ReadExReq miss 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cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 16537500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 16537500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 16537500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3.data 16538000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 66150500 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 21159000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 23835000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 21164500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 21164000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 23835000 # number of demand (read+write) miss cycles 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number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 21159000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 23835000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 21164500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 21164000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 23835000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 21169000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 23836000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 21172000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 23837000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 180007000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 463 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu2.inst 21168500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 23835000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 21172500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 23835500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 180004500 # number of overall miss cycles system.l2c.Writeback_accesses::writebacks 116 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses) @@ -1325,6 +1319,16 @@ system.l2c.ReadExReq_accesses::cpu1.data 139 # nu system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 463 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 463 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 463 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu3.inst 463 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1852 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 324 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 324 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 324 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3.data 324 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1296 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses @@ -1343,20 +1347,21 @@ system.l2c.overall_accesses::cpu2.data 463 # nu system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.912325 # miss rate for ReadReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.870410 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.972222 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses @@ -1375,38 +1380,39 @@ system.l2c.overall_miss_rate::cpu2.data 0.980562 # mi system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52502.481390 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52517.369727 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 52528.535980 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 52503.174603 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 52535.980149 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.data 52504.761905 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52512.708914 # average ReadReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52500 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52500 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52500 # average ReadExReq miss latency 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ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 42537.220844 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 42521.091811 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 42500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 42500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 42500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 42501.587302 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 42500.396825 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42503.722084 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42516.129032 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 42527.295285 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 42537.220844 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 42501.101322 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42510.064177 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42503.722084 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42516.129032 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 42527.295285 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 42537.220844 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42501.101322 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42510.064177 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 2872 # Transaction distribution system.membus.trans_dist::ReadResp 2872 # Transaction distribution system.membus.trans_dist::ReadExReq 556 # Transaction distribution system.membus.trans_dist::ReadExResp 556 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2872 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3437 # Request fanout histogram +system.membus.snoop_fanout::samples 3433 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3437 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3433 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3437 # Request fanout histogram -system.membus.reqLayer0.occupancy 3440968 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3433 # Request fanout histogram +system.membus.reqLayer0.occupancy 3438468 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) system.membus.respLayer1.occupancy 17142500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.4 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 3148 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution system.toL2Bus.trans_dist::Writeback 116 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 736 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7524 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadCleanReq 1852 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1296 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8260 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes) @@ -1591,7 +1603,7 @@ system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 244480 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 0 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3820 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 4556 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -1602,13 +1614,13 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 3820 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 4556 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3820 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2026000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4556 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2394000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 694500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 7a136e99f..679d3d472 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,48 +1,50 @@ +Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simout +Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 08:08:31 -gem5 started Apr 22 2015 08:17:28 -gem5 executing on phenom -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp +gem5 compiled Jul 3 2015 17:16:20 +gem5 started Jul 3 2015 17:20:44 +gem5 executing on ribera.cs.wisc.edu +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 1] Got lock [Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 1, Thread 2] Got lock -[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 1, Thread 2] Got lock +[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 Iteration 1 completed -[Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 2, Thread 2] Got lock +[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 Iteration 2 completed +[Iteration 3, Thread 2] Got lock +[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 3, Thread 1] Got lock [Iteration 3, Thread 1] Critical section done, previously next=3, now next=1 -[Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2 Iteration 3 completed -[Iteration 4, Thread 2] Got lock -[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 4, Thread 1] Got lock [Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 4, Thread 2] Got lock +[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2 Iteration 4 completed -[Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 5, Thread 2] Got lock +[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 5, Thread 1] Got lock +[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 Iteration 5 completed [Iteration 6, Thread 3] Got lock [Iteration 6, Thread 3] Critical section done, previously next=0, now next=3 @@ -51,12 +53,12 @@ Iteration 5 completed [Iteration 6, Thread 2] Got lock [Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 Iteration 6 completed -[Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 7, Thread 3] Got lock [Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 7, Thread 2] Got lock +[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 Iteration 7 completed [Iteration 8, Thread 3] Got lock [Iteration 8, Thread 3] Critical section done, previously next=0, now next=3 @@ -65,19 +67,19 @@ Iteration 7 completed [Iteration 8, Thread 2] Got lock [Iteration 8, Thread 2] Critical section done, previously next=1, now next=2 Iteration 8 completed -[Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 9, Thread 3] Got lock [Iteration 9, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 9, Thread 2] Got lock +[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 Iteration 9 completed -[Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 10, Thread 3] Got lock +[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 Iteration 10 completed PASSED :-) -Exiting @ tick 107944000 because target called exit() +Exiting @ tick 107900000 because target called exit() diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr index 215e9ea82..8a9724ab2 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr @@ -1,85 +1,80 @@ warn: rounding error > tolerance - 0.072760 rounded to 0 + 1.250000 rounded to 1 warn: rounding error > tolerance - 0.072760 rounded to 0 + 1.250000 rounded to 1 warn: rounding error > tolerance - 0.072760 rounded to 0 -warn: rounding error > tolerance - 0.072760 rounded to 0 -warn: rounding error > tolerance - 0.072760 rounded to 0 -warn: rounding error > tolerance - 0.072760 rounded to 0 -system.cpu2: completed 10000 read, 5361 write accesses @731568 -system.cpu5: completed 10000 read, 5557 write accesses @735340 -system.cpu3: completed 10000 read, 5535 write accesses @738863 -system.cpu6: completed 10000 read, 5476 write accesses @748316 -system.cpu0: completed 10000 read, 5560 write accesses @752250 -system.cpu4: completed 10000 read, 5465 write accesses @757289 -system.cpu7: completed 10000 read, 5564 write accesses @760144 -system.cpu1: completed 10000 read, 5530 write accesses @768416 -system.cpu5: completed 20000 read, 11151 write accesses @1477095 -system.cpu2: completed 20000 read, 10827 write accesses @1478088 -system.cpu3: completed 20000 read, 11078 write accesses @1481757 -system.cpu0: completed 20000 read, 11117 write accesses @1493889 -system.cpu6: completed 20000 read, 11080 write accesses @1512346 -system.cpu1: completed 20000 read, 11091 write accesses @1512763 -system.cpu4: completed 20000 read, 10986 write accesses @1520589 -system.cpu7: completed 20000 read, 11078 write accesses @1523748 -system.cpu5: completed 30000 read, 16568 write accesses @2200051 -system.cpu3: completed 30000 read, 16616 write accesses @2221845 -system.cpu2: completed 30000 read, 16217 write accesses @2232672 -system.cpu0: completed 30000 read, 16692 write accesses @2249618 -system.cpu1: completed 30000 read, 16648 write accesses @2263101 -system.cpu6: completed 30000 read, 16745 write accesses @2274150 -system.cpu4: completed 30000 read, 16620 write accesses @2276386 -system.cpu7: completed 30000 read, 16733 write accesses @2277359 -system.cpu5: completed 40000 read, 21987 write accesses @2947352 -system.cpu3: completed 40000 read, 22027 write accesses @2968674 -system.cpu1: completed 40000 read, 22148 write accesses @2995890 -system.cpu0: completed 40000 read, 22166 write accesses @2998152 -system.cpu2: completed 40000 read, 21828 write accesses @3001342 -system.cpu7: completed 40000 read, 22152 write accesses @3022463 -system.cpu6: completed 40000 read, 22388 write accesses @3028895 -system.cpu4: completed 40000 read, 22197 write accesses @3031091 -system.cpu5: completed 50000 read, 27444 write accesses @3696748 -system.cpu3: completed 50000 read, 27708 write accesses @3723471 -system.cpu1: completed 50000 read, 27649 write accesses @3746058 -system.cpu0: completed 50000 read, 27719 write accesses @3747410 -system.cpu2: completed 50000 read, 27424 write accesses @3760076 -system.cpu7: completed 50000 read, 27568 write accesses @3771426 -system.cpu6: completed 50000 read, 28012 write accesses @3777023 -system.cpu4: completed 50000 read, 27741 write accesses @3802071 -system.cpu5: completed 60000 read, 33062 write accesses @4446684 -system.cpu3: completed 60000 read, 33331 write accesses @4487796 -system.cpu2: completed 60000 read, 33035 write accesses @4498626 -system.cpu0: completed 60000 read, 33211 write accesses @4505229 -system.cpu1: completed 60000 read, 33219 write accesses @4525223 -system.cpu6: completed 60000 read, 33545 write accesses @4528416 -system.cpu7: completed 60000 read, 33210 write accesses @4528425 -system.cpu4: completed 60000 read, 33325 write accesses @4560641 -system.cpu5: completed 70000 read, 38698 write accesses @5188287 -system.cpu2: completed 70000 read, 38579 write accesses @5235379 -system.cpu7: completed 70000 read, 38633 write accesses @5255909 -system.cpu0: completed 70000 read, 38682 write accesses @5255973 -system.cpu6: completed 70000 read, 38964 write accesses @5261147 -system.cpu3: completed 70000 read, 38993 write accesses @5267174 -system.cpu1: completed 70000 read, 38888 write accesses @5283161 -system.cpu4: completed 70000 read, 38789 write accesses @5300670 -system.cpu5: completed 80000 read, 44039 write accesses @5937946 -system.cpu2: completed 80000 read, 43995 write accesses @5990383 -system.cpu7: completed 80000 read, 44179 write accesses @5992827 -system.cpu0: completed 80000 read, 44154 write accesses @6000956 -system.cpu6: completed 80000 read, 44514 write accesses @6013988 -system.cpu3: completed 80000 read, 44595 write accesses @6025710 -system.cpu1: completed 80000 read, 44663 write accesses @6042332 -system.cpu4: completed 80000 read, 44390 write accesses @6048987 -system.cpu5: completed 90000 read, 49553 write accesses @6694237 -system.cpu7: completed 90000 read, 49635 write accesses @6734659 -system.cpu2: completed 90000 read, 49508 write accesses @6735285 -system.cpu0: completed 90000 read, 49652 write accesses @6748849 -system.cpu6: completed 90000 read, 50083 write accesses @6767267 -system.cpu1: completed 90000 read, 50078 write accesses @6778899 -system.cpu3: completed 90000 read, 50108 write accesses @6783497 -system.cpu4: completed 90000 read, 50077 write accesses @6811616 -system.cpu5: completed 100000 read, 55112 write accesses @7430292 + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +system.cpu0: completed 10000 read, 5514 write accesses @985789 +system.cpu5: completed 10000 read, 5507 write accesses @985919 +system.cpu6: completed 10000 read, 5525 write accesses @1001074 +system.cpu2: completed 10000 read, 5599 write accesses @1007601 +system.cpu7: completed 10000 read, 5498 write accesses @1017943 +system.cpu4: completed 10000 read, 5572 write accesses @1024769 +system.cpu3: completed 10000 read, 5732 write accesses @1028309 +system.cpu1: completed 10000 read, 5598 write accesses @1041015 +system.cpu6: completed 20000 read, 11013 write accesses @1989998 +system.cpu0: completed 20000 read, 11024 write accesses @2017508 +system.cpu5: completed 20000 read, 11122 write accesses @2018515 +system.cpu2: completed 20000 read, 11126 write accesses @2025419 +system.cpu7: completed 20000 read, 11093 write accesses @2029349 +system.cpu3: completed 20000 read, 11390 write accesses @2036754 +system.cpu4: completed 20000 read, 11097 write accesses @2052341 +system.cpu1: completed 20000 read, 11255 write accesses @2071888 +system.cpu6: completed 30000 read, 16509 write accesses @3011316 +system.cpu2: completed 30000 read, 16563 write accesses @3015985 +system.cpu5: completed 30000 read, 16732 write accesses @3020048 +system.cpu7: completed 30000 read, 16594 write accesses @3039745 +system.cpu0: completed 30000 read, 16606 write accesses @3046317 +system.cpu4: completed 30000 read, 16705 write accesses @3051495 +system.cpu3: completed 30000 read, 17008 write accesses @3067438 +system.cpu1: completed 30000 read, 16891 write accesses @3109610 +system.cpu6: completed 40000 read, 22039 write accesses @4020333 +system.cpu5: completed 40000 read, 22236 write accesses @4027724 +system.cpu0: completed 40000 read, 22043 write accesses @4029762 +system.cpu2: completed 40000 read, 22161 write accesses @4031183 +system.cpu7: completed 40000 read, 22213 write accesses @4045977 +system.cpu4: completed 40000 read, 22298 write accesses @4082210 +system.cpu1: completed 40000 read, 22453 write accesses @4117416 +system.cpu3: completed 40000 read, 22664 write accesses @4121694 +system.cpu0: completed 50000 read, 27441 write accesses @5028972 +system.cpu6: completed 50000 read, 27572 write accesses @5030451 +system.cpu2: completed 50000 read, 27699 write accesses @5051990 +system.cpu5: completed 50000 read, 27966 write accesses @5054641 +system.cpu7: completed 50000 read, 27735 write accesses @5066083 +system.cpu4: completed 50000 read, 27771 write accesses @5088978 +system.cpu1: completed 50000 read, 28051 write accesses @5134928 +system.cpu3: completed 50000 read, 28027 write accesses @5145143 +system.cpu0: completed 60000 read, 32887 write accesses @6041088 +system.cpu6: completed 60000 read, 33047 write accesses @6052178 +system.cpu2: completed 60000 read, 33145 write accesses @6054126 +system.cpu5: completed 60000 read, 33467 write accesses @6058058 +system.cpu7: completed 60000 read, 33424 write accesses @6096363 +system.cpu4: completed 60000 read, 33328 write accesses @6102072 +system.cpu1: completed 60000 read, 33536 write accesses @6144667 +system.cpu3: completed 60000 read, 33718 write accesses @6194345 +system.cpu0: completed 70000 read, 38267 write accesses @7037253 +system.cpu6: completed 70000 read, 38604 write accesses @7069613 +system.cpu2: completed 70000 read, 38746 write accesses @7078099 +system.cpu5: completed 70000 read, 38936 write accesses @7088735 +system.cpu7: completed 70000 read, 39098 write accesses @7112647 +system.cpu4: completed 70000 read, 38903 write accesses @7119773 +system.cpu1: completed 70000 read, 39029 write accesses @7174150 +system.cpu3: completed 70000 read, 39351 write accesses @7212543 +system.cpu0: completed 80000 read, 43876 write accesses @8054755 +system.cpu6: completed 80000 read, 44096 write accesses @8081739 +system.cpu2: completed 80000 read, 44227 write accesses @8083983 +system.cpu5: completed 80000 read, 44434 write accesses @8095705 +system.cpu4: completed 80000 read, 44434 write accesses @8124001 +system.cpu7: completed 80000 read, 44724 write accesses @8128965 +system.cpu1: completed 80000 read, 44680 write accesses @8204951 +system.cpu3: completed 80000 read, 44871 write accesses @8248185 +system.cpu0: completed 90000 read, 49513 write accesses @9064097 +system.cpu2: completed 90000 read, 49820 write accesses @9098554 +system.cpu6: completed 90000 read, 49787 write accesses @9103948 +system.cpu5: completed 90000 read, 49985 write accesses @9122270 +system.cpu4: completed 90000 read, 50071 write accesses @9151457 +system.cpu7: completed 90000 read, 50244 write accesses @9162765 +system.cpu1: completed 90000 read, 50351 write accesses @9237663 +system.cpu3: completed 90000 read, 50544 write accesses @9266852 +system.cpu0: completed 100000 read, 54903 write accesses @10084846 diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt index 4a69b5566..ed5bb3990 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.010085 # Nu sim_ticks 10084846 # Number of ticks simulated final_tick 10084846 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 135609 # Simulator tick rate (ticks/s) -host_mem_usage 534216 # Number of bytes of host memory used -host_seconds 74.37 # Real time elapsed on the host +host_tick_rate 104409 # Simulator tick rate (ticks/s) +host_mem_usage 528428 # Number of bytes of host memory used +host_seconds 96.59 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39539520 # Number of bytes read from this memory @@ -301,12 +301,12 @@ system.cpu6.num_writes 55095 # nu system.cpu7.num_reads 99126 # number of read accesses completed system.cpu7.num_writes 55305 # number of write accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.delayHist::bucket_size 2048 # delay histogram for all message -system.ruby.delayHist::max_bucket 20479 # delay histogram for all message +system.ruby.delayHist::bucket_size 32 # delay histogram for all message +system.ruby.delayHist::max_bucket 319 # delay histogram for all message system.ruby.delayHist::samples 4974912 # delay histogram for all message -system.ruby.delayHist::mean 203.140608 # delay histogram for all message -system.ruby.delayHist::stdev 582.111066 # delay histogram for all message -system.ruby.delayHist | 4834308 97.17% 97.17% | 133920 2.69% 99.87% | 6363 0.13% 99.99% | 304 0.01% 100.00% | 15 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::mean 6.256499 # delay histogram for all message +system.ruby.delayHist::stdev 16.952716 # delay histogram for all message +system.ruby.delayHist | 4677586 94.02% 94.02% | 147880 2.97% 97.00% | 114262 2.30% 99.29% | 31173 0.63% 99.92% | 3456 0.07% 99.99% | 420 0.01% 100.00% | 102 0.00% 100.00% | 25 0.00% 100.00% | 7 0.00% 100.00% | 1 0.00% 100.00% # delay histogram for all message system.ruby.delayHist::total 4974912 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 @@ -942,12 +942,12 @@ system.ruby.network.routers10.throttle9.msg_count.Response_Control::1 3960 system.ruby.network.routers10.throttle9.msg_bytes.Control::0 4942480 system.ruby.network.routers10.throttle9.msg_bytes.Response_Data::1 15964704 system.ruby.network.routers10.throttle9.msg_bytes.Response_Control::1 3168552 -system.ruby.delayVCHist.vnet_0::bucket_size 2048 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::max_bucket 20479 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::bucket_size 32 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::max_bucket 319 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::samples 1568858 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 640.119386 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 891.952930 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 1428254 91.04% 91.04% | 133920 8.54% 99.57% | 6363 0.41% 99.98% | 304 0.02% 100.00% | 15 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 15.791935 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 27.289154 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 1272075 81.08% 81.08% | 147337 9.39% 90.47% | 114262 7.28% 97.76% | 31173 1.99% 99.74% | 3456 0.22% 99.96% | 420 0.03% 99.99% | 102 0.01% 100.00% | 25 0.00% 100.00% | 7 0.00% 100.00% | 1 0.00% 100.00% # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::total 1568858 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 8 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 79 # delay histogram for vnet_1 diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini index 27d9847c3..c0e4f3cf5 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini @@ -71,7 +71,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -82,7 +82,6 @@ size=32768 system=system tags=system.cpu0.l1c.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.port mem_side=system.toL2Bus.slave[0] @@ -124,7 +123,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -135,7 +134,6 @@ size=32768 system=system tags=system.cpu1.l1c.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu1.port mem_side=system.toL2Bus.slave[1] @@ -177,7 +175,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -188,7 +186,6 @@ size=32768 system=system tags=system.cpu2.l1c.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu2.port mem_side=system.toL2Bus.slave[2] @@ -230,7 +227,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -241,7 +238,6 @@ size=32768 system=system tags=system.cpu3.l1c.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu3.port mem_side=system.toL2Bus.slave[3] @@ -283,7 +279,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -294,7 +290,6 @@ size=32768 system=system tags=system.cpu4.l1c.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu4.port mem_side=system.toL2Bus.slave[4] @@ -336,7 +331,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -347,7 +342,6 @@ size=32768 system=system tags=system.cpu5.l1c.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu5.port mem_side=system.toL2Bus.slave[5] @@ -389,7 +383,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -400,7 +394,6 @@ size=32768 system=system tags=system.cpu6.l1c.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu6.port mem_side=system.toL2Bus.slave[6] @@ -442,7 +435,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -453,7 +446,6 @@ size=32768 system=system tags=system.cpu7.l1c.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu7.port mem_side=system.toL2Bus.slave[7] @@ -494,7 +486,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -505,7 +497,6 @@ size=65536 system=system tags=system.l2c.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[0] diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini index 5186e7456..7aa95bb02 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -82,10 +83,11 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -96,7 +98,6 @@ size=262144 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -122,10 +123,11 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -136,7 +138,6 @@ size=131072 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -170,10 +171,11 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -184,7 +186,6 @@ size=2097152 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -203,8 +204,11 @@ size=2097152 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 @@ -218,7 +222,8 @@ eventq_index=0 [system.cpu.workload] type=LiveProcess cmd=vortex bendian.raw -cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing +cwd=build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing +drivers= egid=100 env= errout=cerr @@ -227,6 +232,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/vortex gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -256,11 +262,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt index f5fe53ea2..7015cfc4c 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000323 # Nu sim_ticks 322881 # Number of ticks simulated final_tick 322881 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 2952595 # Simulator tick rate (ticks/s) -host_mem_usage 447776 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_tick_rate 2211083 # Simulator tick rate (ticks/s) +host_mem_usage 441516 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54144 # Number of bytes read from this memory @@ -264,12 +264,12 @@ system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.delayHist::bucket_size 512 # delay histogram for all message -system.ruby.delayHist::max_bucket 5119 # delay histogram for all message +system.ruby.delayHist::bucket_size 4 # delay histogram for all message +system.ruby.delayHist::max_bucket 39 # delay histogram for all message system.ruby.delayHist::samples 6760 # delay histogram for all message -system.ruby.delayHist::mean 50.962278 # delay histogram for all message -system.ruby.delayHist::stdev 238.173200 # delay histogram for all message -system.ruby.delayHist | 6512 96.33% 96.33% | 158 2.34% 98.67% | 46 0.68% 99.35% | 24 0.36% 99.70% | 9 0.13% 99.84% | 8 0.12% 99.96% | 2 0.03% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% # delay histogram for all message +system.ruby.delayHist::mean 0.896450 # delay histogram for all message +system.ruby.delayHist::stdev 2.643920 # delay histogram for all message +system.ruby.delayHist | 5999 88.74% 88.74% | 459 6.79% 95.53% | 195 2.88% 98.42% | 74 1.09% 99.51% | 23 0.34% 99.85% | 5 0.07% 99.93% | 3 0.04% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message system.ruby.delayHist::total 6760 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 @@ -481,12 +481,12 @@ system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 8 system.ruby.network.routers3.throttle2.msg_bytes.Control::0 6768 system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 54216 system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 712 -system.ruby.delayVCHist.vnet_0::bucket_size 512 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::max_bucket 5119 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::samples 2420 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 141.339256 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 381.793770 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 2172 89.75% 89.75% | 158 6.53% 96.28% | 46 1.90% 98.18% | 24 0.99% 99.17% | 9 0.37% 99.55% | 8 0.33% 99.88% | 2 0.08% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 1 0.04% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 1.485950 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 3.479612 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 2005 82.85% 82.85% | 204 8.43% 91.28% | 133 5.50% 96.78% | 53 2.19% 98.97% | 17 0.70% 99.67% | 5 0.21% 99.88% | 1 0.04% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::total 2420 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 4 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 39 # delay histogram for vnet_1 |