diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 16:55:47 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 16:55:47 +0100 |
| commit | dafec4a51542b76a926b390f0cafa6c715a54c49 (patch) | |
| tree | b9088b609725b87ec1ef5f6a5359b3454ed4519c /tests/quick | |
| parent | c661cc75eca97989d72c513550b7a63e995a3982 (diff) | |
| download | gem5-dafec4a51542b76a926b390f0cafa6c715a54c49.tar.xz | |
stats: update and fix e273e86a873d
Diffstat (limited to 'tests/quick')
34 files changed, 13957 insertions, 467 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index 85c0f1360..a1b437e07 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu sim_ticks 2783854535000 # Number of ticks simulated final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1008697 # Simulator instruction rate (inst/s) -host_op_rate 1227927 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19668230366 # Simulator tick rate (ticks/s) -host_mem_usage 576064 # Number of bytes of host memory used -host_seconds 141.54 # Real time elapsed on the host +host_inst_rate 787133 # Simulator instruction rate (inst/s) +host_op_rate 958208 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15348024787 # Simulator tick rate (ticks/s) +host_mem_usage 576068 # Number of bytes of host memory used +host_seconds 181.38 # Real time elapsed on the host sim_insts 142771651 # Number of instructions simulated sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -119,9 +119,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31525949 # DTB read hits +system.cpu.dtb.read_hits 31525950 # DTB read hits system.cpu.dtb.read_misses 8580 # DTB read misses -system.cpu.dtb.write_hits 23124104 # DTB write hits +system.cpu.dtb.write_hits 23124105 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -132,12 +132,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534529 # DTB read accesses -system.cpu.dtb.write_accesses 23125552 # DTB write accesses +system.cpu.dtb.read_accesses 31534530 # DTB read accesses +system.cpu.dtb.write_accesses 23125553 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54650053 # DTB hits +system.cpu.dtb.hits 54650055 # DTB hits system.cpu.dtb.misses 10028 # DTB misses -system.cpu.dtb.accesses 54660081 # DTB accesses +system.cpu.dtb.accesses 54660083 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -220,7 +220,7 @@ system.cpu.num_conditional_control_insts 18730275 # nu system.cpu.num_int_insts 153161279 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions system.cpu.num_int_register_reads 285057575 # number of times the integer registers were read -system.cpu.num_int_register_writes 107178464 # number of times the integer registers were written +system.cpu.num_int_register_writes 107178468 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written system.cpu.num_cc_register_reads 530849543 # number of times the CC registers were read @@ -270,9 +270,9 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class::total 177218432 # Class of executed instruction system.cpu.dcache.tags.replacements 819392 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53783870 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 53783872 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.597765 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.597768 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -282,22 +282,22 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219235080 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219235080 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 30128800 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30128800 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22339791 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22339791 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 219235088 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219235088 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 30128801 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30128801 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22339792 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22339792 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52468591 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52468591 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52863656 # number of overall hits -system.cpu.dcache.overall_hits::total 52863656 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 52468593 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52468593 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52863658 # number of overall hits +system.cpu.dcache.overall_hits::total 52863658 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 396281 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 396281 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses @@ -312,20 +312,20 @@ system.cpu.dcache.demand_misses::cpu.data 697944 # n system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses system.cpu.dcache.overall_misses::total 814065 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525081 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525081 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641454 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641454 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 30525082 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525082 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641455 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641455 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53166535 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53166535 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53677721 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53677721 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 53166537 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53166537 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53677723 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53677723 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 9e43d8fd4..317518f92 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.802883 # Nu sim_ticks 2802882797500 # Number of ticks simulated final_tick 2802882797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 797664 # Simulator instruction rate (inst/s) -host_op_rate 971941 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15227033289 # Simulator tick rate (ticks/s) -host_mem_usage 590380 # Number of bytes of host memory used -host_seconds 184.07 # Real time elapsed on the host +host_inst_rate 748827 # Simulator instruction rate (inst/s) +host_op_rate 912434 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14294755935 # Simulator tick rate (ticks/s) +host_mem_usage 590384 # Number of bytes of host memory used +host_seconds 196.08 # Real time elapsed on the host sim_insts 146828219 # Number of instructions simulated sim_ops 178907974 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -138,9 +138,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 system.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 20339693 # DTB read hits +system.cpu0.dtb.read_hits 20339694 # DTB read hits system.cpu0.dtb.read_misses 6871 # DTB read misses -system.cpu0.dtb.write_hits 16391003 # DTB write hits +system.cpu0.dtb.write_hits 16391004 # DTB write hits system.cpu0.dtb.write_misses 1093 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -151,12 +151,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 20346564 # DTB read accesses -system.cpu0.dtb.write_accesses 16392096 # DTB write accesses +system.cpu0.dtb.read_accesses 20346565 # DTB read accesses +system.cpu0.dtb.write_accesses 16392097 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 36730696 # DTB hits +system.cpu0.dtb.hits 36730698 # DTB hits system.cpu0.dtb.misses 7964 # DTB misses -system.cpu0.dtb.accesses 36738660 # DTB accesses +system.cpu0.dtb.accesses 36738662 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -239,7 +239,7 @@ system.cpu0.num_conditional_control_insts 13204192 # n system.cpu0.num_int_insts 100762477 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions system.cpu0.num_int_register_reads 182456959 # number of times the integer registers were read -system.cpu0.num_int_register_writes 69135393 # number of times the integer registers were written +system.cpu0.num_int_register_writes 69135397 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written system.cpu0.num_cc_register_reads 349970686 # number of times the CC registers were read @@ -289,9 +289,9 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu0.op_class::total 116881836 # Class of executed instruction system.cpu0.dcache.tags.replacements 693478 # number of replacements system.cpu0.dcache.tags.tagsinuse 494.853458 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 35932313 # Total number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 35932315 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 693990 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.776413 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.776416 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853458 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy @@ -301,22 +301,22 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 74113669 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 74113669 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 19108530 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 19108530 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15690319 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15690319 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 74113673 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 74113673 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 19108531 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 19108531 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15690320 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15690320 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346085 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 346085 # number of SoftPFReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379623 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 379623 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363046 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 363046 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34798849 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34798849 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35144934 # number of overall hits -system.cpu0.dcache.overall_hits::total 35144934 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 34798851 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34798851 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35144936 # number of overall hits +system.cpu0.dcache.overall_hits::total 35144936 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 373100 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 373100 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 295799 # number of WriteReq misses @@ -331,20 +331,20 @@ system.cpu0.dcache.demand_misses::cpu0.data 668899 # system.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses system.cpu0.dcache.overall_misses::total 769220 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481630 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 19481630 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986118 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15986118 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481631 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 19481631 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986119 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 15986119 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446406 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 446406 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386363 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 386363 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381477 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 381477 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 35467748 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 35467748 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 35914154 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 35914154 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 35467750 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 35467750 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 35914156 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 35914156 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 491924c10..422d7eb7f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu sim_ticks 2783854535000 # Number of ticks simulated final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 888036 # Simulator instruction rate (inst/s) -host_op_rate 1081042 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17315504636 # Simulator tick rate (ticks/s) -host_mem_usage 573724 # Number of bytes of host memory used -host_seconds 160.77 # Real time elapsed on the host +host_inst_rate 766060 # Simulator instruction rate (inst/s) +host_op_rate 932555 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14937129777 # Simulator tick rate (ticks/s) +host_mem_usage 573732 # Number of bytes of host memory used +host_seconds 186.37 # Real time elapsed on the host sim_insts 142771651 # Number of instructions simulated sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -119,9 +119,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31525949 # DTB read hits +system.cpu.dtb.read_hits 31525950 # DTB read hits system.cpu.dtb.read_misses 8580 # DTB read misses -system.cpu.dtb.write_hits 23124104 # DTB write hits +system.cpu.dtb.write_hits 23124105 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -132,12 +132,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534529 # DTB read accesses -system.cpu.dtb.write_accesses 23125552 # DTB write accesses +system.cpu.dtb.read_accesses 31534530 # DTB read accesses +system.cpu.dtb.write_accesses 23125553 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54650053 # DTB hits +system.cpu.dtb.hits 54650055 # DTB hits system.cpu.dtb.misses 10028 # DTB misses -system.cpu.dtb.accesses 54660081 # DTB accesses +system.cpu.dtb.accesses 54660083 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -220,7 +220,7 @@ system.cpu.num_conditional_control_insts 18730275 # nu system.cpu.num_int_insts 153161279 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions system.cpu.num_int_register_reads 285057575 # number of times the integer registers were read -system.cpu.num_int_register_writes 107178464 # number of times the integer registers were written +system.cpu.num_int_register_writes 107178468 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written system.cpu.num_cc_register_reads 530849543 # number of times the CC registers were read @@ -270,9 +270,9 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class::total 177218432 # Class of executed instruction system.cpu.dcache.tags.replacements 819392 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53783870 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 53783872 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.597765 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.597768 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -282,22 +282,22 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219235080 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219235080 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 30128800 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30128800 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22339791 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22339791 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 219235088 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219235088 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 30128801 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30128801 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22339792 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22339792 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52468591 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52468591 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52863656 # number of overall hits -system.cpu.dcache.overall_hits::total 52863656 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 52468593 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52468593 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52863658 # number of overall hits +system.cpu.dcache.overall_hits::total 52863658 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 396281 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 396281 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses @@ -312,20 +312,20 @@ system.cpu.dcache.demand_misses::cpu.data 697944 # n system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses system.cpu.dcache.overall_misses::total 814065 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525081 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525081 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641454 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641454 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 30525082 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525082 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641455 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641455 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53166535 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53166535 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53677721 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53677721 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 53166537 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53166537 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53677723 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53677723 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 89a189084..2dd6529c6 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -4,13 +4,13 @@ sim_seconds 2.869789 # Nu sim_ticks 2869788970000 # Number of ticks simulated final_tick 2869788970000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 543935 # Simulator instruction rate (inst/s) -host_op_rate 657921 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11865725522 # Simulator tick rate (ticks/s) -host_mem_usage 611884 # Number of bytes of host memory used -host_seconds 241.86 # Real time elapsed on the host -sim_insts 131553572 # Number of instructions simulated -sim_ops 159121620 # Number of ops (including micro ops) simulated +host_inst_rate 480288 # Simulator instruction rate (inst/s) +host_op_rate 580935 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10477281069 # Simulator tick rate (ticks/s) +host_mem_usage 611892 # Number of bytes of host memory used +host_seconds 273.91 # Real time elapsed on the host +sim_insts 131553574 # Number of instructions simulated +sim_ops 159121622 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory @@ -286,12 +286,12 @@ system.physmem.wrPerTurnAround::172-175 2 0.03% 99.97% # Wr system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 6684 # Writes before turning the bus around for reads -system.physmem.totQLat 4572923146 # Total ticks spent queuing -system.physmem.totMemAccLat 8287466896 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4572903146 # Total ticks spent queuing +system.physmem.totMemAccLat 8287446896 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 990545000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23082.86 # Average queueing delay per DRAM burst +system.physmem.avgQLat 23082.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41832.86 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 41832.76 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s @@ -313,28 +313,28 @@ system.physmem_0.preEnergy 190001625 # En system.physmem_0.readEnergy 823219800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 453593520 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 84729045645 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647547992750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1921532542260 # Total energy per rank (pJ) +system.physmem_0.actBackEnergy 84729042225 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647547995750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1921532541840 # Total energy per rank (pJ) system.physmem_0.averagePower 669.573415 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2740710561422 # Time in different power states +system.physmem_0.memoryStateTime::IDLE 2740710565422 # Time in different power states system.physmem_0.memoryStateTime::REF 95828460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33249852578 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33249848578 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 326047680 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 177903000 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 722022600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 425178720 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 84061532610 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1648133530500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1921286682870 # Total energy per rank (pJ) +system.physmem_1.actBackEnergy 84061530045 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648133532750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1921286682555 # Total energy per rank (pJ) system.physmem_1.averagePower 669.487743 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2741691176386 # Time in different power states +system.physmem_1.memoryStateTime::IDLE 2741691180386 # Time in different power states system.physmem_1.memoryStateTime::REF 95828460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32266572364 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32266568364 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -425,9 +425,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6549 system.cpu0.dtb.walker.walkRequestOrigin::total 14492 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25156507 # DTB read hits +system.cpu0.dtb.read_hits 25156508 # DTB read hits system.cpu0.dtb.read_misses 6829 # DTB read misses -system.cpu0.dtb.write_hits 18749940 # DTB write hits +system.cpu0.dtb.write_hits 18749941 # DTB write hits system.cpu0.dtb.write_misses 1114 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -438,12 +438,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 1731 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25163336 # DTB read accesses -system.cpu0.dtb.write_accesses 18751054 # DTB write accesses +system.cpu0.dtb.read_accesses 25163337 # DTB read accesses +system.cpu0.dtb.write_accesses 18751055 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 43906447 # DTB hits +system.cpu0.dtb.hits 43906449 # DTB hits system.cpu0.dtb.misses 7943 # DTB misses -system.cpu0.dtb.accesses 43914390 # DTB accesses +system.cpu0.dtb.accesses 43914392 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -533,19 +533,19 @@ system.cpu0.numWorkItemsStarted 0 # nu system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed -system.cpu0.committedInsts 115352403 # Number of instructions committed -system.cpu0.committedOps 139380192 # Number of ops (including micro ops) committed +system.cpu0.committedInsts 115352405 # Number of instructions committed +system.cpu0.committedOps 139380194 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 123360698 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9756 # Number of float alu accesses system.cpu0.num_func_calls 12675179 # number of times a function call or return occured system.cpu0.num_conditional_control_insts 15700187 # number of instructions that are conditional controls system.cpu0.num_int_insts 123360698 # number of integer instructions system.cpu0.num_fp_insts 9756 # number of float instructions -system.cpu0.num_int_register_reads 227087076 # number of times the integer registers were read -system.cpu0.num_int_register_writes 85717148 # number of times the integer registers were written +system.cpu0.num_int_register_reads 227087077 # number of times the integer registers were read +system.cpu0.num_int_register_writes 85717152 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7496 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 504942673 # number of times the CC registers were read +system.cpu0.num_cc_register_reads 504942676 # number of times the CC registers were read system.cpu0.num_cc_register_writes 52291767 # number of times the CC registers were written system.cpu0.num_mem_refs 45042977 # number of memory refs system.cpu0.num_load_insts 25408336 # Number of load instructions @@ -592,9 +592,9 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu0.op_class::total 143145074 # Class of executed instruction system.cpu0.dcache.tags.replacements 692159 # number of replacements system.cpu0.dcache.tags.tagsinuse 489.914647 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43035504 # Total number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 43035506 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 692671 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 62.129790 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 62.129793 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.914647 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956865 # Average percentage of cache occupancy @@ -604,22 +604,22 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 103 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88449495 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88449495 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 23895287 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23895287 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 18018355 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18018355 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 88449499 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88449499 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 23895288 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23895288 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 18018356 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18018356 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319106 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 319106 # number of SoftPFReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365501 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 365501 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362365 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 362365 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 41913642 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41913642 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 42232748 # number of overall hits -system.cpu0.dcache.overall_hits::total 42232748 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 41913644 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41913644 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 42232750 # number of overall hits +system.cpu0.dcache.overall_hits::total 42232750 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 396096 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 396096 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 325040 # number of WriteReq misses @@ -634,8 +634,8 @@ system.cpu0.dcache.demand_misses::cpu0.data 721136 # system.cpu0.dcache.demand_misses::total 721136 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 848828 # number of overall misses system.cpu0.dcache.overall_misses::total 848828 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5078700000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5078700000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5078698000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5078698000 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5729362000 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 5729362000 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 329182500 # number of LoadLockedReq miss cycles @@ -644,24 +644,24 @@ system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472585500 system.cpu0.dcache.StoreCondReq_miss_latency::total 472585500 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1446500 # number of StoreCondFailReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1446500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 10808062000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 10808062000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 10808062000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 10808062000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291383 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 24291383 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 18343395 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 18343395 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 10808060000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 10808060000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 10808060000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 10808060000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291384 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24291384 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18343396 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18343396 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446798 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 446798 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387085 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 387085 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382166 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 382166 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 42634778 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42634778 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 43081576 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43081576 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 42634780 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42634780 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 43081578 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43081578 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016306 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.016306 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017720 # miss rate for WriteReq accesses @@ -676,8 +676,8 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016914 system.cpu0.dcache.demand_miss_rate::total 0.016914 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019703 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.019703 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12821.891663 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12821.891663 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12821.886613 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12821.886613 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17626.636722 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 17626.636722 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15251.227761 # average LoadLockedReq miss latency @@ -686,10 +686,10 @@ system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23866.749154 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23866.749154 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14987.550199 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14987.550199 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12732.923513 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12732.923513 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14987.547425 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14987.547425 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12732.921157 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12732.921157 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -726,8 +726,8 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28463 system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60255 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4312933000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4312933000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4312931000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4312931000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5404322000 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5404322000 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1615427000 # number of SoftPFReq MSHR miss cycles @@ -738,10 +738,10 @@ system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452825500 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452825500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1405500 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1405500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9717255000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9717255000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11332682000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11332682000 # number of overall MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9717253000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9717253000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11332680000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11332680000 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628901000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628901000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628901000 # number of overall MSHR uncacheable cycles @@ -760,8 +760,8 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016321 system.cpu0.dcache.demand_mshr_miss_rate::total 0.016321 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018484 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.018484 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11631.050236 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11631.050236 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11631.044842 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11631.044842 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16626.636722 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16626.636722 # average WriteReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16076.779921 # average SoftPFReq mshr miss latency @@ -772,10 +772,10 @@ system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22868.819757 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22868.819757 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13964.542748 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13964.542748 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14231.066362 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14231.066362 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13964.539873 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13964.539873 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14231.063850 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14231.063850 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208508.461248 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208508.461248 # average ReadReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110014.123309 # average overall mshr uncacheable latency @@ -977,18 +977,18 @@ system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2047795000 system.cpu0.l2cache.ReadExReq_miss_latency::total 2047795000 # number of ReadExReq miss cycles system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2416123000 # number of ReadCleanReq miss cycles system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2416123000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2805930000 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2805930000 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2805928000 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2805928000 # number of ReadSharedReq miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5649500 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3340000 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2416123000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 4853725000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 7278837500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 4853723000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 7278835500 # number of demand (read+write) miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5649500 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3340000 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2416123000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 4853725000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 7278837500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 4853723000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 7278835500 # number of overall miss cycles system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10462 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4713 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::total 15175 # number of ReadReq accesses(hits+misses) @@ -1056,18 +1056,18 @@ system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47834.501285 system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47834.501285 # average ReadExReq miss latency system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53359.606890 # average ReadCleanReq miss latency system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53359.606890 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29797.381248 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29797.381248 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29797.360009 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29797.360009 # average ReadSharedReq miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35434.598509 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 39857.178450 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35434.583908 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 39857.167498 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35434.598509 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 39857.178450 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35434.583908 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 39857.167498 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1124,8 +1124,8 @@ system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69277 system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2500000 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 6793500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13785840950 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13785840950 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13785822950 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13785822950 # number of HardPFReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1059758500 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1059758500 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 304568000 # number of SCUpgradeReq MSHR miss cycles @@ -1136,19 +1136,19 @@ system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1683019500 system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1683019500 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2144443000 # number of ReadCleanReq MSHR miss cycles system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2144443000 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2236277000 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2236277000 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2236275000 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2236275000 # number of ReadSharedReq MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2500000 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2144443000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3919296500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 6070533000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3919294500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 6070531000 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2500000 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2144443000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3919296500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13785840950 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 19856373950 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3919294500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13785822950 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 19856353950 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 743751500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6374150500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7117902000 # number of ReadReq MSHR uncacheable cycles @@ -1186,8 +1186,8 @@ system.cpu0.l2cache.overall_mshr_miss_rate::total 0.236165 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 18561.475410 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.869237 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53108.869237 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.799894 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53108.799894 # average HardPFReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19237.556274 # average UpgradeReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19237.556274 # average UpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15382.999141 # average SCUpgradeReq mshr miss latency @@ -1198,19 +1198,19 @@ system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40410.571936 system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40410.571936 # average ReadExReq mshr miss latency system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average ReadCleanReq mshr miss latency system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47359.606890 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23755.558388 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23755.558388 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23755.537143 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23755.537143 # average ReadSharedReq mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28863.987186 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33459.182830 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28863.972456 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33459.171806 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28863.987186 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.869237 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45024.974490 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28863.972456 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.799894 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45024.929140 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200495.423377 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174398.539717 # average ReadReq mshr uncacheable latency @@ -2512,30 +2512,30 @@ system.l2c.ReadExReq_miss_latency::total 1749515500 # nu system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 703500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 174000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1440677500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 776893500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 776891500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.inst 189843000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.data 77251000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 16119848689 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 16119828689 # number of ReadSharedReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 703500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 174000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.inst 1440677500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1864554000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1864552000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 189843000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 739106000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 17869364189 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 17869344189 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 703500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 174000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.inst 1440677500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1864554000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1864552000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 189843000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 739106000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of overall miss cycles -system.l2c.overall_miss_latency::total 17869364189 # number of overall miss cycles +system.l2c.overall_miss_latency::total 17869344189 # number of overall miss cycles system.l2c.WritebackDirty_accesses::writebacks 260994 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackDirty_accesses::total 260994 # number of WritebackDirty accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 40660 # number of UpgradeReq accesses(hits+misses) @@ -2628,30 +2628,30 @@ system.l2c.ReadExReq_avg_miss_latency::total 90185.860096 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 100500 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 87000 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 81824.132447 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87665.707515 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87665.481833 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82973.339161 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90246.495327 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 95084.401110 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 95084.283138 # average ReadSharedReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100500 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 92167.770638 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 92167.671775 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 94581.430199 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 94581.324341 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100500 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 92167.770638 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 92167.671775 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 94581.430199 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 94581.324341 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2732,30 +2732,30 @@ system.l2c.ReadExReq_mshr_miss_latency::total 1555525500 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 633500 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 154000 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1264511501 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 688273500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 688271500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 166489000 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 68690501 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 14423954199 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 14423934199 # number of ReadSharedReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 633500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 154000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.inst 1264511501 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 1662254000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1662252000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 166489000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 650235501 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 15979479699 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 15979459699 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 633500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 154000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 1264511501 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 1662254000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1662252000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 166489000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 650235501 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 15979479699 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 15979459699 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 581355000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801887500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11263000 # number of ReadReq MSHR uncacheable cycles @@ -2816,30 +2816,30 @@ system.l2c.ReadExReq_avg_mshr_miss_latency::total 80185.860096 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77665.707515 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77665.481833 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80245.912383 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85088.039022 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85087.921041 # average ReadSharedReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82167.770638 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82167.671775 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 84584.657278 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 84584.551411 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82167.770638 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82167.671775 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 84584.657278 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 84584.551411 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182495.203196 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average ReadReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index db033150d..e1254a2d4 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,13 +4,13 @@ sim_seconds 2.909587 # Nu sim_ticks 2909586837500 # Number of ticks simulated final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 581636 # Simulator instruction rate (inst/s) -host_op_rate 701272 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15048595995 # Simulator tick rate (ticks/s) -host_mem_usage 573724 # Number of bytes of host memory used -host_seconds 193.35 # Real time elapsed on the host -sim_insts 112457033 # Number of instructions simulated -sim_ops 135588117 # Number of ops (including micro ops) simulated +host_inst_rate 495886 # Simulator instruction rate (inst/s) +host_op_rate 597884 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12830006266 # Simulator tick rate (ticks/s) +host_mem_usage 573732 # Number of bytes of host memory used +host_seconds 226.78 # Real time elapsed on the host +sim_insts 112457035 # Number of instructions simulated +sim_ops 135588119 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory @@ -261,12 +261,12 @@ system.physmem.wrPerTurnAround::148-151 1 0.02% 99.89% # Wr system.physmem.wrPerTurnAround::160-163 4 0.07% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-179 2 0.04% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5615 # Writes before turning the bus around for reads -system.physmem.totQLat 1624802000 # Total ticks spent queuing -system.physmem.totMemAccLat 4747089500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1624800000 # Total ticks spent queuing +system.physmem.totMemAccLat 4747087500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 832610000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9757.28 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9757.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28507.28 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28507.27 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s @@ -302,14 +302,14 @@ system.physmem_1.preEnergy 116362125 # En system.physmem_1.readEnergy 596668800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 370733760 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 190039717920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88049301345 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1668512802000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1947898845990 # Total energy per rank (pJ) +system.physmem_1.actBackEnergy 88049300490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668512802750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947898845885 # Total energy per rank (pJ) system.physmem_1.averagePower 669.477277 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2775567504000 # Time in different power states +system.physmem_1.memoryStateTime::IDLE 2775567506000 # Time in different power states system.physmem_1.memoryStateTime::REF 97157320000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 36861865500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36861863500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -389,9 +389,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7382 system.cpu.dtb.walker.walkRequestOrigin::total 16928 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24520655 # DTB read hits +system.cpu.dtb.read_hits 24520656 # DTB read hits system.cpu.dtb.read_misses 8124 # DTB read misses -system.cpu.dtb.write_hits 19606816 # DTB write hits +system.cpu.dtb.write_hits 19606817 # DTB write hits system.cpu.dtb.write_misses 1422 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -402,12 +402,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24528779 # DTB read accesses -system.cpu.dtb.write_accesses 19608238 # DTB write accesses +system.cpu.dtb.read_accesses 24528780 # DTB read accesses +system.cpu.dtb.write_accesses 19608239 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44127471 # DTB hits +system.cpu.dtb.hits 44127473 # DTB hits system.cpu.dtb.misses 9546 # DTB misses -system.cpu.dtb.accesses 44137017 # DTB accesses +system.cpu.dtb.accesses 44137019 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -491,19 +491,19 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu.committedInsts 112457033 # Number of instructions committed -system.cpu.committedOps 135588117 # Number of ops (including micro ops) committed +system.cpu.committedInsts 112457035 # Number of instructions committed +system.cpu.committedOps 135588119 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 119893391 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses system.cpu.num_func_calls 9892146 # number of times a function call or return occured system.cpu.num_conditional_control_insts 15230571 # number of instructions that are conditional controls system.cpu.num_int_insts 119893391 # number of integer instructions system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218063465 # number of times the integer registers were read -system.cpu.num_int_register_writes 82646448 # number of times the integer registers were written +system.cpu.num_int_register_reads 218063466 # number of times the integer registers were read +system.cpu.num_int_register_writes 82646452 # number of times the integer registers were written system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489743456 # number of times the CC registers were read +system.cpu.num_cc_register_reads 489743459 # number of times the CC registers were read system.cpu.num_cc_register_writes 51893999 # number of times the CC registers were written system.cpu.num_mem_refs 45407924 # number of memory refs system.cpu.num_load_insts 24843119 # Number of load instructions @@ -550,9 +550,9 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class::total 138708215 # Class of executed instruction system.cpu.dcache.tags.replacements 819223 # number of replacements system.cpu.dcache.tags.tagsinuse 511.702328 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43236235 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 43236237 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 819735 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.744161 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.744164 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.702328 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy @@ -563,22 +563,22 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177112671 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177112671 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23112983 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23112983 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18824226 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18824226 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 177112679 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177112679 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23112984 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23112984 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18824227 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18824227 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 392786 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 392786 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 443250 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 443250 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460223 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460223 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41937209 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41937209 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42329995 # number of overall hits -system.cpu.dcache.overall_hits::total 42329995 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 41937211 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41937211 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42329997 # number of overall hits +system.cpu.dcache.overall_hits::total 42329997 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 399912 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 399912 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 298709 # number of WriteReq misses @@ -605,20 +605,20 @@ system.cpu.dcache.demand_miss_latency::cpu.data 25589348500 system.cpu.dcache.demand_miss_latency::total 25589348500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 25589348500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 25589348500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23512895 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23512895 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19122935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19122935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 23512896 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23512896 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19122936 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19122936 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 511167 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 511167 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466006 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 466006 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460225 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42635830 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42635830 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43146997 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43146997 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 42635832 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42635832 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43146999 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43146999 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017008 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.017008 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015620 # miss rate for WriteReq accesses @@ -760,12 +760,12 @@ system.cpu.icache.demand_misses::cpu.inst 1696239 # n system.cpu.icache.demand_misses::total 1696239 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1696239 # number of overall misses system.cpu.icache.overall_misses::total 1696239 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24272134000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24272134000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24272134000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24272134000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24272134000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24272134000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24272132000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24272132000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24272132000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24272132000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24272132000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24272132000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 115554258 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 115554258 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 115554258 # number of demand (read+write) accesses @@ -778,12 +778,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.014679 system.cpu.icache.demand_miss_rate::total 0.014679 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.014679 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.014679 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.383289 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14309.383289 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14309.383289 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14309.383289 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.382109 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14309.382109 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.382109 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14309.382109 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.382109 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14309.382109 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -802,12 +802,12 @@ system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22575895000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22575895000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22575895000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22575895000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22575895000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22575895000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22575893000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22575893000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22575893000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22575893000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22575893000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22575893000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1142541000 # number of overall MSHR uncacheable cycles @@ -818,12 +818,12 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014679 system.cpu.icache.demand_mshr_miss_rate::total 0.014679 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.014679 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.383289 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.383289 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.382109 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.382109 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.382109 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.382109 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.382109 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.382109 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency @@ -914,20 +914,20 @@ system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16382558000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 16382558000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2351294500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2351294500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2351292500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2351292500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1615422500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 1615422500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 957500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 266000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2351294500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2351292500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 17997980500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20350498500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20350496500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 957500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 266000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2351294500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 2351292500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 17997980500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20350498500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20350496500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7814 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4041 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 11855 # number of ReadReq accesses(hits+misses) @@ -987,20 +987,20 @@ system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127082.280298 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127082.280298 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130787.323395 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130787.323395 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130787.212148 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130787.212148 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132705.372546 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132705.372546 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130787.323395 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130787.212148 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 127931.820611 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 127931.808038 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130787.323395 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130787.212148 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 127931.820611 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 127931.808038 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1049,20 +1049,20 @@ system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 139000 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15093428000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15093428000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2171514500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2171514500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2171512500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2171512500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1493692500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1493692500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 887500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 246000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171514500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171512500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16587120500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18759768500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18759766500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 887500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 246000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171514500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171512500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16587120500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18759768500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18759766500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888804000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918570000 # number of ReadReq MSHR uncacheable cycles @@ -1101,20 +1101,20 @@ system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117082.280298 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117082.280298 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.323395 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.323395 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.212148 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.212148 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122705.372546 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122705.372546 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.212148 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.808038 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.212148 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.808038 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.532404 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.149402 # average ReadReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index bc56e0971..cde05e946 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783854 # Nu sim_ticks 2783853866500 # Number of ticks simulated final_tick 2783853866500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 806647 # Simulator instruction rate (inst/s) -host_op_rate 981963 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15728650419 # Simulator tick rate (ticks/s) -host_mem_usage 576800 # Number of bytes of host memory used -host_seconds 176.99 # Real time elapsed on the host +host_inst_rate 760140 # Simulator instruction rate (inst/s) +host_op_rate 925348 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14821821018 # Simulator tick rate (ticks/s) +host_mem_usage 577060 # Number of bytes of host memory used +host_seconds 187.82 # Real time elapsed on the host sim_insts 142770436 # Number of instructions simulated sim_ops 173800089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -136,9 +136,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4680 system.cpu0.dtb.walker.walkRequestOrigin::total 10381 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 15997245 # DTB read hits +system.cpu0.dtb.read_hits 15997246 # DTB read hits system.cpu0.dtb.read_misses 4805 # DTB read misses -system.cpu0.dtb.write_hits 11281011 # DTB write hits +system.cpu0.dtb.write_hits 11281012 # DTB write hits system.cpu0.dtb.write_misses 896 # DTB write misses system.cpu0.dtb.flush_tlb 2813 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA @@ -149,12 +149,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 769 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 202 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 16002050 # DTB read accesses -system.cpu0.dtb.write_accesses 11281907 # DTB write accesses +system.cpu0.dtb.read_accesses 16002051 # DTB read accesses +system.cpu0.dtb.write_accesses 11281908 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 27278256 # DTB hits +system.cpu0.dtb.hits 27278258 # DTB hits system.cpu0.dtb.misses 5701 # DTB misses -system.cpu0.dtb.accesses 27283957 # DTB accesses +system.cpu0.dtb.accesses 27283959 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -237,7 +237,7 @@ system.cpu0.num_conditional_control_insts 9459738 # n system.cpu0.num_int_insts 77491639 # number of integer instructions system.cpu0.num_fp_insts 5273 # number of float instructions system.cpu0.num_int_register_reads 144069521 # number of times the integer registers were read -system.cpu0.num_int_register_writes 54447635 # number of times the integer registers were written +system.cpu0.num_int_register_writes 54447639 # number of times the integer registers were written system.cpu0.num_fp_register_reads 4051 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written system.cpu0.num_cc_register_reads 268878195 # number of times the CC registers were read @@ -287,9 +287,9 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu0.op_class::total 89752341 # Class of executed instruction system.cpu0.dcache.tags.replacements 819388 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 53783376 # Total number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 53783378 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 819900 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 65.597483 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 65.597485 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.830508 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.166666 # Average occupied blocks per requestor @@ -301,14 +301,14 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 219233084 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 219233084 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15305417 # number of ReadReq hits +system.cpu0.dcache.tags.tag_accesses 219233092 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 219233092 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15305418 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 14823075 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 30128492 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10893994 # number of WriteReq hits +system.cpu0.dcache.ReadReq_hits::total 30128493 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10893995 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu1.data 11445651 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 22339645 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 22339646 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185752 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209291 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 395043 # number of SoftPFReq hits @@ -318,12 +318,12 @@ system.cpu0.dcache.LoadLockedReq_hits::total 457316 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236694 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223428 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26199411 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 26199413 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu1.data 26268726 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 52468137 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26385163 # number of overall hits +system.cpu0.dcache.demand_hits::total 52468139 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 26385165 # number of overall hits system.cpu0.dcache.overall_hits::cpu1.data 26478017 # number of overall hits -system.cpu0.dcache.overall_hits::total 52863180 # number of overall hits +system.cpu0.dcache.overall_hits::total 52863182 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 197452 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu1.data 198861 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 396313 # number of ReadReq misses @@ -344,12 +344,12 @@ system.cpu0.dcache.demand_misses::total 697978 # nu system.cpu0.dcache.overall_misses::cpu0.data 389311 # number of overall misses system.cpu0.dcache.overall_misses::cpu1.data 424732 # number of overall misses system.cpu0.dcache.overall_misses::total 814043 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502869 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502870 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu1.data 15021936 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 30524805 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 11031501 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 30524806 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 11031502 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609809 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 22641310 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 22641311 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240104 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 271004 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 511108 # number of SoftPFReq accesses(hits+misses) @@ -359,12 +359,12 @@ system.cpu0.dcache.LoadLockedReq_accesses::total 465945 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236694 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223430 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 26534370 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 26534372 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu1.data 26631745 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 53166115 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 26774474 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::total 53166117 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 26774476 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu1.data 26902749 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 53677223 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 53677225 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012736 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013238 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 0b3858068..444bbfba5 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -4,13 +4,13 @@ sim_seconds 2.903880 # Nu sim_ticks 2903879904500 # Number of ticks simulated final_tick 2903879904500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 558564 # Simulator instruction rate (inst/s) -host_op_rate 673462 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14421337908 # Simulator tick rate (ticks/s) -host_mem_usage 577056 # Number of bytes of host memory used -host_seconds 201.36 # Real time elapsed on the host -sim_insts 112472356 # Number of instructions simulated -sim_ops 135608165 # Number of ops (including micro ops) simulated +host_inst_rate 505304 # Simulator instruction rate (inst/s) +host_op_rate 609246 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13046252349 # Simulator tick rate (ticks/s) +host_mem_usage 577060 # Number of bytes of host memory used +host_seconds 222.58 # Real time elapsed on the host +sim_insts 112472358 # Number of instructions simulated +sim_ops 135608167 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory @@ -291,12 +291,12 @@ system.physmem.wrPerTurnAround::176-179 1 0.02% 99.97% # Wr system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5814 # Writes before turning the bus around for reads -system.physmem.totQLat 1475229250 # Total ticks spent queuing -system.physmem.totMemAccLat 4623710500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1475227250 # Total ticks spent queuing +system.physmem.totMemAccLat 4623708500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 839595000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8785.36 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8785.35 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27535.36 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27535.35 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.70 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s @@ -584,9 +584,9 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu0.op_class::total 68839780 # Class of executed instruction system.cpu0.dcache.tags.replacements 819212 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.827217 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43241766 # Total number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 43241768 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 819724 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.751616 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.751619 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1013369500 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 311.161528 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu1.data 200.665688 # Average occupied blocks per requestor @@ -599,14 +599,14 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::1 369 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177132709 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177132709 # Number of data accesses +system.cpu0.dcache.tags.tag_accesses 177132717 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 177132717 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 11490299 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11626239 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23116538 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 11626240 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23116539 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 9270780 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9555063 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18825843 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 9555064 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18825844 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200211 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::cpu1.data 192673 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 392884 # number of SoftPFReq hits @@ -617,11 +617,11 @@ system.cpu0.dcache.StoreCondReq_hits::cpu0.data 232922 system.cpu0.dcache.StoreCondReq_hits::cpu1.data 227346 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 460268 # number of StoreCondReq hits system.cpu0.dcache.demand_hits::cpu0.data 20761079 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 21181302 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41942381 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 21181304 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41942383 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.data 20961290 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21373975 # number of overall hits -system.cpu0.dcache.overall_hits::total 42335265 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 21373977 # number of overall hits +system.cpu0.dcache.overall_hits::total 42335267 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 199689 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu1.data 200118 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 399807 # number of ReadReq misses @@ -660,11 +660,11 @@ system.cpu0.dcache.overall_miss_latency::cpu0.data 8732466000 system.cpu0.dcache.overall_miss_latency::cpu1.data 9861594500 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 18594060500 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 11689988 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 11826357 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23516345 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 11826358 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23516346 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 9413501 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9710991 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19124492 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9710992 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19124493 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 257183 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 253897 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 511080 # number of SoftPFReq accesses(hits+misses) @@ -675,11 +675,11 @@ system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 232924 system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 227346 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 460270 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.data 21103489 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 21537348 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42640837 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 21537350 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42640839 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 21360672 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 21791245 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43151917 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 21791247 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43151919 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.017082 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.016921 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.017001 # miss rate for ReadReq accesses @@ -878,14 +878,14 @@ system.cpu0.icache.overall_misses::cpu0.inst 854412 system.cpu0.icache.overall_misses::cpu1.inst 844092 # number of overall misses system.cpu0.icache.overall_misses::total 1698504 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11714597500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11693316500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 23407914000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11693314500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 23407912000 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu0.inst 11714597500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 11693316500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 23407914000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 11693314500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 23407912000 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu0.inst 11714597500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 11693316500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 23407914000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 11693314500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 23407912000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 57466570 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu1.inst 58103866 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 115570436 # number of ReadReq accesses(hits+misses) @@ -905,14 +905,14 @@ system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014868 system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014527 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.014697 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13710.712747 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13853.130346 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13781.488887 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13853.127977 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13781.487709 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13710.712747 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13853.130346 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13781.488887 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13853.127977 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13781.487709 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13710.712747 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13853.130346 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13781.488887 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13853.127977 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13781.487709 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -935,14 +935,14 @@ system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10860185500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10849224500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 21709410000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10849222500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 21709408000 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10860185500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10849224500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 21709410000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10849222500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 21709408000 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10860185500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10849224500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 21709410000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10849222500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 21709408000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 687287000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 687287000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 687287000 # number of overall MSHR uncacheable cycles @@ -957,14 +957,14 @@ system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014868 system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014527 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.014697 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12710.712747 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12853.130346 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12781.488887 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12853.127977 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12781.487709 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12710.712747 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12853.130346 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12781.488887 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12853.127977 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12781.487709 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12710.712747 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12853.130346 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12781.488887 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12853.127977 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12781.487709 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 76179.006872 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 76179.006872 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 76179.006872 # average overall mshr uncacheable latency @@ -1034,9 +1034,9 @@ system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5422 system.cpu1.dtb.walker.walkRequestOrigin::total 11977 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12327133 # DTB read hits +system.cpu1.dtb.read_hits 12327134 # DTB read hits system.cpu1.dtb.read_misses 5631 # DTB read misses -system.cpu1.dtb.write_hits 9951025 # DTB write hits +system.cpu1.dtb.write_hits 9951026 # DTB write hits system.cpu1.dtb.write_misses 924 # DTB write misses system.cpu1.dtb.flush_tlb 2933 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA @@ -1047,12 +1047,12 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 895 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 222 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12332764 # DTB read accesses -system.cpu1.dtb.write_accesses 9951949 # DTB write accesses +system.cpu1.dtb.read_accesses 12332765 # DTB read accesses +system.cpu1.dtb.write_accesses 9951950 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 22278158 # DTB hits +system.cpu1.dtb.hits 22278160 # DTB hits system.cpu1.dtb.misses 6555 # DTB misses -system.cpu1.dtb.accesses 22284713 # DTB accesses +system.cpu1.dtb.accesses 22284715 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1138,19 +1138,19 @@ system.cpu1.numWorkItemsStarted 0 # nu system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 56542374 # Number of instructions committed -system.cpu1.committedOps 68331078 # Number of ops (including micro ops) committed +system.cpu1.committedInsts 56542376 # Number of instructions committed +system.cpu1.committedOps 68331080 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 60434186 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5384 # Number of float alu accesses system.cpu1.num_func_calls 4958421 # number of times a function call or return occured system.cpu1.num_conditional_control_insts 7671718 # number of instructions that are conditional controls system.cpu1.num_int_insts 60434186 # number of integer instructions system.cpu1.num_fp_insts 5384 # number of float instructions -system.cpu1.num_int_register_reads 109968089 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41558580 # number of times the integer registers were written +system.cpu1.num_int_register_reads 109968090 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41558584 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3965 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1422 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 246670954 # number of times the CC registers were read +system.cpu1.num_cc_register_reads 246670957 # number of times the CC registers were read system.cpu1.num_cc_register_writes 26165253 # number of times the CC registers were written system.cpu1.num_mem_refs 22910809 # number of memory refs system.cpu1.num_load_insts 12487681 # Number of load instructions @@ -1510,8 +1510,8 @@ system.l2c.ReadExReq_miss_latency::cpu0.data 4487898000 system.l2c.ReadExReq_miss_latency::cpu1.data 5568339500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 10056237500 # number of ReadExReq miss cycles system.l2c.ReadCleanReq_miss_latency::cpu0.inst 663327500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 794140000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1457467500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 794138000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1457465500 # number of ReadCleanReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.data 478260000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.data 540016500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::total 1018276500 # number of ReadSharedReq miss cycles @@ -1521,18 +1521,18 @@ system.l2c.demand_miss_latency::cpu0.inst 663327500 # n system.l2c.demand_miss_latency::cpu0.data 4966158000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 447000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.itb.walker 83500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 794140000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 794138000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 6108356000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 12532847000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 12532845000 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 251000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 84000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.inst 663327500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 4966158000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 447000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.itb.walker 83500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 794140000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 794138000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 6108356000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 12532847000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 12532845000 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 6059 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 3328 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 5254 # number of ReadReq accesses(hits+misses) @@ -1625,8 +1625,8 @@ system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77402.907849 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76857.688061 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 77100.056735 # average ReadExReq miss latency system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 81479.855055 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80688.884373 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 81046.961019 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80688.681162 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 81046.849803 # average ReadCleanReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 84933.404369 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 83671.599008 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::total 84259.536616 # average ReadSharedReq miss latency @@ -1636,18 +1636,18 @@ system.l2c.demand_avg_miss_latency::cpu0.inst 81479.855055 system.l2c.demand_avg_miss_latency::cpu0.data 78069.515186 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89400 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 80688.884373 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 80688.681162 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 77415.035993 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 78081.895719 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 78081.883259 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83666.666667 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 84000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 81479.855055 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 78069.515186 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89400 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 80688.884373 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 80688.681162 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 77415.035993 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 78081.895719 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 78081.883259 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1718,8 +1718,8 @@ system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3908088000 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4843839500 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 8751927500 # number of ReadExReq MSHR miss cycles system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 581917500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 695720000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1277637500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 695718000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1277635500 # number of ReadCleanReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 421950000 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 475476500 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::total 897426500 # number of ReadSharedReq MSHR miss cycles @@ -1729,18 +1729,18 @@ system.l2c.demand_mshr_miss_latency::cpu0.inst 581917500 system.l2c.demand_mshr_miss_latency::cpu0.data 4330038000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 397000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 73500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 695720000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 695718000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 5319316000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 10927757000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 10927755000 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 221000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 74000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 581917500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.data 4330038000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 397000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 73500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 695720000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 695718000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 5319316000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 10927757000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 10927755000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 574512000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2654142000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3237757500 # number of ReadReq MSHR uncacheable cycles @@ -1800,8 +1800,8 @@ system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67402.907849 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66857.688061 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 67100.056735 # average ReadExReq mshr miss latency system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71479.855055 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70688.884373 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71046.961019 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70688.681162 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71046.849803 # average ReadCleanReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74933.404369 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73671.599008 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74259.536616 # average ReadSharedReq mshr miss latency @@ -1811,18 +1811,18 @@ system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71479.855055 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68069.515186 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79400 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70688.884373 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70688.681162 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67415.035993 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 68081.895719 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 68081.883259 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71479.855055 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68069.515186 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79400 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70688.884373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70688.681162 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67415.035993 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 68081.895719 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 68081.883259 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63679.006872 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184008.735441 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193715.298552 # average ReadReq mshr uncacheable latency diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 8765a9cf5..203ef51d3 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 17232500 # Number of ticks simulated final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66942 # Simulator instruction rate (inst/s) -host_op_rate 78386 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 251130115 # Simulator tick rate (ticks/s) -host_mem_usage 265932 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 37479 # Simulator instruction rate (inst/s) +host_op_rate 43886 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140595410 # Simulator tick rate (ticks/s) +host_mem_usage 265936 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -791,7 +791,7 @@ system.cpu.int_regfile_writes 4270 # nu system.cpu.fp_regfile_reads 32 # number of floating regfile reads system.cpu.cc_regfile_reads 27801 # number of cc regfile reads system.cpu.cc_regfile_writes 3276 # number of cc regfile writes -system.cpu.misc_regfile_reads 3018 # number of misc regfile reads +system.cpu.misc_regfile_reads 3010 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 88.359063 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index f8ba6e8d6..17fbc7c06 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18821000 # Number of ticks simulated final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 45352 # Simulator instruction rate (inst/s) -host_op_rate 53108 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 185838458 # Simulator tick rate (ticks/s) -host_mem_usage 261708 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 22479 # Simulator instruction rate (inst/s) +host_op_rate 26323 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 92110547 # Simulator tick rate (ticks/s) +host_mem_usage 261716 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -672,7 +672,7 @@ system.cpu.int_regfile_writes 3787 # nu system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.cc_regfile_reads 24229 # number of cc regfile reads system.cpu.cc_regfile_writes 2921 # number of cc regfile writes -system.cpu.misc_regfile_reads 2586 # number of misc regfile reads +system.cpu.misc_regfile_reads 2578 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 1 # number of replacements system.cpu.dcache.tags.tagsinuse 84.368926 # Cycle average of tags in use diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index e69de29bb..917779471 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -0,0 +1,947 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000029 # Number of seconds simulated +sim_ticks 28845500 # Number of ticks simulated +final_tick 28845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 50478 # Simulator instruction rate (inst/s) +host_op_rate 50473 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 100846842 # Simulator tick rate (ticks/s) +host_mem_usage 247864 # Number of bytes of host memory used +host_seconds 0.29 # Real time elapsed on the host +sim_insts 14436 # Number of instructions simulated +sim_ops 14436 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory +system.physmem.bytes_read::total 32640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory +system.physmem.num_reads::total 510 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 805394256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 326151393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1131545648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 805394256 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 805394256 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 805394256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 326151393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1131545648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 511 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 511 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 32704 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 32704 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 105 # Per bank write bursts +system.physmem.perBankRdBursts::1 28 # Per bank write bursts +system.physmem.perBankRdBursts::2 53 # Per bank write bursts +system.physmem.perBankRdBursts::3 27 # Per bank write bursts +system.physmem.perBankRdBursts::4 23 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 32 # Per bank write bursts +system.physmem.perBankRdBursts::7 38 # Per bank write bursts +system.physmem.perBankRdBursts::8 7 # Per bank write bursts +system.physmem.perBankRdBursts::9 4 # Per bank write bursts +system.physmem.perBankRdBursts::10 2 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 57 # Per bank write bursts +system.physmem.perBankRdBursts::13 31 # Per bank write bursts +system.physmem.perBankRdBursts::14 63 # Per bank write bursts +system.physmem.perBankRdBursts::15 41 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 28814000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 511 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 412.160000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 276.286075 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.271863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 17.33% 17.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18 24.00% 41.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 12 16.00% 57.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 9.33% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5 6.67% 73.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8 10.67% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.33% 85.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 11 14.67% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation +system.physmem.totQLat 3584250 # Total ticks spent queuing +system.physmem.totMemAccLat 13165500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2555000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7014.19 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25764.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1133.76 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1133.76 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 8.86 # Data bus utilization in percentage +system.physmem.busUtilRead 8.86 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 428 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.76 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 56387.48 # Average gap between requests +system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2121600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 15733710 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 369750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 20229825 # Total energy per rank (pJ) +system.physmem_0.averagePower 856.515480 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 717750 # Time in different power states +system.physmem_0.memoryStateTime::REF 780000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27177750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 241920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 132000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1396200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 15520815 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 556500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 19373115 # Total energy per rank (pJ) +system.physmem_1.averagePower 820.243027 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4073500 # Time in different power states +system.physmem_1.memoryStateTime::REF 780000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21995000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 12618 # Number of BP lookups +system.cpu.branchPred.condPredicted 7653 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1475 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9458 # Number of BTB lookups +system.cpu.branchPred.BTBHits 0 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 736 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 9458 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 1844 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 7614 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 897 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.workload.num_syscalls 18 # Number of system calls +system.cpu.numCycles 57692 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 15531 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 59063 # Number of instructions fetch has processed +system.cpu.fetch.Branches 12618 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2580 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 17477 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3145 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 7530 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 719 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 35695 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.654658 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.906598 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22943 64.28% 64.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4506 12.62% 76.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 507 1.42% 78.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 451 1.26% 79.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 761 2.13% 81.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 707 1.98% 83.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 297 0.83% 84.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 355 0.99% 85.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5168 14.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 35695 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.218713 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.023764 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12449 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 12945 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 7933 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 796 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1572 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 42061 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1572 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13228 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1813 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9713 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 7918 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1451 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 37021 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full +system.cpu.rename.SQFullEvents 1034 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 31983 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 66431 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 54837 # Number of integer rename lookups +system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 18164 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 796 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 801 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4352 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 4576 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2922 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 15 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 28829 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 757 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 25362 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 15150 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 11340 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 35695 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.710520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.505149 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 26438 74.07% 74.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3266 9.15% 83.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1617 4.53% 87.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1544 4.33% 92.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1236 3.46% 95.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 754 2.11% 97.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 464 1.30% 98.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 276 0.77% 99.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 100 0.28% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 35695 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 153 52.04% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53 18.03% 70.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 88 29.93% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 18585 73.28% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 4271 16.84% 90.12% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2506 9.88% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 25362 # Type of FU issued +system.cpu.iq.rate 0.439610 # Inst issue rate +system.cpu.iq.fu_busy_cnt 294 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011592 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 86830 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 44763 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 22607 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 25656 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 2351 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1474 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 1572 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1846 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 31165 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 242 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 4576 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2922 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 757 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 211 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1623 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1834 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 23714 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3945 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1648 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 1579 # number of nop insts executed +system.cpu.iew.exec_refs 6244 # number of memory reference insts executed +system.cpu.iew.exec_branches 5021 # Number of branches executed +system.cpu.iew.exec_stores 2299 # Number of stores executed +system.cpu.iew.exec_rate 0.411045 # Inst execution rate +system.cpu.iew.wb_sent 23102 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 22607 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10530 # num instructions producing a value +system.cpu.iew.wb_consumers 13790 # num instructions consuming a value +system.cpu.iew.wb_rate 0.391857 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.763597 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 15914 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1475 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 32556 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.465721 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.244675 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 25812 79.28% 79.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3638 11.17% 90.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1209 3.71% 94.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 603 1.85% 96.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 337 1.04% 97.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 302 0.93% 97.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 374 1.15% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 53 0.16% 99.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 228 0.70% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 32556 # Number of insts commited each cycle +system.cpu.commit.committedInsts 15162 # Number of instructions committed +system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 3673 # Number of memory references committed +system.cpu.commit.loads 2225 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 3358 # Number of branches committed +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.int_insts 12174 # Number of committed integer instructions. +system.cpu.commit.function_calls 187 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 726 4.79% 4.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 10763 70.99% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 15162 # Class of committed instruction +system.cpu.commit.bw_lim_events 228 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 62581 # The number of ROB reads +system.cpu.rob.rob_writes 65380 # The number of ROB writes +system.cpu.timesIdled 195 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21997 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 14436 # Number of Instructions Simulated +system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 3.996398 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.996398 # CPI: Total CPI of All Threads +system.cpu.ipc 0.250225 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.250225 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 36850 # number of integer regfile reads +system.cpu.int_regfile_writes 20548 # number of integer regfile writes +system.cpu.misc_regfile_reads 8142 # number of misc regfile reads +system.cpu.misc_regfile_writes 569 # number of misc regfile writes +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 99.867537 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4648 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 31.835616 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 99.867537 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024382 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024382 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 10540 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 10540 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 3609 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3609 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 4642 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4642 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4642 # number of overall hits +system.cpu.dcache.overall_hits::total 4642 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 140 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 140 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 549 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 549 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 549 # number of overall misses +system.cpu.dcache.overall_misses::total 549 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9339500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9339500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27134481 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27134481 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36473981 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36473981 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36473981 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36473981 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3749 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3749 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 5191 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5191 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5191 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5191 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037343 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.037343 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.105760 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.105760 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.105760 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.105760 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66710.714286 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66710.714286 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66343.474328 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66343.474328 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66437.123862 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66437.123862 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1313 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.086957 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 401 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 401 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 401 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 401 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5108500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5108500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6578000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6578000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11686500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11686500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11686500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11686500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017338 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017338 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028511 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028511 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028511 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028511 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78592.307692 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78592.307692 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79253.012048 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79253.012048 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 206.414108 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 6949 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 19.038356 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 206.414108 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.100788 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.100788 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 15425 # Number of tag accesses +system.cpu.icache.tags.data_accesses 15425 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 6949 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6949 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 6949 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6949 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 6949 # number of overall hits +system.cpu.icache.overall_hits::total 6949 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 581 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 581 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 581 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 581 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 581 # number of overall misses +system.cpu.icache.overall_misses::total 581 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 40819000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 40819000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 40819000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 40819000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 40819000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 40819000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 7530 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 7530 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 7530 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 7530 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 7530 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 7530 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.077158 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.077158 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.077158 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.077158 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.077158 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.077158 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70256.454389 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70256.454389 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70256.454389 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70256.454389 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 190 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 95 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 216 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 216 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 216 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 216 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 216 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 216 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27746500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27746500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27746500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27746500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27746500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27746500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.048473 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.048473 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.048473 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76017.808219 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76017.808219 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 240.923513 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.004695 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.773852 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 35.149660 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006280 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001073 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007352 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 65 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 511 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses +system.cpu.l2cache.overall_misses::total 511 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6452500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6452500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27176000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 27176000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5013500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5013500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27176000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11466000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 38642000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27176000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11466000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 38642000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 365 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 365 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 513 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 365 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 513 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994521 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994521 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994521 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.996101 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994521 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.996101 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77740.963855 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77740.963855 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74865.013774 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74865.013774 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77130.769231 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77130.769231 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74865.013774 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75620.352250 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74865.013774 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75620.352250 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 511 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 511 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5622500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5622500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23546000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23546000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4383500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4383500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23546000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10006000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 33552000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23546000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10006000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 33552000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994521 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.996101 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.996101 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67740.963855 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67740.963855 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64865.013774 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64865.013774 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67438.461538 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67438.461538 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1024 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 513 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.003899 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.062378 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 511 99.61% 99.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 0.39% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 513 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 256500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.trans_dist::ReadResp 426 # Transaction distribution +system.membus.trans_dist::ReadExReq 83 # Transaction distribution +system.membus.trans_dist::ReadExResp 83 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 428 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1020 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 32576 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 511 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 511 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 511 # Request fanout histogram +system.membus.reqLayer0.occupancy 623500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2694000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 9.3 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index e69de29bb..036ee4f34 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -0,0 +1,124 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000008 # Number of seconds simulated +sim_ticks 7612000 # Number of ticks simulated +final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 353219 # Simulator instruction rate (inst/s) +host_op_rate 353015 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 177141347 # Simulator tick rate (ticks/s) +host_mem_usage 236080 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +sim_insts 15162 # Number of instructions simulated +sim_ops 15162 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 60828 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11342 # Number of bytes read from this memory +system.physmem.bytes_read::total 72170 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 60828 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 60828 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 9042 # Number of bytes written to this memory +system.physmem.bytes_written::total 9042 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15207 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2225 # Number of read requests responded to by this memory +system.physmem.num_reads::total 17432 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 1442 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1442 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 6 # Number of other requests responded to by this memory +system.physmem.num_other::total 6 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7991066737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1490015765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9481082501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7991066737 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7991066737 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1187861272 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1187861272 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7991066737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2677877036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10668943773 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.workload.num_syscalls 18 # Number of system calls +system.cpu.numCycles 15225 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 15162 # Number of instructions committed +system.cpu.committedOps 15162 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 385 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls +system.cpu.num_int_insts 12219 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 29037 # number of times the integer registers were read +system.cpu.num_int_register_writes 13819 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 3683 # number of memory refs +system.cpu.num_load_insts 2231 # Number of load instructions +system.cpu.num_store_insts 1452 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 15224.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 3363 # Number of branches fetched +system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction +system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction +system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 15207 # Class of executed instruction +system.membus.trans_dist::ReadReq 17432 # Transaction distribution +system.membus.trans_dist::ReadResp 17432 # Transaction distribution +system.membus.trans_dist::WriteReq 1442 # Transaction distribution +system.membus.trans_dist::WriteResp 1442 # Transaction distribution +system.membus.trans_dist::SwapReq 6 # Transaction distribution +system.membus.trans_dist::SwapResp 6 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 30414 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 7346 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 37760 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 60828 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 20442 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 81270 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 18880 # Request fanout histogram +system.membus.snoop_fanout::mean 0.805456 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.395860 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3673 19.45% 19.45% # Request fanout histogram +system.membus.snoop_fanout::1 15207 80.55% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 18880 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index e69de29bb..35f2e5918 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -0,0 +1,474 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000044 # Number of seconds simulated +sim_ticks 44282500 # Number of ticks simulated +final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 282453 # Simulator instruction rate (inst/s) +host_op_rate 282325 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 824249311 # Simulator tick rate (ticks/s) +host_mem_usage 245052 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +sim_insts 15162 # Number of instructions simulated +sim_ops 15162 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory +system.physmem.bytes_read::total 26624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory +system.physmem.num_reads::total 416 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 401784000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 199446734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 601230734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 401784000 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 401784000 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 401784000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 199446734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 601230734 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.workload.num_syscalls 18 # Number of system calls +system.cpu.numCycles 88565 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 15162 # Number of instructions committed +system.cpu.committedOps 15162 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 385 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls +system.cpu.num_int_insts 12219 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 29037 # number of times the integer registers were read +system.cpu.num_int_register_writes 13818 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 3683 # number of memory refs +system.cpu.num_load_insts 2231 # Number of load instructions +system.cpu.num_store_insts 1452 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 88564.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 3363 # Number of branches fetched +system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction +system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction +system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction +system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 15207 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 97.148649 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 97.148649 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.023718 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.023718 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits +system.cpu.dcache.overall_hits::total 3529 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses +system.cpu.dcache.overall_misses::total 138 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3286000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3286000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5270000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5270000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8556000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8556000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8556000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8556000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3233000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3233000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5185000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5185000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8418000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8418000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8418000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8418000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 151.748662 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 151.748662 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.074096 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.074096 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses +system.cpu.icache.tags.data_accesses 30696 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits +system.cpu.icache.overall_hits::total 14928 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses +system.cpu.icache.overall_misses::total 280 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17264500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17264500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17264500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17264500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17264500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17264500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61658.928571 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61658.928571 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61658.928571 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61658.928571 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16984500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16984500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16984500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16984500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16984500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16984500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60658.928571 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60658.928571 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 182.297739 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 151.068800 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.228940 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000953 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005563 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses +system.cpu.l2cache.overall_misses::total 416 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5057500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5057500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8211000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24752500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8211000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24752500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 280 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 280 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 53 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992857 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59501.201923 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59501.201923 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4207500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4207500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6831000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20592500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6831000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20592500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992857 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 280 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 53 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004785 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.069088 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 416 99.52% 99.52% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 0.48% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.trans_dist::ReadResp 331 # Transaction distribution +system.membus.trans_dist::ReadExReq 85 # Transaction distribution +system.membus.trans_dist::ReadExResp 85 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 331 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 416 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 416 # Request fanout histogram +system.membus.reqLayer0.occupancy 416500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2080000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.7 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index e69de29bb..edbbb089b 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,243 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.054141 # Number of seconds simulated +sim_ticks 54141000500 # Number of ticks simulated +final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 991860 # Simulator instruction rate (inst/s) +host_op_rate 996799 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 592702245 # Simulator tick rate (ticks/s) +host_mem_usage 389728 # Number of bytes of host memory used +host_seconds 91.35 # Real time elapsed on the host +sim_insts 90602408 # Number of instructions simulated +sim_ops 91053639 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 431323084 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory +system.physmem.bytes_read::total 521339682 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 431323084 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 431323084 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory +system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 107830771 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 22461532 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130292303 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory +system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7966662604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1662632703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9629295306 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7966662604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7966662604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 349238799 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 349238799 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7966662604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2011871502 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9978534106 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 442 # Number of system calls +system.cpu.numCycles 108282002 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 90602408 # Number of instructions committed +system.cpu.committedOps 91053639 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses +system.cpu.num_func_calls 112245 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls +system.cpu.num_int_insts 72326352 # number of integer instructions +system.cpu.num_fp_insts 48 # number of float instructions +system.cpu.num_int_register_reads 124257699 # number of times the integer registers were read +system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written +system.cpu.num_fp_register_reads 54 # number of times the floating registers were read +system.cpu.num_fp_register_writes 30 # number of times the floating registers were written +system.cpu.num_cc_register_reads 271814243 # number of times the CC registers were read +system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written +system.cpu.num_mem_refs 27220755 # number of memory refs +system.cpu.num_load_insts 22475911 # Number of load instructions +system.cpu.num_store_insts 4744844 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 108282001.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 18732305 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction +system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction +system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 91054081 # Class of executed instruction +system.membus.trans_dist::ReadReq 130287906 # Transaction distribution +system.membus.trans_dist::ReadResp 130291793 # Transaction distribution +system.membus.trans_dist::WriteReq 4734981 # Transaction distribution +system.membus.trans_dist::WriteResp 4734981 # Transaction distribution +system.membus.trans_dist::SoftPFReq 510 # Transaction distribution +system.membus.trans_dist::SoftPFResp 510 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution +system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution +system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661542 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 270062342 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323084 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 540247820 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 135031171 # Request fanout histogram +system.membus.snoop_fanout::mean 0.798562 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 27200400 20.14% 20.14% # Request fanout histogram +system.membus.snoop_fanout::1 107830771 79.86% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 135031171 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index e69de29bb..60ec36514 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,648 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.147149 # Number of seconds simulated +sim_ticks 147148719500 # Number of ticks simulated +final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 596574 # Simulator instruction rate (inst/s) +host_op_rate 599539 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 969178238 # Simulator tick rate (ticks/s) +host_mem_usage 398700 # Number of bytes of host memory used +host_seconds 151.83 # Real time elapsed on the host +sim_insts 90576862 # Number of instructions simulated +sim_ops 91026991 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory +system.physmem.bytes_read::total 981760 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 36928 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 250957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6420933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6671890 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 250957 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 250957 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 250957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6420933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6671890 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 442 # Number of system calls +system.cpu.numCycles 294297439 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 90576862 # Number of instructions committed +system.cpu.committedOps 91026991 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses +system.cpu.num_func_calls 112245 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls +system.cpu.num_int_insts 72326352 # number of integer instructions +system.cpu.num_fp_insts 48 # number of float instructions +system.cpu.num_int_register_reads 124237033 # number of times the integer registers were read +system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written +system.cpu.num_fp_register_reads 54 # number of times the floating registers were read +system.cpu.num_fp_register_writes 30 # number of times the floating registers were written +system.cpu.num_cc_register_reads 339191621 # number of times the CC registers were read +system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written +system.cpu.num_mem_refs 27220755 # number of memory refs +system.cpu.num_load_insts 22475911 # Number of load instructions +system.cpu.num_store_insts 4744844 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 294297438.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 18732305 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction +system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction +system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 91054081 # Class of executed instruction +system.cpu.dcache.tags.replacements 942702 # number of replacements +system.cpu.dcache.tags.tagsinuse 3565.478025 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 54453325500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.478025 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.870478 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.870478 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1357 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits +system.cpu.dcache.overall_hits::total 26245827 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses +system.cpu.dcache.overall_misses::total 946799 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713009000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11713009000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1319019500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1319019500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13032028500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13032028500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13032028500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13032028500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.750892 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.750892 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28299.673883 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28299.673883 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13764.346808 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13764.346808 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13764.303194 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13764.303194 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks +system.cpu.dcache.writebacks::total 942334 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812776000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812776000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1272410500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1272410500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 134000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 134000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12085186500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12085186500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12085320500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12085320500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.713135 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.713135 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency +system.cpu.icache.tags.replacements 2 # number of replacements +system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.111710 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.249078 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.249078 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses +system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 107830173 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 107830173 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 107830173 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 107830173 # number of overall hits +system.cpu.icache.overall_hits::total 107830173 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses +system.cpu.icache.overall_misses::total 599 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 36093000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 36093000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 36093000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 36093000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 36093000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 36093000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 107830772 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 107830772 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 107830772 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60255.425710 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 60255.425710 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 60255.425710 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 60255.425710 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 2 # number of writebacks +system.cpu.icache.writebacks::total 2 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35494000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 35494000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35494000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 35494000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35494000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 35494000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 8876.269803 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.164592 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 194.224030 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.270882 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.005927 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.291890 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1473 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15181828 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15181828 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 899974 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 899974 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932035 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 932057 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 932035 # number of overall hits +system.cpu.l2cache.overall_hits::total 932057 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 577 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 577 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 215 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 215 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 577 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14763 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15340 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 577 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14763 # number of overall misses +system.cpu.l2cache.overall_misses::total 15340 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 865856500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 865856500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34343500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 34343500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12794500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 12794500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 34343500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 878651000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 912994500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 34343500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 878651000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 912994500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 942334 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 942334 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 599 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 599 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 900189 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 900189 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 946798 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 947397 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 599 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.963272 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.963272 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000239 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000239 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963272 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015593 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016192 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963272 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015593 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59517.218862 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59517.218862 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59520.797227 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59520.797227 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59509.302326 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59509.302326 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59517.242503 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59517.242503 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 577 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 577 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 215 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 215 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 577 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14763 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 577 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14763 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 720376500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 720376500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 28573500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 28573500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10644500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10644500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28573500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 731021000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 759594500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28573500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 731021000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 759594500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.963272 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000239 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000239 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49517.218862 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49517.218862 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49520.797227 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49520.797227 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49509.302326 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49509.302326 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1200 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836298 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2837498 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 120942912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 947397 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000132 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.011486 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 947272 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 125 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 947397 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.trans_dist::ReadResp 792 # Transaction distribution +system.membus.trans_dist::ReadExReq 14548 # Transaction distribution +system.membus.trans_dist::ReadExResp 14548 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 792 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 15340 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15340 # Request fanout histogram +system.membus.reqLayer0.occupancy 15604500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 76700000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index e69de29bb..95dd6c0ff 100644 --- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -0,0 +1,124 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.122216 # Number of seconds simulated +sim_ticks 122215823500 # Number of ticks simulated +final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1393980 # Simulator instruction rate (inst/s) +host_op_rate 1394037 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 698723411 # Simulator tick rate (ticks/s) +host_mem_usage 370524 # Number of bytes of host memory used +host_seconds 174.91 # Real time elapsed on the host +sim_insts 243825150 # Number of instructions simulated +sim_ops 243835265 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 328674008 # Number of bytes read from this memory +system.physmem.bytes_read::total 1306360000 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 977685992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977685992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 91606089 # Number of bytes written to this memory +system.physmem.bytes_written::total 91606089 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 244421498 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 82220433 # Number of read requests responded to by this memory +system.physmem.num_reads::total 326641931 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 22901951 # Number of write requests responded to by this memory +system.physmem.num_writes::total 22901951 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 3886 # Number of other requests responded to by this memory +system.physmem.num_other::total 3886 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999667834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2689291768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10688959601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999667834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999667834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 749543606 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 749543606 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.workload.num_syscalls 443 # Number of system calls +system.cpu.numCycles 244431648 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 243825150 # Number of instructions committed +system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses +system.cpu.num_func_calls 4252956 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls +system.cpu.num_int_insts 194726494 # number of integer instructions +system.cpu.num_fp_insts 11630 # number of float instructions +system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read +system.cpu.num_int_register_writes 215451554 # number of times the integer registers were written +system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read +system.cpu.num_fp_register_writes 90 # number of times the floating registers were written +system.cpu.num_mem_refs 105711441 # number of memory refs +system.cpu.num_load_insts 82803521 # Number of load instructions +system.cpu.num_store_insts 22907920 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 244431647.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 29302884 # Number of branches fetched +system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction +system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction +system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 244431613 # Class of executed instruction +system.membus.trans_dist::ReadReq 326641931 # Transaction distribution +system.membus.trans_dist::ReadResp 326641931 # Transaction distribution +system.membus.trans_dist::WriteReq 22901951 # Transaction distribution +system.membus.trans_dist::WriteResp 22901951 # Transaction distribution +system.membus.trans_dist::SwapReq 3886 # Transaction distribution +system.membus.trans_dist::SwapResp 3886 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 488842996 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 210252540 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 699095536 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 977685992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 420311185 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1397997177 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 349547768 # Request fanout histogram +system.membus.snoop_fanout::mean 0.699251 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.458584 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 105126270 30.07% 30.07% # Request fanout histogram +system.membus.snoop_fanout::1 244421498 69.93% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 349547768 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index e69de29bb..aba308f8c 100644 --- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -0,0 +1,127 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.168950 # Number of seconds simulated +sim_ticks 168950040000 # Number of ticks simulated +final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 769614 # Simulator instruction rate (inst/s) +host_op_rate 1355167 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 823011137 # Simulator tick rate (ticks/s) +host_mem_usage 396564 # Number of bytes of host memory used +host_seconds 205.28 # Real time elapsed on the host +sim_insts 157988548 # Number of instructions simulated +sim_ops 278192465 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 717246013 # Number of bytes read from this memory +system.physmem.bytes_read::total 2458815325 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1741569312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1741569312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 243173117 # Number of bytes written to this memory +system.physmem.bytes_written::total 243173117 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 217696164 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 90779447 # Number of read requests responded to by this memory +system.physmem.num_reads::total 308475611 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 31439752 # Number of write requests responded to by this memory +system.physmem.num_writes::total 31439752 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 10308191179 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4245314254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14553505433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10308191179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10308191179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1439319677 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1439319677 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.workload.num_syscalls 444 # Number of system calls +system.cpu.numCycles 337900081 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 157988548 # Number of instructions committed +system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses +system.cpu.num_func_calls 8475189 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls +system.cpu.num_int_insts 278169482 # number of integer instructions +system.cpu.num_fp_insts 40 # number of float instructions +system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read +system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written +system.cpu.num_fp_register_reads 40 # number of times the floating registers were read +system.cpu.num_fp_register_writes 26 # number of times the floating registers were written +system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read +system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written +system.cpu.num_mem_refs 122219137 # number of memory refs +system.cpu.num_load_insts 90779385 # Number of load instructions +system.cpu.num_store_insts 31439752 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 337900080.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 29309705 # Number of branches fetched +system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction +system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction +system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 278192465 # Class of executed instruction +system.membus.trans_dist::ReadReq 308475611 # Transaction distribution +system.membus.trans_dist::ReadResp 308475611 # Transaction distribution +system.membus.trans_dist::WriteReq 31439752 # Transaction distribution +system.membus.trans_dist::WriteResp 31439752 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 339915363 # Request fanout histogram +system.membus.snoop_fanout::mean 0.640442 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 122219199 35.96% 35.96% # Request fanout histogram +system.membus.snoop_fanout::1 217696164 64.04% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 339915363 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index e69de29bb..28924494c 100644 --- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -0,0 +1,152 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.199332 # Number of seconds simulated +sim_ticks 199332411500 # Number of ticks simulated +final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1428598 # Simulator instruction rate (inst/s) +host_op_rate 1428597 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 714299076 # Simulator tick rate (ticks/s) +host_mem_usage 244476 # Number of bytes of host memory used +host_seconds 279.06 # Real time elapsed on the host +sim_insts 398664595 # Number of instructions simulated +sim_ops 398664595 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 1594658604 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 662449271 # Number of bytes read from this memory +system.physmem.bytes_read::total 2257107875 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1594658604 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1594658604 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 492356798 # Number of bytes written to this memory +system.physmem.bytes_written::total 492356798 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 398664651 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 94754489 # Number of read requests responded to by this memory +system.physmem.num_reads::total 493419140 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 73520729 # Number of write requests responded to by this memory +system.physmem.num_writes::total 73520729 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999996548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3323339471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11323336020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999996548 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999996548 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2470028804 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2470028804 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 94754489 # DTB read hits +system.cpu.dtb.read_misses 21 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 94754510 # DTB read accesses +system.cpu.dtb.write_hits 73520729 # DTB write hits +system.cpu.dtb.write_misses 35 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 73520764 # DTB write accesses +system.cpu.dtb.data_hits 168275218 # DTB hits +system.cpu.dtb.data_misses 56 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 168275274 # DTB accesses +system.cpu.itb.fetch_hits 398664651 # ITB hits +system.cpu.itb.fetch_misses 173 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 398664824 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 215 # Number of system calls +system.cpu.numCycles 398664824 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 398664595 # Number of instructions committed +system.cpu.committedOps 398664595 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses +system.cpu.num_func_calls 16015498 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 25997787 # number of instructions that are conditional controls +system.cpu.num_int_insts 316365907 # number of integer instructions +system.cpu.num_fp_insts 155295119 # number of float instructions +system.cpu.num_int_register_reads 372938760 # number of times the integer registers were read +system.cpu.num_int_register_writes 159335860 # number of times the integer registers were written +system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read +system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written +system.cpu.num_mem_refs 168275274 # number of memory refs +system.cpu.num_load_insts 94754510 # Number of load instructions +system.cpu.num_store_insts 73520764 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 398664824 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 44587532 # Number of branches fetched +system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction +system.cpu.op_class::IntAlu 141652555 35.53% 41.33% # Class of executed instruction +system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction +system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction +system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction +system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction +system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction +system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::MemRead 94754510 23.77% 81.56% # Class of executed instruction +system.cpu.op_class::MemWrite 73520764 18.44% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 398664651 # Class of executed instruction +system.membus.trans_dist::ReadReq 493419140 # Transaction distribution +system.membus.trans_dist::ReadResp 493419140 # Transaction distribution +system.membus.trans_dist::WriteReq 73520729 # Transaction distribution +system.membus.trans_dist::WriteResp 73520729 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 797329302 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336550436 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1133879738 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1594658604 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1154806069 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2749464673 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 566939869 # Request fanout histogram +system.membus.snoop_fanout::mean 0.703187 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.456853 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 168275218 29.68% 29.68% # Request fanout histogram +system.membus.snoop_fanout::1 398664651 70.32% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 566939869 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index e69de29bb..3f4ff4c5a 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -0,0 +1,2902 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000125 # Number of seconds simulated +sim_ticks 124523000 # Number of ticks simulated +final_tick 124523000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 139641 # Simulator instruction rate (inst/s) +host_op_rate 139640 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15068671 # Simulator tick rate (ticks/s) +host_mem_usage 262532 # Number of bytes of host memory used +host_seconds 8.26 # Real time elapsed on the host +sim_insts 1153943 # Number of instructions simulated +sim_ops 1153943 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu0.inst 24000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 896 # Number of bytes read from this memory +system.physmem.bytes_read::total 45632 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 24000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 31488 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 375 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 170 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 92 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 14 # Number of read requests responded to by this memory +system.physmem.num_reads::total 713 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 192735479 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 87373417 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 47284437 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11307148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 7195458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7709419 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 5653574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7195458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 366454390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 192735479 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 47284437 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 7195458 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 5653574 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 252868948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 192735479 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 87373417 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 47284437 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11307148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 7195458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7709419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 5653574 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7195458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 366454390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 713 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 713 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 45632 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 45632 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 120 # Per bank write bursts +system.physmem.perBankRdBursts::1 45 # Per bank write bursts +system.physmem.perBankRdBursts::2 31 # Per bank write bursts +system.physmem.perBankRdBursts::3 62 # Per bank write bursts +system.physmem.perBankRdBursts::4 69 # Per bank write bursts +system.physmem.perBankRdBursts::5 28 # Per bank write bursts +system.physmem.perBankRdBursts::6 19 # Per bank write bursts +system.physmem.perBankRdBursts::7 28 # Per bank write bursts +system.physmem.perBankRdBursts::8 7 # Per bank write bursts +system.physmem.perBankRdBursts::9 31 # Per bank write bursts +system.physmem.perBankRdBursts::10 23 # Per bank write bursts +system.physmem.perBankRdBursts::11 13 # Per bank write bursts +system.physmem.perBankRdBursts::12 70 # Per bank write bursts +system.physmem.perBankRdBursts::13 47 # Per bank write bursts +system.physmem.perBankRdBursts::14 19 # Per bank write bursts +system.physmem.perBankRdBursts::15 101 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 124288000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 713 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 171 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 249.637427 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 165.941235 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 244.016459 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 63 36.84% 36.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41 23.98% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 28 16.37% 77.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 13 7.60% 84.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8 4.68% 89.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8 4.68% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 1.75% 95.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.58% 96.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 3.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 171 # Bytes accessed per row activation +system.physmem.totQLat 6387250 # Total ticks spent queuing +system.physmem.totMemAccLat 19756000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3565000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8958.27 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 27708.27 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 366.45 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 366.45 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.86 # Data bus utilization in percentage +system.physmem.busUtilRead 2.86 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 530 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 174316.97 # Average gap between requests +system.physmem.pageHitRate 74.33 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 816480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 445500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2917200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 46677870 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29286750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 87772200 # Total energy per rank (pJ) +system.physmem_0.averagePower 749.845263 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 50196500 # Time in different power states +system.physmem_0.memoryStateTime::REF 3900000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 64717500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 430920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 235125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2215200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 50794695 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 25675500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 86979840 # Total energy per rank (pJ) +system.physmem_1.averagePower 743.076065 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 46915750 # Time in different power states +system.physmem_1.memoryStateTime::REF 3900000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 70805750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu0.branchPred.lookups 98739 # Number of BP lookups +system.cpu0.branchPred.condPredicted 94242 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1562 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 96047 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 0 # Number of BTB hits +system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu0.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 1131 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 96047 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 88694 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 7353 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 1035 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.workload.num_syscalls 89 # Number of system calls +system.cpu0.numCycles 249047 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.fetch.icacheStallCycles 23160 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 582455 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 98739 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 89825 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 194593 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3423 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 66 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 2218 # Number of stall cycles due to pending traps +system.cpu0.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7952 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 853 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 221760 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.626511 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.263155 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34377 15.50% 15.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 91683 41.34% 56.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 679 0.31% 57.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1006 0.45% 57.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 517 0.23% 57.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 87238 39.34% 97.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 730 0.33% 97.51% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 482 0.22% 97.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5048 2.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 221760 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.396467 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.338735 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17619 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 19820 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 181778 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 832 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1711 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 564879 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 1711 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18296 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2376 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 16107 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 181922 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1348 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 559910 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 869 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 383145 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1115796 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 842870 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 364171 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 18974 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1067 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1095 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5253 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 178633 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 90222 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 87104 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 86835 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 467056 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1095 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 463006 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 16506 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13395 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 536 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 221760 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.087870 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.110825 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 37234 16.79% 16.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4446 2.00% 18.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 88426 39.87% 58.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 88102 39.73% 98.40% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1676 0.76% 99.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 983 0.44% 99.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 568 0.26% 99.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 225 0.10% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 100 0.05% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 221760 # Number of insts issued each cycle +system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 134 40.48% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 76 22.96% 63.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 121 36.56% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 195503 42.22% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.22% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 178044 38.45% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 89459 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::total 463006 # Type of FU issued +system.cpu0.iq.rate 1.859111 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 331 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000715 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1148221 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 484707 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 460421 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 463337 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 86583 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu0.iew.lsq.thread0.squashedLoads 2958 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 52 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1878 # Number of stores squashed +system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 11 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu0.iew.iewSquashCycles 1711 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 2375 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 555874 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 119 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 178633 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 90222 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 980 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 52 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 232 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1679 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1911 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 461536 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 177679 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1470 # Number of squashed instructions skipped in execute +system.cpu0.iew.exec_swp 0 # number of swp insts executed +system.cpu0.iew.exec_nop 87723 # number of nop insts executed +system.cpu0.iew.exec_refs 266935 # number of memory reference insts executed +system.cpu0.iew.exec_branches 91696 # Number of branches executed +system.cpu0.iew.exec_stores 89256 # Number of stores executed +system.cpu0.iew.exec_rate 1.853208 # Inst execution rate +system.cpu0.iew.wb_sent 460886 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 460421 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 273043 # num instructions producing a value +system.cpu0.iew.wb_consumers 276596 # num instructions consuming a value +system.cpu0.iew.wb_rate 1.848731 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.987155 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 17182 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 1562 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 218398 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.466176 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.142349 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 37197 17.03% 17.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 90473 41.43% 58.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2051 0.94% 59.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 612 0.28% 59.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 499 0.23% 59.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 86381 39.55% 99.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 448 0.21% 99.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 288 0.13% 99.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 449 0.21% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::total 218398 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 538608 # Number of instructions committed +system.cpu0.commit.committedOps 538608 # Number of ops (including micro ops) committed +system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu0.commit.refs 264019 # Number of memory references committed +system.cpu0.commit.loads 175675 # Number of loads committed +system.cpu0.commit.membars 84 # Number of memory barriers committed +system.cpu0.commit.branches 90231 # Number of branches committed +system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 362502 # Number of committed integer instructions. +system.cpu0.commit.function_calls 223 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 86963 16.15% 16.15% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 187542 34.82% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 175759 32.63% 83.60% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 88344 16.40% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::total 538608 # Class of committed instruction +system.cpu0.commit.bw_lim_events 449 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 772578 # The number of ROB reads +system.cpu0.rob.rob_writes 1114998 # The number of ROB writes +system.cpu0.timesIdled 315 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27287 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 451561 # Number of Instructions Simulated +system.cpu0.committedOps 451561 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.551525 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.551525 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.813156 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.813156 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 825039 # number of integer regfile reads +system.cpu0.int_regfile_writes 371919 # number of integer regfile writes +system.cpu0.fp_regfile_reads 192 # number of floating regfile reads +system.cpu0.misc_regfile_reads 269052 # number of misc regfile reads +system.cpu0.misc_regfile_writes 564 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 142.724931 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 178078 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 172 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 1035.337209 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.724931 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.278760 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.278760 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 170 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.332031 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 717658 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 717658 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 90413 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 90413 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 87748 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 87748 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 23 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 23 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 178161 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 178161 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 178161 # number of overall hits +system.cpu0.dcache.overall_hits::total 178161 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 578 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 578 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 554 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 554 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 19 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 19 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1132 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1132 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1132 # number of overall misses +system.cpu0.dcache.overall_misses::total 1132 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 18168000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 18168000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36152490 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 36152490 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 521000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 521000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 54320490 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 54320490 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 54320490 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 54320490 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 90991 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 90991 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 88302 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 88302 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 179293 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 179293 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 179293 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 179293 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006352 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006352 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006274 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006274 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.452381 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.452381 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006314 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006314 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006314 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006314 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31432.525952 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 31432.525952 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65257.202166 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 65257.202166 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 27421.052632 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 27421.052632 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47986.298587 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 47986.298587 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47986.298587 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 47986.298587 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 832 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 37.818182 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu0.dcache.writebacks::total 1 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 385 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 385 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 387 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 387 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 772 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 772 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 772 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 772 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 193 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 193 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 167 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 167 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 19 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 19 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 7230000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7230000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8425000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8425000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 502000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 502000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15655000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15655000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15655000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15655000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002121 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002121 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001891 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001891 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.452381 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.452381 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002008 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002008 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002008 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002008 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37461.139896 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37461.139896 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 50449.101796 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 50449.101796 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26421.052632 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26421.052632 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 43486.111111 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 43486.111111 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 43486.111111 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 43486.111111 # average overall mshr miss latency +system.cpu0.icache.tags.replacements 394 # number of replacements +system.cpu0.icache.tags.tagsinuse 248.905102 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7041 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 695 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.130935 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 248.905102 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.486143 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.486143 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.587891 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 8647 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 8647 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 7041 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7041 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7041 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7041 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7041 # number of overall hits +system.cpu0.icache.overall_hits::total 7041 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 911 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 911 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 911 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 911 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 911 # number of overall misses +system.cpu0.icache.overall_misses::total 911 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 43691000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 43691000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 43691000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 43691000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 43691000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 43691000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7952 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7952 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7952 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7952 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7952 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7952 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.114562 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.114562 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.114562 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.114562 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.114562 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.114562 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47959.385291 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 47959.385291 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47959.385291 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 47959.385291 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47959.385291 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 47959.385291 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.250000 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.writebacks::writebacks 394 # number of writebacks +system.cpu0.icache.writebacks::total 394 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 215 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 215 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 215 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 215 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 696 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 696 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 696 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 696 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 696 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 696 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 33693000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 33693000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 33693000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 33693000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 33693000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 33693000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087525 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.087525 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087525 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.087525 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087525 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.087525 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 48409.482759 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 48409.482759 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 48409.482759 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 48409.482759 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 48409.482759 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 48409.482759 # average overall mshr miss latency +system.cpu1.branchPred.lookups 70381 # Number of BP lookups +system.cpu1.branchPred.condPredicted 62763 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 2321 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 62113 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 0 # Number of BTB hits +system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu1.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 1978 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 62113 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 52196 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 9917 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 1232 # Number of mispredicted indirect branches. +system.cpu1.numCycles 193493 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.fetch.icacheStallCycles 35625 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 388406 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 70381 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 54174 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 147522 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4799 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 1696 # Number of stall cycles due to pending traps +system.cpu1.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 23532 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 933 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 187271 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 2.074032 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.377312 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 61181 32.67% 32.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 61333 32.75% 65.42% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 6091 3.25% 68.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3354 1.79% 70.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 663 0.35% 70.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 43826 23.40% 94.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1093 0.58% 94.80% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1351 0.72% 95.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 8379 4.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::total 187271 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.363739 # Number of branch fetches per cycle +system.cpu1.fetch.rate 2.007339 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 22629 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 55115 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 103585 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3533 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2399 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 358317 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2399 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 23637 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 25102 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 14378 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 104390 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 17355 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 351725 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 14900 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 247787 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 679105 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 526513 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 34 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 220167 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 27620 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1612 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1735 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 22764 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 99432 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 48003 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 46782 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 41727 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 289849 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 6510 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 288395 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 24134 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 20047 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 1135 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 187271 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.539988 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.388620 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 65886 35.18% 35.18% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 21449 11.45% 46.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 46526 24.84% 71.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 46214 24.68% 96.16% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3599 1.92% 98.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1752 0.94% 99.01% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1124 0.60% 99.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 416 0.22% 99.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 305 0.16% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 187271 # Number of insts issued each cycle +system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 198 39.68% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 39.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 73 14.63% 54.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 228 45.69% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 138505 48.03% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.03% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 102963 35.70% 83.73% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 46927 16.27% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::total 288395 # Type of FU issued +system.cpu1.iq.rate 1.490467 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 499 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001730 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 764671 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 320465 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 284383 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 288894 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 41593 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu1.iew.lsq.thread0.squashedLoads 4579 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 38 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 2647 # Number of stores squashed +system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu1.iew.iewSquashCycles 2399 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 8044 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 344307 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 270 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 99432 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 48003 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1487 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 446 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2454 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 2900 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 285809 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 97701 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2586 # Number of squashed instructions skipped in execute +system.cpu1.iew.exec_swp 0 # number of swp insts executed +system.cpu1.iew.exec_nop 47948 # number of nop insts executed +system.cpu1.iew.exec_refs 144318 # number of memory reference insts executed +system.cpu1.iew.exec_branches 58093 # Number of branches executed +system.cpu1.iew.exec_stores 46617 # Number of stores executed +system.cpu1.iew.exec_rate 1.477103 # Inst execution rate +system.cpu1.iew.wb_sent 284919 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 284383 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 161989 # num instructions producing a value +system.cpu1.iew.wb_consumers 169394 # num instructions consuming a value +system.cpu1.iew.wb_rate 1.469733 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.956285 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 25278 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 5375 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 2321 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 182469 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.748204 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.087021 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 70580 38.68% 38.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 54368 29.80% 68.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5362 2.94% 71.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 6062 3.32% 74.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1316 0.72% 75.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 41726 22.87% 98.33% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 809 0.44% 98.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1001 0.55% 99.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1245 0.68% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::total 182469 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 318993 # Number of instructions committed +system.cpu1.commit.committedOps 318993 # Number of ops (including micro ops) committed +system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu1.commit.refs 140209 # Number of memory references committed +system.cpu1.commit.loads 94853 # Number of loads committed +system.cpu1.commit.membars 4659 # Number of memory barriers committed +system.cpu1.commit.branches 55980 # Number of branches committed +system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 218308 # Number of committed integer instructions. +system.cpu1.commit.function_calls 322 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 46768 14.66% 14.66% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 127357 39.92% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.59% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 99512 31.20% 85.78% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 45356 14.22% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::total 318993 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1245 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 524909 # The number of ROB reads +system.cpu1.rob.rob_writes 693389 # The number of ROB writes +system.cpu1.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 6222 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 47433 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 267566 # Number of Instructions Simulated +system.cpu1.committedOps 267566 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.723160 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.723160 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.382820 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.382820 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 496242 # number of integer regfile reads +system.cpu1.int_regfile_writes 230976 # number of integer regfile writes +system.cpu1.fp_regfile_writes 64 # number of floating regfile writes +system.cpu1.misc_regfile_reads 146210 # number of misc regfile reads +system.cpu1.misc_regfile_writes 648 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 26.604916 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 52484 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1693.032258 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.604916 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051963 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.051963 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.060547 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 405985 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 405985 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 55568 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 55568 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 45140 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 45140 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 100708 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 100708 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 100708 # number of overall hits +system.cpu1.dcache.overall_hits::total 100708 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 507 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 507 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 146 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 146 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 653 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 653 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 653 # number of overall misses +system.cpu1.dcache.overall_misses::total 653 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9264000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 9264000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3726500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3726500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 796000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 796000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12990500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12990500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12990500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12990500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 56075 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 56075 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 45286 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 45286 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 101361 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 101361 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 101361 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 101361 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009041 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.009041 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003224 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.003224 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.828571 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.828571 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006442 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.006442 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006442 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.006442 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18272.189349 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 18272.189349 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25523.972603 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25523.972603 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 13724.137931 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 13724.137931 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19893.568147 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19893.568147 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19893.568147 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 19893.568147 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 341 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 341 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 40 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 40 # number of WriteReq MSHR hits +system.cpu1.dcache.SwapReq_mshr_hits::cpu1.data 2 # number of SwapReq MSHR hits +system.cpu1.dcache.SwapReq_mshr_hits::total 2 # number of SwapReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 381 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 381 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 381 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 381 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 272 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 272 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2098000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2098000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1657500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1657500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 738000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 738000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3755500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3755500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3755500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3755500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002960 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002960 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002341 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002341 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002683 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.002683 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002683 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.002683 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12638.554217 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12638.554217 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15636.792453 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15636.792453 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 13178.571429 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 13178.571429 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13806.985294 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13806.985294 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13806.985294 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13806.985294 # average overall mshr miss latency +system.cpu1.icache.tags.replacements 579 # number of replacements +system.cpu1.icache.tags.tagsinuse 98.515696 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 22662 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 713 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 31.784011 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 98.515696 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.192413 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.192413 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 8 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.261719 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 24245 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 24245 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 22662 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 22662 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 22662 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 22662 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 22662 # number of overall hits +system.cpu1.icache.overall_hits::total 22662 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 870 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 870 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 870 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 870 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 870 # number of overall misses +system.cpu1.icache.overall_misses::total 870 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 19533000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 19533000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 19533000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 19533000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 19533000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 19533000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 23532 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 23532 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 23532 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 23532 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 23532 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 23532 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.036971 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.036971 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.036971 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.036971 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.036971 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.036971 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22451.724138 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 22451.724138 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22451.724138 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 22451.724138 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22451.724138 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 22451.724138 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 141 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 35.250000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 579 # number of writebacks +system.cpu1.icache.writebacks::total 579 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 157 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 157 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 157 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 157 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 157 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 157 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 713 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 713 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 713 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 713 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 713 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 713 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 15250000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 15250000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 15250000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 15250000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 15250000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 15250000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030299 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030299 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030299 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.030299 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030299 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.030299 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21388.499299 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 21388.499299 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 21388.499299 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 21388.499299 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 21388.499299 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 21388.499299 # average overall mshr miss latency +system.cpu2.branchPred.lookups 63667 # Number of BP lookups +system.cpu2.branchPred.condPredicted 55684 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 2455 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 55606 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 0 # Number of BTB hits +system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 2018 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. +system.cpu2.branchPred.indirectLookups 55606 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 44645 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 10961 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 1342 # Number of mispredicted indirect branches. +system.cpu2.numCycles 193104 # number of cpu cycles simulated +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.fetch.icacheStallCycles 40968 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 342539 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 63667 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 46663 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 146022 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 5067 # Number of cycles fetch has spent squashing +system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 1848 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 29416 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 951 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 191398 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.789669 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.326327 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 76889 40.17% 40.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 56601 29.57% 69.74% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 8825 4.61% 74.36% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3447 1.80% 76.16% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 694 0.36% 76.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 33672 17.59% 94.11% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 980 0.51% 94.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 1389 0.73% 95.35% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 8901 4.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::total 191398 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.329703 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.773858 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 22836 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 76803 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 84446 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4770 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2533 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 310490 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2533 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 23870 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 37657 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 14813 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 85216 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 27299 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 303538 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 23577 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full +system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 211726 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 571973 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 446566 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 26 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 182781 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 28945 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1674 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1822 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 33085 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 82000 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 37987 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 39268 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 31634 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 245836 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 9182 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 247097 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 85 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 25038 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19372 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 1244 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 191398 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.291011 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.381781 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 81765 42.72% 42.72% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 29268 15.29% 58.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 36754 19.20% 77.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 36522 19.08% 96.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3555 1.86% 98.15% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1723 0.90% 99.05% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 1061 0.55% 99.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 446 0.23% 99.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 304 0.16% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 191398 # Number of insts issued each cycle +system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 203 40.76% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 40.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 64 12.85% 53.61% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 231 46.39% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 121951 49.35% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 88101 35.65% 85.01% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 37045 14.99% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::total 247097 # Type of FU issued +system.cpu2.iq.rate 1.279606 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 498 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.002015 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 686175 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 280041 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 243170 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 247595 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 31591 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu2.iew.lsq.thread0.squashedLoads 4554 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 33 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 2621 # Number of stores squashed +system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu2.iew.iewSquashCycles 2533 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 10681 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 295617 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 336 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 82000 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 37987 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1539 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 446 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 2642 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 3088 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 244561 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 80330 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 2536 # Number of squashed instructions skipped in execute +system.cpu2.iew.exec_swp 0 # number of swp insts executed +system.cpu2.iew.exec_nop 40599 # number of nop insts executed +system.cpu2.iew.exec_refs 117071 # number of memory reference insts executed +system.cpu2.iew.exec_branches 50931 # Number of branches executed +system.cpu2.iew.exec_stores 36741 # Number of stores executed +system.cpu2.iew.exec_rate 1.266473 # Inst execution rate +system.cpu2.iew.wb_sent 243660 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 243170 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 134852 # num instructions producing a value +system.cpu2.iew.wb_consumers 142392 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.259270 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.947048 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 26266 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 7938 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 2455 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 186363 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.445163 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.976076 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 89147 47.84% 47.84% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 47087 25.27% 73.10% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5442 2.92% 76.02% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 8636 4.63% 80.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1280 0.69% 81.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 31787 17.06% 98.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 722 0.39% 98.79% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1037 0.56% 99.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1225 0.66% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::total 186363 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 269325 # Number of instructions committed +system.cpu2.commit.committedOps 269325 # Number of ops (including micro ops) committed +system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu2.commit.refs 112812 # Number of memory references committed +system.cpu2.commit.loads 77446 # Number of loads committed +system.cpu2.commit.membars 7225 # Number of memory barriers committed +system.cpu2.commit.branches 48554 # Number of branches committed +system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 183489 # Number of committed integer instructions. +system.cpu2.commit.function_calls 322 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 39345 14.61% 14.61% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 109943 40.82% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.43% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 84671 31.44% 86.87% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 35366 13.13% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::total 269325 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1225 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 480143 # The number of ROB reads +system.cpu2.rob.rob_writes 596277 # The number of ROB writes +system.cpu2.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1706 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 47823 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 222755 # Number of Instructions Simulated +system.cpu2.committedOps 222755 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.866890 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.866890 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.153549 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.153549 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 415553 # number of integer regfile reads +system.cpu2.int_regfile_writes 194388 # number of integer regfile writes +system.cpu2.fp_regfile_writes 64 # number of floating regfile writes +system.cpu2.misc_regfile_reads 119022 # number of misc regfile reads +system.cpu2.misc_regfile_writes 648 # number of misc regfile writes +system.cpu2.dcache.tags.replacements 0 # number of replacements +system.cpu2.dcache.tags.tagsinuse 25.641689 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 42500 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1416.666667 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.641689 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.050081 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.050081 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 336580 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 336580 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 48215 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 48215 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 35154 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 35154 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 83369 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 83369 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 83369 # number of overall hits +system.cpu2.dcache.overall_hits::total 83369 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 500 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 500 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 145 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 145 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 645 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 645 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 645 # number of overall misses +system.cpu2.dcache.overall_misses::total 645 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 8163500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 8163500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3144500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3144500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 806000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 806000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 11308000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 11308000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 11308000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 11308000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 48715 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 48715 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 35299 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 35299 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 67 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 84014 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 84014 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 84014 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 84014 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010264 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.010264 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004108 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004108 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.805970 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.805970 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007677 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.007677 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007677 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.007677 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16327 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 16327 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21686.206897 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 21686.206897 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 14925.925926 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 14925.925926 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17531.782946 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17531.782946 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17531.782946 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17531.782946 # average overall miss latency +system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 338 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 338 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 39 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 39 # number of WriteReq MSHR hits +system.cpu2.dcache.SwapReq_mshr_hits::cpu2.data 2 # number of SwapReq MSHR hits +system.cpu2.dcache.SwapReq_mshr_hits::total 2 # number of SwapReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 377 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 377 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 377 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 377 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 52 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1730500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1730500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1679500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1679500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 752000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 752000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3410000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3410000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3410000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3410000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003325 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003325 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003003 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003003 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.776119 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.776119 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003190 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003190 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003190 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003190 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10682.098765 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10682.098765 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15844.339623 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15844.339623 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 14461.538462 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 14461.538462 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12723.880597 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12723.880597 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12723.880597 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12723.880597 # average overall mshr miss latency +system.cpu2.icache.tags.replacements 598 # number of replacements +system.cpu2.icache.tags.tagsinuse 95.853337 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 28564 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 733 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 38.968622 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 95.853337 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.187214 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.187214 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.263672 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 30149 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 30149 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 28564 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 28564 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 28564 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 28564 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 28564 # number of overall hits +system.cpu2.icache.overall_hits::total 28564 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 852 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 852 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 852 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 852 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 852 # number of overall misses +system.cpu2.icache.overall_misses::total 852 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 12789500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 12789500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 12789500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 12789500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 12789500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 12789500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 29416 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 29416 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 29416 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 29416 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 29416 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 29416 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.028964 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.028964 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.028964 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.028964 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.028964 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.028964 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15011.150235 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 15011.150235 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15011.150235 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 15011.150235 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15011.150235 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 15011.150235 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 111 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs 22.200000 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu2.icache.writebacks::writebacks 598 # number of writebacks +system.cpu2.icache.writebacks::total 598 # number of writebacks +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 119 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 119 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 119 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 119 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 119 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 733 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 733 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 733 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 733 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10899500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 10899500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10899500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 10899500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10899500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 10899500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024918 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024918 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024918 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.024918 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024918 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.024918 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 14869.713506 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 14869.713506 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 14869.713506 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 14869.713506 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 14869.713506 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 14869.713506 # average overall mshr miss latency +system.cpu3.branchPred.lookups 61800 # Number of BP lookups +system.cpu3.branchPred.condPredicted 53939 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 2339 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 53501 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 0 # Number of BTB hits +system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu3.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 1989 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. +system.cpu3.branchPred.indirectLookups 53501 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 43109 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 10392 # Number of indirect misses. +system.cpu3.branchPredindirectMispredicted 1225 # Number of mispredicted indirect branches. +system.cpu3.numCycles 192748 # number of cpu cycles simulated +system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu3.fetch.icacheStallCycles 41262 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 329189 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 61800 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 45098 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 145688 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 4833 # Number of cycles fetch has spent squashing +system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 1762 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 30337 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 926 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 191141 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.722231 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.297340 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 79632 41.66% 41.66% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 55527 29.05% 70.71% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 9457 4.95% 75.66% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3401 1.78% 77.44% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 679 0.36% 77.79% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 31347 16.40% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1154 0.60% 94.80% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 1382 0.72% 95.52% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 8562 4.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::total 191141 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.320626 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.707872 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 22425 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 81552 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 79630 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 5108 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2416 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 297344 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2416 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 23427 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 40476 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 14673 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 80471 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 29668 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 290876 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 25659 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full +system.cpu3.rename.RenamedOperands 201895 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 544124 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 425656 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 36 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 173837 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 28058 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1657 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1795 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 35428 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 77674 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 35638 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 37571 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 29275 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 234657 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 9848 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 236528 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 68 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 24579 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 19470 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 1266 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 191141 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.237453 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.372875 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 84630 44.28% 44.28% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 31019 16.23% 60.50% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 34273 17.93% 78.44% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 34156 17.87% 96.30% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3613 1.89% 98.20% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1675 0.88% 99.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 1066 0.56% 99.63% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 400 0.21% 99.84% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 309 0.16% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 191141 # Number of insts issued each cycle +system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 176 38.18% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 38.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 50 10.85% 49.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 235 50.98% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 117496 49.68% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 84415 35.69% 85.36% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 34617 14.64% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::total 236528 # Type of FU issued +system.cpu3.iq.rate 1.227136 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 461 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001949 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 664726 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 269047 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 232596 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 72 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 236989 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 29180 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu3.iew.lsq.thread0.squashedLoads 4384 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 23 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 2661 # Number of stores squashed +system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu3.iew.iewSquashCycles 2416 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 11113 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 283276 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 304 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 77674 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 35638 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1522 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 35 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 471 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 2483 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 2954 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 233943 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 76012 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 2585 # Number of squashed instructions skipped in execute +system.cpu3.iew.exec_swp 0 # number of swp insts executed +system.cpu3.iew.exec_nop 38771 # number of nop insts executed +system.cpu3.iew.exec_refs 110309 # number of memory reference insts executed +system.cpu3.iew.exec_branches 49060 # Number of branches executed +system.cpu3.iew.exec_stores 34297 # Number of stores executed +system.cpu3.iew.exec_rate 1.213725 # Inst execution rate +system.cpu3.iew.wb_sent 233093 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 232596 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 128296 # num instructions producing a value +system.cpu3.iew.wb_consumers 135910 # num instructions consuming a value +system.cpu3.iew.wb_rate 1.206736 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.943978 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 25736 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 8582 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2339 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 186297 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.382277 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.944418 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 92574 49.69% 49.69% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 45329 24.33% 74.02% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5460 2.93% 76.95% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 9239 4.96% 81.91% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1287 0.69% 82.60% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 29468 15.82% 98.42% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 712 0.38% 98.80% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1036 0.56% 99.36% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1192 0.64% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::total 186297 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 257514 # Number of instructions committed +system.cpu3.commit.committedOps 257514 # Number of ops (including micro ops) committed +system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu3.commit.refs 106267 # Number of memory references committed +system.cpu3.commit.loads 73290 # Number of loads committed +system.cpu3.commit.membars 7865 # Number of memory barriers committed +system.cpu3.commit.branches 46801 # Number of branches committed +system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 175188 # Number of committed integer instructions. +system.cpu3.commit.function_calls 322 # Number of function calls committed. +system.cpu3.commit.op_class_0::No_OpClass 37588 14.60% 14.60% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 105794 41.08% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.68% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 81155 31.51% 87.19% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 32977 12.81% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::total 257514 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1192 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 467769 # The number of ROB reads +system.cpu3.rob.rob_writes 571412 # The number of ROB writes +system.cpu3.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1607 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 48179 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 212061 # Number of Instructions Simulated +system.cpu3.committedOps 212061 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.908927 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.908927 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.100198 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.100198 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 395124 # number of integer regfile reads +system.cpu3.int_regfile_writes 185063 # number of integer regfile writes +system.cpu3.fp_regfile_writes 64 # number of floating regfile writes +system.cpu3.misc_regfile_reads 112177 # number of misc regfile reads +system.cpu3.misc_regfile_writes 648 # number of misc regfile writes +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 24.465247 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 40069 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1381.689655 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.465247 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047784 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.047784 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 319388 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 319388 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 46353 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 46353 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 32769 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 32769 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 79122 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 79122 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 79122 # number of overall hits +system.cpu3.dcache.overall_hits::total 79122 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 454 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 454 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 137 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 137 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 591 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 591 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 591 # number of overall misses +system.cpu3.dcache.overall_misses::total 591 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 6996500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 6996500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2957500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2957500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 770500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 770500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 9954000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 9954000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 9954000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 9954000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 46807 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 46807 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 32906 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 32906 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 79713 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 79713 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 79713 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 79713 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009699 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.009699 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004163 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.004163 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.788732 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.788732 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007414 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.007414 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007414 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.007414 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15410.792952 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 15410.792952 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21587.591241 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 21587.591241 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 13758.928571 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 13758.928571 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16842.639594 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 16842.639594 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16842.639594 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 16842.639594 # average overall miss latency +system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 292 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 292 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 35 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits +system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data 3 # number of SwapReq MSHR hits +system.cpu3.dcache.SwapReq_mshr_hits::total 3 # number of SwapReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 327 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 327 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 327 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 327 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 162 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 102 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 53 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 264 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 264 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1605500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1605500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1601500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1601500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 714500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 714500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3207000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3207000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3207000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3207000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003461 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003461 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003100 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003100 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.746479 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.746479 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003312 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003312 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003312 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003312 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9910.493827 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9910.493827 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15700.980392 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15700.980392 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 13481.132075 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 13481.132075 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12147.727273 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12147.727273 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12147.727273 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12147.727273 # average overall mshr miss latency +system.cpu3.icache.tags.replacements 563 # number of replacements +system.cpu3.icache.tags.tagsinuse 93.764815 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 29516 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 701 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 42.105563 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 93.764815 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.183134 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.183134 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.269531 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 31038 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 31038 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 29516 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 29516 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 29516 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 29516 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 29516 # number of overall hits +system.cpu3.icache.overall_hits::total 29516 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 821 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 821 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 821 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 821 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 821 # number of overall misses +system.cpu3.icache.overall_misses::total 821 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 11709000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 11709000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 11709000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 11709000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 11709000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 11709000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 30337 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 30337 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 30337 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 30337 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 30337 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 30337 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.027063 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.027063 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.027063 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.027063 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.027063 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.027063 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14261.875761 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 14261.875761 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14261.875761 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 14261.875761 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14261.875761 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 14261.875761 # average overall miss latency +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu3.icache.writebacks::writebacks 563 # number of writebacks +system.cpu3.icache.writebacks::total 563 # number of writebacks +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 120 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 120 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 120 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 120 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 120 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 701 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 701 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 701 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 701 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 701 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 701 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 10046500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 10046500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 10046500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 10046500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 10046500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 10046500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.023107 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.023107 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.023107 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.023107 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.023107 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.023107 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 14331.669044 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 14331.669044 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 14331.669044 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 14331.669044 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 14331.669044 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 14331.669044 # average overall mshr miss latency +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 455.287968 # Cycle average of tags in use +system.l2c.tags.total_refs 3075 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 580 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 5.301724 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.808056 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 302.503225 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.822483 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 70.101034 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 5.583860 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 9.384250 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1.286758 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 5.637625 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 1.160677 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004616 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000898 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.001070 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000085 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000143 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000020 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000086 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000018 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006947 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 580 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 408 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.008850 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 31874 # Number of tag accesses +system.l2c.tags.data_accesses 31874 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 709 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 709 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 319 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 617 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 711 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 686 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 2333 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 11 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 319 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 617 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 711 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 686 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits +system.l2c.demand_hits::total 2365 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 319 # number of overall hits +system.l2c.overall_hits::cpu0.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.inst 617 # number of overall hits +system.l2c.overall_hits::cpu1.data 5 # number of overall hits +system.l2c.overall_hits::cpu2.inst 711 # number of overall hits +system.l2c.overall_hits::cpu2.data 11 # number of overall hits +system.l2c.overall_hits::cpu3.inst 686 # number of overall hits +system.l2c.overall_hits::cpu3.data 11 # number of overall hits +system.l2c.overall_hits::total 2365 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 21 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 24 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 85 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 377 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 96 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 22 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 15 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 510 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 76 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 9 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 3 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 90 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 377 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 170 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 96 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 22 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 22 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 15 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 15 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 14 # number of demand (read+write) misses +system.l2c.demand_misses::total 731 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 377 # number of overall misses +system.l2c.overall_misses::cpu0.data 170 # number of overall misses +system.l2c.overall_misses::cpu1.inst 96 # number of overall misses +system.l2c.overall_misses::cpu1.data 22 # number of overall misses +system.l2c.overall_misses::cpu2.inst 22 # number of overall misses +system.l2c.overall_misses::cpu2.data 15 # number of overall misses +system.l2c.overall_misses::cpu3.inst 15 # number of overall misses +system.l2c.overall_misses::cpu3.data 14 # number of overall misses +system.l2c.overall_misses::total 731 # number of overall misses +system.l2c.ReadExReq_miss_latency::cpu0.data 7826000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1039500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 940000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 937500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10743000 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 29108500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 7180500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 1748500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu3.inst 1200000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 39237500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 6133500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 728000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 251500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3.data 195000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 7308000 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 29108500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 13959500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 7180500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1767500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 1748500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1191500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 1200000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 1132500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 57288500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 29108500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 13959500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 7180500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1767500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 1748500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1191500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 1200000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 1132500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 57288500 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 709 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 709 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 24 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 24 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 88 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 696 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 713 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 733 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu3.inst 701 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 2843 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 81 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 14 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 14 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3.data 13 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 122 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 696 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 175 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 713 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 27 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 733 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 701 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3096 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 696 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 175 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 713 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 27 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 733 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 701 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3096 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.875000 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.965909 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.541667 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.134642 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.030014 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.021398 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.179388 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.938272 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.642857 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.214286 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.153846 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.737705 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.541667 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.971429 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.134642 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.814815 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.030014 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.576923 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.021398 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.560000 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.236111 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.541667 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.971429 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.134642 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.814815 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.030014 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.576923 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.021398 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.560000 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.236111 # miss rate for overall accesses +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83255.319149 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 79961.538462 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 78333.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 78125 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 82007.633588 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 77210.875332 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 74796.875000 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 79477.272727 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 80000 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 76936.274510 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 80703.947368 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 80888.888889 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 83833.333333 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 97500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 81200 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 77210.875332 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 82114.705882 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 74796.875000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 80340.909091 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 79477.272727 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 79433.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 80000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 80892.857143 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 78370.041040 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 77210.875332 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 82114.705882 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 74796.875000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 80340.909091 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 79477.272727 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 79433.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 80000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 80892.857143 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 78370.041040 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 8 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 4 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::total 17 # number of ReadCleanReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits +system.l2c.UpgradeReq_mshr_misses::cpu0.data 21 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 20 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 24 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 85 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 376 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 92 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 14 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 11 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 493 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 76 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 9 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 3 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu3.data 2 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 90 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 376 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 170 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 92 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 22 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 14 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 15 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 11 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.data 14 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 714 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 376 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 170 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 92 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 22 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 14 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 15 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 11 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.data 14 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 714 # number of overall MSHR misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 419500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 400000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 480000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 398000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1697500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6886000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 909500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 820000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 817500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 9433000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 25321000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 6077500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 1080000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 797000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 33275500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 5373500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 638000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 221500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 175000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 6408000 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 25321000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 12259500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 6077500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1547500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 1080000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1041500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 797000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 992500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 49116500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 25321000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 12259500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 6077500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1547500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 1080000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1041500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 797000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 992500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 49116500 # number of overall MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.875000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.965909 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.540230 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.129032 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.019100 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.015692 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.173408 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.938272 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.642857 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.214286 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.153846 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.737705 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.540230 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.129032 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.814815 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.019100 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.576923 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.015692 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.560000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.230620 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.540230 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.129032 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.814815 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.019100 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.576923 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.015692 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.560000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.230620 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19976.190476 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 19900 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19970.588235 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73255.319149 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69961.538462 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68333.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 68125 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72007.633588 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 67343.085106 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66059.782609 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 77142.857143 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72454.545455 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 67495.943205 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70703.947368 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 70888.888889 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 73833.333333 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 87500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71200 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67343.085106 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72114.705882 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66059.782609 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70340.909091 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 77142.857143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 69433.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72454.545455 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 70892.857143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 68790.616246 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67343.085106 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72114.705882 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66059.782609 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70340.909091 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 77142.857143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69433.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72454.545455 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 70892.857143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 68790.616246 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 1042 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 329 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadResp 582 # Transaction distribution +system.membus.trans_dist::UpgradeReq 274 # Transaction distribution +system.membus.trans_dist::ReadExReq 186 # Transaction distribution +system.membus.trans_dist::ReadExResp 131 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 582 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1755 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1755 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45632 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45632 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 244 # Total snoops (count) +system.membus.snoop_fanout::samples 1042 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1042 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1042 # Request fanout histogram +system.membus.reqLayer0.occupancy 989502 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3800250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.1 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 6343 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1724 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 3317 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadResp 3517 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 9 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 2134 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 403 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 403 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 2843 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 684 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1785 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 593 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 2005 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 377 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 2064 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1965 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 9526 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69696 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11264 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 82688 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1728 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 85184 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 80896 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 334720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1023 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4207 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.289042 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.099056 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1302 30.95% 30.95% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1193 28.36% 59.31% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 906 21.54% 80.84% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 806 19.16% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 4207 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5321969 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1043498 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 522987 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 1072493 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.9 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 443462 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 1103489 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.9 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 430971 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 1053495 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.8 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 426466 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index e69de29bb..8aafd14ee 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -0,0 +1,997 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000088 # Number of seconds simulated +sim_ticks 87707000 # Number of ticks simulated +final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 856943 # Simulator instruction rate (inst/s) +host_op_rate 856930 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 110961270 # Simulator tick rate (ticks/s) +host_mem_usage 258436 # Number of bytes of host memory used +host_seconds 0.79 # Real time elapsed on the host +sim_insts 677333 # Number of instructions simulated +sim_ops 677333 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::total 35776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::total 559 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 2189107 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 729702 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 2189107 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 729702 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 2189107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.workload.num_syscalls 89 # Number of system calls +system.cpu0.numCycles 175415 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 175326 # Number of instructions committed +system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu0.num_func_calls 390 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls +system.cpu0.num_int_insts 120376 # number of integer instructions +system.cpu0.num_fp_insts 0 # number of float instructions +system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read +system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu0.num_mem_refs 82397 # number of memory refs +system.cpu0.num_load_insts 54591 # Number of load instructions +system.cpu0.num_store_insts 27806 # Number of store instructions +system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu0.num_busy_cycles 175414.998000 # Number of busy cycles +system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu0.Branches 29689 # Number of branches fetched +system.cpu0.op_class::No_OpClass 26416 15.06% 15.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 66491 37.91% 52.97% # Class of executed instruction +system.cpu0.op_class::IntMult 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 52.97% # Class of executed instruction +system.cpu0.op_class::MemRead 54675 31.17% 84.15% # Class of executed instruction +system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 175388 # Class of executed instruction +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 490.311377 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745705 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 329804 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 329804 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits +system.cpu0.dcache.overall_hits::total 82008 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses +system.cpu0.dcache.overall_misses::total 328 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu0.dcache.writebacks::total 1 # number of writebacks +system.cpu0.icache.tags.replacements 215 # number of replacements +system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits +system.cpu0.icache.overall_hits::total 174921 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses +system.cpu0.icache.overall_misses::total 467 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.writebacks::writebacks 215 # number of writebacks +system.cpu0.icache.writebacks::total 215 # number of writebacks +system.cpu1.numCycles 173297 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 167400 # Number of instructions committed +system.cpu1.committedOps 167400 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 107326 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu1.num_func_calls 633 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 34043 # number of instructions that are conditional controls +system.cpu1.num_int_insts 107326 # number of integer instructions +system.cpu1.num_fp_insts 0 # number of float instructions +system.cpu1.num_int_register_reads 254436 # number of times the integer registers were read +system.cpu1.num_int_register_writes 94218 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu1.num_mem_refs 49494 # number of memory refs +system.cpu1.num_load_insts 39345 # Number of load instructions +system.cpu1.num_store_insts 10149 # Number of store instructions +system.cpu1.num_idle_cycles 7872.827276 # Number of idle cycles +system.cpu1.num_busy_cycles 165424.172724 # Number of busy cycles +system.cpu1.not_idle_fraction 0.954570 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.045430 # Percentage of idle cycles +system.cpu1.Branches 35694 # Number of branches fetched +system.cpu1.op_class::No_OpClass 26475 15.81% 15.81% # Class of executed instruction +system.cpu1.op_class::IntAlu 71873 42.93% 58.74% # Class of executed instruction +system.cpu1.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction +system.cpu1.op_class::MemRead 58935 35.20% 93.94% # Class of executed instruction +system.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 167432 # Class of executed instruction +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 828.038462 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.295170 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059170 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.059170 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 198211 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 198211 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 39152 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 39152 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 9968 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 9968 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 49120 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 49120 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 49120 # number of overall hits +system.cpu1.dcache.overall_hits::total 49120 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 185 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 185 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 102 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 102 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 61 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 61 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 287 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 287 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 287 # number of overall misses +system.cpu1.dcache.overall_misses::total 287 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 39337 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 39337 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 10070 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 10070 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 77 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 77 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 49407 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 49407 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 49407 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 49407 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004703 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004703 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.010129 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.010129 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.792208 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.792208 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005809 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005809 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005809 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005809 # miss rate for overall accesses +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.tags.replacements 278 # number of replacements +system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 167074 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 167074 # number of overall hits +system.cpu1.icache.overall_hits::total 167074 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses +system.cpu1.icache.overall_misses::total 358 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 167432 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 278 # number of writebacks +system.cpu1.icache.writebacks::total 278 # number of writebacks +system.cpu2.numCycles 173296 # number of cpu cycles simulated +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.committedInsts 167335 # Number of instructions committed +system.cpu2.committedOps 167335 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 114196 # Number of integer alu accesses +system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu2.num_func_calls 633 # number of times a function call or return occured +system.cpu2.num_conditional_control_insts 30577 # number of instructions that are conditional controls +system.cpu2.num_int_insts 114196 # number of integer instructions +system.cpu2.num_fp_insts 0 # number of float instructions +system.cpu2.num_int_register_reads 295784 # number of times the integer registers were read +system.cpu2.num_int_register_writes 111461 # number of times the integer registers were written +system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu2.num_mem_refs 59830 # number of memory refs +system.cpu2.num_load_insts 42793 # Number of load instructions +system.cpu2.num_store_insts 17037 # Number of store instructions +system.cpu2.num_idle_cycles 7936.997017 # Number of idle cycles +system.cpu2.num_busy_cycles 165359.002983 # Number of busy cycles +system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles +system.cpu2.Branches 32221 # Number of branches fetched +system.cpu2.op_class::No_OpClass 23013 13.75% 13.75% # Class of executed instruction +system.cpu2.op_class::IntAlu 75303 44.99% 58.74% # Class of executed instruction +system.cpu2.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction +system.cpu2.op_class::MemRead 52014 31.08% 89.82% # Class of executed instruction +system.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Class of executed instruction +system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu2.op_class::total 167367 # Class of executed instruction +system.cpu2.dcache.tags.replacements 0 # number of replacements +system.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1313.222222 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.575165 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057764 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.057764 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 239521 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 239521 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 42635 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42635 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 16864 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 16864 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 59499 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 59499 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 59499 # number of overall hits +system.cpu2.dcache.overall_hits::total 59499 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 150 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 150 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 255 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 255 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 255 # number of overall misses +system.cpu2.dcache.overall_misses::total 255 # number of overall misses +system.cpu2.dcache.ReadReq_accesses::cpu2.data 42785 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 42785 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 16969 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 16969 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 59754 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 59754 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 59754 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 59754 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003506 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003506 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006188 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.006188 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.818182 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004267 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004267 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004267 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004267 # miss rate for overall accesses +system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu2.icache.tags.replacements 278 # number of replacements +system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 167009 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 167009 # number of overall hits +system.cpu2.icache.overall_hits::total 167009 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses +system.cpu2.icache.overall_misses::total 358 # number of overall misses +system.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses +system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu2.icache.writebacks::writebacks 278 # number of writebacks +system.cpu2.icache.writebacks::total 278 # number of writebacks +system.cpu3.numCycles 173297 # number of cpu cycles simulated +system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu3.committedInsts 167272 # Number of instructions committed +system.cpu3.committedOps 167272 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 113295 # Number of integer alu accesses +system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu3.num_func_calls 633 # number of times a function call or return occured +system.cpu3.num_conditional_control_insts 30996 # number of instructions that are conditional controls +system.cpu3.num_int_insts 113295 # number of integer instructions +system.cpu3.num_fp_insts 0 # number of float instructions +system.cpu3.num_int_register_reads 290503 # number of times the integer registers were read +system.cpu3.num_int_register_writes 109270 # number of times the integer registers were written +system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu3.num_mem_refs 58510 # number of memory refs +system.cpu3.num_load_insts 42344 # Number of load instructions +system.cpu3.num_store_insts 16166 # Number of store instructions +system.cpu3.num_idle_cycles 7999.282495 # Number of idle cycles +system.cpu3.num_busy_cycles 165297.717505 # Number of busy cycles +system.cpu3.not_idle_fraction 0.953841 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.046159 # Percentage of idle cycles +system.cpu3.Branches 32639 # Number of branches fetched +system.cpu3.op_class::No_OpClass 23433 14.01% 14.01% # Class of executed instruction +system.cpu3.op_class::IntAlu 74851 44.74% 58.75% # Class of executed instruction +system.cpu3.op_class::IntMult 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::IntDiv 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::FloatCmp 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::FloatCvt 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::FloatMult 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::FloatDiv 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::FloatSqrt 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdAdd 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdAddAcc 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdAlu 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdCmp 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdCvt 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdMisc 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdMult 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdMultAcc 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdShift 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdSqrt 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdFloatMult 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction +system.cpu3.op_class::MemRead 52854 31.59% 90.34% # Class of executed instruction +system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Class of executed instruction +system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu3.op_class::total 167304 # Class of executed instruction +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1292.115385 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.848199 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056344 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.056344 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 234241 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 234241 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 42185 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 42185 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 15991 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 15991 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 58176 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 58176 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 58176 # number of overall hits +system.cpu3.dcache.overall_hits::total 58176 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 260 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 260 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 260 # number of overall misses +system.cpu3.dcache.overall_misses::total 260 # number of overall misses +system.cpu3.dcache.ReadReq_accesses::cpu3.data 42336 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 42336 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 16100 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 16100 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 58436 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 58436 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 58436 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 58436 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003567 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003567 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006770 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.006770 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004449 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.004449 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004449 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.004449 # miss rate for overall accesses +system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu3.icache.tags.replacements 279 # number of replacements +system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits +system.cpu3.icache.overall_hits::total 166945 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses +system.cpu3.icache.overall_misses::total 359 # number of overall misses +system.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu3.icache.writebacks::writebacks 279 # number of writebacks +system.cpu3.icache.writebacks::total 279 # number of writebacks +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 367.545675 # Cycle average of tags in use +system.l2c.tags.total_refs 1716 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 422 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.066351 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 56.170311 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.935416 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000857 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.005608 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 422 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.006439 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 19424 # Number of tag accesses +system.l2c.tags.data_accesses 19424 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 185 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 296 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 355 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1194 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 3 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::total 1220 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 185 # number of overall hits +system.l2c.overall_hits::cpu0.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.inst 296 # number of overall hits +system.l2c.overall_hits::cpu1.data 3 # number of overall hits +system.l2c.overall_hits::cpu2.inst 355 # number of overall hits +system.l2c.overall_hits::cpu2.data 9 # number of overall hits +system.l2c.overall_hits::cpu3.inst 358 # number of overall hits +system.l2c.overall_hits::cpu3.data 9 # number of overall hits +system.l2c.overall_hits::total 1220 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 282 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 62 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 3 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 1 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 348 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 75 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses +system.l2c.demand_misses::total 559 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 282 # number of overall misses +system.l2c.overall_misses::cpu0.data 165 # number of overall misses +system.l2c.overall_misses::cpu1.inst 62 # number of overall misses +system.l2c.overall_misses::cpu1.data 20 # number of overall misses +system.l2c.overall_misses::cpu2.inst 3 # number of overall misses +system.l2c.overall_misses::cpu2.data 13 # number of overall misses +system.l2c.overall_misses::cpu3.inst 1 # number of overall misses +system.l2c.overall_misses::cpu3.data 13 # number of overall misses +system.l2c.overall_misses::total 559 # number of overall misses +system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 358 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 358 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu3.inst 359 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1542 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 10 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 10 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3.data 10 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.975610 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.225681 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.742574 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.membus.snoop_filter.tot_requests 879 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 320 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadResp 423 # Transaction distribution +system.membus.trans_dist::UpgradeReq 273 # Transaction distribution +system.membus.trans_dist::UpgradeResp 80 # Transaction distribution +system.membus.trans_dist::ReadExReq 183 # Transaction distribution +system.membus.trans_dist::ReadExResp 136 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 423 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1518 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1518 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 879 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 879 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 879 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1221 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1709 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1050 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 233088 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 0 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.246554 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.199505 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1485 37.90% 37.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 951 24.27% 62.17% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 513 13.09% 75.27% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 969 24.73% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3918 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index e69de29bb..e6dfdce46 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -0,0 +1,1644 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000264 # Number of seconds simulated +sim_ticks 264174500 # Number of ticks simulated +final_tick 264174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 587931 # Simulator instruction rate (inst/s) +host_op_rate 587915 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 234112560 # Simulator tick rate (ticks/s) +host_mem_usage 258432 # Number of bytes of host memory used +host_seconds 1.13 # Real time elapsed on the host +sim_insts 663394 # Number of instructions simulated +sim_ops 663394 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 36608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 3712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 58 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 572 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 69045271 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 39973578 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 1695849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3633962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 14051318 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 5572075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 969056 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3633962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 138575071 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69045271 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 1695849 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 14051318 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 969056 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 85761495 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69045271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 39973578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 1695849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3633962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 14051318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 5572075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 969056 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3633962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 138575071 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.workload.num_syscalls 89 # Number of system calls +system.cpu0.numCycles 528349 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 158268 # Number of instructions committed +system.cpu0.committedOps 158268 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 109004 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu0.num_func_calls 390 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 25981 # number of instructions that are conditional controls +system.cpu0.num_int_insts 109004 # number of integer instructions +system.cpu0.num_fp_insts 0 # number of float instructions +system.cpu0.num_int_register_reads 315170 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110610 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu0.num_mem_refs 73868 # number of memory refs +system.cpu0.num_load_insts 48905 # Number of load instructions +system.cpu0.num_store_insts 24963 # Number of store instructions +system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu0.num_busy_cycles 528348.998000 # Number of busy cycles +system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu0.Branches 26846 # Number of branches fetched +system.cpu0.op_class::No_OpClass 23573 14.89% 14.89% # Class of executed instruction +system.cpu0.op_class::IntAlu 60805 38.40% 53.29% # Class of executed instruction +system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::MemRead 48989 30.94% 84.23% # Class of executed instruction +system.cpu0.op_class::MemWrite 24963 15.77% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 158330 # Class of executed instruction +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 144.970648 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 73336 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 439.137725 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.970648 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283146 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.283146 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 295705 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 295705 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 48725 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48725 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24729 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24729 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 73454 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73454 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73454 # number of overall hits +system.cpu0.dcache.overall_hits::total 73454 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses +system.cpu0.dcache.overall_misses::total 353 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4908500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4908500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7106500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7106500 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 400000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 400000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 12015000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 12015000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 12015000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 12015000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48895 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48895 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24912 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24912 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 73807 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73807 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73807 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73807 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003477 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003477 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007346 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007346 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004783 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004783 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004783 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004783 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28873.529412 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28873.529412 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38833.333333 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38833.333333 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15384.615385 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 15384.615385 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34036.827195 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34036.827195 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34036.827195 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34036.827195 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu0.dcache.writebacks::total 1 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4738500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4738500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6923500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6923500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 374000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 374000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11662000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11662000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11662000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11662000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003477 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003477 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007346 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007346 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004783 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004783 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004783 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004783 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27873.529412 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27873.529412 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37833.333333 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37833.333333 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14384.615385 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14384.615385 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33036.827195 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33036.827195 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33036.827195 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33036.827195 # average overall mshr miss latency +system.cpu0.icache.tags.replacements 215 # number of replacements +system.cpu0.icache.tags.tagsinuse 211.220090 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 157864 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 338.038544 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.220090 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.412539 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.412539 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 158798 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 158798 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 157864 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 157864 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 157864 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 157864 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 157864 # number of overall hits +system.cpu0.icache.overall_hits::total 157864 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses +system.cpu0.icache.overall_misses::total 467 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20426500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 20426500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 20426500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 20426500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 20426500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 20426500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 158331 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 158331 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 158331 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 158331 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 158331 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 158331 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002950 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002950 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002950 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002950 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002950 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002950 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43739.828694 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 43739.828694 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43739.828694 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 43739.828694 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43739.828694 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 43739.828694 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.writebacks::writebacks 215 # number of writebacks +system.cpu0.icache.writebacks::total 215 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19959500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 19959500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19959500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 19959500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19959500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 19959500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002950 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002950 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42739.828694 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 42739.828694 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 42739.828694 # average overall mshr miss latency +system.cpu1.numCycles 528348 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 170000 # Number of instructions committed +system.cpu1.committedOps 170000 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 111041 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu1.num_func_calls 637 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 33487 # number of instructions that are conditional controls +system.cpu1.num_int_insts 111041 # number of integer instructions +system.cpu1.num_fp_insts 0 # number of float instructions +system.cpu1.num_int_register_reads 272446 # number of times the integer registers were read +system.cpu1.num_int_register_writes 102959 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu1.num_mem_refs 53722 # number of memory refs +system.cpu1.num_load_insts 41185 # Number of load instructions +system.cpu1.num_store_insts 12537 # Number of store instructions +system.cpu1.num_idle_cycles 74693.860345 # Number of idle cycles +system.cpu1.num_busy_cycles 453654.139655 # Number of busy cycles +system.cpu1.not_idle_fraction 0.858628 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.141372 # Percentage of idle cycles +system.cpu1.Branches 35142 # Number of branches fetched +system.cpu1.op_class::No_OpClass 25921 15.24% 15.24% # Class of executed instruction +system.cpu1.op_class::IntAlu 74786 43.98% 59.23% # Class of executed instruction +system.cpu1.op_class::IntMult 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.23% # Class of executed instruction +system.cpu1.op_class::MemRead 56788 33.40% 92.63% # Class of executed instruction +system.cpu1.op_class::MemWrite 12537 7.37% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 170032 # Class of executed instruction +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 26.444551 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 27473 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 915.766667 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.444551 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051650 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.051650 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 215113 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 215113 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 41008 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 41008 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 12359 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 12359 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 53367 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 53367 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 53367 # number of overall hits +system.cpu1.dcache.overall_hits::total 53367 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 169 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 169 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 274 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 274 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 274 # number of overall misses +system.cpu1.dcache.overall_misses::total 274 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1910000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1910000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1724000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1724000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 260500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 260500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 3634000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 3634000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 3634000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 3634000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 41177 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 41177 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 12464 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 12464 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 53641 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 53641 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 53641 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 53641 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004104 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004104 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008424 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.008424 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.816901 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005108 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005108 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005108 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005108 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11301.775148 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 11301.775148 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16419.047619 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16419.047619 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4491.379310 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 4491.379310 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13262.773723 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 13262.773723 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13262.773723 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13262.773723 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 169 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 58 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 274 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 274 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1741000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1741000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1619000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1619000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 202500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 202500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3360000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3360000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3360000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3360000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004104 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004104 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008424 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008424 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.816901 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005108 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.005108 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005108 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.005108 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10301.775148 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10301.775148 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15419.047619 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15419.047619 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3491.379310 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3491.379310 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12262.773723 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12262.773723 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12262.773723 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12262.773723 # average overall mshr miss latency +system.cpu1.icache.tags.replacements 280 # number of replacements +system.cpu1.icache.tags.tagsinuse 66.843295 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 169667 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 463.571038 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 66.843295 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130553 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.130553 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 170399 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 170399 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 169667 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 169667 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 169667 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 169667 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 169667 # number of overall hits +system.cpu1.icache.overall_hits::total 169667 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses +system.cpu1.icache.overall_misses::total 366 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5695000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5695000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5695000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5695000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5695000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5695000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 170033 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 170033 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 170033 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 170033 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 170033 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 170033 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002153 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002153 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002153 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002153 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002153 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002153 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15560.109290 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15560.109290 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15560.109290 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15560.109290 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15560.109290 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15560.109290 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 280 # number of writebacks +system.cpu1.icache.writebacks::total 280 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5329000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5329000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5329000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5329000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5329000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5329000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002153 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002153 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002153 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002153 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002153 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002153 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14560.109290 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14560.109290 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14560.109290 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 14560.109290 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14560.109290 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 14560.109290 # average overall mshr miss latency +system.cpu2.numCycles 528349 # number of cpu cycles simulated +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.committedInsts 165687 # Number of instructions committed +system.cpu2.committedOps 165687 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 110528 # Number of integer alu accesses +system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu2.num_func_calls 637 # number of times a function call or return occured +system.cpu2.num_conditional_control_insts 31586 # number of instructions that are conditional controls +system.cpu2.num_int_insts 110528 # number of integer instructions +system.cpu2.num_fp_insts 0 # number of float instructions +system.cpu2.num_int_register_reads 278004 # number of times the integer registers were read +system.cpu2.num_int_register_writes 105995 # number of times the integer registers were written +system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu2.num_mem_refs 55111 # number of memory refs +system.cpu2.num_load_insts 40928 # Number of load instructions +system.cpu2.num_store_insts 14183 # Number of store instructions +system.cpu2.num_idle_cycles 74966.001716 # Number of idle cycles +system.cpu2.num_busy_cycles 453382.998284 # Number of busy cycles +system.cpu2.not_idle_fraction 0.858113 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.141887 # Percentage of idle cycles +system.cpu2.Branches 33243 # Number of branches fetched +system.cpu2.op_class::No_OpClass 24020 14.49% 14.49% # Class of executed instruction +system.cpu2.op_class::IntAlu 74533 44.98% 59.47% # Class of executed instruction +system.cpu2.op_class::IntMult 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::IntDiv 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::FloatAdd 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::FloatCmp 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::FloatCvt 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::FloatMult 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::FloatDiv 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::FloatSqrt 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdAdd 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdAddAcc 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdAlu 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdCmp 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdCvt 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdMisc 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdMult 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdMultAcc 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdShift 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdSqrt 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatMult 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::MemRead 52983 31.97% 91.44% # Class of executed instruction +system.cpu2.op_class::MemWrite 14183 8.56% 100.00% # Class of executed instruction +system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu2.op_class::total 165719 # Class of executed instruction +system.cpu2.dcache.tags.replacements 0 # number of replacements +system.cpu2.dcache.tags.tagsinuse 27.447331 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 30642 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1056.620690 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.447331 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053608 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.053608 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 220669 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 220669 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 40751 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 40751 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 14004 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 14004 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 54755 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 54755 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 54755 # number of overall hits +system.cpu2.dcache.overall_hits::total 54755 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 169 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 169 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 60 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 60 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 274 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 274 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 274 # number of overall misses +system.cpu2.dcache.overall_misses::total 274 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2144500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2144500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1802500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 1802500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 267500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 267500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 3947000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 3947000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 3947000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 3947000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 40920 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 40920 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 14109 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 14109 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 72 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 55029 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 55029 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 55029 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 55029 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.004130 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.004130 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007442 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.007442 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004979 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004979 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004979 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004979 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12689.349112 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 12689.349112 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17166.666667 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 17166.666667 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4458.333333 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 4458.333333 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14405.109489 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 14405.109489 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14405.109489 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 14405.109489 # average overall miss latency +system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 169 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 60 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 274 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 274 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1975500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1975500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1697500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1697500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 207500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 207500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3673000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3673000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3673000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3673000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004130 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004130 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007442 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007442 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.833333 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004979 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004979 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004979 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004979 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11689.349112 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11689.349112 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16166.666667 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16166.666667 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3458.333333 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3458.333333 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13405.109489 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13405.109489 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13405.109489 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13405.109489 # average overall mshr miss latency +system.cpu2.icache.tags.replacements 280 # number of replacements +system.cpu2.icache.tags.tagsinuse 69.258301 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 165354 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 451.786885 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.258301 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135270 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.135270 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 166086 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 166086 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 165354 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 165354 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 165354 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 165354 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 165354 # number of overall hits +system.cpu2.icache.overall_hits::total 165354 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses +system.cpu2.icache.overall_misses::total 366 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8165500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 8165500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 8165500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 8165500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 8165500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 8165500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 165720 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 165720 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 165720 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 165720 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 165720 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 165720 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002209 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002209 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002209 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002209 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002209 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002209 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22310.109290 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 22310.109290 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22310.109290 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 22310.109290 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22310.109290 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 22310.109290 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu2.icache.writebacks::writebacks 280 # number of writebacks +system.cpu2.icache.writebacks::total 280 # number of writebacks +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7799500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 7799500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7799500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 7799500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7799500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 7799500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002209 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002209 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002209 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002209 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21310.109290 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 21310.109290 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 21310.109290 # average overall mshr miss latency +system.cpu3.numCycles 528348 # number of cpu cycles simulated +system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu3.committedInsts 169439 # Number of instructions committed +system.cpu3.committedOps 169439 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 111342 # Number of integer alu accesses +system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu3.num_func_calls 637 # number of times a function call or return occured +system.cpu3.num_conditional_control_insts 33059 # number of instructions that are conditional controls +system.cpu3.num_int_insts 111342 # number of integer instructions +system.cpu3.num_fp_insts 0 # number of float instructions +system.cpu3.num_int_register_reads 275359 # number of times the integer registers were read +system.cpu3.num_int_register_writes 104262 # number of times the integer registers were written +system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu3.num_mem_refs 54451 # number of memory refs +system.cpu3.num_load_insts 41338 # Number of load instructions +system.cpu3.num_store_insts 13113 # Number of store instructions +system.cpu3.num_idle_cycles 75238.859311 # Number of idle cycles +system.cpu3.num_busy_cycles 453109.140689 # Number of busy cycles +system.cpu3.not_idle_fraction 0.857596 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.142404 # Percentage of idle cycles +system.cpu3.Branches 34709 # Number of branches fetched +system.cpu3.op_class::No_OpClass 25492 15.04% 15.04% # Class of executed instruction +system.cpu3.op_class::IntAlu 74930 44.21% 59.26% # Class of executed instruction +system.cpu3.op_class::IntMult 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::IntDiv 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::FloatAdd 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::FloatCmp 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::FloatCvt 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::FloatMult 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::FloatDiv 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::FloatSqrt 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::SimdAdd 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::SimdAddAcc 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::SimdAlu 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::SimdCmp 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::SimdCvt 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::SimdMisc 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::SimdMult 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::SimdMultAcc 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::SimdShift 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::SimdSqrt 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::SimdFloatMult 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.26% # Class of executed instruction +system.cpu3.op_class::MemRead 55936 33.01% 92.26% # Class of executed instruction +system.cpu3.op_class::MemWrite 13113 7.74% 100.00% # Class of executed instruction +system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu3.op_class::total 169471 # Class of executed instruction +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 25.601960 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 28504 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 982.896552 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.601960 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050004 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.050004 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 218004 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 218004 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 41179 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41179 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 12939 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 12939 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 54118 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 54118 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 54118 # number of overall hits +system.cpu3.dcache.overall_hits::total 54118 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 256 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 256 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 256 # number of overall misses +system.cpu3.dcache.overall_misses::total 256 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 1675000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 1675000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1736000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 1736000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 234000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 234000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 3411000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 3411000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 3411000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 3411000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41330 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41330 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 13044 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 13044 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 54374 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 54374 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 54374 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 54374 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003654 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003654 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008050 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.008050 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.776119 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.776119 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004708 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.004708 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004708 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.004708 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 11092.715232 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 11092.715232 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16533.333333 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 16533.333333 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4500 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 4500 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 13324.218750 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 13324.218750 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 13324.218750 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 13324.218750 # average overall miss latency +system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 151 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 52 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 256 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 256 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 256 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 256 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1524000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1524000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1631000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1631000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 182000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 182000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3155000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3155000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3155000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3155000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003654 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003654 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008050 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008050 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.776119 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.776119 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004708 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.004708 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004708 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.004708 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10092.715232 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10092.715232 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15533.333333 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15533.333333 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3500 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3500 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12324.218750 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12324.218750 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12324.218750 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12324.218750 # average overall mshr miss latency +system.cpu3.icache.tags.replacements 281 # number of replacements +system.cpu3.icache.tags.tagsinuse 64.834449 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 169105 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 460.776567 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.834449 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126630 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.126630 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 169839 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 169839 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 169105 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 169105 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 169105 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 169105 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 169105 # number of overall hits +system.cpu3.icache.overall_hits::total 169105 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses +system.cpu3.icache.overall_misses::total 367 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5481500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5481500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5481500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5481500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5481500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5481500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 169472 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 169472 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 169472 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 169472 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 169472 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 169472 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002166 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002166 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002166 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002166 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002166 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002166 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14935.967302 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 14935.967302 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14935.967302 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 14935.967302 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14935.967302 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 14935.967302 # average overall miss latency +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu3.icache.writebacks::writebacks 281 # number of writebacks +system.cpu3.icache.writebacks::total 281 # number of writebacks +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5114500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5114500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5114500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5114500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5114500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5114500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002166 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002166 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002166 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002166 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002166 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13935.967302 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13935.967302 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13935.967302 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 13935.967302 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13935.967302 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 13935.967302 # average overall mshr miss latency +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 346.893205 # Cycle average of tags in use +system.l2c.tags.total_refs 1714 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.995338 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.880236 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 230.548613 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 53.975789 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 6.154320 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.833705 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 46.678374 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 6.077199 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.942850 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.802119 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.003518 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000824 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000094 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000712 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000093 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.005293 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 19677 # Number of tag accesses +system.l2c.tags.data_accesses 19677 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 301 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 357 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1192 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 3 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 301 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 3 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::total 1218 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 182 # number of overall hits +system.l2c.overall_hits::cpu0.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.inst 352 # number of overall hits +system.l2c.overall_hits::cpu1.data 9 # number of overall hits +system.l2c.overall_hits::cpu2.inst 301 # number of overall hits +system.l2c.overall_hits::cpu2.data 3 # number of overall hits +system.l2c.overall_hits::cpu3.inst 357 # number of overall hits +system.l2c.overall_hits::cpu3.data 9 # number of overall hits +system.l2c.overall_hits::total 1218 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 285 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 14 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 65 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 10 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 374 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 2 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 8 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 78 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 65 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 23 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 10 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses +system.l2c.demand_misses::total 594 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 285 # number of overall misses +system.l2c.overall_misses::cpu0.data 165 # number of overall misses +system.l2c.overall_misses::cpu1.inst 14 # number of overall misses +system.l2c.overall_misses::cpu1.data 16 # number of overall misses +system.l2c.overall_misses::cpu2.inst 65 # number of overall misses +system.l2c.overall_misses::cpu2.data 23 # number of overall misses +system.l2c.overall_misses::cpu3.inst 10 # number of overall misses +system.l2c.overall_misses::cpu3.data 16 # number of overall misses +system.l2c.overall_misses::total 594 # number of overall misses +system.l2c.ReadExReq_miss_latency::cpu0.data 5991000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 856000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 911000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 856500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 8614500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 17251500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 835000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3885500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu3.inst 563500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 22535500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 3993500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 120500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 484000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3.data 120000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 4718000 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 17251500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 9984500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 835000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 976500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 3885500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1395000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 563500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 976500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 35868000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 17251500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 9984500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 835000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 976500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 3885500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1395000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 563500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 976500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 35868000 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 15 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 366 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 366 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu3.inst 367 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1566 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 11 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 11 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3.data 11 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 104 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.177596 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.027248 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.238825 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.727273 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.750000 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.640000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.177596 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.884615 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.027248 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.327815 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.038251 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.640000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.177596 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.884615 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.027248 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.327815 # miss rate for overall accesses +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 60515.151515 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 61142.857143 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 60733.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 61178.571429 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 60665.492958 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 60531.578947 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 59642.857143 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 59776.923077 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 56350 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 60255.347594 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 60507.575758 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 60250 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 60500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 60000 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 60487.179487 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 60531.578947 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 60512.121212 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 59642.857143 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 61031.250000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 59776.923077 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 60652.173913 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 56350 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 61031.250000 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 60383.838384 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 60531.578947 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 60512.121212 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 59642.857143 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 61031.250000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 59776.923077 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 60652.173913 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 56350 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 61031.250000 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 60383.838384 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 7 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 7 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 6 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::total 20 # number of ReadCleanReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu3.data 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 2 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.inst 6 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.inst 6 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 22 # number of overall MSHR hits +system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 16 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 17 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 16 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 14 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 15 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 285 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 7 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 58 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 4 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 354 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 66 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 8 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu3.data 1 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 76 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 7 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 15 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 58 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 23 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 4 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.data 15 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 7 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 15 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 58 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 23 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 4 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 561000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 319000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 336500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 331000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1547500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5001000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 716000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 761000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 716500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7194500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 14401500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 358000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 2929500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 203000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 17892000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 3333500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 50500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 404000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 50500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 3838500 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 14401500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 8334500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 358000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 766500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 2929500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1165000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 203000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 767000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 28925000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 14401500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 8334500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 358000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 766500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 2929500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1165000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 203000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 767000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 28925000 # number of overall MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.974684 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010899 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.226054 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.727273 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.730769 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010899 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010899 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20035.714286 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19937.500000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19794.117647 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20687.500000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20097.402597 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 50515.151515 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51142.857143 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 50733.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 51178.571429 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 50665.492958 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 50531.578947 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51142.857143 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 50750 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 50542.372881 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 50507.575758 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 50500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 50500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 50500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 50506.578947 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50531.578947 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51142.857143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51100 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 50750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51133.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 50568.181818 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50531.578947 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51142.857143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51100 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 50750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51133.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 50568.181818 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 916 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 338 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadResp 430 # Transaction distribution +system.membus.trans_dist::UpgradeReq 272 # Transaction distribution +system.membus.trans_dist::ReadExReq 208 # Transaction distribution +system.membus.trans_dist::ReadExResp 142 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1482 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1482 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 261 # Total snoops (count) +system.membus.snoop_fanout::samples 916 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 916 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 916 # Request fanout histogram +system.membus.reqLayer0.occupancy 683633 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2860000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.1 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 3977 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1110 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 420 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 420 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 659 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 377 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1015 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 349 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5868 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41472 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 183616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1028 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2919 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.272011 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.157273 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1002 34.33% 34.33% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 784 26.86% 61.19% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 470 16.10% 77.29% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 663 22.71% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 2919 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3051987 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 501494 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 552489 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 440975 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 552491 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 442472 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 553492 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 403476 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index e69de29bb..d7757f328 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -0,0 +1,152 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.044221 # Number of seconds simulated +sim_ticks 44221003000 # Number of ticks simulated +final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1535738 # Simulator instruction rate (inst/s) +host_op_rate 1535737 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 768748978 # Simulator tick rate (ticks/s) +host_mem_usage 246592 # Number of bytes of host memory used +host_seconds 57.52 # Real time elapsed on the host +sim_insts 88340673 # Number of instructions simulated +sim_ops 88340673 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 126702647 # Number of bytes read from this memory +system.physmem.bytes_read::total 480454939 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 353752292 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 353752292 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 91652896 # Number of bytes written to this memory +system.physmem.bytes_written::total 91652896 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 88438073 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 20276638 # Number of read requests responded to by this memory +system.physmem.num_reads::total 108714711 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 14613377 # Number of write requests responded to by this memory +system.physmem.num_writes::total 14613377 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999644241 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2865214229 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10864858470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999644241 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999644241 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2072610067 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2072610067 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 20276638 # DTB read hits +system.cpu.dtb.read_misses 90148 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 20366786 # DTB read accesses +system.cpu.dtb.write_hits 14613377 # DTB write hits +system.cpu.dtb.write_misses 7252 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 14620629 # DTB write accesses +system.cpu.dtb.data_hits 34890015 # DTB hits +system.cpu.dtb.data_misses 97400 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 34987415 # DTB accesses +system.cpu.itb.fetch_hits 88438073 # ITB hits +system.cpu.itb.fetch_misses 3934 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 88442007 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4583 # Number of system calls +system.cpu.numCycles 88442007 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 88340673 # Number of instructions committed +system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses +system.cpu.num_func_calls 3321606 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls +system.cpu.num_int_insts 78039444 # number of integer instructions +system.cpu.num_fp_insts 267757 # number of float instructions +system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read +system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written +system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read +system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written +system.cpu.num_mem_refs 34987415 # number of memory refs +system.cpu.num_load_insts 20366786 # Number of load instructions +system.cpu.num_store_insts 14620629 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 88442007 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 13754477 # Number of branches fetched +system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction +system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction +system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction +system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction +system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction +system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction +system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction +system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction +system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 88438073 # Class of executed instruction +system.membus.trans_dist::ReadReq 108714711 # Transaction distribution +system.membus.trans_dist::ReadResp 108714711 # Transaction distribution +system.membus.trans_dist::WriteReq 14613377 # Transaction distribution +system.membus.trans_dist::WriteResp 14613377 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 176876146 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 69780030 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 246656176 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 353752292 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 218355543 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 572107835 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 123328088 # Request fanout histogram +system.membus.snoop_fanout::mean 0.717096 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.450410 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 34890015 28.29% 28.29% # Request fanout histogram +system.membus.snoop_fanout::1 88438073 71.71% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 123328088 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index e69de29bb..4daa87195 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -0,0 +1,546 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.134742 # Number of seconds simulated +sim_ticks 134741611500 # Number of ticks simulated +final_tick 134741611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 882134 # Simulator instruction rate (inst/s) +host_op_rate 882134 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1345475029 # Simulator tick rate (ticks/s) +host_mem_usage 255564 # Number of bytes of host memory used +host_seconds 100.14 # Real time elapsed on the host +sim_insts 88340673 # Number of instructions simulated +sim_ops 88340673 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 367360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10138112 # Number of bytes read from this memory +system.physmem.bytes_read::total 10505472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 367360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 367360 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7320448 # Number of bytes written to this memory +system.physmem.bytes_written::total 7320448 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5740 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158408 # Number of read requests responded to by this memory +system.physmem.num_reads::total 164148 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114382 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114382 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2726403 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 75241137 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 77967540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2726403 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2726403 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54329527 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54329527 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54329527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2726403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 75241137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 132297067 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 20276638 # DTB read hits +system.cpu.dtb.read_misses 90148 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 20366786 # DTB read accesses +system.cpu.dtb.write_hits 14613377 # DTB write hits +system.cpu.dtb.write_misses 7252 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 14620629 # DTB write accesses +system.cpu.dtb.data_hits 34890015 # DTB hits +system.cpu.dtb.data_misses 97400 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 34987415 # DTB accesses +system.cpu.itb.fetch_hits 88438074 # ITB hits +system.cpu.itb.fetch_misses 3934 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 88442008 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4583 # Number of system calls +system.cpu.numCycles 269483223 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 88340673 # Number of instructions committed +system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses +system.cpu.num_func_calls 3321606 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls +system.cpu.num_int_insts 78039444 # number of integer instructions +system.cpu.num_fp_insts 267757 # number of float instructions +system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read +system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written +system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read +system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written +system.cpu.num_mem_refs 34987415 # number of memory refs +system.cpu.num_load_insts 20366786 # Number of load instructions +system.cpu.num_store_insts 14620629 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 269483223 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 13754477 # Number of branches fetched +system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction +system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction +system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction +system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction +system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction +system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction +system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction +system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction +system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 88438073 # Class of executed instruction +system.cpu.dcache.tags.replacements 200248 # number of replacements +system.cpu.dcache.tags.tagsinuse 4078.397630 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 983457500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4078.397630 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995703 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995703 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3595 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits +system.cpu.dcache.overall_hits::total 34685671 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses +system.cpu.dcache.overall_misses::total 204344 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2138978000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2138978000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8279807000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8279807000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10418785000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10418785000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10418785000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10418785000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35200.243557 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35200.243557 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57667.657998 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57667.657998 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 50986.498258 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 50986.498258 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 50986.498258 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 50986.498258 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 168278 # number of writebacks +system.cpu.dcache.writebacks::total 168278 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2078212000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2078212000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8136229000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8136229000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10214441000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10214441000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10214441000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10214441000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34200.243557 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34200.243557 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56667.657998 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56667.657998 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49986.498258 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49986.498258 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency +system.cpu.icache.tags.replacements 74391 # number of replacements +system.cpu.icache.tags.tagsinuse 1870.507754 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1870.507754 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.913334 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.913334 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 191 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1708 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.998535 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 176952584 # Number of tag accesses +system.cpu.icache.tags.data_accesses 176952584 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 88361638 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 88361638 # number of overall hits +system.cpu.icache.overall_hits::total 88361638 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 76436 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 76436 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 76436 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses +system.cpu.icache.overall_misses::total 76436 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1275518500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1275518500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1275518500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1275518500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1275518500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1275518500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 88438074 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 88438074 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 88438074 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000864 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000864 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16687.405149 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16687.405149 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16687.405149 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16687.405149 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16687.405149 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16687.405149 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 74391 # number of writebacks +system.cpu.icache.writebacks::total 74391 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 76436 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 76436 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 76436 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1199082500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1199082500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1199082500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1199082500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1199082500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1199082500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15687.405149 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15687.405149 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15687.405149 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15687.405149 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15687.405149 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15687.405149 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 131998 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30708.485304 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 247404 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 164074 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.507881 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 27397.900187 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1667.759999 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1642.825119 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.836118 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.050896 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.050135 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.937149 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32076 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 731 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9441 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21639 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 122 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4751004 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4751004 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 168278 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 168278 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 74391 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 74391 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12696 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12696 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 70696 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 70696 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33240 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 33240 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 70696 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 45936 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 116632 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 70696 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 45936 # number of overall hits +system.cpu.l2cache.overall_hits::total 116632 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 130882 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 130882 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 5740 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 5740 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27526 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 27526 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 5740 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158408 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 164148 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 5740 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158408 # number of overall misses +system.cpu.l2cache.overall_misses::total 164148 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7787542500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7787542500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 341866000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 341866000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1637990000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1637990000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 341866000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9425532500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9767398500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 341866000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9425532500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9767398500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 168278 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 168278 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 74391 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 74391 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 76436 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 76436 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 60766 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 60766 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 76436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 204344 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 280780 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 76436 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 204344 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911574 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911574 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.075096 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.075096 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.452984 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.452984 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.075096 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.775203 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.584614 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.075096 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.775203 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.584614 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.485170 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.485170 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59558.536585 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59558.536585 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59507.011553 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59507.011553 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59558.536585 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.619236 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59503.609547 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59558.536585 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.619236 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59503.609547 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 114382 # number of writebacks +system.cpu.l2cache.writebacks::total 114382 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 105 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 105 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130882 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130882 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 5740 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 5740 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27526 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27526 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5740 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158408 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 164148 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5740 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158408 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 164148 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6478722500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6478722500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284466000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284466000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1362730000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1362730000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284466000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7841452500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8125918500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284466000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7841452500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8125918500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911574 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911574 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.075096 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452984 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452984 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775203 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.584614 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775203 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.584614 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.485170 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.485170 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49558.536585 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49558.536585 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49507.011553 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49507.011553 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49558.536585 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.619236 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.609547 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49558.536585 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.619236 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.609547 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 555419 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 274639 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3875 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3875 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 282660 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 74391 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 49586 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 76436 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 60766 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 227263 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 608936 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 836199 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9652928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23847808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 33500736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 131998 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 412778 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009388 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.096434 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 408903 99.06% 99.06% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3875 0.94% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 412778 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 520378500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadResp 33266 # Transaction distribution +system.membus.trans_dist::WritebackDirty 114382 # Transaction distribution +system.membus.trans_dist::CleanEvict 13845 # Transaction distribution +system.membus.trans_dist::ReadExReq 130882 # Transaction distribution +system.membus.trans_dist::ReadExResp 130882 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 33266 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 456523 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 456523 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17825920 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 292375 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 292375 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 292375 # Request fanout histogram +system.membus.reqLayer0.occupancy 750324500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 820740000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.6 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index e69de29bb..9dc871248 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,243 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.048960 # Number of seconds simulated +sim_ticks 48960022500 # Number of ticks simulated +final_tick 48960022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 866033 # Simulator instruction rate (inst/s) +host_op_rate 1107536 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 597928109 # Simulator tick rate (ticks/s) +host_mem_usage 264428 # Number of bytes of host memory used +host_seconds 81.88 # Real time elapsed on the host +sim_insts 70913204 # Number of instructions simulated +sim_ops 90688159 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 312580364 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory +system.physmem.bytes_read::total 419153709 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 312580364 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 312580364 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory +system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 78145091 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory +system.physmem.num_reads::total 101064821 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory +system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 6384399925 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2176742157 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8561142083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6384399925 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6384399925 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1606621218 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1606621218 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6384399925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3783363376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10167763301 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.numCycles 97920046 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 70913204 # Number of instructions committed +system.cpu.committedOps 90688159 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses +system.cpu.num_func_calls 3311620 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls +system.cpu.num_int_insts 81528528 # number of integer instructions +system.cpu.num_fp_insts 56 # number of float instructions +system.cpu.num_int_register_reads 141479386 # number of times the integer registers were read +system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written +system.cpu.num_fp_register_reads 36 # number of times the floating registers were read +system.cpu.num_fp_register_writes 20 # number of times the floating registers were written +system.cpu.num_cc_register_reads 266608097 # number of times the CC registers were read +system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written +system.cpu.num_mem_refs 43422001 # number of memory refs +system.cpu.num_load_insts 22866262 # Number of load instructions +system.cpu.num_store_insts 20555739 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 97920045.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 13741468 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction +system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction +system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 90690106 # Class of executed instruction +system.membus.trans_dist::ReadReq 100925158 # Transaction distribution +system.membus.trans_dist::ReadResp 100941077 # Transaction distribution +system.membus.trans_dist::WriteReq 19849901 # Transaction distribution +system.membus.trans_dist::WriteResp 19849901 # Transaction distribution +system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution +system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution +system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution +system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290182 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 241861282 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580364 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 497813920 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 120930641 # Request fanout histogram +system.membus.snoop_fanout::mean 0.646198 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 42785550 35.38% 35.38% # Request fanout histogram +system.membus.snoop_fanout::1 78145091 64.62% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 120930641 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index e69de29bb..b5cf25ee6 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,662 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.128077 # Number of seconds simulated +sim_ticks 128076834500 # Number of ticks simulated +final_tick 128076834500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 531513 # Simulator instruction rate (inst/s) +host_op_rate 678593 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 967329196 # Simulator tick rate (ticks/s) +host_mem_usage 273400 # Number of bytes of host memory used +host_seconds 132.40 # Real time elapsed on the host +sim_insts 70373651 # Number of instructions simulated +sim_ops 89847385 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7925248 # Number of bytes read from this memory +system.physmem.bytes_read::total 8158400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 233152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 233152 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5513600 # Number of bytes written to this memory +system.physmem.bytes_written::total 5513600 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3643 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123832 # Number of read requests responded to by this memory +system.physmem.num_reads::total 127475 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 86150 # Number of write requests responded to by this memory +system.physmem.num_writes::total 86150 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1820407 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 61878856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 63699263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1820407 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1820407 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43049159 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43049159 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43049159 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1820407 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 61878856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 106748422 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.numCycles 256153669 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 70373651 # Number of instructions committed +system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses +system.cpu.num_func_calls 3311620 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls +system.cpu.num_int_insts 81528528 # number of integer instructions +system.cpu.num_fp_insts 56 # number of float instructions +system.cpu.num_int_register_reads 141328550 # number of times the integer registers were read +system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written +system.cpu.num_fp_register_reads 36 # number of times the floating registers were read +system.cpu.num_fp_register_writes 20 # number of times the floating registers were written +system.cpu.num_cc_register_reads 334802072 # number of times the CC registers were read +system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written +system.cpu.num_mem_refs 43422001 # number of memory refs +system.cpu.num_load_insts 22866262 # Number of load instructions +system.cpu.num_store_insts 20555739 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 256153668.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 13741468 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction +system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction +system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 90690106 # Class of executed instruction +system.cpu.dcache.tags.replacements 155902 # number of replacements +system.cpu.dcache.tags.tagsinuse 4075.927155 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42601677 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 266.263810 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1109655500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927155 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995099 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995099 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 787 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3263 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22743361 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22743361 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83609 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83609 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 42486230 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42486230 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42569839 # number of overall hits +system.cpu.dcache.overall_hits::total 42569839 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 36706 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 36706 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 40135 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 40135 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 143738 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 143738 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 183873 # number of overall misses +system.cpu.dcache.overall_misses::total 183873 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 577584000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 577584000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6405138000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6405138000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6982722000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6982722000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6982722000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6982722000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001611 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001611 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324339 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.324339 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003372 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003372 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004301 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004301 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15735.411104 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15735.411104 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59843.205770 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59843.205770 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48579.512725 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48579.512725 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37975.787636 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37975.787636 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 128175 # number of writebacks +system.cpu.dcache.writebacks::total 128175 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7598 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7598 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7598 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7598 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7598 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7598 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 495022500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 495022500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6298106000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6298106000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1201109000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1201109000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6793128500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6793128500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7994237500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7994237500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17006.407173 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17006.407173 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58843.205770 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58843.205770 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50344.077458 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50344.077458 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency +system.cpu.icache.tags.replacements 16890 # number of replacements +system.cpu.icache.tags.tagsinuse 1732.356634 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356634 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.845877 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.845877 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses +system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78126184 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78126184 # number of overall hits +system.cpu.icache.overall_hits::total 78126184 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses +system.cpu.icache.overall_misses::total 18908 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 426200500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 426200500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 426200500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 426200500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 426200500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 426200500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78145092 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78145092 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78145092 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78145092 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78145092 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78145092 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22540.749947 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22540.749947 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22540.749947 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22540.749947 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22540.749947 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22540.749947 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 16890 # number of writebacks +system.cpu.icache.writebacks::total 16890 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 407292500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 407292500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 407292500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 407292500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 407292500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 407292500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.749947 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.749947 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 95333 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30336.891531 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 114380 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 126455 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.904511 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605525 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1088.258663 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1490.027343 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.847125 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.033211 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.045472 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.925808 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1225 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 13921 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15196 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 624 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949768 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3017503 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3017503 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 128175 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 128175 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 15790 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4751 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4751 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15265 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 15265 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31415 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 31415 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 15265 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 36166 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 51431 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 15265 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 36166 # number of overall hits +system.cpu.l2cache.overall_hits::total 51431 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 102281 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102281 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3643 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3643 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21551 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 21551 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3643 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 123832 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 127475 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3643 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 123832 # number of overall misses +system.cpu.l2cache.overall_misses::total 127475 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6087670500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6087670500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 217265500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 217265500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1284434000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1284434000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 217265500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7372104500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7589370000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 217265500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7372104500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7589370000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 128175 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 128175 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 15790 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 15790 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 18908 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 18908 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 52966 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 52966 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 159998 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 178906 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955611 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955611 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.192670 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.192670 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.406884 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.406884 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192670 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.773960 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.712525 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192670 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.773960 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.712525 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59519.074901 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59519.074901 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59639.171013 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59639.171013 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59599.740151 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59599.740151 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59639.171013 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59533.113412 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59536.144342 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59639.171013 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59533.113412 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59536.144342 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 86150 # number of writebacks +system.cpu.l2cache.writebacks::total 86150 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 104 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 104 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102281 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3643 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3643 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21551 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21551 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3643 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123832 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 127475 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3643 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123832 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 127475 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5064860500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5064860500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 180835500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 180835500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1068924000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1068924000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180835500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6133784500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6314620000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180835500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6133784500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6314620000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955611 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955611 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.192670 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.406884 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.406884 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773960 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.712525 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773960 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.712525 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49519.074901 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49519.074901 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49639.171013 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49639.171013 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49599.740151 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49599.740151 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3119 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3089 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 214325 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 36910 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54706 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 475898 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 530604 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2291072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18443072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 20734144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 95333 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 274239 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.025051 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.156979 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 267399 97.51% 97.51% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 6810 2.48% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 274239 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 320914000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadResp 25194 # Transaction distribution +system.membus.trans_dist::WritebackDirty 86150 # Transaction distribution +system.membus.trans_dist::CleanEvict 6168 # Transaction distribution +system.membus.trans_dist::ReadExReq 102281 # Transaction distribution +system.membus.trans_dist::ReadExResp 102281 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 25194 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 347268 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 347268 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13672000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13672000 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 219817 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 219817 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 219817 # Request fanout histogram +system.membus.reqLayer0.occupancy 568080092 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 637375000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index e69de29bb..75464de1f 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -0,0 +1,124 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.068149 # Number of seconds simulated +sim_ticks 68148677000 # Number of ticks simulated +final_tick 68148677000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1339454 # Simulator instruction rate (inst/s) +host_op_rate 1356797 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 679186650 # Simulator tick rate (ticks/s) +host_mem_usage 246572 # Number of bytes of host memory used +host_seconds 100.34 # Real time elapsed on the host +sim_insts 134398959 # Number of instructions simulated +sim_ops 136139187 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 538214320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 147559360 # Number of bytes read from this memory +system.physmem.bytes_read::total 685773680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 538214320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 538214320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 89882950 # Number of bytes written to this memory +system.physmem.bytes_written::total 89882950 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 134553580 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 37231300 # Number of read requests responded to by this memory +system.physmem.num_reads::total 171784880 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 20864304 # Number of write requests responded to by this memory +system.physmem.num_writes::total 20864304 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 15916 # Number of other requests responded to by this memory +system.physmem.num_other::total 15916 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7897648842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2165256414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10062905256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7897648842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7897648842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1318924357 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1318924357 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7897648842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3484180771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11381829614 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.numCycles 136297355 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 134398959 # Number of instructions committed +system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses +system.cpu.num_func_calls 1709332 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls +system.cpu.num_int_insts 115187757 # number of integer instructions +system.cpu.num_fp_insts 2326976 # number of float instructions +system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read +system.cpu.num_int_register_writes 113147731 # number of times the integer registers were written +system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written +system.cpu.num_mem_refs 58160261 # number of memory refs +system.cpu.num_load_insts 37275864 # Number of load instructions +system.cpu.num_store_insts 20884397 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 136297354.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 12719094 # Number of branches fetched +system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction +system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction +system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction +system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 136293808 # Class of executed instruction +system.membus.trans_dist::ReadReq 171784880 # Transaction distribution +system.membus.trans_dist::ReadResp 171784880 # Transaction distribution +system.membus.trans_dist::WriteReq 20864304 # Transaction distribution +system.membus.trans_dist::WriteResp 20864304 # Transaction distribution +system.membus.trans_dist::SwapReq 15916 # Transaction distribution +system.membus.trans_dist::SwapResp 15916 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 385330200 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 775783958 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 192665100 # Request fanout histogram +system.membus.snoop_fanout::mean 0.698381 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.458961 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 58111520 30.16% 30.16% # Request fanout histogram +system.membus.snoop_fanout::1 134553580 69.84% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 192665100 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index e69de29bb..18f2ca2b3 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -0,0 +1,535 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.203116 # Number of seconds simulated +sim_ticks 203115946500 # Number of ticks simulated +final_tick 203115946500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 790551 # Simulator instruction rate (inst/s) +host_op_rate 800787 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1194752753 # Simulator tick rate (ticks/s) +host_mem_usage 255284 # Number of bytes of host memory used +host_seconds 170.01 # Real time elapsed on the host +sim_insts 134398959 # Number of instructions simulated +sim_ops 136139187 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 525056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7828352 # Number of bytes read from this memory +system.physmem.bytes_read::total 8353408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 525056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 525056 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5457280 # Number of bytes written to this memory +system.physmem.bytes_written::total 5457280 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8204 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 122318 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130522 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 85270 # Number of write requests responded to by this memory +system.physmem.num_writes::total 85270 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2585006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38541297 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 41126303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2585006 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2585006 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 26867807 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26867807 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 26867807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2585006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 38541297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 67994110 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.numCycles 406231893 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 134398959 # Number of instructions committed +system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses +system.cpu.num_func_calls 1709332 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls +system.cpu.num_int_insts 115187757 # number of integer instructions +system.cpu.num_fp_insts 2326976 # number of float instructions +system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read +system.cpu.num_int_register_writes 113147730 # number of times the integer registers were written +system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written +system.cpu.num_mem_refs 58160261 # number of memory refs +system.cpu.num_load_insts 37275864 # Number of load instructions +system.cpu.num_store_insts 20884397 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 406231892.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 12719094 # Number of branches fetched +system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction +system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction +system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction +system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction +system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 136293808 # Class of executed instruction +system.cpu.dcache.tags.replacements 146583 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.268923 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 150679 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 384.664359 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 822359500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.268923 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997868 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997868 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3586 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 57944940 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 57944940 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 57944940 # number of overall hits +system.cpu.dcache.overall_hits::total 57944940 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 45500 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 45500 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 150664 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 150664 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 150664 # number of overall misses +system.cpu.dcache.overall_misses::total 150664 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1623315500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1623315500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6329554000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6329554000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 441000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 441000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7952869500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7952869500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7952869500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7952869500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35677.263736 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35677.263736 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60187.459587 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60187.459587 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 29400 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 29400 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52785.466336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52785.466336 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 123865 # number of writebacks +system.cpu.dcache.writebacks::total 123865 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45500 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 45500 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 150664 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 150664 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 150664 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 150664 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1577815500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1577815500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6224390000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6224390000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 426000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 426000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7802205500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7802205500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7802205500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7802205500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34677.263736 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34677.263736 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.459587 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.459587 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28400 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28400 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency +system.cpu.icache.tags.replacements 184976 # number of replacements +system.cpu.icache.tags.tagsinuse 2004.181265 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 718.445531 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 144582800500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 2004.181265 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.978604 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.978604 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 269294186 # Number of tag accesses +system.cpu.icache.tags.data_accesses 269294186 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 134366557 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 134366557 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 134366557 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 134366557 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 134366557 # number of overall hits +system.cpu.icache.overall_hits::total 134366557 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses +system.cpu.icache.overall_misses::total 187024 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2835239000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2835239000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2835239000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2835239000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2835239000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2835239000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 134553581 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 134553581 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 134553581 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 134553581 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 134553581 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 134553581 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15159.760245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15159.760245 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15159.760245 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15159.760245 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15159.760245 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15159.760245 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 184976 # number of writebacks +system.cpu.icache.writebacks::total 184976 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2648215000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2648215000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2648215000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2648215000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2648215000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2648215000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14159.760245 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14159.760245 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 99022 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30843.699683 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 433832 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 130065 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.335501 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 26289.169168 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3249.863620 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1304.666895 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.802282 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.099178 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.039815 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.941275 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31043 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 566 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11257 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18470 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 557 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.947357 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 5588812 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 5588812 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 123865 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 123865 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 184923 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 184923 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 3915 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3915 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 178820 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 178820 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 24446 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 24446 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 178820 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 28361 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 207181 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 178820 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 28361 # number of overall hits +system.cpu.l2cache.overall_hits::total 207181 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 101264 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 101264 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8204 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 8204 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21054 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 21054 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 8204 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 122318 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 130522 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 8204 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 122318 # number of overall misses +system.cpu.l2cache.overall_misses::total 130522 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6025890000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6025890000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 488461500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 488461500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1252834000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1252834000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 488461500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7278724000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7767185500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 488461500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7278724000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7767185500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 123865 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 123865 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 184923 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 184923 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187024 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 187024 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 45500 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 45500 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 150679 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 337703 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 150679 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 337703 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962778 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.962778 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043866 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043866 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.462725 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.462725 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043866 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.811779 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.386499 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043866 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.811779 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.386499 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59506.734871 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59506.734871 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59539.431984 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59539.431984 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.747126 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.747126 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59508.630729 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59508.630729 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 85270 # number of writebacks +system.cpu.l2cache.writebacks::total 85270 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101264 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101264 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8204 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8204 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21054 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21054 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8204 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 122318 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 130522 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8204 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 122318 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 130522 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5013250000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5013250000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 406421500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 406421500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1042294000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1042294000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 406421500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6055544000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6461965500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 406421500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6055544000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6461965500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962778 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962778 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043866 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.462725 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.462725 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811779 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.386499 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811779 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.386499 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49506.734871 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49506.734871 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49539.431984 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49539.431984 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.747126 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.747126 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3547 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 36470 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447941 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1006965 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 41378816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 99022 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 436725 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008273 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.090579 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 433112 99.17% 99.17% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3613 0.83% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 436725 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 643472000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.trans_dist::ReadResp 29258 # Transaction distribution +system.membus.trans_dist::WritebackDirty 85270 # Transaction distribution +system.membus.trans_dist::CleanEvict 10301 # Transaction distribution +system.membus.trans_dist::ReadExReq 101264 # Transaction distribution +system.membus.trans_dist::ReadExResp 101264 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 29258 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 356615 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 356615 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13810688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13810688 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 226093 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 226093 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 226093 # Request fanout histogram +system.membus.reqLayer0.occupancy 568574500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 652610000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index e69de29bb..185d54bdc 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -0,0 +1,152 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.045952 # Number of seconds simulated +sim_ticks 45951567500 # Number of ticks simulated +final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1593313 # Simulator instruction rate (inst/s) +host_op_rate 1593310 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 796655733 # Simulator tick rate (ticks/s) +host_mem_usage 242160 # Number of bytes of host memory used +host_seconds 57.68 # Real time elapsed on the host +sim_insts 91903056 # Number of instructions simulated +sim_ops 91903056 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 108337521 # Number of bytes read from this memory +system.physmem.bytes_read::total 475949877 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 367612356 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 367612356 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 30920974 # Number of bytes written to this memory +system.physmem.bytes_written::total 30920974 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 91903089 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 19996198 # Number of read requests responded to by this memory +system.physmem.num_reads::total 111899287 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 6501103 # Number of write requests responded to by this memory +system.physmem.num_writes::total 6501103 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999995996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2357645819 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10357641815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999995996 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999995996 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 672903574 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 672903574 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 19996198 # DTB read hits +system.cpu.dtb.read_misses 10 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 19996208 # DTB read accesses +system.cpu.dtb.write_hits 6501103 # DTB write hits +system.cpu.dtb.write_misses 23 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 6501126 # DTB write accesses +system.cpu.dtb.data_hits 26497301 # DTB hits +system.cpu.dtb.data_misses 33 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 26497334 # DTB accesses +system.cpu.itb.fetch_hits 91903089 # ITB hits +system.cpu.itb.fetch_misses 47 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 91903136 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.numCycles 91903136 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 91903056 # Number of instructions committed +system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses +system.cpu.num_func_calls 2059216 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls +system.cpu.num_int_insts 79581109 # number of integer instructions +system.cpu.num_fp_insts 6862064 # number of float instructions +system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read +system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read +system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written +system.cpu.num_mem_refs 26497334 # number of memory refs +system.cpu.num_load_insts 19996208 # Number of load instructions +system.cpu.num_store_insts 6501126 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 91903136 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 10240685 # Number of branches fetched +system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction +system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction +system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction +system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction +system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction +system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction +system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction +system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 91903089 # Class of executed instruction +system.membus.trans_dist::ReadReq 111899287 # Transaction distribution +system.membus.trans_dist::ReadResp 111899287 # Transaction distribution +system.membus.trans_dist::WriteReq 6501103 # Transaction distribution +system.membus.trans_dist::WriteResp 6501103 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 183806178 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 52994602 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 236800780 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 367612356 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 139258495 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 506870851 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 118400390 # Request fanout histogram +system.membus.snoop_fanout::mean 0.776206 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.416786 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 26497301 22.38% 22.38% # Request fanout histogram +system.membus.snoop_fanout::1 91903089 77.62% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 118400390 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index e69de29bb..356207999 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -0,0 +1,534 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.118763 # Number of seconds simulated +sim_ticks 118762761500 # Number of ticks simulated +final_tick 118762761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 940295 # Simulator instruction rate (inst/s) +host_op_rate 940295 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1215106876 # Simulator tick rate (ticks/s) +host_mem_usage 251128 # Number of bytes of host memory used +host_seconds 97.74 # Real time elapsed on the host +sim_insts 91903056 # Number of instructions simulated +sim_ops 91903056 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory +system.physmem.bytes_read::total 304960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 167744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 167744 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1412429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1155379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2567808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1412429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1412429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1412429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1155379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2567808 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 19996198 # DTB read hits +system.cpu.dtb.read_misses 10 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 19996208 # DTB read accesses +system.cpu.dtb.write_hits 6501103 # DTB write hits +system.cpu.dtb.write_misses 23 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 6501126 # DTB write accesses +system.cpu.dtb.data_hits 26497301 # DTB hits +system.cpu.dtb.data_misses 33 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 26497334 # DTB accesses +system.cpu.itb.fetch_hits 91903090 # ITB hits +system.cpu.itb.fetch_misses 47 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 91903137 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.numCycles 237525523 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 91903056 # Number of instructions committed +system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses +system.cpu.num_func_calls 2059216 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls +system.cpu.num_int_insts 79581109 # number of integer instructions +system.cpu.num_fp_insts 6862064 # number of float instructions +system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read +system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read +system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written +system.cpu.num_mem_refs 26497334 # number of memory refs +system.cpu.num_load_insts 19996208 # Number of load instructions +system.cpu.num_store_insts 6501126 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 237525523 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 10240685 # Number of branches fetched +system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction +system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction +system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction +system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction +system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction +system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction +system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction +system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 91903089 # Class of executed instruction +system.cpu.dcache.tags.replacements 157 # number of replacements +system.cpu.dcache.tags.tagsinuse 1441.946319 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.946319 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352038 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352038 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 491 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits +system.cpu.dcache.overall_hits::total 26495078 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses +system.cpu.dcache.overall_misses::total 2223 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26856500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26856500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 107103000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 107103000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 133959500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 133959500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 133959500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 133959500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56540 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56540 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61271.739130 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61271.739130 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60260.683761 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60260.683761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60260.683761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60260.683761 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26381500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26381500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 105355000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 105355000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 131736500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 131736500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 131736500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 131736500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55540 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55540 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60271.739130 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60271.739130 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency +system.cpu.icache.tags.replacements 6681 # number of replacements +system.cpu.icache.tags.tagsinuse 1417.953327 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1417.953327 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.692360 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.692360 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 585 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 953 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 183814690 # Number of tag accesses +system.cpu.icache.tags.data_accesses 183814690 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 91894580 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 91894580 # number of overall hits +system.cpu.icache.overall_hits::total 91894580 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8510 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8510 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8510 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses +system.cpu.icache.overall_misses::total 8510 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 239145000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 239145000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 239145000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 239145000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 239145000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 239145000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 91903090 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 91903090 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 91903090 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28101.645123 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28101.645123 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28101.645123 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28101.645123 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28101.645123 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28101.645123 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 6681 # number of writebacks +system.cpu.icache.writebacks::total 6681 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 8510 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 8510 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 230635000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 230635000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 230635000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 230635000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 230635000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 230635000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27101.645123 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27101.645123 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2073.923151 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 12687 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.080733 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 17.795341 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1704.894227 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 351.233582 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052029 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.010719 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.063291 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3109 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 703 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2096 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.094879 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 145425 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 145425 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 6681 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 6681 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5889 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 5889 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 53 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 53 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5889 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 5968 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5889 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits +system.cpu.l2cache.overall_hits::total 5968 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2621 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2621 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 422 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 422 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2621 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 4765 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses +system.cpu.l2cache.overall_misses::total 4765 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 102460000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 102460000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155964000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 155964000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 25110500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 25110500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 155964000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 127570500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 283534500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 155964000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 127570500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 283534500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 6681 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 6681 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8510 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 8510 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 475 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 475 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 8510 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 10733 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 8510 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 10733 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.307991 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.307991 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.888421 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.888421 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.307991 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.443958 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.580720 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.580720 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59505.532240 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59505.532240 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59503.554502 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59503.554502 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59505.532240 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.166045 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59503.567681 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59505.532240 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.166045 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59503.567681 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2621 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2621 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 422 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 422 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2621 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4765 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 85240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 85240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129754000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129754000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 20890500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 20890500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129754000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 106130500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 235884500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129754000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 106130500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 235884500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.307991 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.888421 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.580720 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.580720 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49505.532240 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49505.532240 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49503.554502 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49503.554502 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49505.532240 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.166045 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.567681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49505.532240 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.166045 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.567681 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 17571 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 6838 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6681 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 8510 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 475 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23701 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4603 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 28304 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 972224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1121344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10733 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10733 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 10733 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15573500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadResp 3043 # Transaction distribution +system.membus.trans_dist::ReadExReq 1722 # Transaction distribution +system.membus.trans_dist::ReadExResp 1722 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3043 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 4765 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 4765 # Request fanout histogram +system.membus.reqLayer0.occupancy 4782000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 23825000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index e69de29bb..99598cd5b 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,243 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.099596 # Number of seconds simulated +sim_ticks 99596491500 # Number of ticks simulated +final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1040518 # Simulator instruction rate (inst/s) +host_op_rate 1096874 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 601401466 # Simulator tick rate (ticks/s) +host_mem_usage 259948 # Number of bytes of host memory used +host_seconds 165.61 # Real time elapsed on the host +sim_insts 172317410 # Number of instructions simulated +sim_ops 181650342 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 759440208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory +system.physmem.bytes_read::total 869973869 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 759440208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 759440208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory +system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 189860052 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 27777721 # Number of read requests responded to by this memory +system.physmem.num_reads::total 217637773 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory +system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7625170290 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1109814807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8734985097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7625170290 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7625170290 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 454362792 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 454362792 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7625170290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1564177600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9189347890 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.numCycles 199192984 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 172317410 # Number of instructions committed +system.cpu.committedOps 181650342 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses +system.cpu.num_func_calls 3545028 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls +system.cpu.num_int_insts 143085668 # number of integer instructions +system.cpu.num_fp_insts 1752310 # number of float instructions +system.cpu.num_int_register_reads 241970171 # number of times the integer registers were read +system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written +system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written +system.cpu.num_cc_register_reads 543309970 # number of times the CC registers were read +system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written +system.cpu.num_mem_refs 40540779 # number of memory refs +system.cpu.num_load_insts 27896144 # Number of load instructions +system.cpu.num_store_insts 12644635 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 199192983.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 40300312 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 138988213 76.51% 76.51% # Class of executed instruction +system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction +system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction +system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 181650743 # Class of executed instruction +system.membus.trans_dist::ReadReq 217614903 # Transaction distribution +system.membus.trans_dist::ReadResp 217637310 # Transaction distribution +system.membus.trans_dist::WriteReq 12364287 # Transaction distribution +system.membus.trans_dist::WriteResp 12364287 # Transaction distribution +system.membus.trans_dist::SoftPFReq 463 # Transaction distribution +system.membus.trans_dist::SoftPFResp 463 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution +system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution +system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 460048934 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 915226809 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 230024467 # Request fanout histogram +system.membus.snoop_fanout::mean 0.825391 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 40164415 17.46% 17.46% # Request fanout histogram +system.membus.snoop_fanout::1 189860052 82.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 230024467 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index e69de29bb..da877a9a0 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,644 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.230198 # Number of seconds simulated +sim_ticks 230197694500 # Number of ticks simulated +final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 718293 # Simulator instruction rate (inst/s) +host_op_rate 757262 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 962214385 # Simulator tick rate (ticks/s) +host_mem_usage 268920 # Number of bytes of host memory used +host_seconds 239.24 # Real time elapsed on the host +sim_insts 171842484 # Number of instructions simulated +sim_ops 181165371 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory +system.physmem.bytes_read::total 220992 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 480700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 479310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 960010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 480700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 480700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 480700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 479310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 960010 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.numCycles 460395389 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 171842484 # Number of instructions committed +system.cpu.committedOps 181165371 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses +system.cpu.num_func_calls 3545028 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls +system.cpu.num_int_insts 143085668 # number of integer instructions +system.cpu.num_fp_insts 1752310 # number of float instructions +system.cpu.num_int_register_reads 242291225 # number of times the integer registers were read +system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written +system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written +system.cpu.num_cc_register_reads 626384530 # number of times the CC registers were read +system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written +system.cpu.num_mem_refs 40540779 # number of memory refs +system.cpu.num_load_insts 27896144 # Number of load instructions +system.cpu.num_store_insts 12644635 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 460395388.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 40300312 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 138988213 76.51% 76.51% # Class of executed instruction +system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction +system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction +system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 181650743 # Class of executed instruction +system.cpu.dcache.tags.replacements 40 # number of replacements +system.cpu.dcache.tags.tagsinuse 1363.571253 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.571253 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332903 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332903 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits +system.cpu.dcache.overall_hits::total 40117812 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses +system.cpu.dcache.overall_misses::total 1789 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 39940000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39940000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 67838500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 67838500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 107778500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 107778500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 107778500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 107778500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 40119138 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40119138 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40119601 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40119601 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58052.325581 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58052.325581 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61671.363636 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61671.363636 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60278.803132 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60278.803132 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60245.108999 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60245.108999 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1788 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39252000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 39252000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 66738500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 66738500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 105990500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 105990500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 106051500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 106051500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57052.325581 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57052.325581 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60671.363636 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60671.363636 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232 # average overall mshr miss latency +system.cpu.icache.tags.replacements 1506 # number of replacements +system.cpu.icache.tags.tagsinuse 1147.958164 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 62227.794821 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1147.958164 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.560526 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.560526 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 270 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 942 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 379723157 # Number of tag accesses +system.cpu.icache.tags.data_accesses 379723157 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 189857002 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 189857002 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 189857002 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 189857002 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 189857002 # number of overall hits +system.cpu.icache.overall_hits::total 189857002 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses +system.cpu.icache.overall_misses::total 3051 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 124592000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 124592000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 124592000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 124592000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 124592000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 124592000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 189860053 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 189860053 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 189860053 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 189860053 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 189860053 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 189860053 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40836.447067 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 40836.447067 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 40836.447067 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 40836.447067 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 1506 # number of writebacks +system.cpu.icache.writebacks::total 1506 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 121541000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 121541000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 121541000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 121541000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 121541000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 121541000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39836.447067 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39836.447067 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 1675.610098 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.201351 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 3.037805 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.001518 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 503.570775 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035675 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.051136 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2369 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 54045 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 54045 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1448 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1448 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1322 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1322 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 57 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 57 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1322 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 65 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1387 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1322 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 65 # number of overall hits +system.cpu.l2cache.overall_hits::total 1387 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 1092 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1092 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1729 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1729 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 632 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 632 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1729 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1724 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3453 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses +system.cpu.l2cache.overall_misses::total 3453 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65004500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 65004500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 102968000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 102968000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37629500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 37629500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 102968000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 102634000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 205602000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 102968000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 102634000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 205602000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1448 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1448 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1100 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3051 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 3051 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 689 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 689 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 3051 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1789 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 4840 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 3051 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1789 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 4840 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992727 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.992727 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.566699 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.566699 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.917271 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.917271 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.713430 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59527.930403 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59527.930403 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59553.499132 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59553.499132 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59540.348101 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59540.348101 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59553.499132 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59543.006082 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59553.499132 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59543.006082 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1729 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1729 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 632 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 632 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54084500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54084500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85678000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85678000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31309500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31309500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85678000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85394000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 171072000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85678000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85394000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 171072000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.566699 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.917271 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49527.930403 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49527.930403 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49553.499132 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49553.499132 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49540.348101 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49540.348101 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7608 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3618 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11226 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 291648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 407168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4840 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.033471 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.179882 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4678 96.65% 96.65% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 162 3.35% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4840 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4715000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadResp 2361 # Transaction distribution +system.membus.trans_dist::ReadExReq 1092 # Transaction distribution +system.membus.trans_dist::ReadExResp 1092 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2361 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3453 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3453 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3453 # Request fanout histogram +system.membus.reqLayer0.occupancy 3601500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 17265000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index e69de29bb..4c392ae66 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -0,0 +1,124 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.096723 # Number of seconds simulated +sim_ticks 96722945000 # Number of ticks simulated +final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1393535 # Simulator instruction rate (inst/s) +host_op_rate 1393537 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 696772335 # Simulator tick rate (ticks/s) +host_mem_usage 242012 # Number of bytes of host memory used +host_seconds 138.82 # Real time elapsed on the host +sim_insts 193444518 # Number of instructions simulated +sim_ops 193444756 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 223463413 # Number of bytes read from this memory +system.physmem.bytes_read::total 997245553 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 773782140 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 773782140 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 72065412 # Number of bytes written to this memory +system.physmem.bytes_written::total 72065412 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 193445535 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 57735068 # Number of read requests responded to by this memory +system.physmem.num_reads::total 251180603 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 18976439 # Number of write requests responded to by this memory +system.physmem.num_writes::total 18976439 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 22406 # Number of other requests responded to by this memory +system.physmem.num_other::total 22406 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999985319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2310345420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10310330739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999985319 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999985319 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 745070490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 745070490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.workload.num_syscalls 401 # Number of system calls +system.cpu.numCycles 193445891 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 193444518 # Number of instructions committed +system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses +system.cpu.num_func_calls 1957920 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls +system.cpu.num_int_insts 167974806 # number of integer instructions +system.cpu.num_fp_insts 1970372 # number of float instructions +system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read +system.cpu.num_int_register_writes 163060124 # number of times the integer registers were written +system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written +system.cpu.num_mem_refs 76733958 # number of memory refs +system.cpu.num_load_insts 57735091 # Number of load instructions +system.cpu.num_store_insts 18998867 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 193445890.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 15132745 # Number of branches fetched +system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction +system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction +system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction +system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 193445773 # Class of executed instruction +system.membus.trans_dist::ReadReq 251180603 # Transaction distribution +system.membus.trans_dist::ReadResp 251180603 # Transaction distribution +system.membus.trans_dist::WriteReq 18976439 # Transaction distribution +system.membus.trans_dist::WriteResp 18976439 # Transaction distribution +system.membus.trans_dist::SwapReq 22406 # Transaction distribution +system.membus.trans_dist::SwapResp 22406 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 386891070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 153467826 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 540358896 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 773782140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 295708073 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1069490213 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 270179448 # Request fanout histogram +system.membus.snoop_fanout::mean 0.715989 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.450942 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 76733913 28.40% 28.40% # Request fanout histogram +system.membus.snoop_fanout::1 193445535 71.60% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 270179448 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index e69de29bb..812685f18 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -0,0 +1,515 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.270600 # Number of seconds simulated +sim_ticks 270599529500 # Number of ticks simulated +final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 833752 # Simulator instruction rate (inst/s) +host_op_rate 833752 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1166291607 # Simulator tick rate (ticks/s) +host_mem_usage 251752 # Number of bytes of host memory used +host_seconds 232.02 # Real time elapsed on the host +sim_insts 193444518 # Number of instructions simulated +sim_ops 193444756 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory +system.physmem.bytes_read::total 331072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 850733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 372743 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1223476 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 850733 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 850733 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.workload.num_syscalls 401 # Number of system calls +system.cpu.numCycles 541199059 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 193444518 # Number of instructions committed +system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses +system.cpu.num_func_calls 1957920 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls +system.cpu.num_int_insts 167974806 # number of integer instructions +system.cpu.num_fp_insts 1970372 # number of float instructions +system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read +system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written +system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written +system.cpu.num_mem_refs 76733958 # number of memory refs +system.cpu.num_load_insts 57735091 # Number of load instructions +system.cpu.num_store_insts 18998867 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 541199058.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 15132745 # Number of branches fetched +system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction +system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction +system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction +system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 193445773 # Class of executed instruction +system.cpu.dcache.tags.replacements 2 # number of replacements +system.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1237.159344 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.302041 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.302041 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits +system.cpu.dcache.overall_hits::total 76709932 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses +system.cpu.dcache.overall_misses::total 1575 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 30877500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 30877500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 66775000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 66775000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 62000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 62000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 97652500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 97652500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 97652500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 97652500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62003.012048 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62003.012048 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000.928505 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62000.928505 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 62000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 62000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62001.587302 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62001.587302 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2 # number of writebacks +system.cpu.dcache.writebacks::total 2 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30379500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30379500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65698000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 65698000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 61000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 61000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 96077500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 96077500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 96077500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 96077500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61003.012048 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61003.012048 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000.928505 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000.928505 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 61000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 61000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency +system.cpu.icache.tags.replacements 10362 # number of replacements +system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1591.528232 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.777113 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.777113 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses +system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits +system.cpu.icache.overall_hits::total 193433248 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses +system.cpu.icache.overall_misses::total 12288 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 336231000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 336231000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 336231000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 336231000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 336231000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 336231000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27362.548828 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27362.548828 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27362.548828 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27362.548828 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 10362 # number of writebacks +system.cpu.icache.writebacks::total 10362 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323943000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 323943000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323943000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 323943000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323943000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 323943000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26362.548828 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26362.548828 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.203530 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 403.042121 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069434 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.081734 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 10362 # number of WritebackClean hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8691 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 8691 # number of ReadCleanReq hits +system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits +system.cpu.l2cache.overall_hits::total 8691 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 1078 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1078 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3597 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3597 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 498 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 498 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses +system.cpu.l2cache.overall_misses::total 5173 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64142000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 64142000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 214049500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 214049500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29632000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 29632000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 214049500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 93774000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 307823500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 214049500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 93774000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 307823500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 10362 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 10362 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12288 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 12288 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 498 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 498 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.292725 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.927644 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.927644 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59507.784265 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59507.784265 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59502.008032 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59502.008032 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59505.799343 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59505.799343 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3597 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3597 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 498 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 498 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53362000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53362000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 178079500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 178079500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24652000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24652000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178079500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78014000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 256093500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178079500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78014000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 256093500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.292725 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.927644 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.927644 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49507.784265 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49507.784265 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49502.008032 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49502.008032 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 38092 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1449600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1550592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 13864 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000072 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.008493 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 13863 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 13864 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 22478000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadResp 4095 # Transaction distribution +system.membus.trans_dist::ReadExReq 1078 # Transaction distribution +system.membus.trans_dist::ReadExResp 1078 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4095 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5173 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5173 # Request fanout histogram +system.membus.reqLayer0.occupancy 5203000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 25865000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index e69de29bb..a92d8585c 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -0,0 +1,127 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.131393 # Number of seconds simulated +sim_ticks 131393279000 # Number of ticks simulated +final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 719836 # Simulator instruction rate (inst/s) +host_op_rate 1206511 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 716141111 # Simulator tick rate (ticks/s) +host_mem_usage 284280 # Number of bytes of host memory used +host_seconds 183.47 # Real time elapsed on the host +sim_insts 132071193 # Number of instructions simulated +sim_ops 221363385 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 310423752 # Number of bytes read from this memory +system.physmem.bytes_read::total 1698378688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1387954936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1387954936 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 99822191 # Number of bytes written to this memory +system.physmem.bytes_written::total 99822191 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 173494367 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 56682005 # Number of read requests responded to by this memory +system.physmem.num_reads::total 230176372 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 20515731 # Number of write requests responded to by this memory +system.physmem.num_writes::total 20515731 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 10563363260 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2362554267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12925917527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10563363260 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10563363260 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 759720678 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 759720678 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.numCycles 262786559 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 132071193 # Number of instructions committed +system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses +system.cpu.num_func_calls 1595632 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls +system.cpu.num_int_insts 219019986 # number of integer instructions +system.cpu.num_fp_insts 2162459 # number of float instructions +system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read +system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written +system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written +system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read +system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written +system.cpu.num_mem_refs 77165304 # number of memory refs +system.cpu.num_load_insts 56649587 # Number of load instructions +system.cpu.num_store_insts 20515717 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 262786558.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 12326938 # Number of branches fetched +system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction +system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction +system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction +system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction +system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction +system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 221363385 # Class of executed instruction +system.membus.trans_dist::ReadReq 230176372 # Transaction distribution +system.membus.trans_dist::ReadResp 230176372 # Transaction distribution +system.membus.trans_dist::WriteReq 20515731 # Transaction distribution +system.membus.trans_dist::WriteResp 20515731 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 250692103 # Request fanout histogram +system.membus.snoop_fanout::mean 0.692062 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.461641 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 77197736 30.79% 30.79% # Request fanout histogram +system.membus.snoop_fanout::1 173494367 69.21% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 250692103 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index e69de29bb..cbc3cc2d9 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -0,0 +1,507 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.250987 # Number of seconds simulated +sim_ticks 250987138500 # Number of ticks simulated +final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 489633 # Simulator instruction rate (inst/s) +host_op_rate 820669 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 930494730 # Simulator tick rate (ticks/s) +host_mem_usage 293244 # Number of bytes of host memory used +host_seconds 269.74 # Real time elapsed on the host +sim_insts 132071193 # Number of instructions simulated +sim_ops 221363385 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory +system.physmem.bytes_read::total 303040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 724181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 483212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1207393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 724181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 724181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 724181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 483212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1207393 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.numCycles 501974277 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 132071193 # Number of instructions committed +system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses +system.cpu.num_func_calls 1595632 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls +system.cpu.num_int_insts 219019986 # number of integer instructions +system.cpu.num_fp_insts 2162459 # number of float instructions +system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read +system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written +system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written +system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read +system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written +system.cpu.num_mem_refs 77165304 # number of memory refs +system.cpu.num_load_insts 56649587 # Number of load instructions +system.cpu.num_store_insts 20515717 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 501974276.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 12326938 # Number of branches fetched +system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction +system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction +system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction +system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction +system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction +system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction +system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 221363385 # Class of executed instruction +system.cpu.dcache.tags.replacements 41 # number of replacements +system.cpu.dcache.tags.tagsinuse 1363.414730 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.414730 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332865 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332865 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 472 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits +system.cpu.dcache.overall_hits::total 77195831 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses +system.cpu.dcache.overall_misses::total 1905 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 19933500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 19933500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 97691000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 97691000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 117624500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117624500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117624500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117624500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60958.715596 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60958.715596 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61908.111534 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61908.111534 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61745.144357 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61745.144357 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 7 # number of writebacks +system.cpu.dcache.writebacks::total 7 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19606500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 19606500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96113000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 96113000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115719500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 115719500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115719500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 115719500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59958.715596 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59958.715596 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60908.111534 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60908.111534 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency +system.cpu.icache.tags.replacements 2836 # number of replacements +system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1455.245085 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.710569 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.710569 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 415 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses +system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 173489673 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits +system.cpu.icache.overall_hits::total 173489673 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses +system.cpu.icache.overall_misses::total 4694 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 200232500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 200232500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 200232500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 200232500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 200232500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 200232500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 173494367 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 173494367 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 173494367 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42657.115467 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42657.115467 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42657.115467 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42657.115467 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 2836 # number of writebacks +system.cpu.icache.writebacks::total 2836 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195538500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 195538500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195538500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 195538500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195538500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 195538500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41657.115467 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41657.115467 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 0.021821 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.911143 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 228.172589 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055844 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.062808 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 532 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 80550 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 80550 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 2836 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1854 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 7 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits +system.cpu.l2cache.overall_hits::total 1864 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2840 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2840 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 320 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses +system.cpu.l2cache.overall_misses::total 4735 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 93713500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 93713500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 169013000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 169013000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19042000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 19042000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 169013000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112755500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 281768500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 169013000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112755500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 281768500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 7 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 7 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 2836 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 2836 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4694 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 4694 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 327 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 327 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.605028 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.978593 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.978593 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.634921 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.634921 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.619718 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.619718 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59506.250000 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59506.250000 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59507.602957 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59507.602957 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2840 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2840 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 320 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 320 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77963500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77963500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140613000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140613000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15842000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15842000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140613000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 93805500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 234418500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140613000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 93805500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 234418500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.605028 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.978593 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.634921 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.634921 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.619718 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.619718 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49506.250000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49506.250000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12224 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3851 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16075 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 604288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6599 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000152 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.012310 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6598 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6599 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7581000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadResp 3160 # Transaction distribution +system.membus.trans_dist::ReadExReq 1575 # Transaction distribution +system.membus.trans_dist::ReadExResp 1575 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3160 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 4735 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 4735 # Request fanout histogram +system.membus.reqLayer0.occupancy 4771000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 23675000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- |