diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-01-10 18:06:43 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-01-10 18:06:43 -0600 |
| commit | e76442e203bd4ce18e897658a17756a3d00bdeb8 (patch) | |
| tree | 93af3959085146bd965f4f7e8ad8e1dad142ce3d /tests/quick | |
| parent | 7bb65dd4345401f40eccb5c23b563558dfd9e854 (diff) | |
| download | gem5-e76442e203bd4ce18e897658a17756a3d00bdeb8.tar.xz | |
stats: changes due to recent changesets.
Diffstat (limited to 'tests/quick')
5 files changed, 1187 insertions, 1181 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 34b146a05..e85225b4f 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 5.112152 # Number of seconds simulated -sim_ticks 5112152263500 # Number of ticks simulated -final_tick 5112152263500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 5112152301500 # Number of ticks simulated +final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1496341 # Simulator instruction rate (inst/s) -host_op_rate 3063337 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38234881791 # Simulator tick rate (ticks/s) -host_mem_usage 596704 # Number of bytes of host memory used -host_seconds 133.70 # Real time elapsed on the host -sim_insts 200066624 # Number of instructions simulated -sim_ops 409580050 # Number of ops (including micro ops) simulated +host_inst_rate 1049184 # Simulator instruction rate (inst/s) +host_op_rate 2147909 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26808985343 # Simulator tick rate (ticks/s) +host_mem_usage 640900 # Number of bytes of host memory used +host_seconds 190.69 # Real time elapsed on the host +sim_insts 200066731 # Number of instructions simulated +sim_ops 409580371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory @@ -50,38 +50,38 @@ system.physmem.bw_total::pc.south_bridge.ide 5546 system.physmem.bw_total::total 4061951 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10224308491 # number of cpu cycles simulated +system.cpu.numCycles 10224308568 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 200066624 # Number of instructions committed -system.cpu.committedOps 409580050 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374583182 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2308871 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 40001057 # number of instructions that are conditional controls -system.cpu.num_int_insts 374583182 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 682688853 # number of times the integer registers were read -system.cpu.num_int_register_writes 323557399 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.committedInsts 200066731 # Number of instructions committed +system.cpu.committedOps 409580371 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374583495 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses +system.cpu.num_func_calls 2308877 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 40001070 # number of instructions that are conditional controls +system.cpu.num_int_insts 374583495 # number of integer instructions +system.cpu.num_fp_insts 48 # number of float instructions +system.cpu.num_int_register_reads 682689563 # number of times the integer registers were read +system.cpu.num_int_register_writes 323557658 # number of times the integer registers were written +system.cpu.num_fp_register_reads 48 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 233837170 # number of times the CC registers were read -system.cpu.num_cc_register_writes 157316360 # number of times the CC registers were written -system.cpu.num_mem_refs 35666925 # number of memory refs -system.cpu.num_load_insts 27243229 # Number of load instructions -system.cpu.num_store_insts 8423696 # Number of store instructions -system.cpu.num_idle_cycles 9770324986.701103 # Number of idle cycles -system.cpu.num_busy_cycles 453983504.298896 # Number of busy cycles +system.cpu.num_cc_register_reads 233837318 # number of times the CC registers were read +system.cpu.num_cc_register_writes 157316420 # number of times the CC registers were written +system.cpu.num_mem_refs 35667022 # number of memory refs +system.cpu.num_load_insts 27243255 # Number of load instructions +system.cpu.num_store_insts 8423767 # Number of store instructions +system.cpu.num_idle_cycles 9770324721.656570 # Number of idle cycles +system.cpu.num_busy_cycles 453983846.343430 # Number of busy cycles system.cpu.not_idle_fraction 0.044402 # Percentage of non-idle cycles system.cpu.idle_fraction 0.955598 # Percentage of idle cycles -system.cpu.Branches 43152131 # Number of branches fetched -system.cpu.op_class::No_OpClass 172748 0.04% 0.04% # Class of executed instruction -system.cpu.op_class::IntAlu 373476362 91.18% 91.23% # Class of executed instruction +system.cpu.Branches 43152159 # Number of branches fetched +system.cpu.op_class::No_OpClass 172754 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 373476545 91.18% 91.23% # Class of executed instruction system.cpu.op_class::IntMult 144577 0.04% 91.26% # Class of executed instruction -system.cpu.op_class::IntDiv 123058 0.03% 91.29% # Class of executed instruction +system.cpu.op_class::IntDiv 123078 0.03% 91.29% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::FloatCvt 16 0.00% 91.29% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 91.29% # Class of executed instruction @@ -105,18 +105,18 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction -system.cpu.op_class::MemRead 27240640 6.65% 97.94% # Class of executed instruction -system.cpu.op_class::MemWrite 8423696 2.06% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 27240665 6.65% 97.94% # Class of executed instruction +system.cpu.op_class::MemWrite 8423767 2.06% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 409581081 # Class of executed instruction +system.cpu.op_class::total 409581402 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 1621913 # number of replacements +system.cpu.dcache.tags.replacements 1621902 # number of replacements system.cpu.dcache.tags.tagsinuse 511.999425 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20181070 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1622425 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.438831 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 20181182 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1622414 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.438984 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy @@ -126,48 +126,48 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 282 system.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88836495 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88836495 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12023306 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12023306 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8096585 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8096585 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 58898 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 58898 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20119891 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20119891 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20178789 # number of overall hits -system.cpu.dcache.overall_hits::total 20178789 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 905254 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 905254 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316711 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316711 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 402759 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 402759 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1221965 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1221965 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1624724 # number of overall misses -system.cpu.dcache.overall_misses::total 1624724 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 12928560 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12928560 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8413296 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8413296 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 88836888 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88836888 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12023339 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12023339 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8096662 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8096662 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 58900 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 58900 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20120001 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20120001 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20178901 # number of overall hits +system.cpu.dcache.overall_hits::total 20178901 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 905249 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 905249 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316707 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316707 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 402757 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 402757 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1221956 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1221956 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1624713 # number of overall misses +system.cpu.dcache.overall_misses::total 1624713 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 12928588 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12928588 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8413369 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8413369 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 461657 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 461657 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21341856 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21341856 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21803513 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21803513 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037644 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037644 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872420 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.872420 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057257 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057257 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074517 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074517 # miss rate for overall accesses +system.cpu.dcache.demand_accesses::cpu.data 21341957 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21341957 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21803614 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21803614 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070019 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070019 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037643 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037643 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872416 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.872416 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057256 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057256 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074516 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074516 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -176,49 +176,49 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1535795 # number of writebacks -system.cpu.dcache.writebacks::total 1535795 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1535783 # number of writebacks +system.cpu.dcache.writebacks::total 1535783 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7755 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.014024 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 12942 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7769 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.665851 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5100454103000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014024 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313376 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313376 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 7749 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.013997 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12940 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7763 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.666881 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5100454141000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013997 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313375 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313375 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 52772 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 52772 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12943 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12943 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12943 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12943 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12943 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12943 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8962 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8962 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8962 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8962 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8962 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8962 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21905 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21905 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21905 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21905 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21905 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21905 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409130 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409130 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409130 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409130 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409130 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409130 # miss rate for overall accesses +system.cpu.dtb_walker_cache.tags.tag_accesses 52753 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 52753 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12941 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12941 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12941 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12941 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12941 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12941 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8957 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8957 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8957 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8957 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8957 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8957 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21898 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21898 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21898 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21898 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21898 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21898 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409033 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409033 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409033 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409033 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409033 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409033 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -227,16 +227,16 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2457 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2457 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::writebacks 2453 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2453 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 792213 # number of replacements -system.cpu.icache.tags.tagsinuse 510.662957 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 243675024 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 792725 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 307.389100 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 148913080500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.662957 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 792216 # number of replacements +system.cpu.icache.tags.tagsinuse 510.662956 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 243675150 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 792728 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 307.388095 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 148913118500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.662956 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997389 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -245,26 +245,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 130 system.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 245260488 # Number of tag accesses -system.cpu.icache.tags.data_accesses 245260488 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 243675024 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243675024 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243675024 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243675024 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243675024 # number of overall hits -system.cpu.icache.overall_hits::total 243675024 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 792732 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 792732 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 792732 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 792732 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 792732 # number of overall misses -system.cpu.icache.overall_misses::total 792732 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244467756 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244467756 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244467756 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244467756 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244467756 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244467756 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 245260620 # Number of tag accesses +system.cpu.icache.tags.data_accesses 245260620 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 243675150 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243675150 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243675150 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243675150 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243675150 # number of overall hits +system.cpu.icache.overall_hits::total 243675150 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 792735 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 792735 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 792735 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 792735 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 792735 # number of overall misses +system.cpu.icache.overall_misses::total 792735 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 244467885 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244467885 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244467885 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244467885 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244467885 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244467885 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003243 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003243 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003243 # miss rate for demand accesses @@ -285,7 +285,7 @@ system.cpu.itb_walker_cache.tags.tagsinuse 3.026546 # system.cpu.itb_walker_cache.tags.total_refs 7763 # Total number of references to valid blocks. system.cpu.itb_walker_cache.tags.sampled_refs 3597 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.tags.avg_refs 2.158187 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5102144858000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.warmup_cycle 5102144896000 # Cycle when the warmup percentage was hit. system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026546 # Average occupied blocks per requestor system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189159 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_percent::total 0.189159 # Average percentage of cache occupancy @@ -336,16 +336,16 @@ system.cpu.itb_walker_cache.writebacks::writebacks 545 system.cpu.itb_walker_cache.writebacks::total 545 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 106219 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64823.931621 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3459892 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 64823.931305 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3459867 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 170177 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 20.331138 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 20.330991 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 51929.109660 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 51929.109466 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132289 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2455.813692 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10438.873502 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2455.813677 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10438.873394 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.792375 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy @@ -359,29 +359,29 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3349 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20908 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39411 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975922 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 32213022 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 32213022 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6661 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 32212786 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 32212786 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6656 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2896 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 779364 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1275206 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2064127 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1538797 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1538797 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 779367 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1275199 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2064118 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1538781 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1538781 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 22 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 22 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 179775 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 179775 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6661 # number of demand (read+write) hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 179771 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 179771 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6656 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 2896 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 779364 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1454981 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2243902 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6661 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 779367 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1454970 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2243889 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6656 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 2896 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 779364 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1454981 # number of overall hits -system.cpu.l2cache.overall_hits::total 2243902 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 779367 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1454970 # number of overall hits +system.cpu.l2cache.overall_hits::total 2243889 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 13355 # number of ReadReq misses @@ -401,27 +401,27 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker 5 system.cpu.l2cache.overall_misses::cpu.inst 13355 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 166813 # number of overall misses system.cpu.l2cache.overall_misses::total 180174 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6662 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6657 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2901 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 792719 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1307369 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2109651 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1538797 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1538797 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 792722 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1307362 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2109642 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1538781 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1538781 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1829 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1829 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 314425 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 314425 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6662 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 314421 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 314421 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6657 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 2901 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 792719 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1621794 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2424076 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6662 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 792722 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1621783 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2424063 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6657 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 2901 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 792719 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1621794 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2424076 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 792722 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1621783 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2424063 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000150 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001724 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016847 # miss rate for ReadReq accesses @@ -429,17 +429,17 @@ system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024601 system.cpu.l2cache.ReadReq_miss_rate::total 0.021579 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987972 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987972 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428242 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.428242 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428247 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.428247 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000150 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001724 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016847 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102857 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102858 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.074327 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000150 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001724 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016847 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102857 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102858 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.074327 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -452,39 +452,39 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 98110 # number of writebacks system.cpu.l2cache.writebacks::total 98110 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 15971499 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 15971499 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 15971490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 15971490 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13943 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13943 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1538797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1538781 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2281 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2281 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 314430 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 314430 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1585464 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32527803 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 314426 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 314426 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1585470 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32527769 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9455 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20381 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 34143103 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50734848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227551993 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20367 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 34143061 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50735040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227550521 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 279337657 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 279335801 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 48002 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4017293 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 4017264 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3.011855 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.108231 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3969670 98.81% 98.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3969641 98.81% 98.81% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 47623 1.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4017293 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4017264 # Request fanout histogram system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution system.iobus.trans_dist::WriteReq 57724 # Transaction distribution @@ -545,7 +545,7 @@ system.iocache.tags.tagsinuse 0.042441 # Cy system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47584 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4994875215009 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 4994875253009 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 852b32ebc..b290fab5a 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.188454 # Number of seconds simulated -sim_ticks 5188454477000 # Number of ticks simulated -final_tick 5188454477000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.188464 # Number of seconds simulated +sim_ticks 5188464227000 # Number of ticks simulated +final_tick 5188464227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1005236 # Simulator instruction rate (inst/s) -host_op_rate 1937641 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40503850527 # Simulator tick rate (ticks/s) -host_mem_usage 596712 # Number of bytes of host memory used -host_seconds 128.10 # Real time elapsed on the host -sim_insts 128768549 # Number of instructions simulated -sim_ops 248207575 # Number of ops (including micro ops) simulated +host_inst_rate 671592 # Simulator instruction rate (inst/s) +host_op_rate 1294539 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27056983658 # Simulator tick rate (ticks/s) +host_mem_usage 641928 # Number of bytes of host memory used +host_seconds 191.76 # Real time elapsed on the host +sim_insts 128784844 # Number of instructions simulated +sim_ops 248241672 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 828736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9035840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 828672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9042304 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 9893312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 828736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 828736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8124416 # Number of bytes written to this memory -system.physmem.bytes_written::total 8124416 # Number of bytes written to this memory +system.physmem.bytes_read::total 9899712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 828672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 828672 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8125568 # Number of bytes written to this memory +system.physmem.bytes_written::total 8125568 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12949 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141185 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12948 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141286 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 154583 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126944 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126944 # Number of write requests responded to by this memory +system.physmem.num_reads::total 154683 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126962 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126962 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159727 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1741528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 159714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1742771 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 5464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1906794 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159727 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159727 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1565864 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1565864 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1565864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 1908024 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 159714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 159714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1566083 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1566083 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1566083 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1741528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 159714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1742771 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 5464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3472658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 154583 # Number of read requests accepted -system.physmem.writeReqs 173664 # Number of write requests accepted -system.physmem.readBursts 154583 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 173664 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9885440 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7872 # Total number of bytes read from write queue -system.physmem.bytesWritten 10960768 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9893312 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11114496 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 123 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2370 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1582 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10392 # Per bank write bursts -system.physmem.perBankRdBursts::1 9723 # Per bank write bursts -system.physmem.perBankRdBursts::2 9455 # Per bank write bursts -system.physmem.perBankRdBursts::3 9480 # Per bank write bursts -system.physmem.perBankRdBursts::4 9901 # Per bank write bursts -system.physmem.perBankRdBursts::5 9535 # Per bank write bursts -system.physmem.perBankRdBursts::6 9436 # Per bank write bursts -system.physmem.perBankRdBursts::7 9264 # Per bank write bursts -system.physmem.perBankRdBursts::8 9069 # Per bank write bursts -system.physmem.perBankRdBursts::9 9032 # Per bank write bursts -system.physmem.perBankRdBursts::10 9333 # Per bank write bursts -system.physmem.perBankRdBursts::11 9426 # Per bank write bursts -system.physmem.perBankRdBursts::12 9943 # Per bank write bursts -system.physmem.perBankRdBursts::13 10317 # Per bank write bursts -system.physmem.perBankRdBursts::14 10185 # Per bank write bursts -system.physmem.perBankRdBursts::15 9969 # Per bank write bursts -system.physmem.perBankWrBursts::0 11290 # Per bank write bursts -system.physmem.perBankWrBursts::1 10662 # Per bank write bursts -system.physmem.perBankWrBursts::2 11268 # Per bank write bursts -system.physmem.perBankWrBursts::3 10649 # Per bank write bursts -system.physmem.perBankWrBursts::4 10537 # Per bank write bursts -system.physmem.perBankWrBursts::5 10374 # Per bank write bursts -system.physmem.perBankWrBursts::6 10316 # Per bank write bursts -system.physmem.perBankWrBursts::7 10238 # Per bank write bursts -system.physmem.perBankWrBursts::8 10391 # Per bank write bursts -system.physmem.perBankWrBursts::9 10158 # Per bank write bursts -system.physmem.perBankWrBursts::10 10967 # Per bank write bursts -system.physmem.perBankWrBursts::11 11299 # Per bank write bursts -system.physmem.perBankWrBursts::12 11272 # Per bank write bursts -system.physmem.perBankWrBursts::13 11296 # Per bank write bursts -system.physmem.perBankWrBursts::14 10371 # Per bank write bursts -system.physmem.perBankWrBursts::15 10174 # Per bank write bursts +system.physmem.bw_total::total 3474107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 154683 # Number of read requests accepted +system.physmem.writeReqs 173682 # Number of write requests accepted +system.physmem.readBursts 154683 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 173682 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9893504 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue +system.physmem.bytesWritten 10954816 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9899712 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11115648 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2485 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1609 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10173 # Per bank write bursts +system.physmem.perBankRdBursts::1 9740 # Per bank write bursts +system.physmem.perBankRdBursts::2 9593 # Per bank write bursts +system.physmem.perBankRdBursts::3 9430 # Per bank write bursts +system.physmem.perBankRdBursts::4 10001 # Per bank write bursts +system.physmem.perBankRdBursts::5 9691 # Per bank write bursts +system.physmem.perBankRdBursts::6 9399 # Per bank write bursts +system.physmem.perBankRdBursts::7 9276 # Per bank write bursts +system.physmem.perBankRdBursts::8 9154 # Per bank write bursts +system.physmem.perBankRdBursts::9 9223 # Per bank write bursts +system.physmem.perBankRdBursts::10 9471 # Per bank write bursts +system.physmem.perBankRdBursts::11 9338 # Per bank write bursts +system.physmem.perBankRdBursts::12 9899 # Per bank write bursts +system.physmem.perBankRdBursts::13 10266 # Per bank write bursts +system.physmem.perBankRdBursts::14 9992 # Per bank write bursts +system.physmem.perBankRdBursts::15 9940 # Per bank write bursts +system.physmem.perBankWrBursts::0 11451 # Per bank write bursts +system.physmem.perBankWrBursts::1 10885 # Per bank write bursts +system.physmem.perBankWrBursts::2 11361 # Per bank write bursts +system.physmem.perBankWrBursts::3 10717 # Per bank write bursts +system.physmem.perBankWrBursts::4 11001 # Per bank write bursts +system.physmem.perBankWrBursts::5 10578 # Per bank write bursts +system.physmem.perBankWrBursts::6 10603 # Per bank write bursts +system.physmem.perBankWrBursts::7 9872 # Per bank write bursts +system.physmem.perBankWrBursts::8 10400 # Per bank write bursts +system.physmem.perBankWrBursts::9 10659 # Per bank write bursts +system.physmem.perBankWrBursts::10 10851 # Per bank write bursts +system.physmem.perBankWrBursts::11 10912 # Per bank write bursts +system.physmem.perBankWrBursts::12 10837 # Per bank write bursts +system.physmem.perBankWrBursts::13 10879 # Per bank write bursts +system.physmem.perBankWrBursts::14 9964 # Per bank write bursts +system.physmem.perBankWrBursts::15 10199 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5188454413500 # Total gap between requests +system.physmem.totGap 5188464163500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154583 # Read request sizes (log2) +system.physmem.readPktSize::6 154683 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 173664 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 66 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 58 # What read queue length does an incoming req see +system.physmem.writePktSize::6 173682 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151354 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see @@ -156,137 +156,134 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 11221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 10213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 11279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 12272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58761 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 354.761560 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 206.245927 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 358.668619 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19719 33.56% 33.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 13641 23.21% 56.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5790 9.85% 66.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3461 5.89% 72.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2363 4.02% 76.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1647 2.80% 79.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1118 1.90% 81.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1023 1.74% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9999 17.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58761 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6350 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.321575 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 600.921026 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6349 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58562 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 356.003142 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 207.252442 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 358.966719 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19491 33.28% 33.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13719 23.43% 56.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5713 9.76% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3485 5.95% 72.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2346 4.01% 76.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1652 2.82% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1138 1.94% 81.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1007 1.72% 82.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10011 17.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58562 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6360 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.303774 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 600.449814 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6359 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6350 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6350 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 26.970394 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.564885 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 26.510023 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4926 77.57% 77.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 38 0.60% 78.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 20 0.31% 78.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 294 4.63% 83.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 158 2.49% 85.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 56 0.88% 86.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 42 0.66% 87.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 42 0.66% 87.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 172 2.71% 90.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 12 0.19% 90.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 18 0.28% 90.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 13 0.20% 91.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 29 0.46% 91.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 15 0.24% 91.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 10 0.16% 92.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 51 0.80% 92.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 104 1.64% 94.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 11 0.17% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 7 0.11% 94.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 15 0.24% 95.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 146 2.30% 97.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.08% 97.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 14 0.22% 97.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.05% 97.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 26 0.41% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 98.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 6 0.09% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 98.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 29 0.46% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 4 0.06% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 9 0.14% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 18 0.28% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 10 0.16% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 5 0.08% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 5 0.08% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.03% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.59% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6360 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6360 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 26.913365 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 21.548238 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 26.273775 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4929 77.50% 77.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 43 0.68% 78.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 22 0.35% 78.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 287 4.51% 83.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 171 2.69% 85.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 54 0.85% 86.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 36 0.57% 87.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 31 0.49% 87.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 174 2.74% 90.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 19 0.30% 90.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 20 0.31% 90.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 9 0.14% 91.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 42 0.66% 91.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 19 0.30% 92.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 8 0.13% 92.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 53 0.83% 93.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 89 1.40% 94.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 11 0.17% 94.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 4 0.06% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 14 0.22% 94.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 158 2.48% 97.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 97.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 9 0.14% 97.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 4 0.06% 97.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 23 0.36% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 5 0.08% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 8 0.13% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 4 0.06% 98.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 28 0.44% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 11 0.17% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 9 0.14% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 14 0.22% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 8 0.13% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 4 0.06% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 7 0.11% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.03% 99.59% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-179 6 0.09% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.05% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 7 0.11% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6350 # Writes before turning the bus around for reads -system.physmem.totQLat 1440123750 # Total ticks spent queuing -system.physmem.totMemAccLat 4336248750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 772300000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9323.60 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::180-183 3 0.05% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 4 0.06% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 3 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 2 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6360 # Writes before turning the bus around for reads +system.physmem.totQLat 1439298500 # Total ticks spent queuing +system.physmem.totMemAccLat 4337786000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 772930000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9310.67 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28073.60 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28060.67 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s @@ -297,240 +294,241 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 22.93 # Average write queue length when enqueuing -system.physmem.readRowHits 126965 # Number of row buffer hits during reads -system.physmem.writeRowHits 139995 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.20 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.73 # Row buffer hit rate for writes -system.physmem.avgGap 15806555.47 # Average gap between requests -system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 220290840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 120198375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 602050800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 552964320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 338884550160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 134005273470 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2995523664000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3469908991965 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.775183 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4983224613500 # Time in different power states -system.physmem_0.memoryStateTime::REF 173253860000 # Time in different power states +system.physmem.readRowHits 127137 # Number of row buffer hits during reads +system.physmem.writeRowHits 140055 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.24 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.81 # Row buffer hit rate for writes +system.physmem.avgGap 15800904.98 # Average gap between requests +system.physmem.pageHitRate 82.02 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 219436560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 119732250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 602963400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 560312640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 338885058720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 133861007610 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2995654884750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3469903395930 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.773100 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4983444491000 # Time in different power states +system.physmem_0.memoryStateTime::REF 173254120000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31975122750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31762771500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 223942320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122190750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 602729400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 556813440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 338884550160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 134550538605 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2995045361250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3469986125925 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.790049 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4982425910500 # Time in different power states -system.physmem_1.memoryStateTime::REF 173253860000 # Time in different power states +system.physmem_1.actEnergy 223292160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 121836000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 602799600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 548862480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 338885058720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 134523004185 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2995074186000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3469979039145 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.787680 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4982479156750 # Time in different power states +system.physmem_1.memoryStateTime::REF 173254120000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32774591500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32730835250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10376908954 # number of cpu cycles simulated +system.cpu.numCycles 10376928454 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128768549 # Number of instructions committed -system.cpu.committedOps 248207575 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232776792 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2318393 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23210237 # number of instructions that are conditional controls -system.cpu.num_int_insts 232776792 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 436093789 # number of times the integer registers were read -system.cpu.num_int_register_writes 198513181 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.committedInsts 128784844 # Number of instructions committed +system.cpu.committedOps 248241672 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232811079 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses +system.cpu.num_func_calls 2318021 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23218427 # number of instructions that are conditional controls +system.cpu.num_int_insts 232811079 # number of integer instructions +system.cpu.num_fp_insts 48 # number of float instructions +system.cpu.num_int_register_reads 436120957 # number of times the integer registers were read +system.cpu.num_int_register_writes 198544312 # number of times the integer registers were written +system.cpu.num_fp_register_reads 48 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 133234655 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95751573 # number of times the CC registers were written -system.cpu.num_mem_refs 22383387 # number of memory refs -system.cpu.num_load_insts 13964107 # Number of load instructions -system.cpu.num_store_insts 8419280 # Number of store instructions -system.cpu.num_idle_cycles 9778785583.998116 # Number of idle cycles -system.cpu.num_busy_cycles 598123370.001885 # Number of busy cycles -system.cpu.not_idle_fraction 0.057640 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942360 # Percentage of idle cycles -system.cpu.Branches 26388104 # Number of branches fetched -system.cpu.op_class::No_OpClass 172612 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 225394100 90.81% 90.88% # Class of executed instruction -system.cpu.op_class::IntMult 140617 0.06% 90.93% # Class of executed instruction -system.cpu.op_class::IntDiv 123416 0.05% 90.98% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.98% # Class of executed instruction -system.cpu.op_class::MemRead 13959118 5.62% 96.61% # Class of executed instruction -system.cpu.op_class::MemWrite 8419280 3.39% 100.00% # Class of executed instruction +system.cpu.num_cc_register_reads 133281322 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95783918 # number of times the CC registers were written +system.cpu.num_mem_refs 22376754 # number of memory refs +system.cpu.num_load_insts 13962110 # Number of load instructions +system.cpu.num_store_insts 8414644 # Number of store instructions +system.cpu.num_idle_cycles 9778737102.998116 # Number of idle cycles +system.cpu.num_busy_cycles 598191351.001885 # Number of busy cycles +system.cpu.not_idle_fraction 0.057646 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942354 # Percentage of idle cycles +system.cpu.Branches 26395735 # Number of branches fetched +system.cpu.op_class::No_OpClass 172520 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 225434965 90.81% 90.88% # Class of executed instruction +system.cpu.op_class::IntMult 140546 0.06% 90.94% # Class of executed instruction +system.cpu.op_class::IntDiv 123415 0.05% 90.99% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction +system.cpu.op_class::MemRead 13957123 5.62% 96.61% # Class of executed instruction +system.cpu.op_class::MemWrite 8414644 3.39% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 248209143 # Class of executed instruction +system.cpu.op_class::total 248243229 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 1623444 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20166944 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1623956 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.418405 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1624253 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996840 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20159481 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1624765 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.407629 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996840 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 87 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88826058 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88826058 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12020150 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12020150 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8085355 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8085355 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 59272 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 59272 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20105505 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20105505 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20164777 # number of overall hits -system.cpu.dcache.overall_hits::total 20164777 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 907010 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 907010 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 325954 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 325954 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 402776 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 402776 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1232964 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1232964 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1635740 # number of overall misses -system.cpu.dcache.overall_misses::total 1635740 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12729308500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12729308500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11333106054 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11333106054 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24062414554 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24062414554 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24062414554 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24062414554 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12927160 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12927160 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8411309 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8411309 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 462048 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 462048 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21338469 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21338469 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21800517 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21800517 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070163 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070163 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038752 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.038752 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871719 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.871719 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057781 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057781 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075032 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075032 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14034.364009 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14034.364009 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34769.035060 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34769.035060 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19515.910078 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19515.910078 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14710.415197 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14710.415197 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9503 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88800329 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88800329 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12017170 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12017170 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8080876 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8080876 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 59251 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 59251 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20098046 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20098046 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20157297 # number of overall hits +system.cpu.dcache.overall_hits::total 20157297 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 908286 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 908286 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 325792 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 325792 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 402501 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 402501 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1234078 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1234078 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1636579 # number of overall misses +system.cpu.dcache.overall_misses::total 1636579 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12749281750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12749281750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11335230829 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11335230829 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24084512579 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24084512579 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24084512579 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24084512579 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12925456 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12925456 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8406668 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8406668 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461752 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461752 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21332124 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21332124 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21793876 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21793876 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070271 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070271 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038754 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.038754 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871682 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.871682 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057851 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057851 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075094 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075094 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14036.637964 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14036.637964 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34792.845831 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34792.845831 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19516.199607 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19516.199607 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14716.376404 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14716.376404 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9103 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 92 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 96 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 103.293478 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 94.822917 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1539984 # number of writebacks -system.cpu.dcache.writebacks::total 1539984 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1540563 # number of writebacks +system.cpu.dcache.writebacks::total 1540563 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 290 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 290 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9259 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9259 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9549 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9549 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9549 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9549 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906720 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 906720 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316695 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 316695 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402742 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402742 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1223415 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1223415 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1626157 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1626157 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10908565500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10908565500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10195656140 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10195656140 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5345944000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5345944000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21104221640 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21104221640 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26450165640 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26450165640 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9246 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9246 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9536 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9536 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9536 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9536 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907996 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 907996 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316546 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 316546 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402467 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 402467 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1224542 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1224542 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1627009 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1627009 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10925755250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10925755250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10200095361 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10200095361 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5340766250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5340766250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21125850611 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21125850611 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26466616861 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26466616861 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94247525000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94247525000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2568414500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2568414500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96815939500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96815939500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070141 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070141 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037651 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037651 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871645 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871645 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057334 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057334 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074593 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12030.798372 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12030.798372 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32193.928354 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32193.928354 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13273.867637 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13273.867637 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17250.255751 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17250.255751 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16265.444013 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16265.444013 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2568413500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2568413500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96815938500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96815938500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070249 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070249 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037654 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037654 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871609 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871609 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057404 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057404 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074654 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074654 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12032.823107 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12032.823107 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32223.106155 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32223.106155 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13270.072453 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13270.072453 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17252.042487 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17252.042487 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16267.037774 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16267.037774 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -538,59 +536,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 8115 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.053285 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13021 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 8129 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.601796 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5157393413000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.053285 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315830 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315830 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 54039 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 54039 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13023 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13023 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13023 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13023 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13023 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13023 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9331 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 9331 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9331 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 9331 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9331 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 9331 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97236000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97236000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97236000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 97236000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97236000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 97236000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22354 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22354 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22354 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22354 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22354 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22354 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.417420 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.417420 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.417420 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.417420 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.417420 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.417420 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10420.748044 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10420.748044 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10420.748044 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10420.748044 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10420.748044 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10420.748044 # average overall miss latency +system.cpu.dtb_walker_cache.tags.replacements 7518 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.053105 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13360 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7533 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.773530 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5157758038000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.053105 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315819 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315819 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 52972 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 52972 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13370 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13370 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13370 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13370 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13370 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13370 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8744 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8744 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8744 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8744 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8744 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8744 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92278000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92278000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92278000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 92278000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92278000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 92278000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22114 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22114 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22114 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22114 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22114 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22114 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395406 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395406 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395406 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395406 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395406 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395406 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10553.293687 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10553.293687 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10553.293687 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10553.293687 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10553.293687 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10553.293687 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -599,86 +596,86 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3011 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3011 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9331 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9331 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9331 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 9331 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9331 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 9331 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 78573500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 78573500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 78573500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 78573500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 78573500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 78573500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.417420 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.417420 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.417420 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.417420 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.417420 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.417420 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8420.694459 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8420.694459 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8420.694459 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8420.694459 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8420.694459 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8420.694459 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2885 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2885 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8744 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8744 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8744 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8744 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8744 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8744 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74789500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74789500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74789500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74789500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395406 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395406 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395406 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395406 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395406 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395406 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8553.236505 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8553.236505 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8553.236505 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 793710 # number of replacements -system.cpu.icache.tags.tagsinuse 510.347195 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145088955 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 794222 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.680604 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 794079 # number of replacements +system.cpu.icache.tags.tagsinuse 510.347189 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 145115978 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 794591 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 182.629778 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 161164789250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.347195 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.347189 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.996772 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.996772 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 307 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146677413 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146677413 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 145088955 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145088955 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145088955 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145088955 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145088955 # number of overall hits -system.cpu.icache.overall_hits::total 145088955 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 794229 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 794229 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 794229 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 794229 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 794229 # number of overall misses -system.cpu.icache.overall_misses::total 794229 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11146745615 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11146745615 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11146745615 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11146745615 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11146745615 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11146745615 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145883184 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145883184 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145883184 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145883184 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145883184 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145883184 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005444 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005444 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005444 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005444 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005444 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005444 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14034.674653 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14034.674653 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14034.674653 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14034.674653 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14034.674653 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14034.674653 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146705174 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146705174 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 145115978 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145115978 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145115978 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145115978 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145115978 # number of overall hits +system.cpu.icache.overall_hits::total 145115978 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 794598 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 794598 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 794598 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 794598 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 794598 # number of overall misses +system.cpu.icache.overall_misses::total 794598 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11149966366 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11149966366 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11149966366 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11149966366 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11149966366 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11149966366 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145910576 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145910576 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145910576 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145910576 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145910576 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145910576 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005446 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005446 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005446 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005446 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005446 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005446 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14032.210459 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14032.210459 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14032.210459 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14032.210459 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14032.210459 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14032.210459 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -687,88 +684,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 794229 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 794229 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 794229 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 794229 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 794229 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 794229 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9553400385 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9553400385 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9553400385 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9553400385 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9553400385 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9553400385 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005444 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005444 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005444 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12028.521226 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12028.521226 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12028.521226 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12028.521226 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12028.521226 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12028.521226 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 794598 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 794598 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 794598 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 794598 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 794598 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 794598 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9555900634 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9555900634 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9555900634 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9555900634 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9555900634 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9555900634 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005446 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005446 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005446 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12026.081911 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12026.081911 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12026.081911 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12026.081911 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12026.081911 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12026.081911 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 4028 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.070596 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7432 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 4039 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.840059 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5161717779000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.070596 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191912 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.191912 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 3473 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.069566 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7987 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3486 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.291165 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5161163241000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069566 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191848 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.191848 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 29565 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 29565 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7435 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7435 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 28991 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 28991 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7985 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7985 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7437 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7437 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7437 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7437 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4897 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4897 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4897 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4897 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4897 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4897 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 48969750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 48969750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 48969750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 48969750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 48969750 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 48969750 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12332 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12332 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7987 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7987 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7987 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7987 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4339 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4339 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4339 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4339 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4339 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4339 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 42562750 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 42562750 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 42562750 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 42562750 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 42562750 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 42562750 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12324 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12324 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12334 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12334 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12334 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12334 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.397097 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.397097 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.397033 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.397033 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.397033 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.397033 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9999.948948 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9999.948948 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9999.948948 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9999.948948 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9999.948948 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9999.948948 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12326 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12326 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12326 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12326 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.352077 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.352077 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.352020 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.352020 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.352020 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.352020 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9809.345471 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9809.345471 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9809.345471 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9809.345471 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9809.345471 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9809.345471 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -777,177 +774,177 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4897 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4897 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4897 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4897 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4897 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4897 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 39174250 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 39174250 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 39174250 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 39174250 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 39174250 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 39174250 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.397097 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.397097 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.397033 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.397033 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.397033 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.397033 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7999.642638 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7999.642638 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7999.642638 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7999.642638 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7999.642638 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7999.642638 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 618 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 618 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4339 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4339 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4339 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4339 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4339 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4339 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33883250 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33883250 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33883250 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33883250 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33883250 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33883250 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.352077 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.352077 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.352020 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.352020 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.352020 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.352020 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7808.999770 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7808.999770 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7808.999770 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 87241 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64748.665455 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3494859 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 151936 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 23.002179 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 87360 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64748.911122 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3495788 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 152066 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 22.988623 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50323.834449 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006391 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141287 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3224.989333 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11199.693995 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.767881 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50325.123938 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006393 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141290 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3224.854795 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11198.784706 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.767900 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049209 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.170894 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.987986 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64695 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3016 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5015 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56538 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987167 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 32251607 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 32251607 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6647 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3226 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 781266 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1280034 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2071173 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1543797 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1543797 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 314 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 314 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 201020 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 201020 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6647 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3226 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 781266 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1481054 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2272193 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6647 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3226 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 781266 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1481054 # number of overall hits -system.cpu.l2cache.overall_hits::total 2272193 # number of overall hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049207 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.170880 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.987990 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 64706 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2949 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5093 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56562 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987335 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 32257665 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 32257665 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6357 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2756 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 781636 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1281044 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2071793 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1544066 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1544066 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 321 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 321 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 200764 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 200764 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6357 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2756 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 781636 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1481808 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2272557 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6357 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2756 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 781636 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1481808 # number of overall hits +system.cpu.l2cache.overall_hits::total 2272557 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12950 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 28613 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 41569 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1320 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1320 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 113503 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 113503 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12949 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 28624 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 41579 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1347 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1347 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 113593 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 113593 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12950 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 142116 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 155072 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12949 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 142217 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 155172 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12950 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 142116 # number of overall misses -system.cpu.l2cache.overall_misses::total 155072 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 12949 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 142217 # number of overall misses +system.cpu.l2cache.overall_misses::total 155172 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 350750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 946380250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2143813000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3090633250 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15722387 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 15722387 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7833269720 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7833269720 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 405750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 944829500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2144751500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3090076000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16383859 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 16383859 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7839721470 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7839721470 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 350750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 946380250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9977082720 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10923902970 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 405750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 944829500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9984472970 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10929797470 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 350750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 946380250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9977082720 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10923902970 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6648 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3231 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 794216 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1308647 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2112742 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1543797 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1543797 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1634 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1634 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 314523 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 314523 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6648 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3231 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 794216 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1623170 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2427265 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6648 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3231 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 794216 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1623170 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2427265 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000150 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001548 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016305 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021865 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.019675 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.807834 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.807834 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.360873 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.360873 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000150 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001548 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016305 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.087555 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.063888 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000150 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001548 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016305 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.087555 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.063888 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 405750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 944829500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9984472970 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10929797470 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6358 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2761 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 794585 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1309668 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2113372 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1544066 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1544066 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1668 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1668 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 314357 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 314357 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6358 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2761 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 794585 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1624025 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2427729 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6358 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2761 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 794585 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1624025 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2427729 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000157 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001811 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016297 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021856 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.019674 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.807554 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.807554 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361350 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.361350 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000157 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001811 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016297 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.087571 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.063917 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000157 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001811 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016297 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.087571 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.063917 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89250 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 70150 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73079.555985 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74924.439940 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74349.473165 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11910.899242 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11910.899242 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69013.768094 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69013.768094 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 81150 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72965.441347 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74928.434181 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74318.189471 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12163.221232 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12163.221232 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69015.885398 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69015.885398 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 70150 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73079.555985 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70203.796335 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70444.070948 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 81150 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72965.441347 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70205.903443 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70436.660416 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 70150 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73079.555985 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70203.796335 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70444.070948 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 81150 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72965.441347 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70205.903443 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70436.660416 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -956,90 +953,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 80277 # number of writebacks -system.cpu.l2cache.writebacks::total 80277 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 80295 # number of writebacks +system.cpu.l2cache.writebacks::total 80295 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12950 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28613 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 41569 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1320 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1320 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113503 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 113503 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12949 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28624 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 41579 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1347 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1347 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113593 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 113593 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12950 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 142116 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 155072 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12949 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 142217 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 155172 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12950 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 142116 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 155072 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12949 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 142217 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 155172 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 287750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 784145750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1785561500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2570071250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14126802 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14126802 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6414530780 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6414530780 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 342750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 782620000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1786397500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2569436500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14401829 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14401829 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6419846030 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6419846030 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 287750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 784145750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8200092280 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8984602030 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 342750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 782620000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8206243530 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8989282530 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 287750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 784145750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8200092280 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8984602030 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 342750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 782620000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8206243530 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8989282530 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86686810500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86686810500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2401284000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2401284000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89088094500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89088094500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000150 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001548 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016305 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021865 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019675 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.807834 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.807834 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.360873 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.360873 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000150 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001548 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016305 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087555 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063888 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000150 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001548 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016305 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087555 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063888 # mshr miss rate for overall accesses +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2401284500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2401284500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89088095000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89088095000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001811 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021856 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019674 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.807554 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.807554 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361350 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361350 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001811 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087571 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063917 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001811 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087571 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063917 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57550 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60551.795367 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62403.854891 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61826.631625 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10702.122727 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10702.122727 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56514.195924 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56514.195924 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68550 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60438.643911 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62409.079793 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61796.495827 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10691.780995 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10691.780995 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56516.211650 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56516.211650 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60551.795367 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57699.993526 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57938.261130 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68550 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60438.643911 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57702.268575 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57931.086343 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60551.795367 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57699.993526 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57938.261130 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68550 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60438.643911 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57702.268575 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57931.086343 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1047,54 +1044,54 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2700360 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2699834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2700583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2700055 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13918 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13918 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1543797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1544066 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2180 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2180 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 314528 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 314528 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1588445 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5982302 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8930 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18990 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7598667 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50829824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204129411 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 258112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 618176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 255835523 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 53618 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4025992 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011815 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.108054 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 2197 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2197 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 314362 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 314362 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1589183 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5984618 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7718 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 17987 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7599506 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50853440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204220931 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 216256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 591552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 255882179 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 53190 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4026335 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011814 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.108047 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3978424 98.82% 98.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47568 1.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3978769 98.82% 98.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47566 1.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4025992 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3837723500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4026335 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3838165000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 483000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 477000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1193787115 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1194331866 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3055897582 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3057201859 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 7346250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6509250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13996750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 13116250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 230300 # Transaction distribution -system.iobus.trans_dist::ReadResp 230300 # Transaction distribution +system.iobus.trans_dist::ReadReq 230298 # Transaction distribution +system.iobus.trans_dist::ReadResp 230298 # Transaction distribution system.iobus.trans_dist::WriteReq 57726 # Transaction distribution system.iobus.trans_dist::WriteResp 11006 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution @@ -1119,11 +1116,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 480916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95136 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95136 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95132 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95132 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3306 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3306 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 579358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 579354 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -1143,11 +1140,11 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 246738 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027328 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027312 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6612 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6612 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3280678 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3280662 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 3941856 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) @@ -1184,54 +1181,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 448381627 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 448396611 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 469910000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52236750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52232002 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iobus.respLayer2.occupancy 1653000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47513 # number of replacements -system.iocache.tags.tagsinuse 0.108235 # Cycle average of tags in use +system.iocache.tags.replacements 47511 # number of replacements +system.iocache.tags.tagsinuse 0.108263 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47529 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47527 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5045848693000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108235 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006765 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006765 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5045849712000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108263 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006766 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006766 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428112 # Number of tag accesses -system.iocache.tags.data_accesses 428112 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 848 # number of ReadReq misses -system.iocache.ReadReq_misses::total 848 # number of ReadReq misses +system.iocache.tags.tag_accesses 428094 # Number of tag accesses +system.iocache.tags.data_accesses 428094 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 846 # number of ReadReq misses +system.iocache.ReadReq_misses::total 846 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 848 # number of demand (read+write) misses -system.iocache.demand_misses::total 848 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 848 # number of overall misses -system.iocache.overall_misses::total 848 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144284936 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 144284936 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12370106941 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 12370106941 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 144284936 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 144284936 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 144284936 # number of overall miss cycles -system.iocache.overall_miss_latency::total 144284936 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 848 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 848 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 846 # number of demand (read+write) misses +system.iocache.demand_misses::total 846 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 846 # number of overall misses +system.iocache.overall_misses::total 846 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144419686 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 144419686 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12361743923 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 12361743923 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 144419686 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 144419686 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 144419686 # number of overall miss cycles +system.iocache.overall_miss_latency::total 144419686 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 846 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 846 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 848 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 848 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 848 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 848 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 846 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 846 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 846 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 846 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1240,40 +1237,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170147.330189 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 170147.330189 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264771.124593 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264771.124593 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170147.330189 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 170147.330189 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170147.330189 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 170147.330189 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 70958 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 170708.848700 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264592.121640 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264592.121640 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 170708.848700 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 170708.848700 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 70486 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9208 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9156 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.706125 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.698340 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 848 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 848 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 846 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 846 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 848 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 848 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 848 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 848 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100162436 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 100162436 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9940666941 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9940666941 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100162436 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 100162436 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100162436 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 100162436 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 846 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 846 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 846 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 846 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 100401686 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9932299927 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9932299927 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 100401686 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 100401686 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1282,71 +1279,71 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118116.080189 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 118116.080189 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212771.124593 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212771.124593 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118116.080189 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 118116.080189 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118116.080189 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 118116.080189 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 118678.115839 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212592.036109 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212592.036109 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 118678.115839 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 118678.115839 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 624010 # Transaction distribution -system.membus.trans_dist::ReadResp 624010 # Transaction distribution +system.membus.trans_dist::ReadReq 624018 # Transaction distribution +system.membus.trans_dist::ReadResp 624018 # Transaction distribution system.membus.trans_dist::WriteReq 13918 # Transaction distribution system.membus.trans_dist::WriteResp 13918 # Transaction distribution -system.membus.trans_dist::Writeback 126944 # Transaction distribution +system.membus.trans_dist::Writeback 126962 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2146 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1600 # Transaction distribution -system.membus.trans_dist::ReadExReq 113223 # Transaction distribution -system.membus.trans_dist::ReadExResp 113223 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1627 # Transaction distribution +system.membus.trans_dist::ReadExReq 113313 # Transaction distribution +system.membus.trans_dist::ReadExResp 113313 # Transaction distribution system.membus.trans_dist::MessageReq 1653 # Transaction distribution system.membus.trans_dist::MessageResp 1653 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3306 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3306 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392937 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1583959 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1728663 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393192 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584214 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141396 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141396 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1728916 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6612 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6612 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246738 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420209 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15002688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16669635 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15010240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16677187 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22681367 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1621 # Total snoops (count) -system.membus.snoop_fanout::samples 331450 # Request fanout histogram +system.membus.pkt_size::total 22688919 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1602 # Total snoops (count) +system.membus.snoop_fanout::samples 331576 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 331450 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 331576 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 331450 # Request fanout histogram -system.membus.reqLayer0.occupancy 257308500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 331576 # Request fanout histogram +system.membus.reqLayer0.occupancy 257309000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 358085000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 358083500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 3306000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1729709500 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1729903000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.respLayer0.occupancy 1653000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2618865668 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2619799141 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54365250 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 54348998 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini index 960bf1b41..9ee52b54f 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -140,6 +140,7 @@ eventq_index=0 type=LiveProcess cmd=hello cwd= +drivers= egid=100 env= errout=cerr @@ -148,6 +149,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index 8331b5d9d..9bc617783 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -144,6 +144,7 @@ eventq_index=0 type=LiveProcess cmd=hello cwd= +drivers= egid=100 env= errout=cerr @@ -152,6 +153,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -311,7 +313,7 @@ issue_latency=2 number_of_TBEs=256 recycle_latency=10 ruby_system=system.ruby -send_evictions=false +send_evictions=true sequencer=system.ruby.l1_cntrl0.sequencer system=system transitions_per_cycle=4 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini index 5b07510f0..916d9b36b 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini @@ -88,6 +88,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -138,6 +139,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -204,6 +206,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -253,6 +256,7 @@ eventq_index=0 type=LiveProcess cmd=hello cwd= +drivers= egid=100 env= errout=cerr @@ -261,6 +265,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 |