diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
| commit | 324bc9771d1f3129aee87ccb73bcf23ea4c3b60e (patch) | |
| tree | e5ca02cc181b18d2806e30b99da07d6072724988 /tests/quick | |
| parent | 337774e192cb9268244d05e828b395060ba1cefb (diff) | |
| download | gem5-324bc9771d1f3129aee87ccb73bcf23ea4c3b60e.tar.xz | |
stats: Update stats to match cache changes
Diffstat (limited to 'tests/quick')
59 files changed, 26692 insertions, 26404 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 59ee1a74c..af5c79ab1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,52 +4,52 @@ sim_seconds 1.869358 # Nu sim_ticks 1869358498000 # Number of ticks simulated final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2397277 # Simulator instruction rate (inst/s) -host_op_rate 2397276 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68943602925 # Simulator tick rate (ticks/s) -host_mem_usage 377676 # Number of bytes of host memory used -host_seconds 27.11 # Real time elapsed on the host +host_inst_rate 2198730 # Simulator instruction rate (inst/s) +host_op_rate 2198729 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63233555824 # Simulator tick rate (ticks/s) +host_mem_usage 377528 # Number of bytes of host memory used +host_seconds 29.56 # Real time elapsed on the host sim_insts 65000470 # Number of instructions simulated sim_ops 65000470 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 763776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 66536960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 106240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 766208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 758272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66535616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 105984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 766336 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 68174144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 763776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 106240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 870016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7835712 # Number of bytes written to this memory -system.physmem.bytes_written::total 7835712 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11934 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1039640 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1660 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 11972 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 68167168 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 758272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 105984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 864256 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7836224 # Number of bytes written to this memory +system.physmem.bytes_written::total 7836224 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1039619 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1656 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 11974 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1065221 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122433 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122433 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 408577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35593472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56832 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 409878 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 1065112 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122441 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122441 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 405632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35592753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 56695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 409946 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36469272 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 408577 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56832 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 465409 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4191658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4191658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4191658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 408577 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35593472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56832 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 409878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 36465540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 405632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 56695 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 462328 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4191932 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4191932 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4191932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 405632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35592753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 56695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 409946 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40660931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40657473 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses @@ -86,61 +86,6 @@ system.cpu0.itb.data_accesses 0 # DT system.cpu0.numCycles 3738723791 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 49478313 # Number of instructions committed -system.cpu0.committedOps 49478313 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 46202260 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses -system.cpu0.num_func_calls 1124639 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6043708 # number of instructions that are conditional controls -system.cpu0.num_int_insts 46202260 # number of integer instructions -system.cpu0.num_fp_insts 197598 # number of float instructions -system.cpu0.num_int_register_reads 64004164 # number of times the integer registers were read -system.cpu0.num_int_register_writes 34834852 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written -system.cpu0.num_mem_refs 12536155 # number of memory refs -system.cpu0.num_load_insts 7783785 # Number of load instructions -system.cpu0.num_store_insts 4752370 # Number of store instructions -system.cpu0.num_idle_cycles 3689240240.665401 # Number of idle cycles -system.cpu0.num_busy_cycles 49483550.334599 # Number of busy cycles -system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles -system.cpu0.Branches 7530941 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2589824 5.23% 5.23% # Class of executed instruction -system.cpu0.op_class::IntAlu 33436514 67.57% 72.80% # Class of executed instruction -system.cpu0.op_class::IntMult 50547 0.10% 72.90% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction -system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::MemRead 7945621 16.06% 89.02% # Class of executed instruction -system.cpu0.op_class::MemWrite 4758309 9.62% 98.63% # Class of executed instruction -system.cpu0.op_class::IprAccess 675566 1.37% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 49486454 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed system.cpu0.kern.inst.hwrei 150436 # number of hwrei instructions executed @@ -231,6 +176,61 @@ system.cpu0.kern.mode_ticks::kernel 1868349657500 99.95% 99.95% # n system.cpu0.kern.mode_ticks::user 1008632000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 2744 # number of times the context was actually changed +system.cpu0.committedInsts 49478313 # Number of instructions committed +system.cpu0.committedOps 49478313 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 46202260 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses +system.cpu0.num_func_calls 1124639 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6043708 # number of instructions that are conditional controls +system.cpu0.num_int_insts 46202260 # number of integer instructions +system.cpu0.num_fp_insts 197598 # number of float instructions +system.cpu0.num_int_register_reads 64004164 # number of times the integer registers were read +system.cpu0.num_int_register_writes 34834852 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written +system.cpu0.num_mem_refs 12536155 # number of memory refs +system.cpu0.num_load_insts 7783785 # Number of load instructions +system.cpu0.num_store_insts 4752370 # Number of store instructions +system.cpu0.num_idle_cycles 3689240240.665401 # Number of idle cycles +system.cpu0.num_busy_cycles 49483550.334599 # Number of busy cycles +system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles +system.cpu0.Branches 7530941 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2589824 5.23% 5.23% # Class of executed instruction +system.cpu0.op_class::IntAlu 33436514 67.57% 72.80% # Class of executed instruction +system.cpu0.op_class::IntMult 50547 0.10% 72.90% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction +system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::MemRead 7945621 16.06% 89.02% # Class of executed instruction +system.cpu0.op_class::MemWrite 4758309 9.62% 98.63% # Class of executed instruction +system.cpu0.op_class::IprAccess 675566 1.37% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 49486454 # Class of executed instruction system.cpu0.dcache.tags.replacements 1781373 # number of replacements system.cpu0.dcache.tags.tagsinuse 506.187448 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 10705809 # Total number of references to valid blocks. @@ -303,8 +303,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 632989 # number of writebacks -system.cpu0.dcache.writebacks::total 632989 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 632988 # number of writebacks +system.cpu0.dcache.writebacks::total 632988 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 618298 # number of replacements system.cpu0.icache.tags.tagsinuse 511.240646 # Cycle average of tags in use @@ -354,6 +354,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.writebacks::writebacks 618298 # number of writebacks +system.cpu0.icache.writebacks::total 618298 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses @@ -390,61 +392,6 @@ system.cpu1.itb.data_accesses 0 # DT system.cpu1.numCycles 3738297607 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 15522157 # Number of instructions committed -system.cpu1.committedOps 15522157 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 14295542 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses -system.cpu1.num_func_calls 493140 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1540067 # number of instructions that are conditional controls -system.cpu1.num_int_insts 14295542 # number of integer instructions -system.cpu1.num_fp_insts 198941 # number of float instructions -system.cpu1.num_int_register_reads 19514287 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10457599 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written -system.cpu1.num_mem_refs 4961785 # number of memory refs -system.cpu1.num_load_insts 2849089 # Number of load instructions -system.cpu1.num_store_insts 2112696 # Number of store instructions -system.cpu1.num_idle_cycles 3722774671.474094 # Number of idle cycles -system.cpu1.num_busy_cycles 15522935.525906 # Number of busy cycles -system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles -system.cpu1.Branches 2214162 # Number of branches fetched -system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction -system.cpu1.op_class::IntAlu 9156765 58.98% 64.49% # Class of executed instruction -system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction -system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::MemRead 2937015 18.92% 83.66% # Class of executed instruction -system.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction -system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 15525873 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 92290 # number of hwrei instructions executed @@ -518,6 +465,61 @@ system.cpu1.kern.mode_ticks::kernel 5986367000 0.32% 0.32% # nu system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 1862102855500 99.66% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2507 # number of times the context was actually changed +system.cpu1.committedInsts 15522157 # Number of instructions committed +system.cpu1.committedOps 15522157 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 14295542 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses +system.cpu1.num_func_calls 493140 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1540067 # number of instructions that are conditional controls +system.cpu1.num_int_insts 14295542 # number of integer instructions +system.cpu1.num_fp_insts 198941 # number of float instructions +system.cpu1.num_int_register_reads 19514287 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10457599 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written +system.cpu1.num_mem_refs 4961785 # number of memory refs +system.cpu1.num_load_insts 2849089 # Number of load instructions +system.cpu1.num_store_insts 2112696 # Number of store instructions +system.cpu1.num_idle_cycles 3722774671.474094 # Number of idle cycles +system.cpu1.num_busy_cycles 15522935.525906 # Number of busy cycles +system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles +system.cpu1.Branches 2214162 # Number of branches fetched +system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction +system.cpu1.op_class::IntAlu 9156765 58.98% 64.49% # Class of executed instruction +system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction +system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::MemRead 2937015 18.92% 83.66% # Class of executed instruction +system.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction +system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 15525873 # Class of executed instruction system.cpu1.dcache.tags.replacements 201756 # number of replacements system.cpu1.dcache.tags.tagsinuse 497.613037 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 4718402 # Total number of references to valid blocks. @@ -639,6 +641,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.writebacks::writebacks 380671 # number of writebacks +system.cpu1.icache.writebacks::total 380671 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -737,22 +741,22 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 999687 # number of replacements -system.l2c.tags.tagsinuse 65320.982503 # Cycle average of tags in use -system.l2c.tags.total_refs 4249853 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1064737 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.991458 # Average number of references to valid blocks. +system.l2c.tags.replacements 999918 # number of replacements +system.l2c.tags.tagsinuse 65320.982415 # Cycle average of tags in use +system.l2c.tags.total_refs 4249962 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1064968 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.990695 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55911.121944 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4939.470586 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4176.774738 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 179.034361 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 114.580874 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.853136 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.075370 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.063733 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002732 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 55992.770808 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4860.291584 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4178.146657 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 175.172078 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 114.601288 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.854382 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074162 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.063753 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002673 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001749 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65050 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 768 # Occupied blocks per task id @@ -761,62 +765,66 @@ system.l2c.tags.age_task_id_blocks_1024::2 6123 # system.l2c.tags.age_task_id_blocks_1024::3 5943 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 48945 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 46365678 # Number of tag accesses -system.l2c.tags.data_accesses 46365678 # Number of data accesses -system.l2c.Writeback_hits::writebacks 777520 # number of Writeback hits -system.l2c.Writeback_hits::total 777520 # number of Writeback hits +system.l2c.tags.tag_accesses 46365909 # Number of tag accesses +system.l2c.tags.data_accesses 46365909 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 777519 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 777519 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 719211 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 719211 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 577 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 693 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 13 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 50 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 111476 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 111475 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168079 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 606990 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 379552 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 986542 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 626685 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 129013 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 755698 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 606990 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 738161 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 379552 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits -system.l2c.demand_hits::total 1910319 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 606990 # number of overall hits -system.l2c.overall_hits::cpu0.data 738161 # number of overall hits -system.l2c.overall_hits::cpu1.inst 379552 # number of overall hits -system.l2c.overall_hits::cpu1.data 185616 # number of overall hits -system.l2c.overall_hits::total 1910319 # number of overall hits +system.l2c.ReadExReq_hits::total 168078 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 607076 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 379556 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 986632 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 626681 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 129011 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 755692 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 607076 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 738156 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 379556 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 185614 # number of demand (read+write) hits +system.l2c.demand_hits::total 1910402 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 607076 # number of overall hits +system.l2c.overall_hits::cpu0.data 738156 # number of overall hits +system.l2c.overall_hits::cpu1.inst 379556 # number of overall hits +system.l2c.overall_hits::cpu1.data 185614 # number of overall hits +system.l2c.overall_hits::total 1910402 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 2174 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 5180 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 1175 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1110 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2285 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113873 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 113874 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 11069 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124942 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 11934 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 1660 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13594 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 926611 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1033 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 11934 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1040484 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1660 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 12102 # number of demand (read+write) misses -system.l2c.demand_misses::total 1066180 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11934 # number of overall misses -system.l2c.overall_misses::cpu0.data 1040484 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1660 # number of overall misses -system.l2c.overall_misses::cpu1.data 12102 # number of overall misses -system.l2c.overall_misses::total 1066180 # number of overall misses -system.l2c.Writeback_accesses::writebacks 777520 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 777520 # number of Writeback accesses(hits+misses) +system.l2c.ReadExReq_misses::total 124943 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 11848 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 1656 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 13504 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 926615 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1035 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 927650 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 11848 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 1040489 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1656 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 12104 # number of demand (read+write) misses +system.l2c.demand_misses::total 1066097 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11848 # number of overall misses +system.l2c.overall_misses::cpu0.data 1040489 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1656 # number of overall misses +system.l2c.overall_misses::cpu1.data 12104 # number of overall misses +system.l2c.overall_misses::total 1066097 # number of overall misses +system.l2c.WritebackDirty_accesses::writebacks 777519 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 777519 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 719211 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 719211 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 2751 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 5873 # number of UpgradeReq accesses(hits+misses) @@ -848,25 +856,25 @@ system.l2c.UpgradeReq_miss_rate::total 0.882002 # mi system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.969472 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.988424 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.505318 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.505323 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.163568 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.426393 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019282 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004355 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013592 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596545 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.551073 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.019282 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.584987 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004355 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.061208 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.358199 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.019282 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.584987 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004355 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.061208 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.358199 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::total 0.426396 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019143 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004344 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013502 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596548 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007959 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.551076 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.019143 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.584990 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004344 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.061219 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.358171 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.019143 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.584990 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004344 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.061219 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.358171 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -875,47 +883,47 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 80913 # number of writebacks -system.l2c.writebacks::total 80913 # number of writebacks +system.l2c.writebacks::writebacks 80921 # number of writebacks +system.l2c.writebacks::total 80921 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7449 # Transaction distribution -system.membus.trans_dist::ReadResp 948866 # Transaction distribution +system.membus.trans_dist::ReadResp 948782 # Transaction distribution system.membus.trans_dist::WriteReq 14588 # Transaction distribution system.membus.trans_dist::WriteResp 14588 # Transaction distribution -system.membus.trans_dist::Writeback 122433 # Transaction distribution -system.membus.trans_dist::CleanEvict 917961 # Transaction distribution -system.membus.trans_dist::UpgradeReq 19616 # Transaction distribution +system.membus.trans_dist::WritebackDirty 122441 # Transaction distribution +system.membus.trans_dist::CleanEvict 917844 # Transaction distribution +system.membus.trans_dist::UpgradeReq 19642 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 14180 # Transaction distribution -system.membus.trans_dist::UpgradeResp 8160 # Transaction distribution -system.membus.trans_dist::ReadExReq 126472 # Transaction distribution -system.membus.trans_dist::ReadExResp 124247 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 941417 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8186 # Transaction distribution +system.membus.trans_dist::ReadExReq 126447 # Transaction distribution +system.membus.trans_dist::ReadExResp 124222 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 941333 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3174012 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3218086 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3173737 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3217811 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124995 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124995 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3343081 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3342806 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 73455634 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73363008 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 73449170 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 76124370 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 76117906 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2205834 # Request fanout histogram +system.membus.snoop_fanout::samples 2205642 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2205834 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2205642 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2205834 # Request fanout histogram +system.membus.snoop_fanout::total 2205642 # Request fanout histogram system.toL2Bus.snoop_filter.tot_requests 6035921 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 3018741 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 376832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -926,8 +934,9 @@ system.toL2Bus.trans_dist::ReadReq 7449 # Tr system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 777520 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1862622 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 777519 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 719211 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1143412 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 19614 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 14230 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 33844 # Transaction distribution @@ -940,17 +949,17 @@ system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5 system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1014431 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 661358 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 8791862 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612480 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758075 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24397568 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69513536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758011 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40526016 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 243126098 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1083281 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 7141075 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.106201 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.308342 # Request fanout histogram +system.toL2Bus.pkt_size::total 289155538 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1083512 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7141306 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.106198 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.308338 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 6383226 89.39% 89.39% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 6383457 89.39% 89.39% # Request fanout histogram system.toL2Bus.snoop_fanout::1 757309 10.60% 99.99% # Request fanout histogram system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram @@ -958,7 +967,7 @@ system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7141075 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 7141306 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 34e6d6348..3a45545f2 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,42 +4,42 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332273500 # Number of ticks simulated final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2390951 # Simulator instruction rate (inst/s) -host_op_rate 2390950 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72850763127 # Simulator tick rate (ticks/s) -host_mem_usage 374092 # Number of bytes of host memory used -host_seconds 25.11 # Real time elapsed on the host +host_inst_rate 2238603 # Simulator instruction rate (inst/s) +host_op_rate 2238602 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68208828665 # Simulator tick rate (ticks/s) +host_mem_usage 373932 # Number of bytes of host memory used +host_seconds 26.82 # Real time elapsed on the host sim_insts 60038341 # Number of instructions simulated sim_ops 60038341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 856000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66836224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66835456 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 67693184 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 856000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 856000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7414144 # Number of bytes written to this memory -system.physmem.bytes_written::total 7414144 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13375 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044316 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 67686912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7416128 # Number of bytes written to this memory +system.physmem.bytes_written::total 7416128 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044304 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1057706 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115846 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115846 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 467930 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36535858 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 1057608 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115877 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115877 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 464922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36535438 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37004313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 467930 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 467930 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4052924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4052924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4052924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 467930 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36535858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 37000884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 464922 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 464922 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4054008 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4054008 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4054008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 464922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36535438 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41057237 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41054893 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -76,61 +76,6 @@ system.cpu.itb.data_accesses 0 # DT system.cpu.numCycles 3658670905 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60038341 # Number of instructions committed -system.cpu.committedOps 60038341 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 55913563 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses -system.cpu.num_func_calls 1484182 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7110761 # number of instructions that are conditional controls -system.cpu.num_int_insts 55913563 # number of integer instructions -system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 76954014 # number of times the integer registers were read -system.cpu.num_int_register_writes 41740254 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 16115702 # number of memory refs -system.cpu.num_load_insts 9747508 # Number of load instructions -system.cpu.num_store_insts 6368194 # Number of store instructions -system.cpu.num_idle_cycles 3598621691.055137 # Number of idle cycles -system.cpu.num_busy_cycles 60049213.944863 # Number of busy cycles -system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.983587 # Percentage of idle cycles -system.cpu.Branches 9064400 # Number of branches fetched -system.cpu.op_class::No_OpClass 3199098 5.33% 5.33% # Class of executed instruction -system.cpu.op_class::IntAlu 39448273 65.69% 71.02% # Class of executed instruction -system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction -system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction -system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::MemRead 9975076 16.61% 87.80% # Class of executed instruction -system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction -system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 60050179 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed @@ -216,6 +161,61 @@ system.cpu.kern.mode_ticks::kernel 26833319500 1.47% 1.47% # nu system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::idle 1801033671500 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.committedInsts 60038341 # Number of instructions committed +system.cpu.committedOps 60038341 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 55913563 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses +system.cpu.num_func_calls 1484182 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7110761 # number of instructions that are conditional controls +system.cpu.num_int_insts 55913563 # number of integer instructions +system.cpu.num_fp_insts 324460 # number of float instructions +system.cpu.num_int_register_reads 76954014 # number of times the integer registers were read +system.cpu.num_int_register_writes 41740254 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written +system.cpu.num_mem_refs 16115702 # number of memory refs +system.cpu.num_load_insts 9747508 # Number of load instructions +system.cpu.num_store_insts 6368194 # Number of store instructions +system.cpu.num_idle_cycles 3598621691.055137 # Number of idle cycles +system.cpu.num_busy_cycles 60049213.944863 # Number of busy cycles +system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.983587 # Percentage of idle cycles +system.cpu.Branches 9064400 # Number of branches fetched +system.cpu.op_class::No_OpClass 3199098 5.33% 5.33% # Class of executed instruction +system.cpu.op_class::IntAlu 39448273 65.69% 71.02% # Class of executed instruction +system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction +system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction +system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::MemRead 9975076 16.61% 87.80% # Class of executed instruction +system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction +system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 60050179 # Class of executed instruction system.cpu.dcache.tags.replacements 2042728 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 14038398 # Total number of references to valid blocks. @@ -284,8 +284,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 833493 # number of writebacks -system.cpu.dcache.writebacks::total 833493 # number of writebacks +system.cpu.dcache.writebacks::writebacks 833492 # number of writebacks +system.cpu.dcache.writebacks::total 833492 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 919605 # number of replacements system.cpu.icache.tags.tagsinuse 511.215260 # Cycle average of tags in use @@ -335,19 +335,21 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 919605 # number of writebacks +system.cpu.icache.writebacks::total 919605 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 992219 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65424.374112 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4560066 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1057382 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.312600 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 992425 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65424.374115 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4560164 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1057588 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.311853 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 56252.896873 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4923.444270 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4248.032969 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.858351 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075126 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.064820 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 56331.555575 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4843.320500 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4249.498040 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.859551 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073903 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.064842 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id @@ -356,40 +358,44 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3053 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54045 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 48753828 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 48753828 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 833493 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 833493 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 48754034 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 48754034 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 833492 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 833492 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 919353 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 919353 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 187288 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 187288 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906839 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 906839 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811246 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 811246 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906839 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998534 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905373 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906839 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998534 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905373 # number of overall hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906925 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 906925 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811243 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 811243 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906925 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998531 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905456 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 906925 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998531 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905456 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 117066 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 117066 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13375 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 13375 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927641 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 927641 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13375 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044707 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1058082 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13375 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044707 # number of overall misses -system.cpu.l2cache.overall_misses::total 1058082 # number of overall misses -system.cpu.l2cache.Writeback_accesses::writebacks 833493 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 833493 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13289 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 13289 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927644 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044710 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1057999 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1044710 # number of overall misses +system.cpu.l2cache.overall_misses::total 1057999 # number of overall misses +system.cpu.l2cache.WritebackDirty_accesses::writebacks 833492 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 833492 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 919353 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 919353 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 304354 # number of ReadExReq accesses(hits+misses) @@ -408,16 +414,16 @@ system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384638 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.384638 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014535 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014535 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533468 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533468 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014535 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511299 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.357043 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014535 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511299 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.357043 # miss rate for overall accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014441 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014441 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533470 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533470 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014441 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511300 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.357015 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014441 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511300 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.357015 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -426,8 +432,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74334 # number of writebacks -system.cpu.l2cache.writebacks::total 74334 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74365 # number of writebacks +system.cpu.l2cache.writebacks::total 74365 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 5925822 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962455 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -439,8 +445,9 @@ system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 833493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2127019 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 833492 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 919353 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1207667 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution @@ -450,21 +457,21 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738887 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2759817 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6161717 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 8921534 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157102 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 243051950 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1075788 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 7018475 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117733440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157038 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 301890478 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1075994 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 7018681 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000744 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.027269 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 7013252 99.93% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 7013458 99.93% 99.93% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 5223 0.07% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 7018475 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 7018681 # Request fanout histogram system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -563,42 +570,42 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7184 # Transaction distribution -system.membus.trans_dist::ReadResp 948374 # Transaction distribution +system.membus.trans_dist::ReadResp 948291 # Transaction distribution system.membus.trans_dist::WriteReq 9838 # Transaction distribution system.membus.trans_dist::WriteResp 9838 # Transaction distribution -system.membus.trans_dist::Writeback 115846 # Transaction distribution -system.membus.trans_dist::CleanEvict 917156 # Transaction distribution -system.membus.trans_dist::UpgradeReq 132 # Transaction distribution -system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116946 # Transaction distribution -system.membus.trans_dist::ReadExResp 116946 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 941190 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115877 # Transaction distribution +system.membus.trans_dist::CleanEvict 917027 # Transaction distribution +system.membus.trans_dist::UpgradeReq 147 # Transaction distribution +system.membus.trans_dist::UpgradeResp 147 # Transaction distribution +system.membus.trans_dist::ReadExReq 116931 # Transaction distribution +system.membus.trans_dist::ReadExResp 116931 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 941107 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107665 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141709 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107401 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141445 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124977 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124977 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3266686 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3266422 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72466944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513070 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72462656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508782 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 75180974 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 75176686 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2150005 # Request fanout histogram +system.membus.snoop_fanout::samples 2149824 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2150005 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2149824 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2150005 # Request fanout histogram +system.membus.snoop_fanout::total 2149824 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 69fe46592..ce1bb41a0 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.982585 # Number of seconds simulated -sim_ticks 1982585357000 # Number of ticks simulated -final_tick 1982585357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.977709 # Number of seconds simulated +sim_ticks 1977709274000 # Number of ticks simulated +final_tick 1977709274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1043358 # Simulator instruction rate (inst/s) -host_op_rate 1043358 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33918612914 # Simulator tick rate (ticks/s) -host_mem_usage 377952 # Number of bytes of host memory used -host_seconds 58.45 # Real time elapsed on the host -sim_insts 60985541 # Number of instructions simulated -sim_ops 60985541 # Number of ops (including micro ops) simulated +host_inst_rate 1549555 # Simulator instruction rate (inst/s) +host_op_rate 1549555 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51561372502 # Simulator tick rate (ticks/s) +host_mem_usage 334884 # Number of bytes of host memory used +host_seconds 38.36 # Real time elapsed on the host +sim_insts 59435338 # Number of instructions simulated +sim_ops 59435338 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 804544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24689088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 59456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 522432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 694336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 23907392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 165888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1310592 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26076480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 804544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 59456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 864000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7738240 # Number of bytes written to this memory -system.physmem.bytes_written::total 7738240 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12571 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385767 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 929 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8163 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26079168 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 694336 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 165888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 860224 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7747712 # Number of bytes written to this memory +system.physmem.bytes_written::total 7747712 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 10849 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 373553 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2592 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 20478 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 407445 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120910 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120910 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 405805 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12452976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 29989 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 263510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13152765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 405805 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 29989 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 435795 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3903106 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3903106 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3903106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 405805 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12452976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 29989 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 263510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17055871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 407445 # Number of read requests accepted -system.physmem.writeReqs 120910 # Number of write requests accepted -system.physmem.readBursts 407445 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120910 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26068672 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7808 # Total number of bytes read from write queue -system.physmem.bytesWritten 7736640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26076480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7738240 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 122 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 407487 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121058 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121058 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 351081 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12088426 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 83879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 662682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13186553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 351081 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 83879 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 434960 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3917518 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3917518 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3917518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 351081 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12088426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 83879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 662682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17104071 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 407487 # Number of read requests accepted +system.physmem.writeReqs 121058 # Number of write requests accepted +system.physmem.readBursts 407487 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121058 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26071296 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7872 # Total number of bytes read from write queue +system.physmem.bytesWritten 7746112 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26079168 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7747712 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 123 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48696 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25232 # Per bank write bursts -system.physmem.perBankRdBursts::1 25377 # Per bank write bursts -system.physmem.perBankRdBursts::2 25433 # Per bank write bursts -system.physmem.perBankRdBursts::3 24853 # Per bank write bursts -system.physmem.perBankRdBursts::4 25156 # Per bank write bursts -system.physmem.perBankRdBursts::5 25421 # Per bank write bursts -system.physmem.perBankRdBursts::6 25501 # Per bank write bursts -system.physmem.perBankRdBursts::7 25341 # Per bank write bursts -system.physmem.perBankRdBursts::8 25248 # Per bank write bursts -system.physmem.perBankRdBursts::9 25578 # Per bank write bursts -system.physmem.perBankRdBursts::10 25745 # Per bank write bursts -system.physmem.perBankRdBursts::11 25922 # Per bank write bursts -system.physmem.perBankRdBursts::12 25991 # Per bank write bursts -system.physmem.perBankRdBursts::13 25558 # Per bank write bursts -system.physmem.perBankRdBursts::14 25312 # Per bank write bursts -system.physmem.perBankRdBursts::15 25655 # Per bank write bursts -system.physmem.perBankWrBursts::0 7850 # Per bank write bursts -system.physmem.perBankWrBursts::1 7774 # Per bank write bursts -system.physmem.perBankWrBursts::2 7467 # Per bank write bursts -system.physmem.perBankWrBursts::3 6887 # Per bank write bursts -system.physmem.perBankWrBursts::4 7102 # Per bank write bursts -system.physmem.perBankWrBursts::5 7345 # Per bank write bursts -system.physmem.perBankWrBursts::6 7434 # Per bank write bursts -system.physmem.perBankWrBursts::7 7145 # Per bank write bursts -system.physmem.perBankWrBursts::8 7156 # Per bank write bursts -system.physmem.perBankWrBursts::9 7306 # Per bank write bursts -system.physmem.perBankWrBursts::10 7741 # Per bank write bursts -system.physmem.perBankWrBursts::11 8153 # Per bank write bursts -system.physmem.perBankWrBursts::12 8257 # Per bank write bursts -system.physmem.perBankWrBursts::13 7909 # Per bank write bursts -system.physmem.perBankWrBursts::14 7539 # Per bank write bursts -system.physmem.perBankWrBursts::15 7820 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 306935 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25840 # Per bank write bursts +system.physmem.perBankRdBursts::1 26009 # Per bank write bursts +system.physmem.perBankRdBursts::2 26271 # Per bank write bursts +system.physmem.perBankRdBursts::3 25739 # Per bank write bursts +system.physmem.perBankRdBursts::4 24904 # Per bank write bursts +system.physmem.perBankRdBursts::5 25588 # Per bank write bursts +system.physmem.perBankRdBursts::6 25282 # Per bank write bursts +system.physmem.perBankRdBursts::7 25179 # Per bank write bursts +system.physmem.perBankRdBursts::8 24919 # Per bank write bursts +system.physmem.perBankRdBursts::9 24911 # Per bank write bursts +system.physmem.perBankRdBursts::10 25224 # Per bank write bursts +system.physmem.perBankRdBursts::11 25266 # Per bank write bursts +system.physmem.perBankRdBursts::12 25817 # Per bank write bursts +system.physmem.perBankRdBursts::13 25627 # Per bank write bursts +system.physmem.perBankRdBursts::14 25517 # Per bank write bursts +system.physmem.perBankRdBursts::15 25271 # Per bank write bursts +system.physmem.perBankWrBursts::0 8076 # Per bank write bursts +system.physmem.perBankWrBursts::1 7966 # Per bank write bursts +system.physmem.perBankWrBursts::2 8289 # Per bank write bursts +system.physmem.perBankWrBursts::3 8035 # Per bank write bursts +system.physmem.perBankWrBursts::4 7145 # Per bank write bursts +system.physmem.perBankWrBursts::5 7755 # Per bank write bursts +system.physmem.perBankWrBursts::6 7349 # Per bank write bursts +system.physmem.perBankWrBursts::7 7181 # Per bank write bursts +system.physmem.perBankWrBursts::8 6971 # Per bank write bursts +system.physmem.perBankWrBursts::9 7004 # Per bank write bursts +system.physmem.perBankWrBursts::10 7220 # Per bank write bursts +system.physmem.perBankWrBursts::11 7086 # Per bank write bursts +system.physmem.perBankWrBursts::12 7863 # Per bank write bursts +system.physmem.perBankWrBursts::13 7891 # Per bank write bursts +system.physmem.perBankWrBursts::14 7798 # Per bank write bursts +system.physmem.perBankWrBursts::15 7404 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 21 # Number of times write queue was full causing retry -system.physmem.totGap 1982577992500 # Total gap between requests +system.physmem.numWrRetry 19 # Number of times write queue was full causing retry +system.physmem.totGap 1977655892500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 407445 # Read request sizes (log2) +system.physmem.readPktSize::6 407487 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120910 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66 # What read queue length does an incoming req see +system.physmem.writePktSize::6 121058 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 71 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -158,177 +158,187 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67564 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 500.345036 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 302.441164 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 405.330516 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16348 24.20% 24.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12278 18.17% 42.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5298 7.84% 50.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3150 4.66% 54.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2433 3.60% 58.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4298 6.36% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1531 2.27% 67.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2195 3.25% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20033 29.65% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67564 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5409 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.303198 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2854.593157 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5406 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 65 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 68003 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 497.292884 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 300.084252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 405.105473 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16504 24.27% 24.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12590 18.51% 42.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5294 7.78% 50.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3182 4.68% 55.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2479 3.65% 58.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4294 6.31% 65.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1483 2.18% 67.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2078 3.06% 70.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20099 29.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 68003 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5421 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.144069 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2865.262786 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5418 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5409 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5409 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.348863 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.981514 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.757339 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4806 88.85% 88.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 190 3.51% 92.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 24 0.44% 92.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 50 0.92% 93.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 37 0.68% 94.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 6 0.11% 94.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 18 0.33% 94.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 42 0.78% 95.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 29 0.54% 96.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 3 0.06% 96.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 162 3.00% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 1 0.02% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 4 0.07% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.06% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 2 0.04% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 2 0.04% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 4 0.07% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 6 0.11% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 10 0.18% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 2 0.04% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.07% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::312-319 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5409 # Writes before turning the bus around for reads -system.physmem.totQLat 2792890500 # Total ticks spent queuing -system.physmem.totMemAccLat 10430196750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2036615000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6856.70 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5421 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5421 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.326692 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.006479 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.134399 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4779 88.16% 88.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 22 0.41% 88.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 23 0.42% 88.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 175 3.23% 92.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 9 0.17% 92.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 25 0.46% 92.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 50 0.92% 93.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 2 0.04% 93.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 13 0.24% 94.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 19 0.35% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.02% 94.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.11% 94.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 8 0.15% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.04% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 22 0.41% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 20 0.37% 95.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.07% 95.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 34 0.63% 96.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 96.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.04% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 161 2.97% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 3 0.06% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.04% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 6 0.11% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 5 0.09% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 3 0.06% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 16 0.30% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5421 # Writes before turning the bus around for reads +system.physmem.totQLat 2796894000 # Total ticks spent queuing +system.physmem.totMemAccLat 10434969000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2036820000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6865.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25606.70 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.15 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.15 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 25615.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.92 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing -system.physmem.readRowHits 363877 # Number of row buffer hits during reads -system.physmem.writeRowHits 96767 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.33 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.03 # Row buffer hit rate for writes -system.physmem.avgGap 3752359.67 # Average gap between requests -system.physmem.pageHitRate 87.20 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 243303480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132754875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1578049200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 382345920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 129492598560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 72929786580 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1125575674500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1330334513115 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.011108 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1872213779250 # Time in different power states -system.physmem_0.memoryStateTime::REF 66202760000 # Time in different power states +system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing +system.physmem.readRowHits 363824 # Number of row buffer hits during reads +system.physmem.writeRowHits 96570 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.31 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.77 # Row buffer hit rate for writes +system.physmem.avgGap 3741698.23 # Average gap between requests +system.physmem.pageHitRate 87.13 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 262483200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 143220000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1597533600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 400438080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 129174240000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 73962048600 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1121745657750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1327285621230 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.123235 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1865834845500 # Time in different power states +system.physmem_0.memoryStateTime::REF 66040000000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 44165427000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 45832914500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 267480360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 145946625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1599070200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 400988880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 129492598560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 74043413820 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1124598800250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1330548298695 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.118945 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1870589115500 # Time in different power states -system.physmem_1.memoryStateTime::REF 66202760000 # Time in different power states +system.physmem_1.actEnergy 251619480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 137292375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579905600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 383855760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 129174240000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 73584887580 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1122076500750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1327188301545 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.074027 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1866389529250 # Time in different power states +system.physmem_1.memoryStateTime::REF 66040000000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 45790077000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 45278230750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7416955 # DTB read hits +system.cpu0.dtb.read_hits 5727753 # DTB read hits system.cpu0.dtb.read_misses 7442 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490672 # DTB read accesses -system.cpu0.dtb.write_hits 5004564 # DTB write hits +system.cpu0.dtb.write_hits 3981122 # DTB write hits system.cpu0.dtb.write_misses 812 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187451 # DTB write accesses -system.cpu0.dtb.data_hits 12421519 # DTB hits +system.cpu0.dtb.data_hits 9708875 # DTB hits system.cpu0.dtb.data_misses 8254 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678123 # DTB accesses -system.cpu0.itb.fetch_hits 3482641 # ITB hits +system.cpu0.itb.fetch_hits 3124468 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3486512 # ITB accesses +system.cpu0.itb.fetch_accesses 3128339 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -341,91 +351,36 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3964851833 # number of cpu cycles simulated +system.cpu0.numCycles 3955086246 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47325532 # Number of instructions committed -system.cpu0.committedOps 47325532 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 43895499 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 207106 # Number of float alu accesses -system.cpu0.num_func_calls 1185742 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5567031 # number of instructions that are conditional controls -system.cpu0.num_int_insts 43895499 # number of integer instructions -system.cpu0.num_fp_insts 207106 # number of float instructions -system.cpu0.num_int_register_reads 60349527 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32725613 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 100583 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 102386 # number of times the floating registers were written -system.cpu0.num_mem_refs 12461430 # number of memory refs -system.cpu0.num_load_insts 7443904 # Number of load instructions -system.cpu0.num_store_insts 5017526 # Number of store instructions -system.cpu0.num_idle_cycles 3700363584.987226 # Number of idle cycles -system.cpu0.num_busy_cycles 264488248.012774 # Number of busy cycles -system.cpu0.not_idle_fraction 0.066708 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.933292 # Percentage of idle cycles -system.cpu0.Branches 7135463 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2703242 5.71% 5.71% # Class of executed instruction -system.cpu0.op_class::IntAlu 31183402 65.88% 71.59% # Class of executed instruction -system.cpu0.op_class::IntMult 51823 0.11% 71.70% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::FloatAdd 25571 0.05% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1656 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::MemRead 7617030 16.09% 87.85% # Class of executed instruction -system.cpu0.op_class::MemWrite 5023630 10.61% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 727776 1.54% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47334130 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6807 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 162813 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 55930 40.12% 40.12% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 133 0.10% 40.21% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1978 1.42% 41.63% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 435 0.31% 41.94% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 80947 58.06% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139423 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 55420 49.07% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 133 0.12% 49.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1978 1.75% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 435 0.39% 51.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 54986 48.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 112952 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1904955657000 96.09% 96.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 92166000 0.00% 96.10% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 765642500 0.04% 96.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 319863500 0.02% 96.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 76292557500 3.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1982425886500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990881 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4843 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 129735 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 41337 38.33% 38.33% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.12% 38.45% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1972 1.83% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 17 0.02% 40.29% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 64391 59.71% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 107848 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 40894 48.75% 48.75% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.16% 48.90% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1972 2.35% 51.25% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 17 0.02% 51.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 40877 48.73% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 83891 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1907093255000 96.44% 96.44% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 94033500 0.00% 96.44% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 783814000 0.04% 96.48% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 14262000 0.00% 96.48% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 69557728500 3.52% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1977543093000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.989283 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.679284 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810139 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.634825 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.777863 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -457,124 +412,179 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 523 0.35% 0.35% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3026 2.05% 2.41% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 132550 89.80% 92.24% # number of callpals executed -system.cpu0.kern.callpal::rdps 6593 4.47% 96.71% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed -system.cpu0.kern.callpal::rti 4327 2.93% 99.65% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 147613 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6866 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1281 # number of protection mode switches +system.cpu0.kern.callpal::wripir 93 0.08% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::swpctx 1998 1.74% 1.82% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.04% 1.87% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.01% 1.87% # number of callpals executed +system.cpu0.kern.callpal::swpipl 101884 88.63% 90.50% # number of callpals executed +system.cpu0.kern.callpal::rdps 6548 5.70% 96.19% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.20% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.20% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.21% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.21% # number of callpals executed +system.cpu0.kern.callpal::rti 3843 3.34% 99.55% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.33% 99.88% # number of callpals executed +system.cpu0.kern.callpal::imb 136 0.12% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 114960 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5413 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1281 -system.cpu0.kern.mode_good::user 1281 +system.cpu0.kern.mode_good::kernel 1282 +system.cpu0.kern.mode_good::user 1282 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186572 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.236837 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.314472 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1977675856500 99.80% 99.80% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3900112000 0.20% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.382972 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1972827474000 99.80% 99.80% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3894173000 0.20% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3027 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1172695 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.333942 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11237582 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1173114 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.579275 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 143226500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.333942 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986980 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986980 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 371 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 50910847 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 50910847 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6343242 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6343242 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4601243 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4601243 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138155 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 138155 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145460 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 145460 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10944485 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10944485 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10944485 # number of overall hits -system.cpu0.dcache.overall_hits::total 10944485 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 934191 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 934191 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 249028 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 249028 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13578 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13578 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5734 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5734 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1183219 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1183219 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1183219 # number of overall misses -system.cpu0.dcache.overall_misses::total 1183219 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42879044000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 42879044000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16797420000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 16797420000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 151036000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 151036000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 96889000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 96889000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 59676464000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 59676464000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 59676464000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 59676464000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7277433 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7277433 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4850271 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4850271 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151733 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 151733 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151194 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 151194 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12127704 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12127704 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12127704 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12127704 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128368 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.128368 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051343 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051343 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089486 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089486 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037925 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037925 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097563 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097563 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097563 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097563 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45899.654353 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 45899.654353 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67451.933116 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 67451.933116 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11123.582265 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11123.582265 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16897.279386 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16897.279386 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50435.687730 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50435.687730 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50435.687730 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50435.687730 # average overall miss latency +system.cpu0.kern.swap_context 1999 # number of times the context was actually changed +system.cpu0.committedInsts 36251265 # Number of instructions committed +system.cpu0.committedOps 36251265 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33727452 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 135758 # Number of float alu accesses +system.cpu0.num_func_calls 876834 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4248905 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33727452 # number of integer instructions +system.cpu0.num_fp_insts 135758 # number of float instructions +system.cpu0.num_int_register_reads 46333717 # number of times the integer registers were read +system.cpu0.num_int_register_writes 25193797 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 65701 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 66416 # number of times the floating registers were written +system.cpu0.num_mem_refs 9739707 # number of memory refs +system.cpu0.num_load_insts 5749561 # Number of load instructions +system.cpu0.num_store_insts 3990146 # Number of store instructions +system.cpu0.num_idle_cycles 3736968981.972937 # Number of idle cycles +system.cpu0.num_busy_cycles 218117264.027063 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055149 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944851 # Percentage of idle cycles +system.cpu0.Branches 5398761 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1979626 5.46% 5.46% # Class of executed instruction +system.cpu0.op_class::IntAlu 23753610 65.51% 70.97% # Class of executed instruction +system.cpu0.op_class::IntMult 36908 0.10% 71.07% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.07% # Class of executed instruction +system.cpu0.op_class::FloatAdd 22960 0.06% 71.13% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1656 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::MemRead 5882505 16.22% 87.36% # Class of executed instruction +system.cpu0.op_class::MemWrite 3995282 11.02% 98.38% # Class of executed instruction +system.cpu0.op_class::IprAccess 587316 1.62% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 36259863 # Class of executed instruction +system.cpu0.dcache.tags.replacements 822072 # number of replacements +system.cpu0.dcache.tags.tagsinuse 480.504845 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 8885001 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 822496 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 10.802485 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 144706500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.504845 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938486 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.938486 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 424 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 167 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 257 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.828125 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 39682070 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 39682070 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5000163 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5000163 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3644006 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3644006 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117543 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 117543 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123259 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 123259 # number of StoreCondReq hits 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StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 8969500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 53574880000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 53574880000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 53574880000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 53574880000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5612701 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5612701 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3853269 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 3853269 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124394 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 124394 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123895 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 123895 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 9465970 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 9465970 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9465970 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 9465970 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.109134 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.109134 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.054308 # miss rate for WriteReq accesses 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63110.882917 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 71283.819882 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 71283.819882 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13673.259378 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13673.259378 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14102.987421 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14102.987421 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 65192.035541 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 65192.035541 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 65192.035541 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 65192.035541 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -583,126 +593,126 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 672708 # number of writebacks -system.cpu0.dcache.writebacks::total 672708 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934191 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 934191 # number of ReadReq MSHR misses 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number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 137458000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137458000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 91155000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 91155000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58493245000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 58493245000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58493245000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 58493245000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1488672000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1488672000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2316060500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2316060500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3804732500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3804732500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128368 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128368 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051343 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051343 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089486 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089486 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037925 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037925 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097563 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097563 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097563 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097563 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44899.654353 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44899.654353 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66451.933116 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66451.933116 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10123.582265 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10123.582265 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15897.279386 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15897.279386 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49435.687730 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49435.687730 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49435.687730 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49435.687730 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210086.367485 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210086.367485 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214768.221439 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214768.221439 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212911.723559 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212911.723559 # average overall mshr uncacheable latency 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ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.109134 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.054308 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.054308 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055075 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055075 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.005133 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.005133 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086816 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.086816 # mshr miss rate for demand accesses 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average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 223917.659722 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 223917.659722 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 686863 # number of replacements -system.cpu0.icache.tags.tagsinuse 506.493433 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 46646633 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 687375 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.861987 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 58997592500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.493433 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989245 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.989245 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 490042 # number of replacements +system.cpu0.icache.tags.tagsinuse 506.476572 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 35769214 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 490554 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 72.915956 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 58998281500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.476572 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989212 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.989212 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 417 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 296 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48021627 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48021627 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 46646633 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 46646633 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 46646633 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 46646633 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 46646633 # number of overall hits -system.cpu0.icache.overall_hits::total 46646633 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 687497 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 687497 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 687497 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 687497 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 687497 # number of overall misses -system.cpu0.icache.overall_misses::total 687497 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10629492500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10629492500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10629492500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10629492500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10629492500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10629492500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47334130 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47334130 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47334130 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47334130 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47334130 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47334130 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014524 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014524 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014524 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014524 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014524 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014524 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15461.147467 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15461.147467 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15461.147467 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15461.147467 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15461.147467 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15461.147467 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 36750512 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 36750512 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 35769214 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 35769214 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 35769214 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 35769214 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 35769214 # number of overall hits +system.cpu0.icache.overall_hits::total 35769214 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 490649 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 490649 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 490649 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 490649 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 490649 # number of overall misses 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number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 36259863 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 36259863 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013531 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013531 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013531 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013531 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013531 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013531 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15913.971087 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15913.971087 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15913.971087 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15913.971087 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15913.971087 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15913.971087 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -711,51 +721,53 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687497 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 687497 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 687497 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 687497 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 687497 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 687497 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9941995500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9941995500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9941995500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9941995500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9941995500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9941995500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014524 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014524 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014524 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14461.147467 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 14461.147467 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 14461.147467 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 490042 # number of writebacks +system.cpu0.icache.writebacks::total 490042 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490649 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 490649 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 490649 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 490649 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 490649 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 490649 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7317525000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7317525000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7317525000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7317525000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7317525000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7317525000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013531 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013531 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013531 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013531 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013531 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013531 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14913.971087 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14913.971087 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14913.971087 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14913.971087 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14913.971087 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14913.971087 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2508569 # DTB read hits +system.cpu1.dtb.read_hits 3965416 # DTB read hits system.cpu1.dtb.read_misses 2993 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239364 # DTB read accesses -system.cpu1.dtb.write_hits 1828737 # DTB write hits +system.cpu1.dtb.write_hits 2725894 # DTB write hits system.cpu1.dtb.write_misses 342 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105248 # DTB write accesses -system.cpu1.dtb.data_hits 4337306 # DTB hits +system.cpu1.dtb.data_hits 6691310 # DTB hits system.cpu1.dtb.data_misses 3335 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344612 # DTB accesses -system.cpu1.itb.fetch_hits 1989876 # ITB hits +system.cpu1.itb.fetch_hits 2218092 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1991092 # ITB accesses +system.cpu1.itb.fetch_accesses 2219308 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -768,87 +780,32 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3965170714 # number of cpu cycles simulated +system.cpu1.numCycles 3955418548 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13660009 # Number of instructions committed -system.cpu1.committedOps 13660009 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12598388 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 178445 # Number of float alu accesses -system.cpu1.num_func_calls 429702 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1355296 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12598388 # number of integer instructions -system.cpu1.num_fp_insts 178445 # number of float instructions -system.cpu1.num_int_register_reads 17340989 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9240436 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 93179 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 95134 # number of times the floating registers were written -system.cpu1.num_mem_refs 4361445 # number of memory refs -system.cpu1.num_load_insts 2523214 # Number of load instructions -system.cpu1.num_store_insts 1838231 # Number of store instructions -system.cpu1.num_idle_cycles 3912374881.998026 # Number of idle cycles -system.cpu1.num_busy_cycles 52795832.001973 # Number of busy cycles -system.cpu1.not_idle_fraction 0.013315 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.986685 # Percentage of idle cycles -system.cpu1.Branches 1945174 # Number of branches fetched -system.cpu1.op_class::No_OpClass 733210 5.37% 5.37% # Class of executed instruction -system.cpu1.op_class::IntAlu 8079835 59.13% 64.50% # Class of executed instruction -system.cpu1.op_class::IntMult 22791 0.17% 64.67% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.67% # Class of executed instruction -system.cpu1.op_class::FloatAdd 14367 0.11% 64.77% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1986 0.01% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::MemRead 2597857 19.01% 83.80% # Class of executed instruction -system.cpu1.op_class::MemWrite 1839254 13.46% 97.26% # Class of executed instruction -system.cpu1.op_class::IprAccess 374073 2.74% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13663373 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2868 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 81018 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27534 38.52% 38.52% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1971 2.76% 41.28% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 523 0.73% 42.01% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 41447 57.99% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 71475 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26667 48.22% 48.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1971 3.56% 51.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 523 0.95% 52.73% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 26144 47.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 55305 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1912303307000 96.46% 96.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 705769500 0.04% 96.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 367699000 0.02% 96.51% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 69207844500 3.49% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1982584620000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968512 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3977 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 108865 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 40405 40.60% 40.60% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1966 1.98% 42.57% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 93 0.09% 42.67% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 57058 57.33% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 99522 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 39471 48.79% 48.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1966 2.43% 51.21% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 93 0.11% 51.33% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 39378 48.67% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 80908 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1902956585000 96.22% 96.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 734079500 0.04% 96.26% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 70449000 0.00% 96.26% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 73947425500 3.74% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1977708539000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.976884 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.630781 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.773767 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.690140 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.812966 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -864,124 +821,179 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 435 0.59% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2064 2.79% 3.38% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed -system.cpu1.kern.callpal::swpipl 65156 88.12% 91.51% # number of callpals executed -system.cpu1.kern.callpal::rdps 2261 3.06% 94.57% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.57% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.58% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.58% # number of callpals executed -system.cpu1.kern.callpal::rti 3824 5.17% 99.76% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 17 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2247 2.20% 2.22% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 2.22% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.23% # number of callpals executed +system.cpu1.kern.callpal::swpipl 94014 91.97% 94.20% # number of callpals executed +system.cpu1.kern.callpal::rdps 2296 2.25% 96.44% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 96.44% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.00% 96.45% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 96.45% # number of callpals executed +system.cpu1.kern.callpal::rti 3448 3.37% 99.82% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.13% 99.96% # number of callpals executed +system.cpu1.kern.callpal::imb 44 0.04% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 73942 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2112 # number of protection mode switches -system.cpu1.kern.mode_switch::user 464 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2921 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 911 -system.cpu1.kern.mode_good::user 464 -system.cpu1.kern.mode_good::idle 447 -system.cpu1.kern.mode_switch_good::kernel 0.431345 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 102224 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2738 # number of protection mode switches +system.cpu1.kern.mode_switch::user 463 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2043 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 518 +system.cpu1.kern.mode_good::user 463 +system.cpu1.kern.mode_good::idle 55 +system.cpu1.kern.mode_switch_good::kernel 0.189189 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.153030 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.331454 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 19415818500 0.98% 0.98% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1728972000 0.09% 1.07% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1961439827500 98.93% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2065 # number of times the context was actually changed -system.cpu1.dcache.tags.replacements 173710 # number of replacements -system.cpu1.dcache.tags.tagsinuse 481.751289 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4161033 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 174222 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.883511 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 90304766500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.751289 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940920 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.940920 # Average percentage of cache occupancy +system.cpu1.kern.mode_switch_good::idle 0.026921 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.197559 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 70603027000 3.57% 3.57% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1708148000 0.09% 3.66% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1905397362000 96.34% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2248 # number of times the context was actually changed +system.cpu1.committedInsts 23184073 # Number of instructions committed +system.cpu1.committedOps 23184073 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 21342235 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 193178 # Number of float alu accesses +system.cpu1.num_func_calls 708348 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2510657 # number of instructions that are conditional controls +system.cpu1.num_int_insts 21342235 # number of integer instructions +system.cpu1.num_fp_insts 193178 # number of float instructions +system.cpu1.num_int_register_reads 29195011 # number of times the integer registers were read +system.cpu1.num_int_register_writes 15673593 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 100176 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 102374 # number of times the floating registers were written +system.cpu1.num_mem_refs 6716060 # number of memory refs +system.cpu1.num_load_insts 3980976 # Number of load instructions +system.cpu1.num_store_insts 2735084 # Number of store instructions +system.cpu1.num_idle_cycles 3859200221.998049 # Number of idle cycles +system.cpu1.num_busy_cycles 96218326.001951 # Number of busy cycles +system.cpu1.not_idle_fraction 0.024326 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.975674 # Percentage of idle cycles +system.cpu1.Branches 3468812 # Number of branches fetched +system.cpu1.op_class::No_OpClass 1369332 5.91% 5.91% # Class of executed instruction +system.cpu1.op_class::IntAlu 14462485 62.37% 68.28% # Class of executed instruction +system.cpu1.op_class::IntMult 32790 0.14% 68.42% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.42% # Class of executed instruction +system.cpu1.op_class::FloatAdd 15288 0.07% 68.48% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.48% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.48% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.48% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.01% 68.49% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::MemRead 4085109 17.62% 86.11% # Class of executed instruction +system.cpu1.op_class::MemWrite 2736216 11.80% 97.91% # Class of executed instruction +system.cpu1.op_class::IprAccess 484231 2.09% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 23187437 # Class of executed instruction +system.cpu1.dcache.tags.replacements 637928 # number of replacements +system.cpu1.dcache.tags.tagsinuse 487.645459 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6059697 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 638440 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 9.491412 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 77414441500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 487.645459 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.952433 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.952433 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 17592927 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 17592927 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2337017 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2337017 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1705874 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1705874 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50407 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 50407 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 53062 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 53062 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4042891 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4042891 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4042891 # number of overall hits -system.cpu1.dcache.overall_hits::total 4042891 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 123430 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 123430 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 65652 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 65652 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9249 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9249 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6101 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 6101 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 189082 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 189082 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 189082 # number of overall misses -system.cpu1.dcache.overall_misses::total 189082 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1554368000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1554368000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1876323500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1876323500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84244000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 84244000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 98989500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 98989500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 3430691500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 3430691500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 3430691500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 3430691500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2460447 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2460447 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1771526 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1771526 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59656 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 59656 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59163 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 59163 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4231973 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4231973 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4231973 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4231973 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050166 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.050166 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.037060 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.037060 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155039 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155039 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103122 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103122 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044679 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044679 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044679 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044679 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12593.113506 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12593.113506 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28579.837629 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 28579.837629 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.444156 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.444156 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16225.127028 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16225.127028 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18143.934907 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18143.934907 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18143.934907 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18143.934907 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 27453473 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 27453473 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3383453 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3383453 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2527183 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2527183 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 67642 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 67642 # number of LoadLockedReq hits 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for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12952.760901 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12952.760901 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32843.640417 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32843.640417 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12911.891725 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12911.891725 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15905.819296 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15905.819296 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16726.466321 # average overall miss latency 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-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123430 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 123430 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65652 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 65652 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9249 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9249 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6101 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6101 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 189082 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 189082 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 189082 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 189082 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 118 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3347 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3347 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3465 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3465 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1430938000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1430938000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1810671500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1810671500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74995000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74995000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 92888500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 92888500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3241609500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3241609500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3241609500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3241609500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23714500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23714500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 747400000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 747400000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 771114500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 771114500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050166 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050166 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037060 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.037060 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155039 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155039 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103122 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103122 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044679 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044679 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044679 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044679 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11593.113506 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11593.113506 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27579.837629 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27579.837629 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8108.444156 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8108.444156 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15225.127028 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15225.127028 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17143.934907 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17143.934907 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17143.934907 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17143.934907 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200970.338983 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 200970.338983 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 223304.451748 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 223304.451748 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 222543.867244 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 222543.867244 # average overall mshr uncacheable latency +system.cpu1.dcache.writebacks::writebacks 496006 # number of writebacks +system.cpu1.dcache.writebacks::total 496006 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 511536 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 511536 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 119772 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 119772 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12967 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12967 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 653 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 653 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 631308 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 631308 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 631308 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 631308 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2385 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2385 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4228 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4228 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 6613 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 6613 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 6114267500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 6114267500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3813976500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3813976500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 154461500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 154461500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 9733500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 9733500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9928244000 # number of demand (read+write) MSHR miss cycles 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uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.131332 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.131332 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.045249 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.045249 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.160863 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.160863 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.008154 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.008154 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.096502 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.096502 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.096502 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.096502 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11952.760901 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11952.760901 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31843.640417 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31843.640417 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11911.891725 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.891725 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14905.819296 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14905.819296 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15726.466321 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15726.466321 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15726.466321 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15726.466321 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 218041.719078 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 218041.719078 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 234844.252602 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 234844.252602 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 228784.364131 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 228784.364131 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 331160 # number of replacements -system.cpu1.icache.tags.tagsinuse 442.919388 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 13331662 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 331672 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.195319 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1976558526500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.919388 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865077 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.865077 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 510167 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.053321 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 22676720 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 510679 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 44.405037 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 117353975500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.053321 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968854 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.968854 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 31 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13995086 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13995086 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 13331662 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13331662 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13331662 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13331662 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13331662 # number of overall hits -system.cpu1.icache.overall_hits::total 13331662 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 331712 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 331712 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 331712 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 331712 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 331712 # number of overall misses -system.cpu1.icache.overall_misses::total 331712 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4531331500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4531331500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4531331500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4531331500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4531331500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4531331500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13663374 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13663374 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13663374 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13663374 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13663374 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13663374 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024277 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024277 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024277 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024277 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024277 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024277 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13660.438875 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13660.438875 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13660.438875 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13660.438875 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13660.438875 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13660.438875 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 23698156 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 23698156 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 22676720 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 22676720 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 22676720 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 22676720 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 22676720 # number of overall hits +system.cpu1.icache.overall_hits::total 22676720 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 510718 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 510718 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 510718 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 510718 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 510718 # number of overall misses +system.cpu1.icache.overall_misses::total 510718 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7116614500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7116614500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7116614500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7116614500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7116614500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7116614500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 23187438 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 23187438 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 23187438 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 23187438 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 23187438 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 23187438 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022026 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.022026 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022026 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.022026 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022026 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.022026 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13934.528448 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13934.528448 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13934.528448 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13934.528448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13934.528448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13934.528448 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1120,30 +1132,32 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 331712 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 331712 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 331712 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 331712 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 331712 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 331712 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4199619500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4199619500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4199619500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4199619500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4199619500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4199619500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024277 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024277 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024277 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12660.438875 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12660.438875 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12660.438875 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 510167 # number of writebacks +system.cpu1.icache.writebacks::total 510167 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 510718 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 510718 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 510718 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 510718 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 510718 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 510718 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6605896500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6605896500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6605896500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6605896500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6605896500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6605896500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022026 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022026 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022026 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.022026 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022026 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.022026 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12934.528448 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12934.528448 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12934.528448 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12934.528448 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12934.528448 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12934.528448 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1157,110 +1171,110 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7379 # Transaction distribution -system.iobus.trans_dist::ReadResp 7379 # Transaction distribution -system.iobus.trans_dist::WriteReq 55683 # Transaction distribution -system.iobus.trans_dist::WriteResp 55683 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7376 # Transaction distribution +system.iobus.trans_dist::ReadResp 7376 # Transaction distribution +system.iobus.trans_dist::WriteReq 53973 # Transaction distribution +system.iobus.trans_dist::WriteResp 53973 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42670 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39240 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122698 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 82499 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2744123 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13414000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 68786 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2730426 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 11275500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 391000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 174500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15840500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2454000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2460000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6042000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 211500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 130500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 215099489 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215040242 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.occupancy 45000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28539000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26819000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41954000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.566806 # Cycle average of tags in use +system.iocache.tags.replacements 41699 # number of replacements +system.iocache.tags.tagsinuse 0.491123 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1775098751000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.566806 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035425 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035425 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1769281205000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.491123 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.030695 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.030695 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375543 # Number of tag accesses -system.iocache.tags.data_accesses 375543 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.tags.tag_accesses 375561 # Number of tag accesses +system.iocache.tags.data_accesses 375561 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses +system.iocache.ReadReq_misses::total 177 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses -system.iocache.demand_misses::total 175 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 175 # number of overall misses -system.iocache.overall_misses::total 175 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22127883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22127883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5428057606 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5428057606 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 22127883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 22127883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 22127883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 22127883 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 177 # number of demand (read+write) misses +system.iocache.demand_misses::total 177 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 177 # number of overall misses +system.iocache.overall_misses::total 177 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22195883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22195883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5429420359 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5429420359 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22195883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22195883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22195883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22195883 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 177 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 177 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 177 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 177 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1269,40 +1283,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126445.045714 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126445.045714 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130632.884241 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130632.884241 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126445.045714 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126445.045714 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126445.045714 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126445.045714 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125400.468927 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125400.468927 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130665.680569 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130665.680569 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125400.468927 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125400.468927 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125400.468927 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125400.468927 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 74 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 8 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 18.333333 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.250000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 41522 # number of writebacks +system.iocache.writebacks::total 41522 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13377883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13377883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350457606 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3350457606 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13377883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13377883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13377883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13377883 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 177 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 177 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 177 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 177 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13345883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13345883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3351820359 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3351820359 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13345883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13345883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13345883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13345883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1311,195 +1325,199 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76445.045714 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80632.884241 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80632.884241 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76445.045714 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76445.045714 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75400.468927 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75400.468927 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80665.680569 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80665.680569 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75400.468927 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75400.468927 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75400.468927 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75400.468927 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 341926 # number of replacements -system.l2c.tags.tagsinuse 65167.982973 # Cycle average of tags in use -system.l2c.tags.total_refs 3685196 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 406932 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.056049 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 12918028000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54774.174056 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4860.572445 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5374.369214 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 120.511186 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 38.356073 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.835788 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074166 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.082006 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.001839 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000585 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994385 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65006 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 516 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5383 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6300 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52705 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.991913 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 35906123 # Number of tag accesses -system.l2c.tags.data_accesses 35906123 # Number of data accesses -system.l2c.Writeback_hits::writebacks 792419 # number of Writeback hits -system.l2c.Writeback_hits::total 792419 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 186 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 557 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 743 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 39 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 63 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 124095 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 48625 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172720 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 674900 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 330771 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1005671 # number of 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SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480915 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.139213 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.415606 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013246 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.291677 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002954 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260159 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.330343 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.048080 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.172987 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.330343 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.048080 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.172987 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71556.285811 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71793.694690 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71646.178010 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71034.054054 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71513.455328 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71274.271845 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117140.858485 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121861.139369 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 117443.057297 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121479.185185 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113999.243205 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 119537.091988 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114006.107541 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114933.737808 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121765.638337 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 115287.456732 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114933.737808 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121765.638337 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 115287.456732 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197585.944115 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188466.101695 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197436.563021 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203268.082344 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 211804.152973 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 205289.894558 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201014.941242 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 211009.379509 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 202638.129834 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.948596 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.847368 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.931180 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.754902 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.783333 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770270 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.502971 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.164311 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.379463 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.022113 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005075 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013423 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.440287 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002333 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.244587 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.022113 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.455978 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005075 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.033396 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.167457 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.022113 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.455978 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005075 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.033396 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.167457 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71625.864719 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71547.619048 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71613.614263 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71603.896104 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71484.042553 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71538.011696 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116916.776424 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121970.977071 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117714.916573 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120876.301963 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121495.177469 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120995.647645 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113953.687422 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 120959.447800 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113983.554217 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120876.301963 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114771.852488 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121495.177469 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121913.852751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 115336.242358 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120876.301963 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114771.852488 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121495.177469 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121913.852751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 115336.242358 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210247.818862 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 205537.945493 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208687.456591 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 213090.076895 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 223340.468307 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216579.220675 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 212038.133313 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 216919.930440 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 213683.562691 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 7204 # Transaction distribution -system.membus.trans_dist::ReadResp 292756 # Transaction distribution -system.membus.trans_dist::WriteReq 14131 # Transaction distribution -system.membus.trans_dist::WriteResp 14131 # Transaction distribution -system.membus.trans_dist::Writeback 120910 # Transaction distribution -system.membus.trans_dist::CleanEvict 262059 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16821 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11772 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7147 # Transaction distribution -system.membus.trans_dist::ReadExReq 123180 # Transaction distribution -system.membus.trans_dist::ReadExResp 122316 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285552 # Transaction distribution +system.membus.trans_dist::ReadReq 7199 # Transaction distribution +system.membus.trans_dist::ReadResp 292680 # Transaction distribution +system.membus.trans_dist::WriteReq 12421 # Transaction distribution +system.membus.trans_dist::WriteResp 12421 # Transaction distribution +system.membus.trans_dist::WritebackDirty 121058 # Transaction distribution +system.membus.trans_dist::CleanEvict 261934 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4921 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1238 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3449 # Transaction distribution +system.membus.trans_dist::ReadExReq 122558 # Transaction distribution +system.membus.trans_dist::ReadExResp 122429 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285481 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42670 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1193160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1235830 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1360657 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82499 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31156480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31238979 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33897219 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22736 # Total snoops (count) -system.membus.snoop_fanout::samples 883364 # Request fanout histogram +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39240 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1166399 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1205639 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124831 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124831 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1330470 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68786 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31168512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31237298 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2658368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33895666 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3262 # Total snoops (count) +system.membus.snoop_fanout::samples 858545 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 883364 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 858545 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 883364 # Request fanout histogram -system.membus.reqLayer0.occupancy 40609000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 858545 # Request fanout histogram +system.membus.reqLayer0.occupancy 36672500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1325313892 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1323961648 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2193032106 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2184136804 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69837727 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69798217 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4790600 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2395468 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 361643 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 4935792 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2467069 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 374533 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 1240 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1180 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 7204 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2107021 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14131 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14131 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 913350 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1503335 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 17046 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11835 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28881 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297634 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297634 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1019209 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1080623 # Transaction distribution +system.toL2Bus.snoop_filter.hit_single_snoops 1179 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 61 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2152619 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12421 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12421 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 983748 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 732220 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 760785 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 4956 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1289 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 6245 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 324079 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 324079 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1001367 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1144069 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1918193 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3544327 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 867106 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 539630 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6869256 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43998144 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118001405 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 21229504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18604166 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 201833219 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 484490 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5237304 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.138719 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.345885 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1377223 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2478366 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1357708 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1834010 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7047307 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56740736 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 76009449 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 54207360 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 71099081 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 258056626 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 461903 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2920905 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.131024 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.337667 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4511205 86.14% 86.14% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 725687 13.86% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 408 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2538432 86.91% 86.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 382238 13.09% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 234 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5237304 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3205453497 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2920905 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4346798496 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 297883 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 299383 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1031366757 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1802104925 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 736191563 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1248608962 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 498533066 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 767009132 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 293884764 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 969915969 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 2decdfb20..350260732 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.941266 # Number of seconds simulated -sim_ticks 1941266487500 # Number of ticks simulated -final_tick 1941266487500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.941276 # Number of seconds simulated +sim_ticks 1941275996000 # Number of ticks simulated +final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1056307 # Simulator instruction rate (inst/s) -host_op_rate 1056307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36524098946 # Simulator tick rate (ticks/s) -host_mem_usage 374096 # Number of bytes of host memory used -host_seconds 53.15 # Real time elapsed on the host -sim_insts 56143021 # Number of instructions simulated -sim_ops 56143021 # Number of ops (including micro ops) simulated +host_inst_rate 1519860 # Simulator instruction rate (inst/s) +host_op_rate 1519860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52515485940 # Simulator tick rate (ticks/s) +host_mem_usage 331552 # Number of bytes of host memory used +host_seconds 36.97 # Real time elapsed on the host +sim_insts 56182743 # Number of instructions simulated +sim_ops 56182743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 848832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24855488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 844800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24856512 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25705280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 848832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 848832 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7407552 # Number of bytes written to this memory -system.physmem.bytes_written::total 7407552 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13263 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388367 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25702272 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 844800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 844800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7410752 # Number of bytes written to this memory +system.physmem.bytes_written::total 7410752 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13200 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388383 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401645 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115743 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115743 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 437257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12803749 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 401598 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115793 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115793 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 435178 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12804213 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13241500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 437257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 437257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3815835 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3815835 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3815835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 437257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12803749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13239886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 435178 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 435178 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3817464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3817464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3817464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 435178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12804213 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17057335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401645 # Number of read requests accepted -system.physmem.writeReqs 115743 # Number of write requests accepted -system.physmem.readBursts 401645 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115743 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25697728 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue -system.physmem.bytesWritten 7406016 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25705280 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7407552 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17057350 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401598 # Number of read requests accepted +system.physmem.writeReqs 115793 # Number of write requests accepted +system.physmem.readBursts 401598 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115793 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25694784 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue +system.physmem.bytesWritten 7408704 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25702272 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7410752 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 41682 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25168 # Per bank write bursts -system.physmem.perBankRdBursts::1 25510 # Per bank write bursts -system.physmem.perBankRdBursts::2 25518 # Per bank write bursts -system.physmem.perBankRdBursts::3 25527 # Per bank write bursts -system.physmem.perBankRdBursts::4 25065 # Per bank write bursts -system.physmem.perBankRdBursts::5 24960 # Per bank write bursts -system.physmem.perBankRdBursts::6 24241 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 303100 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25225 # Per bank write bursts +system.physmem.perBankRdBursts::1 25628 # Per bank write bursts +system.physmem.perBankRdBursts::2 25541 # Per bank write bursts +system.physmem.perBankRdBursts::3 25494 # Per bank write bursts +system.physmem.perBankRdBursts::4 25069 # Per bank write bursts +system.physmem.perBankRdBursts::5 24955 # Per bank write bursts +system.physmem.perBankRdBursts::6 24242 # Per bank write bursts system.physmem.perBankRdBursts::7 24604 # Per bank write bursts -system.physmem.perBankRdBursts::8 25078 # Per bank write bursts -system.physmem.perBankRdBursts::9 24653 # Per bank write bursts -system.physmem.perBankRdBursts::10 25359 # Per bank write bursts -system.physmem.perBankRdBursts::11 24824 # Per bank write bursts -system.physmem.perBankRdBursts::12 24407 # Per bank write bursts -system.physmem.perBankRdBursts::13 25357 # Per bank write bursts -system.physmem.perBankRdBursts::14 25770 # Per bank write bursts -system.physmem.perBankRdBursts::15 25486 # Per bank write bursts -system.physmem.perBankWrBursts::0 7561 # Per bank write bursts -system.physmem.perBankWrBursts::1 7519 # Per bank write bursts -system.physmem.perBankWrBursts::2 7810 # Per bank write bursts -system.physmem.perBankWrBursts::3 7560 # Per bank write bursts -system.physmem.perBankWrBursts::4 7221 # Per bank write bursts -system.physmem.perBankWrBursts::5 6978 # Per bank write bursts -system.physmem.perBankWrBursts::6 6351 # Per bank write bursts -system.physmem.perBankWrBursts::7 6424 # Per bank write bursts +system.physmem.perBankRdBursts::8 25085 # Per bank write bursts +system.physmem.perBankRdBursts::9 24651 # Per bank write bursts +system.physmem.perBankRdBursts::10 25269 # Per bank write bursts +system.physmem.perBankRdBursts::11 24875 # Per bank write bursts +system.physmem.perBankRdBursts::12 24508 # Per bank write bursts +system.physmem.perBankRdBursts::13 25360 # Per bank write bursts +system.physmem.perBankRdBursts::14 25616 # Per bank write bursts +system.physmem.perBankRdBursts::15 25359 # Per bank write bursts +system.physmem.perBankWrBursts::0 7625 # Per bank write bursts +system.physmem.perBankWrBursts::1 7638 # Per bank write bursts +system.physmem.perBankWrBursts::2 7842 # Per bank write bursts +system.physmem.perBankWrBursts::3 7532 # Per bank write bursts +system.physmem.perBankWrBursts::4 7224 # Per bank write bursts +system.physmem.perBankWrBursts::5 6973 # Per bank write bursts +system.physmem.perBankWrBursts::6 6356 # Per bank write bursts +system.physmem.perBankWrBursts::7 6427 # Per bank write bursts system.physmem.perBankWrBursts::8 7248 # Per bank write bursts -system.physmem.perBankWrBursts::9 6410 # Per bank write bursts -system.physmem.perBankWrBursts::10 7207 # Per bank write bursts -system.physmem.perBankWrBursts::11 6855 # Per bank write bursts -system.physmem.perBankWrBursts::12 6980 # Per bank write bursts -system.physmem.perBankWrBursts::13 7819 # Per bank write bursts -system.physmem.perBankWrBursts::14 7982 # Per bank write bursts -system.physmem.perBankWrBursts::15 7794 # Per bank write bursts +system.physmem.perBankWrBursts::9 6409 # Per bank write bursts +system.physmem.perBankWrBursts::10 7117 # Per bank write bursts +system.physmem.perBankWrBursts::11 6905 # Per bank write bursts +system.physmem.perBankWrBursts::12 7093 # Per bank write bursts +system.physmem.perBankWrBursts::13 7822 # Per bank write bursts +system.physmem.perBankWrBursts::14 7863 # Per bank write bursts +system.physmem.perBankWrBursts::15 7687 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 23 # Number of times write queue was full causing retry -system.physmem.totGap 1941254508500 # Total gap between requests +system.physmem.numWrRetry 16 # Number of times write queue was full causing retry +system.physmem.totGap 1941264122500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401645 # Read request sizes (log2) +system.physmem.readPktSize::6 401598 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115743 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401513 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115793 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401467 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -148,114 +148,123 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 134 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 146 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 176 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 87 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64921 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 509.908104 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 310.461658 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 406.215984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15228 23.46% 23.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11644 17.94% 41.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4997 7.70% 49.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2980 4.59% 53.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2446 3.77% 57.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4228 6.51% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1452 2.24% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2063 3.18% 69.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19883 30.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64921 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5102 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.697570 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2954.645683 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5099 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::56 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 51 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64941 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 509.747124 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 310.189706 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 406.049901 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15359 23.65% 23.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11448 17.63% 41.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4958 7.63% 48.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3153 4.86% 53.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2453 3.78% 57.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4206 6.48% 64.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1429 2.20% 66.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2063 3.18% 69.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19872 30.60% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64941 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5113 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.517700 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2951.127642 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5110 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5102 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5102 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.681105 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.154688 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.203626 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4492 88.04% 88.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 201 3.94% 91.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 29 0.57% 92.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 48 0.94% 93.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 38 0.74% 94.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 6 0.12% 94.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 11 0.22% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 38 0.74% 95.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 34 0.67% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 1 0.02% 96.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 159 3.12% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 2 0.04% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.04% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 5 0.10% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 1 0.02% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 2 0.04% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 3 0.06% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 3 0.06% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 4 0.08% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 8 0.16% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 4 0.08% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 3 0.06% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.08% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5102 # Writes before turning the bus around for reads -system.physmem.totQLat 2705942000 # Total ticks spent queuing -system.physmem.totMemAccLat 10234573250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2007635000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6739.13 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5113 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.640524 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.158069 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.669047 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4483 87.68% 87.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 26 0.51% 88.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 11 0.22% 88.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 181 3.54% 91.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 5 0.10% 92.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 20 0.39% 92.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 39 0.76% 93.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.12% 93.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 12 0.23% 93.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 31 0.61% 94.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.06% 94.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.06% 94.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 9 0.18% 94.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.02% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 22 0.43% 94.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 27 0.53% 95.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.04% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 26 0.51% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.06% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 161 3.15% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 5 0.10% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.04% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.06% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.08% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 4 0.08% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 11 0.22% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 5 0.10% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5113 # Writes before turning the bus around for reads +system.physmem.totQLat 2717940750 # Total ticks spent queuing +system.physmem.totMemAccLat 10245709500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2007405000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6769.79 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25489.13 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25519.79 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.24 # Average system read bandwidth in MiByte/s @@ -265,62 +274,62 @@ system.physmem.busUtil 0.13 # Da system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.77 # Average write queue length when enqueuing -system.physmem.readRowHits 358859 # Number of row buffer hits during reads -system.physmem.writeRowHits 93466 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.75 # Row buffer hit rate for writes -system.physmem.avgGap 3752028.47 # Average gap between requests +system.physmem.avgWrQLen 22.09 # Average write queue length when enqueuing +system.physmem.readRowHits 358828 # Number of row buffer hits during reads +system.physmem.writeRowHits 93473 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.72 # Row buffer hit rate for writes +system.physmem.avgGap 3752025.30 # Average gap between requests system.physmem.pageHitRate 87.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 239349600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 130597500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1564625400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 372107520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 126793670640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 71640444015 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1101913691250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1302654485925 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.035450 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1832853481750 # Time in different power states -system.physmem_0.memoryStateTime::REF 64822940000 # Time in different power states +system.physmem_0.actEnergy 240362640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 131150250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1565912400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 373358160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 71531321220 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1102018756500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1302655548930 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.030615 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1833026995250 # Time in different power states +system.physmem_0.memoryStateTime::REF 64823460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 43583902000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 43425441000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 251453160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 137201625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1567285200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 377751600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 126793670640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 72584952255 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1101085183500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1302797497980 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.109115 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1831469435000 # Time in different power states -system.physmem_1.memoryStateTime::REF 64822940000 # Time in different power states +system.physmem_1.actEnergy 250591320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136731375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1565639400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 376773120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 72715172175 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1100980290750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1302819885900 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.115269 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1831298493250 # Time in different power states +system.physmem_1.memoryStateTime::REF 64823460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 44967962500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 45153943000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9058452 # DTB read hits -system.cpu.dtb.read_misses 10327 # DTB read misses +system.cpu.dtb.read_hits 9064657 # DTB read hits +system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728858 # DTB read accesses -system.cpu.dtb.write_hits 6353129 # DTB write hits -system.cpu.dtb.write_misses 1143 # DTB write misses +system.cpu.dtb.read_accesses 728853 # DTB read accesses +system.cpu.dtb.write_hits 6356207 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291932 # DTB write accesses -system.cpu.dtb.data_hits 15411581 # DTB hits -system.cpu.dtb.data_misses 11470 # DTB misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses +system.cpu.dtb.data_hits 15420864 # DTB hits +system.cpu.dtb.data_misses 11466 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020790 # DTB accesses -system.cpu.itb.fetch_hits 4975133 # ITB hits +system.cpu.dtb.data_accesses 1020784 # DTB accesses +system.cpu.itb.fetch_hits 4975134 # ITB hits system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4980143 # ITB accesses +system.cpu.itb.fetch_accesses 4980144 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -333,87 +342,32 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3882532975 # number of cpu cycles simulated +system.cpu.numCycles 3882551992 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56143021 # Number of instructions committed -system.cpu.committedOps 56143021 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52016582 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1482534 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6465507 # number of instructions that are conditional controls -system.cpu.num_int_insts 52016582 # number of integer instructions -system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71267420 # number of times the integer registers were read -system.cpu.num_int_register_writes 38489507 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15464199 # number of memory refs -system.cpu.num_load_insts 9095305 # Number of load instructions -system.cpu.num_store_insts 6368894 # Number of store instructions -system.cpu.num_idle_cycles 3584401371.998154 # Number of idle cycles -system.cpu.num_busy_cycles 298131603.001846 # Number of busy cycles -system.cpu.not_idle_fraction 0.076788 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.923212 # Percentage of idle cycles -system.cpu.Branches 8418668 # Number of branches fetched -system.cpu.op_class::No_OpClass 3199011 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36202225 64.47% 70.17% # Class of executed instruction -system.cpu.op_class::IntMult 61032 0.11% 70.27% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction -system.cpu.op_class::FloatAdd 38085 0.07% 70.34% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::MemRead 9322424 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6374975 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56154858 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212043 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74906 40.88% 40.88% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212050 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74912 40.88% 40.88% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1935 1.06% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106248 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183220 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73539 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106253 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183231 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73545 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1935 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73539 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149144 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1860736112500 95.85% 95.85% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 92522000 0.00% 95.86% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 746030500 0.04% 95.89% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 79691088500 4.11% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1941265753500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981750 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73545 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149156 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1860509644500 95.84% 95.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94040000 0.00% 95.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 770515500 0.04% 95.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 79901062000 4.12% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1941275262000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692145 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814016 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692169 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814033 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -452,110 +406,165 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175993 91.21% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 176004 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6835 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rti 5160 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192944 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5907 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.callpal::total 192955 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5908 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323345 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.323121 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392117 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 48524962500 2.50% 2.50% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5595783500 0.29% 2.79% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1887145005500 97.21% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.391952 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 48611852500 2.50% 2.50% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5602941000 0.29% 2.79% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1887060466500 97.21% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed -system.cpu.dcache.tags.replacements 1390004 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.973850 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14040102 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1390516 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.097045 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 143374500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.973850 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999949 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999949 # Average percentage of cache occupancy +system.cpu.committedInsts 56182743 # Number of instructions committed +system.cpu.committedOps 56182743 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52054633 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses +system.cpu.num_func_calls 1483394 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6468678 # number of instructions that are conditional controls +system.cpu.num_int_insts 52054633 # number of integer instructions +system.cpu.num_fp_insts 324393 # number of float instructions +system.cpu.num_int_register_reads 71322499 # number of times the integer registers were read +system.cpu.num_int_register_writes 38520900 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written +system.cpu.num_mem_refs 15473474 # number of memory refs +system.cpu.num_load_insts 9101503 # Number of load instructions +system.cpu.num_store_insts 6371971 # Number of store instructions +system.cpu.num_idle_cycles 3583834697.998154 # Number of idle cycles +system.cpu.num_busy_cycles 298717294.001846 # Number of busy cycles +system.cpu.not_idle_fraction 0.076938 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.923062 # Percentage of idle cycles +system.cpu.Branches 8422724 # Number of branches fetched +system.cpu.op_class::No_OpClass 3200638 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36231019 64.47% 70.17% # Class of executed instruction +system.cpu.op_class::IntMult 61043 0.11% 70.28% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction +system.cpu.op_class::FloatAdd 38085 0.07% 70.35% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::MemRead 9328633 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6378052 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 56194576 # Class of executed instruction +system.cpu.dcache.tags.replacements 1390387 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.973391 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14048998 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390899 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.100660 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 145150500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.973391 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999948 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999948 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63112993 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63112993 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7808536 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7808536 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5849272 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5849272 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183025 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183025 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199252 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199252 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13657808 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13657808 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13657808 # number of overall hits -system.cpu.dcache.overall_hits::total 13657808 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069028 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069028 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304257 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304257 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17249 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17249 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373285 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373285 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373285 # number of overall misses -system.cpu.dcache.overall_misses::total 1373285 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 44750637500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 44750637500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17613913000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17613913000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232507000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 232507000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 62364550500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 62364550500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 62364550500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 62364550500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8877564 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8877564 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6153529 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6153529 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200274 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200274 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199252 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199252 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15031093 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15031093 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15031093 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15031093 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120419 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120419 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049444 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049444 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086127 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086127 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091363 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091363 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091363 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091363 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41861.052751 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41861.052751 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57891.562068 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57891.562068 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13479.448084 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13479.448084 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45412.678723 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45412.678723 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45412.678723 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45412.678723 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63150492 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63150492 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7814415 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7814415 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5852271 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5852271 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183035 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183035 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199260 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199260 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13666686 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13666686 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13666686 # number of overall hits +system.cpu.dcache.overall_hits::total 13666686 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069342 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069342 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304328 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304328 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17247 # number of LoadLockedReq misses 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# miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086114 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091332 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091332 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091332 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091332 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41867.681715 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41867.681715 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57944.517100 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57944.517100 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13503.652809 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13503.652809 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45429.404078 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45429.404078 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45429.404078 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45429.404078 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -564,120 +573,120 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834533 # number of writebacks -system.cpu.dcache.writebacks::total 834533 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069028 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069028 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304257 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304257 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17249 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17249 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373285 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373285 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373285 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373285 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 834936 # number of writebacks +system.cpu.dcache.writebacks::total 834936 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069342 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069342 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304328 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304328 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17247 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17247 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373670 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373670 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373670 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373670 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43681609500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43681609500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17309656000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17309656000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215258000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215258000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 60991265500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 60991265500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 60991265500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 60991265500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450109500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450109500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2050243500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2050243500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3500353000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3500353000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120419 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120419 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049444 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049444 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086127 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086127 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091363 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091363 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091363 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091363 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40861.052751 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40861.052751 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56891.562068 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56891.562068 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12479.448084 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12479.448084 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44412.678723 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44412.678723 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44412.678723 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44412.678723 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209251.010101 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209251.010101 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212394.436963 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212394.436963 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211080.805644 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211080.805644 # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43701528500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43701528500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17329811000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17329811000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215650500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215650500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61031339500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 61031339500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61031339500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 61031339500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1527878500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1527878500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2172467000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2172467000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3700345500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3700345500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049431 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049431 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086114 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086114 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091332 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091332 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091332 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091332 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40867.681715 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40867.681715 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56944.517100 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56944.517100 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12503.652809 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12503.652809 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44429.404078 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44429.404078 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44429.404078 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44429.404078 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220473.088023 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220473.088023 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 225056.148348 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225056.148348 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223140.897304 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223140.897304 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 928672 # number of replacements -system.cpu.icache.tags.tagsinuse 506.358595 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55225516 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 929183 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.434488 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 58555927500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 506.358595 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.988982 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.988982 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 928920 # number of replacements +system.cpu.icache.tags.tagsinuse 506.355618 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55264986 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 929431 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.461096 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 58592056500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 506.355618 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.988976 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.988976 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 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(read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929343 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929343 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929343 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12753400000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12753400000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12753400000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12753400000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12753400000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12753400000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016550 # mshr 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12756789500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12756789500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12756789500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12756789500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12756789500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016542 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016542 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for overall accesses 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200894.436963 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200894.436963 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199162.907797 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199162.907797 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383884 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383884 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014200 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250298 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250298 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279525 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173237 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279525 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173237 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71115.384615 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71115.384615 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117548.989899 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117548.989899 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120849.053030 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120849.053030 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113982.979803 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113982.979803 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120849.053030 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115054.458565 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115244.733091 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120849.053030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115054.458565 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115244.733091 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207968.614719 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207968.614719 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213547.808971 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213547.808971 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211216.275704 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211216.275704 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4638553 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2318842 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1135 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1135 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4639815 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319473 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1136 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1136 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2022707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2023267 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 950299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1744757 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 950745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 928699 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 816471 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304240 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304240 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 929343 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086450 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304311 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304311 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 929591 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086762 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787117 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4203130 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6990247 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59476672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142457836 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 201934508 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 419768 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5074727 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000845 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.029056 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787861 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4204279 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6992140 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118929280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142508140 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 261437420 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 419996 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2756910 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001015 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.031841 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5070439 99.92% 99.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4288 0.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2754112 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2798 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5074727 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3166927500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2756910 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4096881500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1394014500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1394386500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2097540500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2098115000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1003,45 +1015,45 @@ system.iobus.pkt_size_system.bridge.master::total 44588 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2706196 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4773000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5340500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 371000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15817000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 1891500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6032000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 212000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 131000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 215085744 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215014002 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.occupancy 45000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23513000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.339381 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.339384 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1774103808000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.339381 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.083711 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.083711 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1774106672000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.339384 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.083712 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.083712 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1055,14 +1067,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21913883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21913883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427871861 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5427871861 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21913883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21913883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21913883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21913883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21742883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21742883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5428926119 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5428926119 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21742883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21742883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21742883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21742883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1079,19 +1091,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126669.843931 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126669.843931 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130628.414059 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130628.414059 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126669.843931 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126669.843931 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126669.843931 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126669.843931 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125681.404624 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125681.404624 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130653.786075 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130653.786075 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125681.404624 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125681.404624 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1105,14 +1117,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13263883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13263883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350271861 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3350271861 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13263883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13263883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13263883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13263883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13092883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13092883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3351326119 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3351326119 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13092883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13092883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13092883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13092883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1121,59 +1133,59 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76669.843931 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80628.414059 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80628.414059 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76669.843931 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76669.843931 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80653.786075 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80653.786075 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 292325 # Transaction distribution +system.membus.trans_dist::ReadResp 292274 # Transaction distribution system.membus.trans_dist::WriteReq 9653 # Transaction distribution system.membus.trans_dist::WriteResp 9653 # Transaction distribution -system.membus.trans_dist::Writeback 115743 # Transaction distribution -system.membus.trans_dist::CleanEvict 261495 # Transaction distribution -system.membus.trans_dist::UpgradeReq 132 # Transaction distribution -system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116679 # Transaction distribution -system.membus.trans_dist::ReadExResp 116679 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285395 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115793 # Transaction distribution +system.membus.trans_dist::CleanEvict 261400 # Transaction distribution +system.membus.trans_dist::UpgradeReq 150 # Transaction distribution +system.membus.trans_dist::UpgradeResp 150 # Transaction distribution +system.membus.trans_dist::ReadExReq 116683 # Transaction distribution +system.membus.trans_dist::ReadExResp 116683 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285344 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139506 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172672 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139403 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172569 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1297489 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1297386 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44588 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499692 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499884 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33157420 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33157612 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 837762 # Request fanout histogram +system.membus.snoop_fanout::samples 837681 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 837762 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 837681 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 837762 # Request fanout histogram -system.membus.reqLayer0.occupancy 30061000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 837681 # Request fanout histogram +system.membus.reqLayer0.occupancy 30116000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1285186893 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1287207146 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2143459620 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2143288852 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69854947 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69814679 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index 14fab3b83..7875c5c7b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1159279 # Simulator instruction rate (inst/s) -host_op_rate 1411237 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22604281025 # Simulator tick rate (ticks/s) -host_mem_usage 628452 # Number of bytes of host memory used -host_seconds 123.16 # Real time elapsed on the host +host_inst_rate 1280554 # Simulator instruction rate (inst/s) +host_op_rate 1558869 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24968967598 # Simulator tick rate (ticks/s) +host_mem_usage 628580 # Number of bytes of host memory used +host_seconds 111.49 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -209,6 +209,8 @@ system.cpu.itb.accesses 147044108 # DT system.cpu.numCycles 5567737188 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed system.cpu.committedInsts 142772879 # Number of instructions committed system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses @@ -266,8 +268,6 @@ system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 177219912 # Class of executed instruction -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed system.cpu.dcache.tags.replacements 819402 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks. @@ -400,6 +400,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 1699214 # number of writebacks +system.cpu.icache.writebacks::total 1699214 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use @@ -433,8 +435,10 @@ system.cpu.l2cache.tags.data_accesses 40582495 # Nu system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 682040 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 682040 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 682040 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 682040 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1667206 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 151146 # number of ReadExReq hits @@ -479,8 +483,10 @@ system.cpu.l2cache.overall_misses::total 181651 # nu system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 11231 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 682040 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 682040 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 682040 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 682040 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) @@ -545,8 +551,9 @@ system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1797302 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 682040 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 130096 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution @@ -559,11 +566,11 @@ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 311939813 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 182974 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram @@ -683,7 +690,7 @@ system.membus.trans_dist::ReadReq 40087 # Tr system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::Writeback 138139 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution system.membus.trans_dist::CleanEvict 7977 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 6c9ee9f79..4554ab525 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,70 +4,66 @@ sim_seconds 2.802895 # Nu sim_ticks 2802894699500 # Number of ticks simulated final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1151168 # Simulator instruction rate (inst/s) -host_op_rate 1402682 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21975358508 # Simulator tick rate (ticks/s) -host_mem_usage 637292 # Number of bytes of host memory used -host_seconds 127.55 # Real time elapsed on the host +host_inst_rate 1249421 # Simulator instruction rate (inst/s) +host_op_rate 1522401 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23850961642 # Simulator tick rate (ticks/s) +host_mem_usage 637428 # Number of bytes of host memory used +host_seconds 117.52 # Real time elapsed on the host sim_insts 146828240 # Number of instructions simulated sim_ops 178908039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1095972 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9418276 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 148052 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1084052 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1108644 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9410404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 153876 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1082576 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11747952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1095972 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 148052 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1244024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8467328 # Number of bytes written to this memory +system.physmem.bytes_read::total 11757100 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1108644 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 153876 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1262520 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8452288 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8484892 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8469852 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25578 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 147680 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2468 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25776 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 147557 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2559 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16935 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 192710 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 132302 # Number of write requests responded to by this memory +system.physmem.num_reads::total 192852 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 132067 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136693 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 136458 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 391014 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3360196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 386762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 395535 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3357388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 386235 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4191364 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 391014 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52821 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3020923 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4194628 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 395535 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54899 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 450434 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3015557 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3027189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3020923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3021823 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3015557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 391014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3366448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52821 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 386776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 395535 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3363640 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 386249 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7218553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7216451 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -232,6 +228,8 @@ system.cpu0.itb.accesses 97442689 # DT system.cpu0.numCycles 5605791368 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed system.cpu0.committedInsts 95426926 # Number of instructions committed system.cpu0.committedOps 115560427 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 100762696 # Number of integer alu accesses @@ -289,8 +287,6 @@ system.cpu0.op_class::MemWrite 17276500 14.78% 100.00% # Cl system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 116882065 # Class of executed instruction -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed system.cpu0.dcache.tags.replacements 693486 # number of replacements system.cpu0.dcache.tags.tagsinuse 494.853665 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 35932410 # Total number of references to valid blocks. @@ -309,32 +305,32 @@ system.cpu0.dcache.tags.tag_accesses 74113887 # Nu system.cpu0.dcache.tags.data_accesses 74113887 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 19108541 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 19108541 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15690436 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15690436 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15690389 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15690389 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363043 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363043 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34798977 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34798977 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35145070 # number of overall hits -system.cpu0.dcache.overall_hits::total 35145070 # number of overall hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363050 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363050 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34798930 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34798930 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35145023 # number of overall hits +system.cpu0.dcache.overall_hits::total 35145023 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 373103 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 373103 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295749 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295749 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295796 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295796 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18442 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18442 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 668852 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 668852 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 769173 # number of overall misses -system.cpu0.dcache.overall_misses::total 769173 # number of overall misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18435 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18435 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 668899 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses +system.cpu0.dcache.overall_misses::total 769220 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481644 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 19481644 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986185 # number of WriteReq accesses(hits+misses) @@ -351,18 +347,18 @@ system.cpu0.dcache.overall_accesses::cpu0.data 35914243 system.cpu0.dcache.overall_accesses::total 35914243 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019152 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018500 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018500 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048343 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048343 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048324 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048324 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.021418 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -371,8 +367,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 511149 # number of writebacks -system.cpu0.dcache.writebacks::total 511149 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 693486 # number of writebacks +system.cpu0.dcache.writebacks::total 693486 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1109735 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use @@ -422,6 +418,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.writebacks::writebacks 1109735 # number of writebacks +system.cpu0.icache.writebacks::total 1109735 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified @@ -429,131 +427,128 @@ system.cpu0.l2cache.prefetcher.pfBufferHit 0 # system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 252605 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16140.025703 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3066089 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 268799 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 11.406624 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 1764261500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 8106.193746 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.314062 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.090207 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4734.889291 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3298.538396 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.494763 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000019 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.288995 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201327 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.985109 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16181 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.replacements 249527 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16129.991654 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2731505 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 265646 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 10.282500 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 16127.358870 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.556147 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.076637 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.984336 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000156 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.984497 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16112 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5523 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7582 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2694 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 59674327 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 59674327 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7815 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3333 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 11148 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 511149 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 511149 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94430 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 94430 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1065344 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1065344 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 351762 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 351762 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7815 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3333 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1065344 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 446192 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1522684 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7815 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3333 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1065344 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 446192 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1522684 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 232 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 124 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 356 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26210 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26210 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18442 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18442 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175093 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 175093 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 44912 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 44912 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 128404 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 128404 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 232 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 124 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 44912 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 303497 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 348765 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 232 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 124 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 44912 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 303497 # number of overall misses -system.cpu0.l2cache.overall_misses::total 348765 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 8047 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3457 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 11504 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 511149 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 511149 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26226 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26226 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18442 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 18442 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5452 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7536 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2638 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983398 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 59699237 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 59699237 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10182 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4496 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 14678 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 510201 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 510201 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1265145 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1265145 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94344 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 94344 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1068613 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1068613 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352244 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 352244 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10182 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4496 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1068613 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 446588 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1529879 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10182 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4496 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1068613 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 446588 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1529879 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 214 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 130 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 344 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26273 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26273 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18435 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18435 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175179 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 175179 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41643 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 41643 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127922 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 127922 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 214 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 130 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 41643 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 303101 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 345088 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 214 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 130 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 41643 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 303101 # number of overall misses +system.cpu0.l2cache.overall_misses::total 345088 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10396 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4626 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 15022 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510201 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 510201 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 1265145 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 1265145 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26273 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26273 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18435 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 18435 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269523 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 269523 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110256 # number of ReadCleanReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::total 1110256 # number of ReadCleanReq accesses(hits+misses) system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480166 # number of ReadSharedReq accesses(hits+misses) system.cpu0.l2cache.ReadSharedReq_accesses::total 480166 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 8047 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3457 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10396 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4626 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.inst 1110256 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.data 749689 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1871449 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 8047 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3457 # number of overall (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1874967 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10396 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4626 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.inst 1110256 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.data 749689 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1871449 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.028831 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035869 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.030946 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999390 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999390 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.overall_accesses::total 1874967 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.028102 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.022900 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649640 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.649640 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040452 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040452 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.267416 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.267416 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.028831 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035869 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040452 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404831 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.186361 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.028831 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035869 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040452 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404831 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.186361 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649959 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.649959 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037508 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037508 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266412 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266412 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.028102 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037508 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404302 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.184050 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.028102 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037508 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404302 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.184050 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -562,50 +557,50 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 192992 # number of writebacks -system.cpu0.l2cache.writebacks::total 192992 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 192911 # number of writebacks +system.cpu0.l2cache.writebacks::total 192911 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 3720205 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860284 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_requests 3720245 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860324 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 118049 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 117943 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 106 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 218142 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215248 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2894 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.trans_dist::ReadReq 61416 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 1651838 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 511149 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1264197 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26226 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18442 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44668 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 510201 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1265145 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26273 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18435 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44708 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110256 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480166 # Transaction distribution system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3327246 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2395204 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2395284 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5764086 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092472 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80884164 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5764166 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 140768632 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92116612 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 152059908 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 522626 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4217611 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.044172 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.205599 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 232968516 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 623122 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4318148 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.066969 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.252635 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 4031417 95.59% 95.59% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 186088 4.41% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 106 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 4031861 93.37% 93.37% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 283393 6.56% 99.93% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 2894 0.07% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4217611 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 4318148 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -745,6 +740,8 @@ system.cpu1.itb.accesses 53673309 # DT system.cpu1.numCycles 5605320274 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed system.cpu1.committedInsts 51401314 # Number of instructions committed system.cpu1.committedOps 63347612 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 56984241 # Number of integer alu accesses @@ -802,8 +799,6 @@ system.cpu1.op_class::MemWrite 7736844 11.82% 100.00% # Cl system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 65459464 # Class of executed instruction -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed system.cpu1.dcache.tags.replacements 191938 # number of replacements system.cpu1.dcache.tags.tagsinuse 472.735415 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 19503509 # Total number of references to valid blocks. @@ -821,32 +816,32 @@ system.cpu1.dcache.tags.tag_accesses 39751979 # Nu system.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7397498 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7397498 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7397500 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7397500 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72436 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 72436 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19256192 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19256192 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19306291 # number of overall hits -system.cpu1.dcache.overall_hits::total 19306291 # number of overall hits +system.cpu1.dcache.demand_hits::cpu1.data 19256194 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19256194 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19306293 # number of overall hits +system.cpu1.dcache.overall_hits::total 19306293 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92464 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92464 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92462 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92462 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22543 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 22543 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229094 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229094 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259813 # number of overall misses -system.cpu1.dcache.overall_misses::total 259813 # number of overall misses +system.cpu1.dcache.demand_misses::cpu1.data 229092 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229092 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259811 # number of overall misses +system.cpu1.dcache.overall_misses::total 259811 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses) @@ -883,8 +878,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 120812 # number of writebacks -system.cpu1.dcache.writebacks::total 120812 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 191938 # number of writebacks +system.cpu1.dcache.writebacks::total 191938 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 523373 # number of replacements system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use @@ -933,6 +928,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.writebacks::writebacks 523373 # number of writebacks +system.cpu1.icache.writebacks::total 523373 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified @@ -940,88 +937,86 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 # system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 48465 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15315.522353 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1296358 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 63323 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 20.472151 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 47555 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15235.297156 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1184961 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 62593 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 18.931206 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8309.782152 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.119682 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.019591 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3270.237857 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3730.363071 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.507189 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000190 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 15230.950549 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.335617 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.010990 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.929623 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000143 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199599 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.227683 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.934785 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.929889 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14839 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15019 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 554 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9338 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4947 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 530 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9526 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4963 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.905701 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 24545002 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 24545002 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3108 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1684 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 4792 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 120812 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 120812 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19803 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 19803 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510140 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 510140 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99386 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 99386 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3108 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1684 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 510140 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 119189 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 634121 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3108 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1684 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 510140 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 119189 # number of overall hits -system.cpu1.l2cache.overall_hits::total 634121 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 340 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 270 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 610 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28840 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28840 # number of UpgradeReq misses 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# number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 118856 # number of overall hits +system.cpu1.l2cache.overall_hits::total 634736 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 336 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 271 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 607 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28846 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28846 # number of UpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22543 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::total 22543 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43813 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 43813 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13745 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 13745 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73281 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 73281 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 340 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 270 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13745 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 117094 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 131449 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 340 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 270 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 13745 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 117094 # number of overall misses -system.cpu1.l2cache.overall_misses::total 131449 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3448 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1954 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 5402 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 120812 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 120812 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28848 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 28848 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43853 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 43853 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13539 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 13539 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73574 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 73574 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 336 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 271 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13539 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 117427 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 131573 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 336 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 271 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13539 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 117427 # number of overall misses +system.cpu1.l2cache.overall_misses::total 131573 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3957 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2184 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 121109 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 121109 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 583044 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 583044 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28846 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28846 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22543 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::total 22543 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses) @@ -1030,39 +1025,39 @@ system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523885 system.cpu1.l2cache.ReadCleanReq_accesses::total 523885 # number of ReadCleanReq accesses(hits+misses) system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172667 # number of ReadSharedReq accesses(hits+misses) system.cpu1.l2cache.ReadSharedReq_accesses::total 172667 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3448 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1954 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3957 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2184 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 523885 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.data 236283 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 765570 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3448 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1954 # number of overall (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 766309 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3957 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2184 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 765570 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.098608 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138178 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.112921 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.overall_accesses::total 766309 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.124084 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.098844 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688710 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688710 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026237 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026237 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.424407 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.424407 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.098608 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138178 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026237 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495567 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.171701 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.098608 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138178 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026237 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495567 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.171701 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689339 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689339 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025843 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025843 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.426103 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.426103 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.124084 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025843 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496976 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.171697 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.124084 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025843 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496976 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.171697 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1071,50 +1066,50 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 32915 # number of writebacks -system.cpu1.l2cache.writebacks::total 32915 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 32818 # number of writebacks +system.cpu1.l2cache.writebacks::total 32818 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 1533423 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773258 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_requests 1533421 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773256 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 88765 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 88649 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 116 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 165978 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164041 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1937 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 120812 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 583341 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 28848 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 121109 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 583044 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 28846 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22543 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51391 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51389 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523885 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172667 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1562572 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 776513 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 776509 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2357779 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22873262 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2357775 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66454020 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27282414 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 56439998 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 273409 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1745865 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.067447 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.251059 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 93773822 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 347349 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1819817 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.108136 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.313960 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1628228 93.26% 93.26% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 117521 6.73% 99.99% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 116 0.01% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1624967 89.29% 89.29% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 192913 10.60% 99.89% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1937 0.11% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1745865 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1819817 # Request fanout histogram system.iobus.trans_dist::ReadReq 30995 # Transaction distribution system.iobus.trans_dist::ReadResp 30995 # Transaction distribution system.iobus.trans_dist::WriteReq 59419 # Transaction distribution @@ -1218,183 +1213,175 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 106968 # number of replacements -system.l2c.tags.tagsinuse 62096.352232 # Cycle average of tags in use -system.l2c.tags.total_refs 248810 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 167499 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.485442 # Average number of references to valid blocks. +system.l2c.tags.replacements 107037 # number of replacements +system.l2c.tags.tagsinuse 62176.956554 # Cycle average of tags in use +system.l2c.tags.total_refs 241620 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 167464 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.442818 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 47767.595021 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.035923 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030795 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7914.071704 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4068.609194 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.861600 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1612.456889 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 728.691105 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.728876 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000062 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 47954.224141 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010653 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030815 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7778.474758 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4056.241083 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1664.556464 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 718.418639 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.731723 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000076 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.120759 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.062082 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.024604 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011119 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.947515 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60524 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1892 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13030 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45506 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.923523 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5237373 # Number of tag accesses -system.l2c.tags.data_accesses 5237373 # Number of data accesses -system.l2c.Writeback_hits::writebacks 225907 # number of Writeback hits -system.l2c.Writeback_hits::total 225907 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 289 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 71 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 360 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 59 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 8 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 14099 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 3087 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 17186 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 93 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 64 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 28346 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 76399 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 42 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 35 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 11438 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11382 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 127799 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 93 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 64 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 28346 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 90498 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11438 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14469 # number of demand (read+write) hits -system.l2c.demand_hits::total 144985 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 93 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 64 # number of overall hits -system.l2c.overall_hits::cpu0.inst 28346 # number of overall hits -system.l2c.overall_hits::cpu0.data 90498 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11438 # number of overall hits -system.l2c.overall_hits::cpu1.data 14469 # number of overall hits -system.l2c.overall_hits::total 144985 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9985 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3298 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13283 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 759 # number of SCUpgradeReq misses +system.l2c.tags.occ_percent::cpu0.inst 0.118690 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.061893 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.025399 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010962 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.948745 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 60421 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1839 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 13234 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 45269 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.921951 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5183068 # Number of tag accesses +system.l2c.tags.data_accesses 5183068 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 225729 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 225729 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 511 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 64 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 575 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 65 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 7 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 13894 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 3132 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 17026 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 74 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 68 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 24882 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 76059 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 36 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 27 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 11145 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11759 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 124050 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 74 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 24882 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 89953 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 36 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 27 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 11145 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 14891 # number of demand (read+write) hits +system.l2c.demand_hits::total 141076 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 74 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 68 # number of overall hits +system.l2c.overall_hits::cpu0.inst 24882 # number of overall hits +system.l2c.overall_hits::cpu0.data 89953 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 36 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 27 # number of overall hits +system.l2c.overall_hits::cpu1.inst 11145 # number of overall hits +system.l2c.overall_hits::cpu1.data 14891 # number of overall hits +system.l2c.overall_hits::total 141076 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 10043 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3295 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13338 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 754 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1178 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1937 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 136565 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15836 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 152401 # number 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accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128174 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.167601 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.090967 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.196465 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.030303 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.368812 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.620227 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.167601 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.539849 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.558824 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.030303 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.368812 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.620227 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.167601 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.539849 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.558824 # miss rate for overall accesses +system.l2c.ReadExReq_accesses::cpu0.data 150419 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 18969 # number of ReadExReq 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accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 82 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 70 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 41643 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 237651 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 36 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 27 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 13539 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 31854 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 324902 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 82 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 70 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 41643 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 237651 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 36 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 27 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13539 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 31854 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 324902 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951582 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980947 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.958672 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.920635 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.994093 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.964072 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.907631 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.834889 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.899485 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.028571 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.402493 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128084 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176823 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.087388 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.202323 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.028571 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.402493 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.621491 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.176823 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.532523 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.565789 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.028571 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.402493 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.621491 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.176823 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.532523 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.565789 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1403,51 +1390,51 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 96112 # number of writebacks -system.l2c.writebacks::total 96112 # number of writebacks +system.l2c.writebacks::writebacks 95877 # number of writebacks +system.l2c.writebacks::total 95877 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 43997 # Transaction distribution -system.membus.trans_dist::ReadResp 75496 # Transaction distribution +system.membus.trans_dist::ReadReq 43996 # Transaction distribution +system.membus.trans_dist::ReadResp 75712 # Transaction distribution system.membus.trans_dist::WriteReq 30846 # Transaction distribution system.membus.trans_dist::WriteResp 30846 # Transaction distribution -system.membus.trans_dist::Writeback 132302 # Transaction distribution -system.membus.trans_dist::CleanEvict 8413 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60363 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40918 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15656 # Transaction distribution -system.membus.trans_dist::ReadExReq 196047 # Transaction distribution -system.membus.trans_dist::ReadExResp 151965 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 31499 # Transaction distribution +system.membus.trans_dist::WritebackDirty 132067 # Transaction distribution +system.membus.trans_dist::CleanEvict 8465 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60519 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40906 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15741 # Transaction distribution +system.membus.trans_dist::ReadExReq 196031 # Transaction distribution +system.membus.trans_dist::ReadExResp 151891 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 31716 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660257 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 781641 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660645 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 782029 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109155 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109155 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 890796 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 891184 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17933452 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18123234 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17927560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18117342 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20455522 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20449630 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 580848 # Request fanout histogram +system.membus.snoop_fanout::samples 581009 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 580848 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 581009 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 580848 # Request fanout histogram +system.membus.snoop_fanout::total 581009 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1489,41 +1476,41 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 874927 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 450220 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 131568 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 9077 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 8809 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 268 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 863003 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 444472 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 128485 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 9552 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 9071 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 481 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 305308 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 301629 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 225907 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 41761 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60287 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40985 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101272 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 213669 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 213669 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 261308 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1153838 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 416020 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1569858 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34685372 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10417714 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45103086 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 180140 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1129657 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.285654 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.452250 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 225729 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 38612 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60623 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40978 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101601 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 213528 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 213528 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 257629 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1143706 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 415843 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1559549 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34428348 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10418866 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 44847214 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 180208 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1117804 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.282168 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.451010 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 807234 71.46% 71.46% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 322155 28.52% 99.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 268 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 802876 71.83% 71.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 314447 28.13% 99.96% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 481 0.04% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1129657 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 1117804 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 8e10ef807..deec780f5 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1171566 # Simulator instruction rate (inst/s) -host_op_rate 1426194 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22843865684 # Simulator tick rate (ticks/s) -host_mem_usage 624228 # Number of bytes of host memory used -host_seconds 121.87 # Real time elapsed on the host +host_inst_rate 1269873 # Simulator instruction rate (inst/s) +host_op_rate 1545867 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24760705808 # Simulator tick rate (ticks/s) +host_mem_usage 624348 # Number of bytes of host memory used +host_seconds 112.43 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -209,6 +209,8 @@ system.cpu.itb.accesses 147044108 # DT system.cpu.numCycles 5567737188 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed system.cpu.committedInsts 142772879 # Number of instructions committed system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses @@ -266,8 +268,6 @@ system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 177219912 # Class of executed instruction -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed system.cpu.dcache.tags.replacements 819402 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks. @@ -400,6 +400,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 1699214 # number of writebacks +system.cpu.icache.writebacks::total 1699214 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use @@ -433,8 +435,10 @@ system.cpu.l2cache.tags.data_accesses 40582495 # Nu system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 682040 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 682040 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 682040 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 682040 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1667206 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 151146 # number of ReadExReq hits @@ -479,8 +483,10 @@ system.cpu.l2cache.overall_misses::total 181651 # nu system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 11231 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 682040 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 682040 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 682040 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 682040 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) @@ -545,8 +551,9 @@ system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1797302 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 682040 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 130096 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution @@ -559,11 +566,11 @@ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 311939813 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 182974 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram @@ -683,7 +690,7 @@ system.membus.trans_dist::ReadReq 40087 # Tr system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::Writeback 138139 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution system.membus.trans_dist::CleanEvict 7977 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 719058a40..29fa724c5 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,156 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.871120 # Number of seconds simulated -sim_ticks 2871119862000 # Number of ticks simulated -final_tick 2871119862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.871820 # Number of seconds simulated +sim_ticks 2871819744000 # Number of ticks simulated +final_tick 2871819744000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 654504 # Simulator instruction rate (inst/s) -host_op_rate 791691 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14285860596 # Simulator tick rate (ticks/s) -host_mem_usage 653456 # Number of bytes of host memory used -host_seconds 200.98 # Real time elapsed on the host -sim_insts 131539806 # Number of instructions simulated -sim_ops 159111212 # Number of ops (including micro ops) simulated +host_inst_rate 897166 # Simulator instruction rate (inst/s) +host_op_rate 1085198 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19602639675 # Simulator tick rate (ticks/s) +host_mem_usage 617092 # Number of bytes of host memory used +host_seconds 146.50 # Real time elapsed on the host +sim_insts 131436334 # Number of instructions simulated +sim_ops 158983282 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1136484 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1250788 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8185344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 157844 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 581136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 673536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1155428 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1268388 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8606976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 151764 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 551380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 345088 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11986604 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1136484 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 157844 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1294328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8637696 # Number of bytes written to this memory +system.physmem.bytes_read::total 12080624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1155428 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 151764 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1307192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8516928 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8655260 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8534492 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26211 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20063 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 127896 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2621 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9100 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 10524 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26507 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134484 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2526 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8636 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5392 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 196438 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 134964 # Number of write requests responded to by this memory +system.physmem.num_reads::total 197908 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 133077 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 139355 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 137468 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 395833 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 435645 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2850924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 54976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 202407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 234590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 402333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 441667 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2997046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52846 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 191997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 120164 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4174888 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 395833 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 54976 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 450809 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3008476 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6104 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4206609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 402333 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52846 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 455179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2965690 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6102 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3014594 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3008476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2971806 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2965690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 395833 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 441748 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2850924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 54976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 202421 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 234590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 402333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 447769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2997046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 192011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 120164 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7189482 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 196438 # Number of read requests accepted -system.physmem.writeReqs 139355 # Number of write requests accepted -system.physmem.readBursts 196438 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 139355 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12561984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue -system.physmem.bytesWritten 8668288 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11986604 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8655260 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 49183 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11406 # Per bank write bursts -system.physmem.perBankRdBursts::1 11655 # Per bank write bursts -system.physmem.perBankRdBursts::2 11752 # Per bank write bursts -system.physmem.perBankRdBursts::3 11575 # Per bank write bursts -system.physmem.perBankRdBursts::4 20585 # Per bank write bursts -system.physmem.perBankRdBursts::5 12467 # Per bank write bursts -system.physmem.perBankRdBursts::6 12095 # Per bank write bursts -system.physmem.perBankRdBursts::7 12222 # Per bank write bursts -system.physmem.perBankRdBursts::8 12044 # Per bank write bursts -system.physmem.perBankRdBursts::9 12120 # Per bank write bursts -system.physmem.perBankRdBursts::10 11627 # Per bank write bursts -system.physmem.perBankRdBursts::11 11103 # Per bank write bursts -system.physmem.perBankRdBursts::12 11588 # Per bank write bursts -system.physmem.perBankRdBursts::13 11719 # Per bank write bursts -system.physmem.perBankRdBursts::14 10853 # Per bank write bursts -system.physmem.perBankRdBursts::15 11470 # Per bank write bursts -system.physmem.perBankWrBursts::0 8250 # Per bank write bursts -system.physmem.perBankWrBursts::1 8603 # Per bank write bursts -system.physmem.perBankWrBursts::2 8782 # Per bank write bursts -system.physmem.perBankWrBursts::3 8359 # Per bank write bursts -system.physmem.perBankWrBursts::4 8401 # Per bank write bursts -system.physmem.perBankWrBursts::5 9093 # Per bank write bursts -system.physmem.perBankWrBursts::6 8866 # Per bank write bursts -system.physmem.perBankWrBursts::7 8828 # Per bank write bursts -system.physmem.perBankWrBursts::8 8708 # Per bank write bursts -system.physmem.perBankWrBursts::9 8716 # Per bank write bursts -system.physmem.perBankWrBursts::10 8411 # Per bank write bursts -system.physmem.perBankWrBursts::11 8212 # Per bank write bursts -system.physmem.perBankWrBursts::12 8400 # Per bank write bursts -system.physmem.perBankWrBursts::13 8108 # Per bank write bursts -system.physmem.perBankWrBursts::14 7766 # Per bank write bursts -system.physmem.perBankWrBursts::15 7939 # Per bank write bursts +system.physmem.bw_total::total 7178416 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 197908 # Number of read requests accepted +system.physmem.writeReqs 137468 # Number of write requests accepted +system.physmem.readBursts 197908 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 137468 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12655744 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10368 # Total number of bytes read from write queue +system.physmem.bytesWritten 8547392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12080624 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8534492 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 162 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 64406 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11744 # Per bank write bursts +system.physmem.perBankRdBursts::1 11857 # Per bank write bursts +system.physmem.perBankRdBursts::2 11924 # Per bank write bursts +system.physmem.perBankRdBursts::3 11590 # Per bank write bursts +system.physmem.perBankRdBursts::4 20227 # Per bank write bursts +system.physmem.perBankRdBursts::5 11881 # Per bank write bursts +system.physmem.perBankRdBursts::6 12481 # Per bank write bursts +system.physmem.perBankRdBursts::7 12857 # Per bank write bursts +system.physmem.perBankRdBursts::8 12335 # Per bank write bursts +system.physmem.perBankRdBursts::9 12711 # Per bank write bursts +system.physmem.perBankRdBursts::10 11891 # Per bank write bursts +system.physmem.perBankRdBursts::11 11251 # Per bank write bursts +system.physmem.perBankRdBursts::12 11484 # Per bank write bursts +system.physmem.perBankRdBursts::13 11698 # Per bank write bursts +system.physmem.perBankRdBursts::14 10879 # Per bank write bursts +system.physmem.perBankRdBursts::15 10936 # Per bank write bursts +system.physmem.perBankWrBursts::0 8367 # Per bank write bursts +system.physmem.perBankWrBursts::1 8665 # Per bank write bursts +system.physmem.perBankWrBursts::2 8799 # Per bank write bursts +system.physmem.perBankWrBursts::3 8189 # Per bank write bursts +system.physmem.perBankWrBursts::4 7964 # Per bank write bursts +system.physmem.perBankWrBursts::5 8309 # Per bank write bursts +system.physmem.perBankWrBursts::6 8959 # Per bank write bursts +system.physmem.perBankWrBursts::7 8936 # Per bank write bursts +system.physmem.perBankWrBursts::8 8719 # Per bank write bursts +system.physmem.perBankWrBursts::9 9048 # Per bank write bursts +system.physmem.perBankWrBursts::10 8437 # Per bank write bursts +system.physmem.perBankWrBursts::11 8181 # Per bank write bursts +system.physmem.perBankWrBursts::12 8223 # Per bank write bursts +system.physmem.perBankWrBursts::13 7876 # Per bank write bursts +system.physmem.perBankWrBursts::14 7572 # Per bank write bursts +system.physmem.perBankWrBursts::15 7309 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 25 # Number of times write queue was full causing retry -system.physmem.totGap 2871119474000 # Total gap between requests +system.physmem.numWrRetry 22 # Number of times write queue was full causing retry +system.physmem.totGap 2871819304000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 9731 # Read request sizes (log2) +system.physmem.readPktSize::2 9732 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 186679 # Read request sizes (log2) +system.physmem.readPktSize::6 188148 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 134964 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 137894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15510 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10092 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8580 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6925 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4544 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3804 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 133077 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 139055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -180,161 +184,163 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8728 # What write queue length does an incoming req see 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length does an incoming req see +system.physmem.wrQLenPdf::36 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 68 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 87652 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 242.210195 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 137.335340 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.154059 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46068 52.56% 52.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17715 20.21% 72.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6262 7.14% 79.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3427 3.91% 83.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2480 2.83% 86.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1647 1.88% 88.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 825 0.94% 89.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 930 1.06% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8298 9.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 87652 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6626 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.622698 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 552.814463 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6624 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::54 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 79 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 87485 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 242.362371 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 136.946957 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 304.393854 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46305 52.93% 52.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17523 20.03% 72.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6069 6.94% 79.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3389 3.87% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2483 2.84% 86.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1521 1.74% 88.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 858 0.98% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 952 1.09% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8385 9.58% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 87485 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6517 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.342949 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 586.244331 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6515 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6626 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6626 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.440990 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.878741 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.359150 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5426 81.89% 81.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 462 6.97% 88.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 72 1.09% 89.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 157 2.37% 92.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 32 0.48% 92.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 137 2.07% 94.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 41 0.62% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 17 0.26% 95.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 26 0.39% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 21 0.32% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.12% 96.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.06% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 152 2.29% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.08% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.05% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 25 0.38% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.06% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.05% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.20% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6626 # Writes before turning the bus around for reads -system.physmem.totQLat 4505900396 # Total ticks spent queuing -system.physmem.totMemAccLat 8186169146 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 981405000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22956.38 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6517 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6517 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.493018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.920871 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.293044 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5326 81.72% 81.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 466 7.15% 88.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 68 1.04% 89.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 161 2.47% 92.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 25 0.38% 92.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 129 1.98% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 31 0.48% 95.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 20 0.31% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 32 0.49% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.28% 96.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 9 0.14% 96.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.11% 96.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 150 2.30% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.09% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 7 0.11% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 24 0.37% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 5 0.08% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.06% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.05% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.05% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.05% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 9 0.14% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6517 # Writes before turning the bus around for reads +system.physmem.totQLat 4471540489 # Total ticks spent queuing +system.physmem.totMemAccLat 8179277989 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 988730000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22612.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41706.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.17 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41362.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.21 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.23 # Average write queue length when enqueuing -system.physmem.readRowHits 163849 # Number of row buffer hits during reads -system.physmem.writeRowHits 80221 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.22 # Row buffer hit rate for writes -system.physmem.avgGap 8550266.01 # Average gap between requests -system.physmem.pageHitRate 73.57 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 338884560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 184907250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 809296800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 448299360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187527431520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 85706052435 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647489846750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1922504718675 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.601510 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2740606830696 # Time in different power states -system.physmem_0.memoryStateTime::REF 95872920000 # Time in different power states +system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.95 # Average write queue length when enqueuing +system.physmem.readRowHits 164996 # Number of row buffer hits during reads +system.physmem.writeRowHits 78817 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.01 # Row buffer hit rate for writes +system.physmem.avgGap 8562983.95 # Average gap between requests +system.physmem.pageHitRate 73.59 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 341636400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 186408750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 815575800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 441858240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187573201920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 85932696690 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647711485250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1923002863050 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.611581 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2740967841659 # Time in different power states +system.physmem_0.memoryStateTime::REF 95896320000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34639965804 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34954258341 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 323764560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 176657250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 721687200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 429364800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187527431520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 84711391605 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1648362356250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1922252653185 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.513716 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2742063716846 # Time in different power states -system.physmem_1.memoryStateTime::REF 95872920000 # Time in different power states +system.physmem_1.actEnergy 319750200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 174466875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 726835200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 423565200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187573201920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85000293540 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648529382750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1922747495685 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.522659 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2742335596201 # Time in different power states +system.physmem_1.memoryStateTime::REF 95896320000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33181034404 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33587665799 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -390,56 +396,57 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 5019 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5019 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1041 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 3978 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 5019 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5019 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5019 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 4056 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 10869.452663 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9826.177645 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7625.006320 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 4042 99.65% 99.65% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 10 0.25% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.07% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 4056 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 8797 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 8797 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1607 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7190 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 8797 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 8797 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 8797 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 7279 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12032.971562 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11059.534367 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6527.254746 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 7242 99.49% 99.49% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 32 0.44% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 7279 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 1809726500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 1809726500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 1809726500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3032 74.75% 74.75% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1024 25.25% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4056 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5019 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5719 78.57% 78.57% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1560 21.43% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 7279 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8797 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5019 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4056 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8797 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7279 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4056 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 9075 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7279 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 16076 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 23515104 # DTB read hits -system.cpu0.dtb.read_misses 4346 # DTB read misses -system.cpu0.dtb.write_hits 17278792 # DTB write hits -system.cpu0.dtb.write_misses 673 # DTB write misses +system.cpu0.dtb.read_hits 25745693 # DTB read hits +system.cpu0.dtb.read_misses 7581 # DTB read misses +system.cpu0.dtb.write_hits 19246585 # DTB write hits +system.cpu0.dtb.write_misses 1216 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2434 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3751 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1554 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1856 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 187 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 23519450 # DTB read accesses -system.cpu0.dtb.write_accesses 17279465 # DTB write accesses +system.cpu0.dtb.perms_faults 321 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25753274 # DTB read accesses +system.cpu0.dtb.write_accesses 19247801 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 40793896 # DTB hits -system.cpu0.dtb.misses 5019 # DTB misses -system.cpu0.dtb.accesses 40798915 # DTB accesses +system.cpu0.dtb.hits 44992278 # DTB hits +system.cpu0.dtb.misses 8797 # DTB misses +system.cpu0.dtb.accesses 45001075 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -469,38 +476,39 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 2305 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2305 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 237 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2068 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 2305 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2305 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2305 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 1509 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 10774.022531 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 9696.406116 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 7256.111559 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 1436 95.16% 95.16% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 61 4.04% 99.20% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 10 0.66% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.07% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 1509 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 3674 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3674 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 320 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3354 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3674 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3674 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3674 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2576 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12417.119565 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11509.653289 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6255.531301 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 2268 88.04% 88.04% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 277 10.75% 98.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 28 1.09% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2576 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 1809154500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 1809154500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 1809154500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1272 84.29% 84.29% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 237 15.71% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1509 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2256 87.58% 87.58% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 320 12.42% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2576 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2305 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2305 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3674 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3674 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1509 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1509 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 3814 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 111711640 # ITB inst hits -system.cpu0.itb.inst_misses 2305 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2576 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2576 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6250 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 121573780 # ITB inst hits +system.cpu0.itb.inst_misses 3674 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -509,178 +517,179 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1402 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 111713945 # ITB inst accesses -system.cpu0.itb.hits 111711640 # DTB hits -system.cpu0.itb.misses 2305 # DTB misses -system.cpu0.itb.accesses 111713945 # DTB accesses -system.cpu0.numCycles 5741309822 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 121577454 # ITB inst accesses +system.cpu0.itb.hits 121573780 # DTB hits +system.cpu0.itb.misses 3674 # DTB misses +system.cpu0.itb.accesses 121577454 # DTB accesses +system.cpu0.numCycles 5743639488 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 108455216 # Number of instructions committed -system.cpu0.committedOps 130919966 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 115934267 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4495 # Number of float alu accesses -system.cpu0.num_func_calls 12371356 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14793634 # number of instructions that are conditional controls -system.cpu0.num_int_insts 115934267 # number of integer instructions -system.cpu0.num_fp_insts 4495 # number of float instructions -system.cpu0.num_int_register_reads 213655151 # number of times the integer registers were read -system.cpu0.num_int_register_writes 80737315 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3581 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 474775860 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 48809609 # number of times the CC registers were written -system.cpu0.num_mem_refs 41877995 # number of memory refs -system.cpu0.num_load_insts 23749275 # Number of load instructions -system.cpu0.num_store_insts 18128720 # Number of store instructions -system.cpu0.num_idle_cycles 5480212444.901863 # Number of idle cycles -system.cpu0.num_busy_cycles 261097377.098137 # Number of busy cycles -system.cpu0.not_idle_fraction 0.045477 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.954523 # Percentage of idle cycles -system.cpu0.Branches 27818534 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2172 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 92606456 68.80% 68.80% # Class of executed instruction -system.cpu0.op_class::IntMult 105045 0.08% 68.88% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 7793 0.01% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::MemRead 23749275 17.64% 86.53% # Class of executed instruction -system.cpu0.op_class::MemWrite 18128720 13.47% 100.00% # Class of executed instruction +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 1907 # number of quiesce instructions executed +system.cpu0.committedInsts 117757184 # Number of instructions committed +system.cpu0.committedOps 142314769 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 125928094 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 11483 # Number of float alu accesses +system.cpu0.num_func_calls 12772213 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 16007583 # number of instructions that are conditional controls +system.cpu0.num_int_insts 125928094 # number of integer instructions +system.cpu0.num_fp_insts 11483 # number of float instructions +system.cpu0.num_int_register_reads 231704258 # number of times the integer registers were read +system.cpu0.num_int_register_writes 87445622 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 8771 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 2716 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 515435615 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 53492348 # number of times the CC registers were written +system.cpu0.num_mem_refs 46148278 # number of memory refs +system.cpu0.num_load_insts 26004695 # Number of load instructions +system.cpu0.num_store_insts 20143583 # Number of store instructions +system.cpu0.num_idle_cycles 5456012961.442100 # Number of idle cycles +system.cpu0.num_busy_cycles 287626526.557900 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050077 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949923 # Percentage of idle cycles +system.cpu0.Branches 29545337 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2315 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 99836654 68.33% 68.33% # Class of executed instruction +system.cpu0.op_class::IntMult 112117 0.08% 68.41% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8321 0.01% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::MemRead 26004695 17.80% 86.21% # Class of executed instruction +system.cpu0.op_class::MemWrite 20143583 13.79% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 134599461 # Class of executed instruction -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1796 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 588364 # number of replacements -system.cpu0.dcache.tags.tagsinuse 493.639030 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 40011095 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 588715 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 67.963437 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1836356000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.639030 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.964139 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.964139 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.685547 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 82121594 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 82121594 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 22367728 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 22367728 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 16608644 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16608644 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 300494 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 300494 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 340955 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 340955 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 337105 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 337105 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 38976372 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 38976372 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 39276866 # number of overall hits -system.cpu0.dcache.overall_hits::total 39276866 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 340778 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 340778 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 289444 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 289444 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 113643 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 113643 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20322 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20322 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19364 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19364 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 630222 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 630222 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 743865 # number of overall misses -system.cpu0.dcache.overall_misses::total 743865 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4892226500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4892226500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5708519500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5708519500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 329935000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 329935000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 454112500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 454112500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1575000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1575000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 10600746000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 10600746000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 10600746000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 10600746000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 22708506 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 22708506 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16898088 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16898088 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 414137 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 414137 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 361277 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 361277 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 356469 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 356469 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 39606594 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 39606594 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 40020731 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 40020731 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015007 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.015007 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017129 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017129 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.274409 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.274409 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056250 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056250 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054322 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054322 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015912 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.015912 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018587 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.018587 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14356.051447 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14356.051447 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19722.362530 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19722.362530 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16235.360693 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16235.360693 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23451.378847 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23451.378847 # average StoreCondReq miss latency +system.cpu0.op_class::total 146107685 # Class of executed instruction +system.cpu0.dcache.tags.replacements 732170 # number of replacements +system.cpu0.dcache.tags.tagsinuse 488.694805 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 44080957 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 732682 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 60.163832 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1836359000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 488.694805 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.954482 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.954482 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id 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+system.cpu0.dcache.LoadLockedReq_misses::total 22252 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19918 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19918 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 755334 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 755334 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 888490 # number of overall misses +system.cpu0.dcache.overall_misses::total 888490 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5661692500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5661692500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6946372000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6946372000 # number of WriteReq miss cycles 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number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24858317 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24858317 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18830641 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18830641 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 459654 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 459654 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396454 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 396454 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391491 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 391491 # 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16820.653674 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14250.900365 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14250.900365 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16692.038886 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16692.038886 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14190.440523 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14190.440523 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -689,149 +698,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan 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# number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1553984000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101488000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101488000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 434796500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 434796500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1527000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1527000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9567803000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9567803000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11121787000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11121787000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6274722500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6274722500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5086196500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5086196500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11360919000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11360919000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.013895 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013895 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017129 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017129 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.209667 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.209667 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017156 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017156 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054322 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054322 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015275 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015275 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017286 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.017286 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13147.901719 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13147.901719 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18722.378845 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18722.378845 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17896.649814 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17896.649814 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16374.314295 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16374.314295 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22453.857674 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22453.857674 # average StoreCondReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15552 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15552 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25279 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25279 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25279 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25279 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 392795 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 392795 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337260 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 337260 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106103 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 106103 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6700 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6700 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19918 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19918 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 730055 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 730055 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 836158 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 836158 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31819 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31819 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60318 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60318 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4839458000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4839458000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6609064500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6609064500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1736821000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1736821000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104360500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104360500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 487321500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 487321500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1579000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1579000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11448522500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11448522500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13185343500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13185343500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6629856000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6629856000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5400865000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5400865000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12030721000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12030721000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015801 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015801 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017910 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017910 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230832 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.230832 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016900 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016900 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.050877 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.050877 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016710 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016710 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018940 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12320.569254 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12320.569254 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19596.348514 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19596.348514 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16369.197855 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16369.197855 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15576.194030 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15576.194030 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24466.387187 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24466.387187 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15814.890237 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15814.890237 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16076.174659 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16076.174659 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197703.777806 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 197703.777806 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179135.579192 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 179135.579192 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 188936.139429 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 188936.139429 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15681.726034 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15681.726034 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15768.961727 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15768.961727 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208361.544989 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208361.544989 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189510.684585 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189510.684585 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199454.905667 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199454.905667 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 987035 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.323984 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 110724084 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 987547 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 112.120318 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 14346160000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.323984 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998680 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998680 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1146899 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.321434 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 120426360 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1147411 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 104.954859 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 14862010000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321434 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998675 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998675 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 103 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::4 9 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 224410836 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 224410836 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 110724084 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 110724084 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 110724084 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 110724084 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 110724084 # number of overall hits -system.cpu0.icache.overall_hits::total 110724084 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 987556 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 987556 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 987556 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 987556 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 987556 # number of overall misses -system.cpu0.icache.overall_misses::total 987556 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10780435500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10780435500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10780435500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10780435500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10780435500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10780435500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 111711640 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 111711640 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 111711640 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 111711640 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 111711640 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 111711640 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.008840 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.008840 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.008840 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.008840 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.008840 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.008840 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10916.277659 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10916.277659 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10916.277659 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10916.277659 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10916.277659 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10916.277659 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 244294980 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 244294980 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 120426360 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 120426360 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 120426360 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 120426360 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 120426360 # number of overall hits +system.cpu0.icache.overall_hits::total 120426360 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1147420 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1147420 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1147420 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1147420 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1147420 # number of overall misses +system.cpu0.icache.overall_misses::total 1147420 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12257879000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12257879000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12257879000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12257879000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12257879000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12257879000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 121573780 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 121573780 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 121573780 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 121573780 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 121573780 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 121573780 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009438 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009438 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009438 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.009438 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009438 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.009438 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10682.992278 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10682.992278 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10682.992278 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10682.992278 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10682.992278 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10682.992278 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -840,236 +849,238 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 987556 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 987556 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 987556 # number of demand (read+write) MSHR misses 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system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1253876500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.008840 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.008840 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.008840 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.008840 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.008840 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.008840 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10416.277659 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10416.277659 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10416.277659 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10416.277659 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10416.277659 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10416.277659 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009438 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009438 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009438 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009438 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009438 # mshr miss rate for overall accesses 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system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1606259 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1606313 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 46 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1935560 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1935650 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 78 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 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946461 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 946461 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 317431 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 317431 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 5209 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 2366 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 946461 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 514573 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1468609 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 5209 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 2366 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 946461 # number of overall hits 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accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 2583 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 8105 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 443106 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 443106 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 53430 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 53430 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19362 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 19362 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # 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cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10894066500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12080278000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.056682 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.084011 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.065392 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11561891500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12748103000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.016027 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015693 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.015925 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.474752 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.474752 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.921289 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.921289 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158123 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158123 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041613 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041613 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.222954 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.222954 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.056682 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.084011 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041613 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.199216 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.103665 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.056682 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.084011 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041613 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.199216 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.148427 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.148427 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040844 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040844 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.186417 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.186417 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.016027 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015693 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040844 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.172811 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093922 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.016027 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015693 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040844 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.172811 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.244353 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 16343.396226 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83027.252039 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83027.252039 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 31352.992194 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31352.992194 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16210.561722 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16210.561722 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 583500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 583500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 58928.736033 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 58928.736033 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69856.539725 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28234.315480 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28234.315480 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37154.705168 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44993.304398 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37154.705168 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83027.252039 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66891.537242 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229818 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21436.758893 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76826.616510 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 76826.616510 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25907.101794 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25907.101794 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16991.636108 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16991.636108 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 109090.181818 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 109090.181818 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56425.478817 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56425.478817 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 64594.281447 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64594.281447 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28280.131987 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28280.131987 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 64594.281447 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36937.980254 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 43989.729541 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 64594.281447 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36937.980254 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76826.616510 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63406.833032 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189703.746298 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176816.216879 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171635.579192 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 171635.579192 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200348.549609 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185135.084841 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182006.421278 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182006.421278 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181172.215662 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 174689.138577 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191682.275606 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183849.192385 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 3288140 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1656034 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 25235 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 165607 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 165490 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 117 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 54153 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1498300 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28393 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28393 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 629767 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1193646 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 275537 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 87023 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42073 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 110674 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 255600 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 251928 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 987556 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 494836 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3354 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2960662 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2239612 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 6956 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 14519 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5221749 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 63239672 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 73903156 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10332 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22088 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 137175248 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 821565 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4077224 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.054943 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.227994 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 3903345 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1968246 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28892 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 321222 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 317069 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4153 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 63874 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1765403 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28499 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28499 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 733576 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1348863 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 190188 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 312390 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 85764 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42077 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112758 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 84 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 301102 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 297729 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1147420 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 574776 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3316 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3438002 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2673168 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11871 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27031 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6150072 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 145478520 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 101119646 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 19372 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 44176 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 246661714 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 988213 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2981714 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.123543 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.333265 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 3853328 94.51% 94.51% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 223779 5.49% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 117 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2617497 87.78% 87.78% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 360064 12.08% 99.86% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4153 0.14% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4077224 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2138731998 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2981714 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 3884130992 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115020156 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115184885 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1490356000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1730152000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1049276975 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1265237983 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 4373000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7028000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 8998497 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 15993487 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1315,64 +1323,57 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6206 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6206 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1170 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5036 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 6206 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6206 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6206 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5005 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 10147.252747 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9159.943965 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 4842.286315 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-4095 42 0.84% 0.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-8191 2213 44.22% 45.05% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1504 30.05% 75.10% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-16383 1077 21.52% 96.62% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-20479 52 1.04% 97.66% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::20480-24575 27 0.54% 98.20% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-28671 32 0.64% 98.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::28672-32767 42 0.84% 99.68% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-36863 5 0.10% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::36864-40959 7 0.14% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.06% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5005 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1704519828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1704519828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1704519828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3865 77.22% 77.22% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1140 22.78% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5005 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6206 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 2355 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 2355 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 481 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1874 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 2355 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 2355 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 2355 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1709 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11678.466940 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11002.721261 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5695.537695 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 1565 91.57% 91.57% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 135 7.90% 99.47% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-49151 5 0.29% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.18% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1709 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1207257828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1207257828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1207257828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1228 71.85% 71.85% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 481 28.15% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1709 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2355 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6206 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5005 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2355 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1709 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5005 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 11211 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1709 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 4064 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5575996 # DTB read hits -system.cpu1.dtb.read_misses 5233 # DTB read misses -system.cpu1.dtb.write_hits 4889133 # DTB write hits -system.cpu1.dtb.write_misses 973 # DTB write misses +system.cpu1.dtb.read_hits 3323284 # DTB read hits +system.cpu1.dtb.read_misses 1962 # DTB read misses +system.cpu1.dtb.write_hits 2909831 # DTB write hits +system.cpu1.dtb.write_misses 393 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3067 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1652 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 530 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 231 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 258 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5581229 # DTB read accesses -system.cpu1.dtb.write_accesses 4890106 # DTB write accesses +system.cpu1.dtb.perms_faults 124 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3325246 # DTB read accesses +system.cpu1.dtb.write_accesses 2910224 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 10465129 # DTB hits -system.cpu1.dtb.misses 6206 # DTB misses -system.cpu1.dtb.accesses 10471335 # DTB accesses +system.cpu1.dtb.hits 6233115 # DTB hits +system.cpu1.dtb.misses 2355 # DTB misses +system.cpu1.dtb.accesses 6235470 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1402,46 +1403,44 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 2787 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2787 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 249 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2538 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2787 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2787 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2787 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1928 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11234.439834 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 9816.231267 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6428.442620 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 752 39.00% 39.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 479 24.84% 63.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 554 28.73% 92.58% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 71 3.68% 96.27% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.10% 96.37% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 0.78% 97.15% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 0.88% 98.03% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 5 0.26% 98.29% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 26 1.35% 99.64% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.16% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.05% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::53248-57343 2 0.10% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1928 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1705600828 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1705600828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1705600828 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1679 87.09% 87.09% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 249 12.91% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1928 # Table walker page sizes translated +system.cpu1.itb.walker.walks 1376 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1376 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 134 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1242 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1376 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1376 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1376 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 819 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11895.604396 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11259.508648 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5169.477869 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 116 14.16% 14.16% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 583 71.18% 85.35% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 72 8.79% 94.14% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 8 0.98% 95.12% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.12% 95.24% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 22 2.69% 97.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 7 0.85% 98.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 98.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.61% 99.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.12% 99.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 3 0.37% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 819 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1208095828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1208095828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1208095828 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 685 83.64% 83.64% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 134 16.36% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 819 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2787 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2787 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1376 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1376 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1928 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1928 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 4715 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 23850368 # ITB inst hits -system.cpu1.itb.inst_misses 2787 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 819 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 819 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2195 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 13877832 # ITB inst hits +system.cpu1.itb.inst_misses 1376 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1450,179 +1449,178 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1894 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 883 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 23853155 # ITB inst accesses -system.cpu1.itb.hits 23850368 # DTB hits -system.cpu1.itb.misses 2787 # DTB misses -system.cpu1.itb.accesses 23853155 # DTB accesses -system.cpu1.numCycles 5742239724 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 13879208 # ITB inst accesses +system.cpu1.itb.hits 13877832 # DTB hits +system.cpu1.itb.misses 1376 # DTB misses +system.cpu1.itb.accesses 13879208 # DTB accesses +system.cpu1.numCycles 5742698802 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 23084590 # Number of instructions committed -system.cpu1.committedOps 28191246 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 25227117 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6988 # Number of float alu accesses -system.cpu1.num_func_calls 1341368 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2715447 # number of instructions that are conditional controls -system.cpu1.num_int_insts 25227117 # number of integer instructions -system.cpu1.num_fp_insts 6988 # number of float instructions -system.cpu1.num_int_register_reads 45751310 # number of times the integer registers were read -system.cpu1.num_int_register_writes 17465196 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 5190 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1800 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 102291851 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 9890204 # number of times the CC registers were written -system.cpu1.num_mem_refs 10752307 # number of memory refs -system.cpu1.num_load_insts 5706058 # Number of load instructions -system.cpu1.num_store_insts 5046249 # Number of store instructions -system.cpu1.num_idle_cycles 5671495056.418025 # Number of idle cycles -system.cpu1.num_busy_cycles 70744667.581975 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012320 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987680 # Percentage of idle cycles -system.cpu1.Branches 4219564 # Number of branches fetched -system.cpu1.op_class::No_OpClass 167 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 17843088 62.32% 62.32% # Class of executed instruction -system.cpu1.op_class::IntMult 31349 0.11% 62.43% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3702 0.01% 62.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 62.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.44% # Class of executed instruction -system.cpu1.op_class::MemRead 5706058 19.93% 82.37% # Class of executed instruction -system.cpu1.op_class::MemWrite 5046249 17.63% 100.00% # Class of executed instruction +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed +system.cpu1.committedInsts 13679150 # Number of instructions committed +system.cpu1.committedOps 16668513 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 15113644 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu1.num_func_calls 913162 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1492467 # number of instructions that are conditional controls +system.cpu1.num_int_insts 15113644 # number of integer instructions +system.cpu1.num_fp_insts 0 # number of float instructions +system.cpu1.num_int_register_reads 27463830 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10666857 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 61159895 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 5174219 # number of times the CC registers were written +system.cpu1.num_mem_refs 6447631 # number of memory refs +system.cpu1.num_load_insts 3428751 # Number of load instructions +system.cpu1.num_store_insts 3018880 # Number of store instructions +system.cpu1.num_idle_cycles 5696160545.959164 # Number of idle cycles +system.cpu1.num_busy_cycles 46538256.040836 # Number of busy cycles +system.cpu1.not_idle_fraction 0.008104 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.991896 # Percentage of idle cycles +system.cpu1.Branches 2456488 # Number of branches fetched +system.cpu1.op_class::No_OpClass 24 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 10511910 61.88% 61.88% # Class of executed instruction +system.cpu1.op_class::IntMult 24272 0.14% 62.03% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3188 0.02% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::MemRead 3428751 20.18% 82.23% # Class of executed instruction +system.cpu1.op_class::MemWrite 3018880 17.77% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 28630613 # Class of executed instruction -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2852 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 292035 # number of replacements -system.cpu1.dcache.tags.tagsinuse 469.567308 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 10109505 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 292547 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 34.556858 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 105794397000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.567308 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917124 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.917124 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 21253597 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 21253597 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 5149175 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 5149175 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4639914 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4639914 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 67630 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 67630 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 103001 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 103001 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 95778 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 95778 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 9789089 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 9789089 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 9856719 # number of overall hits -system.cpu1.dcache.overall_hits::total 9856719 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 190277 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 190277 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 126690 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 126690 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 44121 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 44121 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18673 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 18673 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23929 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23929 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 316967 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 316967 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 361088 # number of overall misses -system.cpu1.dcache.overall_misses::total 361088 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2557291000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2557291000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3433917500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3433917500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 339355000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 339355000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 630190000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 630190000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5470500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5470500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5991208500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5991208500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5991208500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5991208500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 5339452 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 5339452 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4766604 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4766604 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 111751 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 111751 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 121674 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 121674 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 119707 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 119707 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 10106056 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 10106056 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 10217807 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 10217807 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035636 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035636 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.026579 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.026579 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.394815 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.394815 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.153467 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.153467 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.199896 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.199896 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031364 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031364 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035339 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035339 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13439.832455 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13439.832455 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27104.881995 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 27104.881995 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18173.566111 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18173.566111 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26335.826821 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26335.826821 # average StoreCondReq miss latency +system.cpu1.op_class::total 16987025 # Class of executed instruction +system.cpu1.dcache.tags.replacements 147592 # number of replacements +system.cpu1.dcache.tags.tagsinuse 468.392474 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6004450 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 147942 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 40.586514 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 106294932000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.392474 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.914829 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.914829 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 318 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.683594 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 12646180 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 12646180 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3055213 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3055213 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2743263 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2743263 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41902 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 41902 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69872 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 69872 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61606 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 61606 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 5798476 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 5798476 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 5840378 # number of overall hits +system.cpu1.dcache.overall_hits::total 5840378 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 112221 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 112221 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 79294 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 79294 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24421 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 24421 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16601 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16601 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23085 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23085 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 191515 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 191515 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 215936 # number of overall misses +system.cpu1.dcache.overall_misses::total 215936 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1751790500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1751790500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2724343500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2724343500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320772500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 320772500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 629240500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 629240500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3762500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3762500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4476134000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4476134000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4476134000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4476134000 # number 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18901.679039 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16592.100818 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16592.100818 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23372.237162 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23372.237162 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20728.984514 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20728.984514 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1631,147 +1629,147 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 180790 # number of writebacks -system.cpu1.dcache.writebacks::total 180790 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 404 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 404 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13063 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13063 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 404 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 404 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 404 # number of overall MSHR hits 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-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 606310000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5421500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5421500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5659664500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5659664500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6308471000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6308471000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 420340500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 420340500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 296300500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 296300500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 716641000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 716641000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035560 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035560 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026579 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026579 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.385446 # mshr miss rate for SoftPFReq accesses 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12389.528790 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12389.528790 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26104.881995 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26104.881995 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15062.601569 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15062.601569 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17406.684492 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17406.684492 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25337.874546 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25337.874546 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 147592 # number of writebacks +system.cpu1.dcache.writebacks::total 147592 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 221 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11676 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11676 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 221 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 221 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 221 # number of overall MSHR hits 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demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 191294 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 215244 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 215244 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3081 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3081 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2423 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2423 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5504 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5504 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1626671000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1626671000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2645049500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2645049500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 437326000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 437326000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90573500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90573500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 606189500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 606189500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3728500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3728500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4271720500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4271720500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4709046500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4709046500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 439448500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 439448500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 303112500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 303112500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742561000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742561000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035360 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035360 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028093 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028093 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.361112 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.361112 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056954 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056954 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.272579 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.272579 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031936 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031936 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035540 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035540 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14523.848214 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14523.848214 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33357.498676 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33357.498676 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18259.958246 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18259.958246 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18390.558376 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18390.558376 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26259.021009 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26259.021009 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17878.477586 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17878.477586 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17541.217950 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17541.217950 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 133738.625517 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 133738.625517 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117579.563492 # average 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9177.472926 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9177.472926 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9177.472926 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9177.472926 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9177.472926 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 28219802 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 28219802 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 13413679 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13413679 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13413679 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13413679 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13413679 # number of overall hits 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# number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 463636 # number of writebacks +system.cpu1.icache.writebacks::total 463636 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 464148 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 464148 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 464148 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 464148 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 464148 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 464148 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall 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average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8677.472926 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8677.472926 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8677.472926 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8677.472926 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 135451.977401 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 135451.977401 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 135451.977401 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 135451.977401 # average overall mshr uncacheable latency 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overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8582.058955 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8582.058955 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8582.058955 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 437692 # number of hwpf issued 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SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18756.324727 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 3473500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 3473500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45074.983669 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45074.983669 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54921.222607 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54921.222607 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16536.009279 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16536.009279 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14391.304348 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14001.683502 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54921.222607 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26097.681084 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28399.260892 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14391.304348 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14001.683502 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54921.222607 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26097.681084 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43947.047320 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30968.426593 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134518.662772 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134030.386740 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117594.510937 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117594.510937 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127068.223110 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127020.330928 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 1936586 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 978536 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 13921 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 103851 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 103732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 119 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 19887 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 919525 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2520 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2520 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 223940 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 770866 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 41722 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 69543 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41698 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86819 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 50 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 103431 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 101180 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 622926 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 309787 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 46 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1858177 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1153867 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8365 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 17379 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3037788 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 39867972 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 35780458 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12160 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24548 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 75685138 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 354401 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2220337 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.063895 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.244785 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 1323663 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 668360 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10107 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 169443 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 166760 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2683 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 10105 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 652363 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2423 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2423 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 118404 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 509576 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 86260 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 25020 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 70278 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40907 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 84739 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 84 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 57602 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 55059 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 464148 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 215012 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 32 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1383984 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 718041 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4385 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7029 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2113439 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 58847556 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24276952 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7068 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 83142776 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 355785 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 998697 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.187513 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.397146 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 2078588 93.62% 93.62% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 141630 6.38% 99.99% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 119 0.01% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 814111 81.52% 81.52% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 181903 18.21% 99.73% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 2683 0.27% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2220337 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1156529000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 998697 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1278018500 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80617594 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79432929 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 934566000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 696399000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 534214495 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 317143500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 5325000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 2618000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 11246990 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 4229000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31011 # Transaction distribution -system.iobus.trans_dist::ReadResp 31011 # Transaction distribution -system.iobus.trans_dist::WriteReq 59422 # Transaction distribution -system.iobus.trans_dist::WriteResp 59422 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56596 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 31021 # Transaction distribution +system.iobus.trans_dist::ReadResp 31021 # Transaction distribution +system.iobus.trans_dist::WriteReq 59425 # Transaction distribution +system.iobus.trans_dist::WriteResp 59425 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -2253,11 +2242,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107910 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71540 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180892 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -2278,96 +2267,96 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162790 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321264 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321264 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484054 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40088000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48741500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 32500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 93000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 609500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 23500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6155500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 165000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 32044000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 119500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186504974 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186329030 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 37500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84712000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36780000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36460 # number of replacements -system.iocache.tags.tagsinuse 14.383048 # Cycle average of tags in use +system.iocache.tags.replacements 36461 # number of replacements +system.iocache.tags.tagsinuse 14.380003 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36476 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 290140338000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.383048 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.898940 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.898940 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 290757542000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.380003 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.898750 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.898750 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328302 # Number of tag accesses -system.iocache.tags.data_accesses 328302 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 254 # number of ReadReq misses -system.iocache.ReadReq_misses::total 254 # number of ReadReq misses +system.iocache.tags.tag_accesses 328311 # Number of tag accesses +system.iocache.tags.data_accesses 328311 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses +system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 254 # number of demand (read+write) misses -system.iocache.demand_misses::total 254 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 254 # number of overall misses -system.iocache.overall_misses::total 254 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 33010877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 33010877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4717790097 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4717790097 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 33010877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 33010877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 33010877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 33010877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 254 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 254 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses +system.iocache.demand_misses::total 255 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 255 # number of overall misses +system.iocache.overall_misses::total 255 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 32882376 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32882376 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4738851654 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4738851654 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32882376 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32882376 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32882376 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32882376 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 254 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 254 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 254 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 254 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2376,40 +2365,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129964.082677 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129964.082677 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130239.346759 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130239.346759 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 129964.082677 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 129964.082677 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 129964.082677 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 129964.082677 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128950.494118 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128950.494118 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130820.772250 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130820.772250 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128950.494118 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128950.494118 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128950.494118 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128950.494118 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 99 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 3.571429 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.262626 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 254 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 254 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 254 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 254 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 254 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 254 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 20310877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 20310877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2906590097 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2906590097 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 20310877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 20310877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 20310877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 20310877 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 20132376 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 20132376 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2927651654 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2927651654 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 20132376 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 20132376 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 20132376 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 20132376 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2418,289 +2407,304 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79964.082677 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 79964.082677 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80239.346759 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80239.346759 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 79964.082677 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 79964.082677 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 79964.082677 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 79964.082677 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78950.494118 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 78950.494118 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80820.772250 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80820.772250 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 78950.494118 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 78950.494118 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 78950.494118 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 78950.494118 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 127982 # number of replacements -system.l2c.tags.tagsinuse 63841.400540 # Cycle average of tags in use -system.l2c.tags.total_refs 386797 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 192628 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.008000 # Average number of references to valid blocks. +system.l2c.tags.replacements 123906 # number of replacements +system.l2c.tags.tagsinuse 62994.829806 # Cycle average of tags in use +system.l2c.tags.total_refs 421817 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 187980 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.243946 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12055.995118 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.049810 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.047185 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7486.510812 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2815.662270 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37403.783442 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1406.932882 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 489.801266 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2179.617757 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.183960 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000047 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 13459.681359 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.946988 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.042686 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7381.464495 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2783.395152 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35774.545550 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954481 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1451.828957 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 405.858901 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1734.111238 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.205378 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.114235 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042964 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.570736 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.021468 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.007474 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.033258 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.974142 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31928 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.112632 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.042471 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.545876 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.022153 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.006193 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.026460 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.961225 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 31889 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 32714 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 74 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4325 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 27529 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 32181 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 315 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5132 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 26438 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2359 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 30054 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.487183 # Percentage of cache occupancy per task id +system.l2c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 384 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2392 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 29385 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.486588 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.499176 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5261289 # Number of tag accesses -system.l2c.tags.data_accesses 5261289 # Number of data accesses -system.l2c.Writeback_hits::writebacks 224862 # number of Writeback hits -system.l2c.Writeback_hits::total 224862 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1507 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1131 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2638 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 135 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 177 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 312 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3596 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1989 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5585 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 55 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 33 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 23888 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 41259 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 41598 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 52 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 64 # number of ReadSharedReq hits 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0.078610 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.525937 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.536275 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.098361 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.057143 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.418506 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.305392 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.754803 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.127432 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.396445 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.525937 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.553759 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.098361 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.057143 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.418506 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.305392 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.754803 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.127432 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.396445 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.525937 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.553759 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 76013.832853 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73964.006630 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75238.376780 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77363.529412 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76840.694006 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76971.943296 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135438.267702 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121123.554024 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 129379.232212 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average ReadSharedReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.225495 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.536387 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.253953 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.216624 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.590930 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.382377 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.733622 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.855459 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.779344 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.066667 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.373242 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.158446 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738913 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.043478 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.272318 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.136403 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614893 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.549795 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.066667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.373242 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.281832 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738913 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.043478 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.272318 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.577358 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614893 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.566633 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.066667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.373242 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.281832 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738913 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.043478 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.272318 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.577358 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614893 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.566633 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75375.839642 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75068.282918 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75316.375677 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77319.185059 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76712.999217 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76904.340836 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135426.566550 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120947.932619 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 129462.492772 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 125500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126557.694531 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128658.644401 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133834.881063 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121472.130117 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126214.027354 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124281.872088 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 138253.172589 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133423.918387 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131543.532275 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121962.434383 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 133377.699704 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121472.130117 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131358.315863 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124281.872088 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122529.162801 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 133024.254633 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131543.532275 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121962.434383 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 133377.699704 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121472.130117 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131358.315863 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124281.872088 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122529.162801 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 133024.254633 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171703.525742 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109951.977401 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 107879.738770 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154992.229331 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 154635.508752 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 93079.365079 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 149617.507198 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182348.062478 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116633.690708 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163370.351052 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165006.070388 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100577.177053 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159957.522153 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 163644.251717 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109951.977401 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 101289.008659 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 152776.587233 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174154.332040 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109561.352481 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 161963.602069 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 44076 # Transaction distribution -system.membus.trans_dist::ReadResp 212234 # Transaction distribution -system.membus.trans_dist::WriteReq 30913 # Transaction distribution -system.membus.trans_dist::WriteResp 30913 # Transaction distribution -system.membus.trans_dist::Writeback 134964 # Transaction distribution -system.membus.trans_dist::CleanEvict 15319 # Transaction distribution -system.membus.trans_dist::UpgradeReq 74839 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40260 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12961 # Transaction distribution -system.membus.trans_dist::ReadExReq 39815 # Transaction distribution -system.membus.trans_dist::ReadExResp 19093 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 168158 # Transaction distribution +system.membus.trans_dist::ReadReq 44096 # Transaction distribution +system.membus.trans_dist::ReadResp 213882 # Transaction distribution +system.membus.trans_dist::WriteReq 30922 # Transaction distribution +system.membus.trans_dist::WriteResp 30922 # Transaction distribution +system.membus.trans_dist::WritebackDirty 133077 # Transaction distribution +system.membus.trans_dist::CleanEvict 14603 # Transaction distribution +system.membus.trans_dist::UpgradeReq 73616 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 39905 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13581 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 39514 # Transaction distribution +system.membus.trans_dist::ReadExResp 18935 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 169786 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13734 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664805 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 786483 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108936 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108936 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 895419 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162790 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664049 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 785783 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108937 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108937 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 894720 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27468 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18323720 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18514046 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27532 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18296972 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18487386 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20832190 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123434 # Total snoops (count) -system.membus.snoop_fanout::samples 584834 # Request fanout histogram +system.membus.pkt_size::total 20805530 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 121102 # Total snoops (count) +system.membus.snoop_fanout::samples 582015 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 584834 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 582015 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 584834 # Request fanout histogram -system.membus.reqLayer0.occupancy 88258000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 582015 # Request fanout histogram +system.membus.reqLayer0.occupancy 88274000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11355499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11368000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 974246641 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 966740692 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1126274005 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1134075509 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64655929 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64085297 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -3003,52 +3020,52 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 910965 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 460102 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 151032 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 21991 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 21404 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 587 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 44080 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 476819 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 359850 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 80476 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 77372 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40572 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 117944 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 97 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51046 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51046 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 432754 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 961177 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 518872 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 139554 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 20662 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 19793 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 869 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 44099 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 468456 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30922 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30922 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 390602 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 84323 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 107685 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 42919 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 150604 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 84 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 84 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50476 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50476 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 424372 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1048506 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 332828 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1381334 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 29760096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6517470 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 36277566 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 449108 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1186895 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.300945 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.459746 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1224412 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249093 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1473505 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34296330 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3743120 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 38039450 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 438983 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 897187 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.337621 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.474943 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 830292 69.95% 69.95% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 356016 30.00% 99.95% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 587 0.05% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 595147 66.33% 66.33% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 301171 33.57% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 869 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1186895 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 806375018 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 897187 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 864296758 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 359119 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 360622 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 593704114 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 647366860 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 252660411 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 201908331 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 79e3a7b0a..05fb1382f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.909343 # Number of seconds simulated -sim_ticks 2909343316500 # Number of ticks simulated -final_tick 2909343316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.909604 # Number of seconds simulated +sim_ticks 2909603958500 # Number of ticks simulated +final_tick 2909603958500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 666869 # Simulator instruction rate (inst/s) -host_op_rate 804035 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17251437084 # Simulator tick rate (ticks/s) -host_mem_usage 624248 # Number of bytes of host memory used -host_seconds 168.64 # Real time elapsed on the host -sim_insts 112463069 # Number of instructions simulated -sim_ops 135595282 # Number of ops (including micro ops) simulated +host_inst_rate 894735 # Simulator instruction rate (inst/s) +host_op_rate 1078768 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23149732072 # Simulator tick rate (ticks/s) +host_mem_usage 579968 # Number of bytes of host memory used +host_seconds 125.69 # Real time elapsed on the host +sim_insts 112455934 # Number of instructions simulated +sim_ops 135586369 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1184996 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8901092 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1186596 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8901732 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10087624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1184996 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1184996 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7517376 # Number of bytes written to this memory +system.physmem.bytes_read::total 10089864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1186596 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1186596 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7512000 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7534900 # Number of bytes written to this memory +system.physmem.bytes_written::total 7529524 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26969 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 139599 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26994 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 139609 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166592 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117459 # Number of write requests responded to by this memory +system.physmem.num_reads::total 166627 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117375 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121840 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121756 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 407307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3059485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 407820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3059431 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3467320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 407307 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 407307 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2583874 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3467779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 407820 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407820 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2581795 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6023 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2589897 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2583874 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2587817 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2581795 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 407307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3065508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 407820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3065454 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6057217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166592 # Number of read requests accepted -system.physmem.writeReqs 121840 # Number of write requests accepted -system.physmem.readBursts 166592 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121840 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10654272 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue -system.physmem.bytesWritten 7547776 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10087624 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7534900 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6055597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166627 # Number of read requests accepted +system.physmem.writeReqs 121756 # Number of write requests accepted +system.physmem.readBursts 166627 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121756 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10656896 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue +system.physmem.bytesWritten 7542080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10089864 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7529524 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40724 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10226 # Per bank write bursts -system.physmem.perBankRdBursts::1 9700 # Per bank write bursts -system.physmem.perBankRdBursts::2 10356 # Per bank write bursts -system.physmem.perBankRdBursts::3 10496 # Per bank write bursts -system.physmem.perBankRdBursts::4 18505 # Per bank write bursts -system.physmem.perBankRdBursts::5 10022 # Per bank write bursts -system.physmem.perBankRdBursts::6 10179 # Per bank write bursts -system.physmem.perBankRdBursts::7 10614 # Per bank write bursts -system.physmem.perBankRdBursts::8 9478 # Per bank write bursts -system.physmem.perBankRdBursts::9 10041 # Per bank write bursts -system.physmem.perBankRdBursts::10 9320 # Per bank write bursts -system.physmem.perBankRdBursts::11 9342 # Per bank write bursts -system.physmem.perBankRdBursts::12 9424 # Per bank write bursts -system.physmem.perBankRdBursts::13 10229 # Per bank write bursts -system.physmem.perBankRdBursts::14 9340 # Per bank write bursts -system.physmem.perBankRdBursts::15 9201 # Per bank write bursts -system.physmem.perBankWrBursts::0 7577 # Per bank write bursts -system.physmem.perBankWrBursts::1 7036 # Per bank write bursts -system.physmem.perBankWrBursts::2 7887 # Per bank write bursts -system.physmem.perBankWrBursts::3 8049 # Per bank write bursts -system.physmem.perBankWrBursts::4 7151 # Per bank write bursts -system.physmem.perBankWrBursts::5 7579 # Per bank write bursts -system.physmem.perBankWrBursts::6 7566 # Per bank write bursts -system.physmem.perBankWrBursts::7 7770 # Per bank write bursts -system.physmem.perBankWrBursts::8 7275 # Per bank write bursts -system.physmem.perBankWrBursts::9 7619 # Per bank write bursts -system.physmem.perBankWrBursts::10 6810 # Per bank write bursts -system.physmem.perBankWrBursts::11 7097 # Per bank write bursts -system.physmem.perBankWrBursts::12 7200 # Per bank write bursts -system.physmem.perBankWrBursts::13 7753 # Per bank write bursts -system.physmem.perBankWrBursts::14 6925 # Per bank write bursts -system.physmem.perBankWrBursts::15 6640 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 47113 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10077 # Per bank write bursts +system.physmem.perBankRdBursts::1 9979 # Per bank write bursts +system.physmem.perBankRdBursts::2 10695 # Per bank write bursts +system.physmem.perBankRdBursts::3 10661 # Per bank write bursts +system.physmem.perBankRdBursts::4 18797 # Per bank write bursts +system.physmem.perBankRdBursts::5 9659 # Per bank write bursts +system.physmem.perBankRdBursts::6 9665 # Per bank write bursts +system.physmem.perBankRdBursts::7 10488 # Per bank write bursts +system.physmem.perBankRdBursts::8 9276 # Per bank write bursts +system.physmem.perBankRdBursts::9 9973 # Per bank write bursts +system.physmem.perBankRdBursts::10 9230 # Per bank write bursts +system.physmem.perBankRdBursts::11 8679 # Per bank write bursts +system.physmem.perBankRdBursts::12 9820 # Per bank write bursts +system.physmem.perBankRdBursts::13 10379 # Per bank write bursts +system.physmem.perBankRdBursts::14 9723 # Per bank write bursts +system.physmem.perBankRdBursts::15 9413 # Per bank write bursts +system.physmem.perBankWrBursts::0 7393 # Per bank write bursts +system.physmem.perBankWrBursts::1 7263 # Per bank write bursts +system.physmem.perBankWrBursts::2 8282 # Per bank write bursts +system.physmem.perBankWrBursts::3 8171 # Per bank write bursts +system.physmem.perBankWrBursts::4 7489 # Per bank write bursts +system.physmem.perBankWrBursts::5 7265 # Per bank write bursts +system.physmem.perBankWrBursts::6 7108 # Per bank write bursts +system.physmem.perBankWrBursts::7 7662 # Per bank write bursts +system.physmem.perBankWrBursts::8 7080 # Per bank write bursts +system.physmem.perBankWrBursts::9 7523 # Per bank write bursts +system.physmem.perBankWrBursts::10 6693 # Per bank write bursts +system.physmem.perBankWrBursts::11 6470 # Per bank write bursts +system.physmem.perBankWrBursts::12 7534 # Per bank write bursts +system.physmem.perBankWrBursts::13 7859 # Per bank write bursts +system.physmem.perBankWrBursts::14 7265 # Per bank write bursts +system.physmem.perBankWrBursts::15 6788 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 2909342872000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2909603601500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157020 # Read request sizes (log2) +system.physmem.readPktSize::6 157055 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117459 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 258 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117375 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165631 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,109 +159,116 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58587 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 310.682984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.521208 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.535953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21321 36.39% 36.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14587 24.90% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6073 10.37% 71.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3205 5.47% 77.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2612 4.46% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1486 2.54% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1112 1.90% 86.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1062 1.81% 87.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7129 12.17% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58587 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5766 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.870621 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 589.954659 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5765 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58748 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 309.779261 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.856223 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.388013 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21447 36.51% 36.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14643 24.93% 61.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6082 10.35% 71.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3222 5.48% 77.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2599 4.42% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1493 2.54% 84.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1038 1.77% 86.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1067 1.82% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7157 12.18% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58748 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5762 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.896737 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 590.107660 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5761 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5766 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5766 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.453347 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.695263 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.074003 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4962 86.06% 86.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 90 1.56% 87.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 33 0.57% 88.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 174 3.02% 91.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 30 0.52% 91.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 151 2.62% 94.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 46 0.80% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.09% 95.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 17 0.29% 95.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 15 0.26% 95.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.12% 95.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.03% 95.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 166 2.88% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.09% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.14% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 26 0.45% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.03% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.29% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 4 0.07% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5766 # Writes before turning the bus around for reads -system.physmem.totQLat 1636363750 # Total ticks spent queuing -system.physmem.totMemAccLat 4757732500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 832365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9829.60 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5762 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5762 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.452100 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.700018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.100411 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4964 86.15% 86.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 94 1.63% 87.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 35 0.61% 88.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 168 2.92% 91.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 22 0.38% 91.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 152 2.64% 94.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 51 0.89% 95.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.12% 95.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 11 0.19% 95.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 15 0.26% 95.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.05% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.07% 95.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 174 3.02% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 7 0.12% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.05% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 18 0.31% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.07% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.03% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 15 0.26% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5762 # Writes before turning the bus around for reads +system.physmem.totQLat 1626690000 # Total ticks spent queuing +system.physmem.totMemAccLat 4748827500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 832570000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9769.09 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28579.60 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28519.09 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s @@ -271,40 +278,40 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.26 # Average write queue length when enqueuing -system.physmem.readRowHits 136200 # Number of row buffer hits during reads -system.physmem.writeRowHits 89619 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.98 # Row buffer hit rate for writes -system.physmem.avgGap 10086754.84 # Average gap between requests -system.physmem.pageHitRate 79.39 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229098240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125004000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 702764400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392785200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 190023952560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 90217297485 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1666466226750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1948157128635 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.621597 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2772138232000 # Time in different power states -system.physmem_0.memoryStateTime::REF 97149260000 # Time in different power states +system.physmem.avgWrQLen 26.01 # Average write queue length when enqueuing +system.physmem.readRowHits 136108 # Number of row buffer hits during reads +system.physmem.writeRowHits 89502 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.74 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.93 # Row buffer hit rate for writes +system.physmem.avgGap 10089372.82 # Average gap between requests +system.physmem.pageHitRate 79.33 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 230496840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125767125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 702163800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392901840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 190040735040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 90194010705 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666640821500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1948326896850 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.620811 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2772423900000 # Time in different power states +system.physmem_0.memoryStateTime::REF 97157840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 40052866750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40015565000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 213819480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116667375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 595717200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371427120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 190023952560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88066202985 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1668353151750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1947740938470 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.478544 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2775299661000 # Time in different power states -system.physmem_1.memoryStateTime::REF 97149260000 # Time in different power states +system.physmem_1.actEnergy 213638040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116568375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 596637600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 370733760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 190040735040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88104913965 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668473362500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947916589280 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.479792 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2775503002250 # Time in different power states +system.physmem_1.memoryStateTime::REF 97157840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 36894247500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36942968250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -354,55 +361,56 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 9555 # Table walker walks requested -system.cpu.dtb.walker.walksShort 9555 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1270 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8285 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 9555 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 9555 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 9555 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7391 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12962.724936 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 10716.855962 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8397.253568 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 7386 99.93% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7391 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 9546 # Table walker walks requested +system.cpu.dtb.walker.walksShort 9546 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1255 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 9546 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 9546 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 9546 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7382 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 13188.702249 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10926.693941 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 9189.684239 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7377 99.93% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-360447 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7382 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 1638910500 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 1638910500 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 1638910500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6168 83.45% 83.45% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1223 16.55% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7391 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9555 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 6174 83.64% 83.64% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1208 16.36% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7382 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9546 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9555 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7391 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9546 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7382 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7391 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 16946 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7382 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 16928 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24521784 # DTB read hits -system.cpu.dtb.read_misses 8135 # DTB read misses -system.cpu.dtb.write_hits 19607400 # DTB write hits -system.cpu.dtb.write_misses 1420 # DTB write misses +system.cpu.dtb.read_hits 24520223 # DTB read hits +system.cpu.dtb.read_misses 8124 # DTB read misses +system.cpu.dtb.write_hits 19606444 # DTB write hits +system.cpu.dtb.write_misses 1422 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1651 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24529919 # DTB read accesses -system.cpu.dtb.write_accesses 19608820 # DTB write accesses +system.cpu.dtb.read_accesses 24528347 # DTB read accesses +system.cpu.dtb.write_accesses 19607866 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44129184 # DTB hits -system.cpu.dtb.misses 9555 # DTB misses -system.cpu.dtb.accesses 44138739 # DTB accesses +system.cpu.dtb.hits 44126667 # DTB hits +system.cpu.dtb.misses 9546 # DTB misses +system.cpu.dtb.accesses 44136213 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -440,11 +448,11 @@ system.cpu.itb.walker.walkWaitTime::samples 4763 # system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12663.288288 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10495.066195 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7808.701731 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 2418 77.80% 77.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 688 22.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12722.007722 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10527.196882 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7865.701982 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2410 77.54% 77.54% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 696 22.39% 99.94% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 1638383000 # Table walker pending requests distribution @@ -460,7 +468,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115560644 # ITB inst hits +system.cpu.itb.inst_hits 115553087 # ITB inst hits system.cpu.itb.inst_misses 4763 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -477,38 +485,40 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115565407 # ITB inst accesses -system.cpu.itb.hits 115560644 # DTB hits +system.cpu.itb.inst_accesses 115557850 # ITB inst accesses +system.cpu.itb.hits 115553087 # DTB hits system.cpu.itb.misses 4763 # DTB misses -system.cpu.itb.accesses 115565407 # DTB accesses -system.cpu.numCycles 5818686633 # number of cpu cycles simulated +system.cpu.itb.accesses 115557850 # DTB accesses +system.cpu.numCycles 5819207917 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112463069 # Number of instructions committed -system.cpu.committedOps 135595282 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119900050 # Number of integer alu accesses +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed +system.cpu.committedInsts 112455934 # Number of instructions committed +system.cpu.committedOps 135586369 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119891885 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses -system.cpu.num_func_calls 9893453 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15231190 # number of instructions that are conditional controls -system.cpu.num_int_insts 119900050 # number of integer instructions +system.cpu.num_func_calls 9891908 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15230427 # number of instructions that are conditional controls +system.cpu.num_int_insts 119891885 # number of integer instructions system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218076436 # number of times the integer registers were read -system.cpu.num_int_register_writes 82650791 # number of times the integer registers were written +system.cpu.num_int_register_reads 218060317 # number of times the integer registers were read +system.cpu.num_int_register_writes 82644878 # number of times the integer registers were written system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489768723 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51897400 # number of times the CC registers were written -system.cpu.num_mem_refs 45409486 # number of memory refs -system.cpu.num_load_insts 24844046 # Number of load instructions -system.cpu.num_store_insts 20565440 # Number of store instructions -system.cpu.num_idle_cycles 5379802959.980151 # Number of idle cycles -system.cpu.num_busy_cycles 438883673.019849 # Number of busy cycles -system.cpu.not_idle_fraction 0.075427 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.924573 # Percentage of idle cycles -system.cpu.Branches 25918657 # Number of branches fetched +system.cpu.num_cc_register_reads 489736143 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51894204 # number of times the CC registers were written +system.cpu.num_mem_refs 45406948 # number of memory refs +system.cpu.num_load_insts 24842511 # Number of load instructions +system.cpu.num_store_insts 20564437 # Number of store instructions +system.cpu.num_idle_cycles 5379072532.100152 # Number of idle cycles +system.cpu.num_busy_cycles 440135384.899849 # Number of busy cycles +system.cpu.not_idle_fraction 0.075635 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.924365 # Percentage of idle cycles +system.cpu.Branches 25916368 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93180998 67.17% 67.18% # Class of executed instruction -system.cpu.op_class::IntMult 114440 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93174225 67.17% 67.18% # Class of executed instruction +system.cpu.op_class::IntMult 114427 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -536,256 +546,254 @@ system.cpu.op_class::SimdFloatMisc 8455 0.01% 67.26% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24844046 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20565440 14.83% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24842511 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20564437 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138715716 # Class of executed instruction -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 821347 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.702129 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43235829 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 821859 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.607356 # Average number of references to valid blocks. +system.cpu.op_class::total 138706392 # Class of executed instruction +system.cpu.dcache.tags.replacements 819093 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.702336 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43235572 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819605 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.751718 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.702129 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999418 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.702336 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999419 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177121649 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177121649 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23112263 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23112263 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18824569 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18824569 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392807 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392807 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443229 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443229 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460200 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460200 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41936832 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41936832 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42329639 # number of overall hits -system.cpu.dcache.overall_hits::total 42329639 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 401818 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 401818 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 298972 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 298972 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118323 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118323 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22757 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22757 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 177109325 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177109325 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23112645 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23112645 # number of ReadReq hits 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25616463000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 25616463000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 25616463000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23514081 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23514081 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19123541 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19123541 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511130 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511130 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 25600196000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 25600196000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 25600196000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 25600196000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23512501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23512501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19122583 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19122583 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511149 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511149 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465986 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465986 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460202 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460202 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42637622 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42637622 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43148752 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43148752 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017088 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017088 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015634 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015634 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231493 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.231493 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048836 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048836 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460205 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460205 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42635084 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42635084 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43146233 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43146233 # number of overall (read+write) accesses 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system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36553.693689 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36553.693689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31273.417709 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31273.417709 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36650.402221 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36650.402221 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31339.606103 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31339.606103 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 100 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 685107 # number of writebacks -system.cpu.dcache.writebacks::total 685107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 939 # number of 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of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696089 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1696089 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1696089 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1696089 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1696089 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1696089 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses 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overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014678 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014678 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014678 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.218443 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.218443 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.218443 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.218443 # 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-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.171658 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.062853 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435700 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435700 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010600 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010600 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023240 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023240 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010600 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062936 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010600 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062936 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 122777.777778 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70800.548446 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70800.548446 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 147055.555556 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70804.014599 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70804.014599 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117148.641724 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117148.641724 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121367.271917 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121367.271917 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122269.562739 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122269.562739 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117148.281025 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117148.281025 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120754.797263 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120754.797263 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122558.535984 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122558.535984 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121367.271917 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117594.404752 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118020.597685 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120754.797263 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117615.043307 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117971.572979 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121367.271917 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117594.404752 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118020.597685 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120754.797263 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117615.043307 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117971.572979 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178159.563877 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163777.353088 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162173.039980 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162173.039980 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189149.238872 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172298.182271 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.310559 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.310559 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170649.352087 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 163124.038731 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181557.094692 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172579.218881 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5058225 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2539566 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38059 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 583 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 583 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5052300 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536604 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38129 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 67216 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2289899 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 67213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2287266 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 802569 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1801014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2759 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 801101 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1664804 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 134612 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2763 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696794 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 525904 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2765 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295878 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295878 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696089 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 523979 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5077168 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2580972 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13250 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25621 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7697011 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108629432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96644509 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31124 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205321201 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 175948 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5294343 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018110 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.133351 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5074993 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574186 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13257 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25655 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7688091 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215131128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96411485 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16164 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 311590049 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 175874 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2773719 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.020869 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.142946 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5198460 98.19% 98.19% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 95883 1.81% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2715834 97.91% 97.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 57885 2.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5294343 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3265837500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 2773719 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4957066000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2554213000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2553155500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1279146500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1275758999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17840000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17837000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30177 # Transaction distribution system.iobus.trans_dist::ReadResp 30177 # Transaction distribution @@ -1235,63 +1250,63 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46338000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 94500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 644500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 52500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6288500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 174000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 36469500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 127000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186318027 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186222546 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 37000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36418 # number of replacements -system.iocache.tags.tagsinuse 1.083918 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.084136 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 313622510000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.083918 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067745 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067745 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 313818895000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.084136 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067758 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067758 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1305,14 +1320,14 @@ system.iocache.demand_misses::realview.ide 228 # system.iocache.demand_misses::total 228 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 228 # number of overall misses system.iocache.overall_misses::total 228 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28366877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28366877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4697294150 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4697294150 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28366877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28366877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28366877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28366877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28180377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28180377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4715427169 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4715427169 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28180377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28180377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28180377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28180377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1329,19 +1344,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124416.127193 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124416.127193 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129673.535501 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129673.535501 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124416.127193 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124416.127193 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124416.127193 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124416.127193 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123598.144737 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123598.144737 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130174.115752 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130174.115752 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123598.144737 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123598.144737 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 753 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 81 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.296296 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1355,14 +1370,14 @@ system.iocache.demand_mshr_misses::realview.ide 228 system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16966877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16966877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886094150 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2886094150 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16966877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16966877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16966877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16966877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16780377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16780377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2904227169 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2904227169 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16780377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16780377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16780377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16780377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1371,68 +1386,68 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74416.127193 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74416.127193 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79673.535501 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79673.535501 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74416.127193 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74416.127193 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74416.127193 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74416.127193 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80174.115752 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80174.115752 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70632 # Transaction distribution +system.membus.trans_dist::ReadResp 70548 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::Writeback 117459 # Transaction distribution -system.membus.trans_dist::CleanEvict 6342 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4500 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117375 # Transaction distribution +system.membus.trans_dist::CleanEvict 6392 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4502 # Transaction distribution -system.membus.trans_dist::ReadExReq 127038 # Transaction distribution -system.membus.trans_dist::ReadExResp 127038 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30472 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4499 # Transaction distribution +system.membus.trans_dist::ReadExReq 127157 # Transaction distribution +system.membus.trans_dist::ReadExResp 127157 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30388 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438793 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546385 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438823 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546415 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 655279 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 655309 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15305404 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15468757 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15302268 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15465621 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17785877 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17782741 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 492 # Total snoops (count) -system.membus.snoop_fanout::samples 390004 # Request fanout histogram +system.membus.snoop_fanout::samples 389999 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 390004 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 389999 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 390004 # Request fanout histogram -system.membus.reqLayer0.occupancy 90504500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 389999 # Request fanout histogram +system.membus.reqLayer0.occupancy 90471000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1698500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1726000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 821932659 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 823075656 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 952275997 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 952261248 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64458066 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64129261 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 83f940052..037583e12 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1174884 # Simulator instruction rate (inst/s) -host_op_rate 1430233 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22908545755 # Simulator tick rate (ticks/s) -host_mem_usage 623708 # Number of bytes of host memory used -host_seconds 121.52 # Real time elapsed on the host +host_inst_rate 1268879 # Simulator instruction rate (inst/s) +host_op_rate 1544656 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24741311872 # Simulator tick rate (ticks/s) +host_mem_usage 623824 # Number of bytes of host memory used +host_seconds 112.52 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -226,6 +226,8 @@ system.cpu0.itb.accesses 74781709 # DT system.cpu0.numCycles 5536444792 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 3083 # number of quiesce instructions executed system.cpu0.committedInsts 72626333 # Number of instructions committed system.cpu0.committedOps 87972335 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 77485858 # Number of integer alu accesses @@ -283,8 +285,6 @@ system.cpu0.op_class::MemWrite 11749540 13.09% 100.00% # Cl system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 89742700 # Class of executed instruction -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3083 # number of quiesce instructions executed system.cpu0.dcache.tags.replacements 819402 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 53784414 # Total number of references to valid blocks. @@ -459,6 +459,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.writebacks::writebacks 1699214 # number of writebacks +system.cpu0.icache.writebacks::total 1699214 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -599,6 +601,8 @@ system.cpu1.itb.accesses 72262399 # DT system.cpu1.numCycles 88040649 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.committedInsts 70146546 # Number of instructions committed system.cpu1.committedOps 85830789 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 75676825 # Number of integer alu accesses @@ -656,8 +660,6 @@ system.cpu1.op_class::MemWrite 12333852 14.10% 100.00% # Cl system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 87477212 # Class of executed instruction -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -801,8 +803,10 @@ system.l2c.ReadReq_hits::cpu0.itb.walker 2287 # nu system.l2c.ReadReq_hits::cpu1.dtb.walker 5001 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 2453 # number of ReadReq hits system.l2c.ReadReq_hits::total 14441 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 682264 # number of Writeback hits -system.l2c.Writeback_hits::total 682264 # number of Writeback hits +system.l2c.WritebackDirty_hits::writebacks 682264 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 682264 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1667206 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits @@ -872,8 +876,10 @@ system.l2c.ReadReq_accesses::cpu0.itb.walker 2288 system.l2c.ReadReq_accesses::cpu1.dtb.walker 5003 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 2453 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 14449 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 682264 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 682264 # number of Writeback accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 682264 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 682264 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1262 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1494 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) @@ -955,7 +961,7 @@ system.membus.trans_dist::ReadReq 40087 # Tr system.membus.trans_dist::ReadResp 74196 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::Writeback 138133 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138133 # Transaction distribution system.membus.trans_dist::CleanEvict 7977 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution @@ -1044,8 +1050,9 @@ system.toL2Bus.trans_dist::ReadReq 71244 # Tr system.toL2Bus.trans_dist::ReadResp 2291984 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 682264 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1797078 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 682264 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 129872 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution @@ -1058,11 +1065,11 @@ system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2 system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20804 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41510 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 7721762 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96323169 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41608 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83020 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205266733 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 311967917 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 182968 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 5322627 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 0.018535 # Request fanout histogram diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index a4264e923..6e04c32d2 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,136 +1,136 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.909388 # Number of seconds simulated -sim_ticks 2909387991500 # Number of ticks simulated -final_tick 2909387991500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.909654 # Number of seconds simulated +sim_ticks 2909653700500 # Number of ticks simulated +final_tick 2909653700500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 670421 # Simulator instruction rate (inst/s) -host_op_rate 808321 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17345176485 # Simulator tick rate (ticks/s) -host_mem_usage 625252 # Number of bytes of host memory used -host_seconds 167.73 # Real time elapsed on the host -sim_insts 112452815 # Number of instructions simulated -sim_ops 135583410 # Number of ops (including micro ops) simulated +host_inst_rate 811232 # Simulator instruction rate (inst/s) +host_op_rate 978087 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20990567196 # Simulator tick rate (ticks/s) +host_mem_usage 580224 # Number of bytes of host memory used +host_seconds 138.62 # Real time elapsed on the host +sim_insts 112450652 # Number of instructions simulated +sim_ops 135579653 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 538144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4761988 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 521248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4656256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 646852 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4138720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 665348 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4245540 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10087176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 538144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 646852 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1184996 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7517248 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 8860 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 8664 # Number of bytes written to this memory -system.physmem.bytes_written::total 7534772 # Number of bytes written to this memory +system.physmem.bytes_read::total 10089864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 521248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 665348 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1186596 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7511936 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 8852 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 8672 # Number of bytes written to this memory +system.physmem.bytes_written::total 7529460 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13696 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 74910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13432 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73257 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 13273 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 64683 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 13562 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 66353 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166585 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117457 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 2215 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2166 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121838 # Number of write requests responded to by this memory +system.physmem.num_reads::total 166627 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117374 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2213 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2168 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121755 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 184968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1636766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 179144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1600278 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 222333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1422540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 228669 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1459122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3467113 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 184968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 222333 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 407301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2583790 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 3045 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2978 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2589813 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2583790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3467720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 179144 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 228669 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407813 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2581729 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 3042 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2980 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2587751 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2581729 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 184968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1639812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 179144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1603321 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 222333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1425518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 228669 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1462103 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6056926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166585 # Number of read requests accepted -system.physmem.writeReqs 121838 # Number of write requests accepted -system.physmem.readBursts 166585 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121838 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10654272 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue -system.physmem.bytesWritten 7548800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10087176 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7534772 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6055471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166627 # Number of read requests accepted +system.physmem.writeReqs 121755 # Number of write requests accepted +system.physmem.readBursts 166627 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121755 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10658432 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5696 # Total number of bytes read from write queue +system.physmem.bytesWritten 7541440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10089864 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7529460 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 89 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40727 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10228 # Per bank write bursts -system.physmem.perBankRdBursts::1 9700 # Per bank write bursts -system.physmem.perBankRdBursts::2 10356 # Per bank write bursts -system.physmem.perBankRdBursts::3 10495 # Per bank write bursts -system.physmem.perBankRdBursts::4 18506 # Per bank write bursts -system.physmem.perBankRdBursts::5 10022 # Per bank write bursts -system.physmem.perBankRdBursts::6 10178 # Per bank write bursts -system.physmem.perBankRdBursts::7 10614 # Per bank write bursts -system.physmem.perBankRdBursts::8 9477 # Per bank write bursts -system.physmem.perBankRdBursts::9 10047 # Per bank write bursts -system.physmem.perBankRdBursts::10 9317 # Per bank write bursts -system.physmem.perBankRdBursts::11 9342 # Per bank write bursts -system.physmem.perBankRdBursts::12 9423 # Per bank write bursts -system.physmem.perBankRdBursts::13 10228 # Per bank write bursts -system.physmem.perBankRdBursts::14 9339 # Per bank write bursts -system.physmem.perBankRdBursts::15 9201 # Per bank write bursts -system.physmem.perBankWrBursts::0 7595 # Per bank write bursts -system.physmem.perBankWrBursts::1 7036 # Per bank write bursts -system.physmem.perBankWrBursts::2 7887 # Per bank write bursts -system.physmem.perBankWrBursts::3 8047 # Per bank write bursts -system.physmem.perBankWrBursts::4 7152 # Per bank write bursts -system.physmem.perBankWrBursts::5 7580 # Per bank write bursts -system.physmem.perBankWrBursts::6 7566 # Per bank write bursts -system.physmem.perBankWrBursts::7 7770 # Per bank write bursts -system.physmem.perBankWrBursts::8 7275 # Per bank write bursts -system.physmem.perBankWrBursts::9 7619 # Per bank write bursts -system.physmem.perBankWrBursts::10 6806 # Per bank write bursts -system.physmem.perBankWrBursts::11 7096 # Per bank write bursts -system.physmem.perBankWrBursts::12 7204 # Per bank write bursts -system.physmem.perBankWrBursts::13 7753 # Per bank write bursts -system.physmem.perBankWrBursts::14 6924 # Per bank write bursts -system.physmem.perBankWrBursts::15 6640 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 47114 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10080 # Per bank write bursts +system.physmem.perBankRdBursts::1 9979 # Per bank write bursts +system.physmem.perBankRdBursts::2 10697 # Per bank write bursts +system.physmem.perBankRdBursts::3 10658 # Per bank write bursts +system.physmem.perBankRdBursts::4 18793 # Per bank write bursts +system.physmem.perBankRdBursts::5 9660 # Per bank write bursts +system.physmem.perBankRdBursts::6 9676 # Per bank write bursts +system.physmem.perBankRdBursts::7 10492 # Per bank write bursts +system.physmem.perBankRdBursts::8 9276 # Per bank write bursts +system.physmem.perBankRdBursts::9 9982 # Per bank write bursts +system.physmem.perBankRdBursts::10 9231 # Per bank write bursts +system.physmem.perBankRdBursts::11 8678 # Per bank write bursts +system.physmem.perBankRdBursts::12 9823 # Per bank write bursts +system.physmem.perBankRdBursts::13 10380 # Per bank write bursts +system.physmem.perBankRdBursts::14 9720 # Per bank write bursts +system.physmem.perBankRdBursts::15 9413 # Per bank write bursts +system.physmem.perBankWrBursts::0 7393 # Per bank write bursts +system.physmem.perBankWrBursts::1 7263 # Per bank write bursts +system.physmem.perBankWrBursts::2 8284 # Per bank write bursts +system.physmem.perBankWrBursts::3 8168 # Per bank write bursts +system.physmem.perBankWrBursts::4 7485 # Per bank write bursts +system.physmem.perBankWrBursts::5 7265 # Per bank write bursts +system.physmem.perBankWrBursts::6 7108 # Per bank write bursts +system.physmem.perBankWrBursts::7 7667 # Per bank write bursts +system.physmem.perBankWrBursts::8 7080 # Per bank write bursts +system.physmem.perBankWrBursts::9 7523 # Per bank write bursts +system.physmem.perBankWrBursts::10 6694 # Per bank write bursts +system.physmem.perBankWrBursts::11 6470 # Per bank write bursts +system.physmem.perBankWrBursts::12 7527 # Per bank write bursts +system.physmem.perBankWrBursts::13 7859 # Per bank write bursts +system.physmem.perBankWrBursts::14 7261 # Per bank write bursts +system.physmem.perBankWrBursts::15 6788 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2909387547000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 2909653343500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157013 # Read request sizes (log2) +system.physmem.readPktSize::6 157055 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117457 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165681 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 523 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117374 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 617 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -161,132 +161,137 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 168 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 165 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9126 # What write queue length does an incoming req see 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does an incoming req see -system.physmem.wrQLenPdf::39 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58549 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 310.902116 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.522866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.172226 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21290 36.36% 36.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14652 25.03% 61.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6083 10.39% 71.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3178 5.43% 77.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2491 4.25% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1565 2.67% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1038 1.77% 85.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1041 1.78% 87.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7211 12.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58549 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5743 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.986941 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 548.492879 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5740 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::36 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58556 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 310.810301 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.232220 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.272692 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21388 36.53% 36.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14563 24.87% 61.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6001 10.25% 71.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3238 5.53% 77.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2533 4.33% 81.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1526 2.61% 84.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1009 1.72% 85.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1158 1.98% 87.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7140 12.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58556 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5712 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.151786 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 545.492775 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5709 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 2 0.04% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5743 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5743 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.538046 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.602147 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.025411 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 27 0.47% 0.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 14 0.24% 0.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 12 0.21% 0.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 14 0.24% 1.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4750 82.71% 83.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 125 2.18% 86.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 82 1.43% 87.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 205 3.57% 91.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 32 0.56% 91.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 152 2.65% 94.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 51 0.89% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.10% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 11 0.19% 95.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 18 0.31% 95.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 9 0.16% 95.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.02% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 172 2.99% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.10% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.09% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 21 0.37% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.05% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.24% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5743 # Writes before turning the bus around for reads -system.physmem.totQLat 1603192250 # Total ticks spent queuing -system.physmem.totMemAccLat 4724561000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 832365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9630.34 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5712 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5712 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.629377 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.719500 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.211627 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 18 0.32% 0.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 9 0.16% 0.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 8 0.14% 0.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 11 0.19% 0.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4765 83.42% 84.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 125 2.19% 86.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 59 1.03% 87.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 204 3.57% 91.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 32 0.56% 91.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 148 2.59% 94.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 51 0.89% 95.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 8 0.14% 95.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.16% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 17 0.30% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.09% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.14% 95.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 167 2.92% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.11% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 19 0.33% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.07% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.04% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.05% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.04% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 15 0.26% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5712 # Writes before turning the bus around for reads +system.physmem.totQLat 1608810750 # Total ticks spent queuing +system.physmem.totMemAccLat 4731398250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 832690000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9660.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28380.34 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28410.32 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s @@ -296,40 +301,40 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.27 # Average write queue length when enqueuing -system.physmem.readRowHits 136293 # Number of row buffer hits during reads -system.physmem.writeRowHits 89580 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.95 # Row buffer hit rate for writes -system.physmem.avgGap 10087224.48 # Average gap between requests -system.physmem.pageHitRate 79.41 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229158720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125037000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 702772200 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 12.25 # Average write queue length when enqueuing +system.physmem.readRowHits 136274 # Number of row buffer hits during reads +system.physmem.writeRowHits 89542 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.97 # Row buffer hit rate for writes +system.physmem.avgGap 10089580.29 # Average gap between requests +system.physmem.pageHitRate 79.40 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 230519520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125779500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 702273000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 392901840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 190027003920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 90369730305 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1666360544250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1948207148235 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.628037 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2771956641500 # Time in different power states -system.physmem_0.memoryStateTime::REF 97150820000 # Time in different power states +system.physmem_0.refreshEnergy 190044294960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 90285662430 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666593127500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1948374558750 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.624648 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2772342347250 # Time in different power states +system.physmem_0.memoryStateTime::REF 97159660000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 40279614750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40149801500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 213471720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116477625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 595709400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371414160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 190027003920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88357601520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1668125569500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1947807247845 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.490585 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2774916457500 # Time in different power states -system.physmem_1.memoryStateTime::REF 97150820000 # Time in different power states +system.physmem_1.actEnergy 212163840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 115764000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 596715600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 370668960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 190044294960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88503009660 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668156858000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947999475020 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.495738 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2774969217000 # Time in different power states +system.physmem_1.memoryStateTime::REF 97159660000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 37320566000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 37524675500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -379,58 +384,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 6929 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 6929 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2193 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4735 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 6928 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 6928 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 6928 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 5821 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12939.357499 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11196.384549 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7211.949482 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 4588 78.82% 78.82% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1229 21.11% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-147455 4 0.07% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 5821 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 1237488496 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean -0.616549 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 2000461000 161.65% 161.65% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -762972504 -61.65% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1237488496 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3649 62.70% 62.70% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 2171 37.30% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5820 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6929 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 6385 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 6385 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1824 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4559 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 2 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 6383 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 6383 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 6383 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 5318 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 13413.689357 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11614.000174 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7416.349168 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 3990 75.03% 75.03% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1324 24.90% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-147455 4 0.08% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 5318 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1993677436 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean -0.003389 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 2000434000 100.34% 100.34% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -6756564 -0.34% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1993677436 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3519 66.20% 66.20% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1797 33.80% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5316 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6385 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6929 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5820 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6385 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5316 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5820 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 12749 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5316 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 11701 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12044488 # DTB read hits -system.cpu0.dtb.read_misses 5975 # DTB read misses -system.cpu0.dtb.write_hits 9654865 # DTB write hits -system.cpu0.dtb.write_misses 954 # DTB write misses +system.cpu0.dtb.read_hits 12043498 # DTB read hits +system.cpu0.dtb.read_misses 5581 # DTB read misses +system.cpu0.dtb.write_hits 9607194 # DTB write hits +system.cpu0.dtb.write_misses 804 # DTB write misses system.cpu0.dtb.flush_tlb 2940 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 441 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 4388 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3980 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 864 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 867 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 231 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12050463 # DTB read accesses -system.cpu0.dtb.write_accesses 9655819 # DTB write accesses +system.cpu0.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12049079 # DTB read accesses +system.cpu0.dtb.write_accesses 9607998 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21699353 # DTB hits -system.cpu0.dtb.misses 6929 # DTB misses -system.cpu0.dtb.accesses 21706282 # DTB accesses +system.cpu0.dtb.hits 21650692 # DTB hits +system.cpu0.dtb.misses 6385 # DTB misses +system.cpu0.dtb.accesses 21657077 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -460,256 +465,256 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3426 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3426 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 828 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2598 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3426 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3426 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3426 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2558 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12817.630962 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11147.269267 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6399.295854 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::4096-6143 694 27.13% 27.13% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::10240-12287 823 32.17% 59.30% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::12288-14335 178 6.96% 66.26% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::14336-16383 343 13.41% 79.67% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-18431 1 0.04% 79.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::22528-24575 515 20.13% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-26623 4 0.16% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2558 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 3199 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3199 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 683 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2516 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3199 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3199 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3199 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2347 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 13274.818918 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11551.422255 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6527.623179 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::4096-6143 600 25.56% 25.56% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::10240-12287 656 27.95% 53.52% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::12288-14335 193 8.22% 61.74% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::14336-16383 387 16.49% 78.23% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-18431 3 0.13% 78.36% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::22528-24575 500 21.30% 99.66% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-26623 8 0.34% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2347 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 2000380500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 2000380500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 2000380500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1730 67.63% 67.63% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 828 32.37% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2558 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 1664 70.90% 70.90% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 683 29.10% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2347 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3426 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3426 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3199 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3199 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2558 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2558 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 5984 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 56823446 # ITB inst hits -system.cpu0.itb.inst_misses 3426 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2347 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2347 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5546 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 56739503 # ITB inst hits +system.cpu0.itb.inst_misses 3199 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 2940 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 441 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2582 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2369 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 56826872 # ITB inst accesses -system.cpu0.itb.hits 56823446 # DTB hits -system.cpu0.itb.misses 3426 # DTB misses -system.cpu0.itb.accesses 56826872 # DTB accesses -system.cpu0.numCycles 2910048510 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 56742702 # ITB inst accesses +system.cpu0.itb.hits 56739503 # DTB hits +system.cpu0.itb.misses 3199 # DTB misses +system.cpu0.itb.accesses 56742702 # DTB accesses +system.cpu0.numCycles 2910044532 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 55288600 # Number of instructions committed -system.cpu0.committedOps 66713599 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 58931600 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5354 # Number of float alu accesses -system.cpu0.num_func_calls 4809440 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7565706 # number of instructions that are conditional controls -system.cpu0.num_int_insts 58931600 # number of integer instructions -system.cpu0.num_fp_insts 5354 # number of float instructions -system.cpu0.num_int_register_reads 107138015 # number of times the integer registers were read -system.cpu0.num_int_register_writes 40582750 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4124 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1232 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 240777875 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 25734446 # number of times the CC registers were written -system.cpu0.num_mem_refs 22316238 # number of memory refs -system.cpu0.num_load_insts 12197914 # Number of load instructions -system.cpu0.num_store_insts 10118324 # Number of store instructions -system.cpu0.num_idle_cycles 2666885275.671365 # Number of idle cycles -system.cpu0.num_busy_cycles 243163234.328635 # Number of busy cycles -system.cpu0.not_idle_fraction 0.083560 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.916440 # Percentage of idle cycles -system.cpu0.Branches 12750711 # Number of branches fetched -system.cpu0.op_class::No_OpClass 119 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 45844704 67.20% 67.20% # Class of executed instruction -system.cpu0.op_class::IntMult 57827 0.08% 67.28% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3997 0.01% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::MemRead 12197914 17.88% 85.17% # Class of executed instruction -system.cpu0.op_class::MemWrite 10118324 14.83% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 68222885 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 821400 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.702036 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43232181 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 821912 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.599525 # Average number of references to valid blocks. +system.cpu0.committedInsts 55201459 # Number of instructions committed +system.cpu0.committedOps 66609946 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 58847772 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5145 # Number of float alu accesses +system.cpu0.num_func_calls 4820077 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7555989 # number of instructions that are conditional controls +system.cpu0.num_int_insts 58847772 # number of integer instructions +system.cpu0.num_fp_insts 5145 # number of float instructions +system.cpu0.num_int_register_reads 106933475 # number of times the integer registers were read +system.cpu0.num_int_register_writes 40499308 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3730 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1418 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 240486031 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 25664833 # number of times the CC registers were written +system.cpu0.num_mem_refs 22274491 # number of memory refs +system.cpu0.num_load_insts 12198391 # Number of load instructions +system.cpu0.num_store_insts 10076100 # Number of store instructions +system.cpu0.num_idle_cycles 2694628360.005429 # Number of idle cycles +system.cpu0.num_busy_cycles 215416171.994570 # Number of busy cycles +system.cpu0.not_idle_fraction 0.074025 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.925975 # Percentage of idle cycles +system.cpu0.Branches 12743161 # Number of branches fetched +system.cpu0.op_class::No_OpClass 131 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 45792912 67.22% 67.22% # Class of executed instruction +system.cpu0.op_class::IntMult 56104 0.08% 67.30% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.30% # Class of executed instruction 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67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3963 0.01% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::MemRead 12198391 17.91% 85.21% # Class of executed instruction +system.cpu0.op_class::MemWrite 10076100 14.79% 100.00% # Class of executed instruction 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# Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.657689 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 43.309115 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 468.393077 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.084588 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.914830 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177107266 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177107266 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11359748 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11750430 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23110178 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9271451 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9551716 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18823167 # number of WriteReq hits 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(read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20821517 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21504522 # number of overall hits -system.cpu0.dcache.overall_hits::total 42326039 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197790 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 204093 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 401883 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 151382 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 147597 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 298979 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 58506 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 59775 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 118281 # number of SoftPFReq misses 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WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5544191000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5824787000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11368978000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017217 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016725 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016966 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015946 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015301 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231398 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.223875 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227541 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017079 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019404 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018282 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000008 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016621 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016221 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016417 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019130 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.018712 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018917 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15162.609022 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15163.629489 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15163.127298 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 65879.506811 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59734.344194 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62845.823620 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14006.742043 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13774.679242 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13889.269308 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13606.183146 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13461.169191 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13526.408451 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016648 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016085 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016361 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019173 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.018564 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018863 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15507.469476 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14830.063464 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15167.905490 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 64979.244160 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 60982.963460 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62983.285112 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13848.966558 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13920.725989 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13885.163493 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13655.419489 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13448.515275 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13541.730250 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37180.146542 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 33892.999089 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35530.620263 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33904.704683 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31006.127998 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32448.350937 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190199.669421 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191093.892462 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190659.531762 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173647.785478 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 173695.207154 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173672.387546 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 182462.518925 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 182882.213282 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 182679.244640 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36731.464128 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34548.101298 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35638.705941 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33484.119869 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31581.105705 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32530.606414 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203199.486872 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200212.775849 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201652.129231 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 186345.470162 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182743.274648 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184491.427743 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 195252.368375 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 192034.386127 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193590.307695 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1696133 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.440350 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 113853580 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1696645 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.105128 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 28968175500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 264.675620 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 245.764730 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.516945 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.480009 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1695285 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.436603 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 113852008 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1695797 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.137758 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 29075840500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 59.971705 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 450.464899 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.117132 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.879814 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.996946 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 117246882 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 117246882 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 55981187 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 57872393 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 113853580 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 55981187 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 57872393 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 113853580 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 55981187 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 57872393 # number of overall hits -system.cpu0.icache.overall_hits::total 113853580 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 842259 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 854392 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1696651 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 842259 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 854392 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1696651 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 842259 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 854392 # number of overall misses -system.cpu0.icache.overall_misses::total 1696651 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11932408500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 12314837000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 24247245500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11932408500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 12314837000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 24247245500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11932408500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 12314837000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 24247245500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 56823446 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 58726785 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 115550231 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 56823446 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 58726785 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 115550231 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 56823446 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 58726785 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 115550231 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014822 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014549 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014683 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014822 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014549 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014683 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014822 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014549 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014683 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14167.148704 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14413.567777 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14291.239330 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14167.148704 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14413.567777 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14291.239330 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14167.148704 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14413.567777 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14291.239330 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 117243614 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 117243614 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 55899037 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 57952971 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 113852008 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 55899037 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 57952971 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 113852008 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 55899037 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 57952971 # number of overall hits +system.cpu0.icache.overall_hits::total 113852008 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 840466 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 855337 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1695803 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 840466 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 855337 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1695803 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 840466 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 855337 # number of overall misses +system.cpu0.icache.overall_misses::total 1695803 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11890019000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 12374432000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 24264451000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11890019000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 12374432000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 24264451000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11890019000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 12374432000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 24264451000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 56739503 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 58808308 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 115547811 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 56739503 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 58808308 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 115547811 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 56739503 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 58808308 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 115547811 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014813 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014544 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014676 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014813 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014544 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014676 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014813 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014544 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014676 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14146.936342 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14467.317560 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14308.531710 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14146.936342 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14467.317560 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14308.531710 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14146.936342 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14467.317560 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14308.531710 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -921,54 +926,56 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 842259 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 854392 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1696651 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 842259 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 854392 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1696651 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 842259 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 854392 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1696651 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1695285 # number of writebacks +system.cpu0.icache.writebacks::total 1695285 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 840466 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 855337 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1695803 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 840466 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 855337 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1695803 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 840466 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 855337 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1695803 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 5645 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 3377 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 5645 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 3377 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11090149500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11460445000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 22550594500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11090149500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11460445000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 22550594500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11090149500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11460445000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 22550594500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11049553000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11519095000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 22568648000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11049553000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11519095000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 22568648000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11049553000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11519095000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 22568648000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 713903000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 428990000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1142893000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 713903000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 428990000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1142893000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014822 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014549 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014683 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014822 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014549 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014683 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014822 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014549 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014683 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13167.148704 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13413.567777 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13291.239330 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13167.148704 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13413.567777 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13291.239330 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13167.148704 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13413.567777 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13291.239330 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014813 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014544 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014676 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014813 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014544 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014676 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014813 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014544 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014676 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13146.936342 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13467.317560 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13308.531710 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13146.936342 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13467.317560 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13308.531710 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13146.936342 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13467.317560 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13308.531710 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126678.452671 # average ReadReq mshr uncacheable latency @@ -1005,54 +1012,54 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6703 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6703 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 2138 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4565 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 6703 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6703 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6703 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5647 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 13331.414911 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11611.737502 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7443.565061 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 5646 99.98% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 6953 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6953 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 2226 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4727 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 6953 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6953 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6953 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5856 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 13269.296448 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11561.565854 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7342.287931 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 5855 99.98% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::262144-294911 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5647 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5856 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 1639416500 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1639416500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1639416500 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3534 62.58% 62.58% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 2113 37.42% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5647 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6703 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 3650 62.33% 62.33% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 2206 37.67% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5856 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6953 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6703 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5647 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6953 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5856 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5647 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 12350 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5856 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 12809 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 12475099 # DTB read hits -system.cpu1.dtb.read_misses 5811 # DTB read misses -system.cpu1.dtb.write_hits 9951122 # DTB write hits -system.cpu1.dtb.write_misses 892 # DTB write misses +system.cpu1.dtb.read_misses 5924 # DTB read misses +system.cpu1.dtb.write_hits 9998125 # DTB write hits +system.cpu1.dtb.write_misses 1029 # DTB write misses system.cpu1.dtb.flush_tlb 2942 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 476 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4467 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 4683 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 929 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 921 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 214 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12480910 # DTB read accesses -system.cpu1.dtb.write_accesses 9952014 # DTB write accesses +system.cpu1.dtb.perms_faults 228 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12481023 # DTB read accesses +system.cpu1.dtb.write_accesses 9999154 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 22426221 # DTB hits -system.cpu1.dtb.misses 6703 # DTB misses -system.cpu1.dtb.accesses 22432924 # DTB accesses +system.cpu1.dtb.hits 22473224 # DTB hits +system.cpu1.dtb.misses 6953 # DTB misses +system.cpu1.dtb.accesses 22480177 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1082,117 +1089,117 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3400 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3400 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 811 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2589 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 3400 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3400 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3400 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2613 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 13798.698814 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 12017.058980 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 7032.742162 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-16383 1945 74.44% 74.44% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-32767 667 25.53% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 3510 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3510 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 846 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2664 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 3510 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3510 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3510 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2707 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 13960.103436 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 12104.099399 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 7184.126564 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-16383 1964 72.55% 72.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-32767 742 27.41% 99.96% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2613 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2707 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1638889000 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1638889000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1638889000 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1802 68.96% 68.96% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 811 31.04% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2613 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 1861 68.75% 68.75% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 846 31.25% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2707 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3400 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3400 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3510 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3510 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2613 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2613 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 6013 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 58726785 # ITB inst hits -system.cpu1.itb.inst_misses 3400 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2707 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2707 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 6217 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 58808308 # ITB inst hits +system.cpu1.itb.inst_misses 3510 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 2942 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 476 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2616 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2708 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 58730185 # ITB inst accesses -system.cpu1.itb.hits 58726785 # DTB hits -system.cpu1.itb.misses 3400 # DTB misses -system.cpu1.itb.accesses 58730185 # DTB accesses -system.cpu1.numCycles 2908727473 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 58811818 # ITB inst accesses +system.cpu1.itb.hits 58808308 # DTB hits +system.cpu1.itb.misses 3510 # DTB misses +system.cpu1.itb.accesses 58811818 # DTB accesses +system.cpu1.numCycles 2909262869 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 57164215 # Number of instructions committed -system.cpu1.committedOps 68869811 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 60957593 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5807 # Number of float alu accesses -system.cpu1.num_func_calls 5082908 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7664467 # number of instructions that are conditional controls -system.cpu1.num_int_insts 60957593 # number of integer instructions -system.cpu1.num_fp_insts 5807 # number of float instructions -system.cpu1.num_int_register_reads 110918664 # number of times the integer registers were read -system.cpu1.num_int_register_writes 42060766 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4325 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1484 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 248948036 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26157973 # number of times the CC registers were written -system.cpu1.num_mem_refs 23089661 # number of memory refs -system.cpu1.num_load_insts 12644031 # Number of load instructions -system.cpu1.num_store_insts 10445630 # Number of store instructions -system.cpu1.num_idle_cycles 2688977301.144567 # Number of idle cycles -system.cpu1.num_busy_cycles 219750171.855433 # Number of busy cycles -system.cpu1.not_idle_fraction 0.075549 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.924451 # Percentage of idle cycles -system.cpu1.Branches 13165858 # Number of branches fetched -system.cpu1.op_class::No_OpClass 2218 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 47327866 67.15% 67.15% # Class of executed instruction -system.cpu1.op_class::IntMult 56561 0.08% 67.23% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4450 0.01% 67.24% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.24% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.24% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.24% # Class of executed instruction -system.cpu1.op_class::MemRead 12644031 17.94% 85.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 10445630 14.82% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 70480756 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu1.committedInsts 57249193 # Number of instructions committed +system.cpu1.committedOps 68969707 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 61038090 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5951 # Number of float alu accesses +system.cpu1.num_func_calls 5071147 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7673896 # number of instructions that are conditional controls +system.cpu1.num_int_insts 61038090 # number of integer instructions +system.cpu1.num_fp_insts 5951 # number of float instructions +system.cpu1.num_int_register_reads 111115264 # number of times the integer registers were read +system.cpu1.num_int_register_writes 42140927 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4654 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1298 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 249224724 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26227815 # number of times the CC registers were written +system.cpu1.num_mem_refs 23129732 # number of memory refs +system.cpu1.num_load_insts 12642519 # Number of load instructions +system.cpu1.num_store_insts 10487213 # Number of store instructions +system.cpu1.num_idle_cycles 2689871255.481362 # Number of idle cycles +system.cpu1.num_busy_cycles 219391613.518638 # Number of busy cycles +system.cpu1.not_idle_fraction 0.075411 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.924589 # Percentage of idle cycles +system.cpu1.Branches 13171953 # Number of branches fetched +system.cpu1.op_class::No_OpClass 2206 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 47377307 67.13% 67.14% # Class of executed instruction +system.cpu1.op_class::IntMult 58319 0.08% 67.22% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4478 0.01% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::MemRead 12642519 17.91% 85.14% # Class of executed instruction +system.cpu1.op_class::MemWrite 10487213 14.86% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 70572042 # Class of executed instruction system.iobus.trans_dist::ReadReq 30177 # Transaction distribution system.iobus.trans_dist::ReadResp 30177 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1247,63 +1254,63 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46335000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 98000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 95000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 644000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6286500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 172500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 36458500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 126500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186329023 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186202055 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 37000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36418 # number of replacements -system.iocache.tags.tagsinuse 1.084103 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.084308 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 313630728000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.084103 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067756 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067756 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 313834390000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.084308 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067769 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067769 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1317,14 +1324,14 @@ system.iocache.demand_misses::realview.ide 228 # system.iocache.demand_misses::total 228 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 228 # number of overall misses system.iocache.overall_misses::total 228 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28361877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28361877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4696967146 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4696967146 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28361877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28361877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28361877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28361877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28182877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28182877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4712497178 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4712497178 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28182877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28182877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28182877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28182877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1341,19 +1348,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124394.197368 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124394.197368 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129664.508227 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129664.508227 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124394.197368 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124394.197368 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124394.197368 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124394.197368 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123609.109649 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123609.109649 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130093.230400 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130093.230400 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123609.109649 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123609.109649 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123609.109649 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123609.109649 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 617 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 60 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 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accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000649 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009565 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.184504 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000481 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000296 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011585 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.158911 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.062674 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000649 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009565 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.184504 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000481 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000296 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011585 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.158911 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.062674 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 122750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 127333.333333 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.453990 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.417423 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.435725 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009271 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011910 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010602 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.025203 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.021300 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023241 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000688 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009271 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.180642 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000286 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011910 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.163709 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.062775 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000688 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009271 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.180642 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000286 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011910 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.163709 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.062775 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 124500 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70817.211949 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70784.540702 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70801.275046 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 122750 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70812.861272 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70803.387334 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70808.169220 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116781.514727 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117326.893666 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 117033.472056 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120446.933962 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120738.886644 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120607.886822 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122228.169709 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121606.601033 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 121914.474220 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 122750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120446.933962 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117220.938255 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127333.333333 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116824.829679 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117354.534107 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117078.304141 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120547.099589 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120769.755571 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120673.257690 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122722.763980 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121158.612696 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122002.054063 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120547.099589 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117349.408448 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120738.886644 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117730.520420 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 117814.183220 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 122750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120446.933962 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117220.938255 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120769.755571 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117671.540656 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 117861.634983 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120547.099589 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117349.408448 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120738.886644 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117730.520420 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 117814.183220 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120769.755571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117671.540656 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 117861.634983 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177699.603306 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190696.288151 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 178593.892462 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163786.068227 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162147.785478 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162195.207154 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 162172.387546 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187709.397471 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172306.635956 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 174840.241990 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171239.049296 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172986.715720 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 170429.932045 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 183219.739391 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 170854.184528 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 163128.939173 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179998.763682 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 172583.580569 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70627 # Transaction distribution +system.membus.trans_dist::ReadResp 70546 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::Writeback 117457 # Transaction distribution -system.membus.trans_dist::CleanEvict 6338 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117374 # Transaction distribution +system.membus.trans_dist::CleanEvict 6393 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution -system.membus.trans_dist::ReadExReq 127036 # Transaction distribution -system.membus.trans_dist::ReadExResp 127036 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30467 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4499 # Transaction distribution +system.membus.trans_dist::ReadExReq 127159 # Transaction distribution +system.membus.trans_dist::ReadExResp 127159 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30386 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438779 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 546371 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438823 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 546415 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 655265 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 655309 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15304828 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15468181 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15302204 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15465557 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17785301 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17782677 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 492 # Total snoops (count) -system.membus.snoop_fanout::samples 389991 # Request fanout histogram +system.membus.snoop_fanout::samples 390002 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 389991 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 390002 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 389991 # Request fanout histogram -system.membus.reqLayer0.occupancy 90490000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 390002 # Request fanout histogram +system.membus.reqLayer0.occupancy 90453500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1693000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1722000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 821977659 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 823113783 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 952225245 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 952221498 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64492032 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64071640 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1920,59 +1931,60 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5059453 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2540884 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 38074 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 582 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 582 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5052869 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2537534 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 38120 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 75104 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2297700 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 74671 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2294380 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 802762 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1800707 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2769 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 801219 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1664516 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 134433 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2765 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2771 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296210 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296210 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1696651 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 525960 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2767 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295861 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295861 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1695803 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 523921 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5076713 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581153 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18522 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 35333 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7711721 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108619704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96660573 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26036 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 49608 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205355921 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 176740 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5302052 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.018353 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.134225 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5074132 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2573976 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18410 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34795 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7701313 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 215094328 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96414109 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26084 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 48692 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 311583213 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 176501 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2780821 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021276 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.144303 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5204742 98.16% 98.16% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 97310 1.84% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2721656 97.87% 97.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 59165 2.13% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5302052 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3269894500 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 2780821 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4960265000 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2553998500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2552726500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1279231000 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1275647499 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12013000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11889000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 22931000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 22622000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 838105743..cc979e9fa 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,55 +4,57 @@ sim_seconds 5.112152 # Nu sim_ticks 5112152301500 # Number of ticks simulated final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1349307 # Simulator instruction rate (inst/s) -host_op_rate 2762327 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34477807791 # Simulator tick rate (ticks/s) -host_mem_usage 659588 # Number of bytes of host memory used -host_seconds 148.27 # Real time elapsed on the host +host_inst_rate 1265336 # Simulator instruction rate (inst/s) +host_op_rate 2590419 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32332152611 # Simulator tick rate (ticks/s) +host_mem_usage 659496 # Number of bytes of host memory used +host_seconds 158.11 # Real time elapsed on the host sim_insts 200066731 # Number of instructions simulated sim_ops 409580371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 853568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10615616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 846912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10615104 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11497920 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 853568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 853568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9269440 # Number of bytes written to this memory -system.physmem.bytes_written::total 9269440 # Number of bytes written to this memory +system.physmem.bytes_read::total 11490752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 846912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 846912 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9270016 # Number of bytes written to this memory +system.physmem.bytes_written::total 9270016 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 13337 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165869 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 13233 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 165861 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 179655 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 144835 # Number of write requests responded to by this memory -system.physmem.num_writes::total 144835 # Number of write requests responded to by this memory +system.physmem.num_reads::total 179543 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 144844 # Number of write requests responded to by this memory +system.physmem.num_writes::total 144844 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 166968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2076545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 165666 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2076445 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2249135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 166968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 166968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1813217 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1813217 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1813217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 2247733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 165666 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 165666 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1813329 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1813329 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1813329 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 166968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2076545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 165666 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2076445 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 5546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4062352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4061062 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.numCycles 10224308568 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.committedInsts 200066731 # Number of instructions committed system.cpu.committedOps 409580371 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 374583495 # Number of integer alu accesses @@ -110,8 +112,6 @@ system.cpu.op_class::MemWrite 8423767 2.06% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 409581402 # Class of executed instruction -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.dcache.tags.replacements 1621902 # number of replacements system.cpu.dcache.tags.tagsinuse 511.999425 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 20181182 # Total number of references to valid blocks. @@ -279,6 +279,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 792216 # number of writebacks +system.cpu.icache.writebacks::total 792216 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.tags.replacements 3586 # number of replacements system.cpu.itb_walker_cache.tags.tagsinuse 3.026546 # Cycle average of tags in use @@ -335,22 +337,22 @@ system.cpu.itb_walker_cache.cache_copies 0 # nu system.cpu.itb_walker_cache.writebacks::writebacks 545 # number of writebacks system.cpu.itb_walker_cache.writebacks::total 545 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 106193 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64823.931305 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4340112 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 170151 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 25.507414 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 106204 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64823.931309 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4340224 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 170162 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.506423 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 51850.671935 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 51928.965552 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135113 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2531.452775 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10441.669005 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.791178 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2458.314401 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10436.513764 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.792373 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038627 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.159327 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.037511 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.159249 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.989135 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 63958 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id @@ -359,52 +361,56 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3349 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20908 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39411 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975922 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 39255968 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 39255968 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 1538777 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1538777 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 39255979 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39255979 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 1538777 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1538777 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 792205 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 792205 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 21 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 21 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 179780 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 179780 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 779384 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 779384 # number of ReadCleanReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 179774 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 179774 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 779488 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 779488 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6656 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 2896 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1275199 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1284751 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1275198 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1284750 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 6656 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 2896 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 779384 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1454979 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2243915 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 779488 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1454972 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2244012 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 6656 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 2896 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 779384 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1454979 # number of overall hits -system.cpu.l2cache.overall_hits::total 2243915 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 779488 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1454972 # number of overall hits +system.cpu.l2cache.overall_hits::total 2244012 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 1808 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 1808 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 134641 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 134641 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13338 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 13338 # number of ReadCleanReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 134647 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 134647 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13234 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 13234 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 1 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 32163 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 32169 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 32164 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 32170 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 13338 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 166804 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 180148 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 13234 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 166811 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 180051 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 13338 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 166804 # number of overall misses -system.cpu.l2cache.overall_misses::total 180148 # number of overall misses -system.cpu.l2cache.Writeback_accesses::writebacks 1538777 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1538777 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.inst 13234 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 166811 # number of overall misses +system.cpu.l2cache.overall_misses::total 180051 # number of overall misses +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1538777 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 1538777 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 792205 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 792205 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1829 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1829 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 314421 # number of ReadExReq accesses(hits+misses) @@ -427,24 +433,24 @@ system.cpu.l2cache.overall_accesses::cpu.data 1621783 system.cpu.l2cache.overall_accesses::total 2424063 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988518 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988518 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428219 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.428219 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016826 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016826 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428238 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.428238 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016694 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016694 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000150 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001724 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024601 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024427 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024602 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024428 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000150 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001724 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016826 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102852 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.074317 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016694 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102857 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.074277 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000150 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001724 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016826 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102852 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.074317 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016694 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102857 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.074277 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -453,8 +459,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98168 # number of writebacks -system.cpu.l2cache.writebacks::total 98168 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 98177 # number of writebacks +system.cpu.l2cache.writebacks::total 98177 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 4856313 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425286 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -466,8 +472,9 @@ system.cpu.toL2Bus.trans_dist::ReadReq 13857337 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 15971490 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13943 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13943 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1538777 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 880405 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1538777 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 792205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 88200 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2281 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 314426 # Transaction distribution @@ -479,17 +486,17 @@ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 10293 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 22163 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 35023462 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50735040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101436160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227550265 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 279335545 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 203459 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 18930673 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 330036665 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 203470 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 18930684 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.001304 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.042949 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 18911114 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 18911125 99.90% 99.90% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 14428 0.08% 99.97% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 5131 0.03% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram @@ -497,7 +504,7 @@ system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Re system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 18930673 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 18930684 # Request fanout histogram system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution system.iobus.trans_dist::WriteReq 57724 # Transaction distribution @@ -602,16 +609,16 @@ system.iocache.writebacks::writebacks 46667 # nu system.iocache.writebacks::total 46667 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 13857337 # Transaction distribution -system.membus.trans_dist::ReadResp 13903747 # Transaction distribution +system.membus.trans_dist::ReadResp 13903644 # Transaction distribution system.membus.trans_dist::WriteReq 13943 # Transaction distribution system.membus.trans_dist::WriteResp 13943 # Transaction distribution -system.membus.trans_dist::Writeback 144835 # Transaction distribution -system.membus.trans_dist::CleanEvict 8392 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2546 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2094 # Transaction distribution -system.membus.trans_dist::ReadExReq 134360 # Transaction distribution -system.membus.trans_dist::ReadExResp 134355 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 46410 # Transaction distribution +system.membus.trans_dist::WritebackDirty 144844 # Transaction distribution +system.membus.trans_dist::CleanEvict 8271 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2561 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2109 # Transaction distribution +system.membus.trans_dist::ReadExReq 134351 # Transaction distribution +system.membus.trans_dist::ReadExResp 134346 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 46307 # Transaction distribution system.membus.trans_dist::MessageReq 1696 # Transaction distribution system.membus.trans_dist::MessageResp 1696 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution @@ -620,32 +627,32 @@ system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slav system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 470559 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28213119 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 470253 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28212813 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142283 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 142283 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28358794 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28358488 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17793920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43218681 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17787328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43212089 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3044480 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3044480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 46269945 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46263353 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 14256770 # Request fanout histogram +system.membus.snoop_fanout::samples 14256561 # Request fanout histogram system.membus.snoop_fanout::mean 1.000119 # Request fanout histogram system.membus.snoop_fanout::stdev 0.010906 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 14255074 99.99% 99.99% # Request fanout histogram +system.membus.snoop_fanout::1 14254865 99.99% 99.99% # Request fanout histogram system.membus.snoop_fanout::2 1696 0.01% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 14256770 # Request fanout histogram +system.membus.snoop_fanout::total 14256561 # Request fanout histogram system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 75f6b48c4..8281393dd 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,130 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.194921 # Number of seconds simulated -sim_ticks 5194921252500 # Number of ticks simulated -final_tick 5194921252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.194978 # Number of seconds simulated +sim_ticks 5194978362500 # Number of ticks simulated +final_tick 5194978362500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 334832 # Simulator instruction rate (inst/s) -host_op_rate 645401 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13521111808 # Simulator tick rate (ticks/s) -host_mem_usage 605972 # Number of bytes of host memory used -host_seconds 384.21 # Real time elapsed on the host -sim_insts 128645145 # Number of instructions simulated -sim_ops 247968363 # Number of ops (including micro ops) simulated +host_inst_rate 1008714 # Simulator instruction rate (inst/s) +host_op_rate 1944281 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40800285815 # Simulator tick rate (ticks/s) +host_mem_usage 616472 # Number of bytes of host memory used +host_seconds 127.33 # Real time elapsed on the host +sim_insts 128436556 # Number of instructions simulated +sim_ops 247559471 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 824576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8975232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 821184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9031104 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 9828480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 824576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 824576 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8074432 # Number of bytes written to this memory -system.physmem.bytes_written::total 8074432 # Number of bytes written to this memory +system.physmem.bytes_read::total 9881024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 821184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 821184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8151488 # Number of bytes written to this memory +system.physmem.bytes_written::total 8151488 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12884 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140238 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12831 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141111 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 153570 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126163 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126163 # Number of write requests responded to by this memory +system.physmem.num_reads::total 154391 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 127367 # Number of write requests responded to by this memory +system.physmem.num_writes::total 127367 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158727 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1727694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1738430 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1891940 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158727 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158727 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1554293 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1554293 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1554293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 1902034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1569109 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1569109 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1569109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1727694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 158073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1738430 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 5458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3446234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 153570 # Number of read requests accepted -system.physmem.writeReqs 126163 # Number of write requests accepted -system.physmem.readBursts 153570 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 126163 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9818304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue -system.physmem.bytesWritten 8073216 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9828480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8074432 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 3471143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 154391 # Number of read requests accepted +system.physmem.writeReqs 127367 # Number of write requests accepted +system.physmem.readBursts 154391 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 127367 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9871424 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue +system.physmem.bytesWritten 8149376 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9881024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8151488 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48373 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9606 # Per bank write bursts -system.physmem.perBankRdBursts::1 9083 # Per bank write bursts -system.physmem.perBankRdBursts::2 10021 # Per bank write bursts -system.physmem.perBankRdBursts::3 9578 # Per bank write bursts -system.physmem.perBankRdBursts::4 9425 # Per bank write bursts -system.physmem.perBankRdBursts::5 9133 # Per bank write bursts -system.physmem.perBankRdBursts::6 9428 # Per bank write bursts -system.physmem.perBankRdBursts::7 9379 # Per bank write bursts -system.physmem.perBankRdBursts::8 9296 # Per bank write bursts -system.physmem.perBankRdBursts::9 9532 # Per bank write bursts -system.physmem.perBankRdBursts::10 9485 # Per bank write bursts -system.physmem.perBankRdBursts::11 9788 # Per bank write bursts -system.physmem.perBankRdBursts::12 9982 # Per bank write bursts -system.physmem.perBankRdBursts::13 10070 # Per bank write bursts -system.physmem.perBankRdBursts::14 9926 # Per bank write bursts -system.physmem.perBankRdBursts::15 9679 # Per bank write bursts -system.physmem.perBankWrBursts::0 8208 # Per bank write bursts -system.physmem.perBankWrBursts::1 7344 # Per bank write bursts -system.physmem.perBankWrBursts::2 8031 # Per bank write bursts -system.physmem.perBankWrBursts::3 7623 # Per bank write bursts -system.physmem.perBankWrBursts::4 7645 # Per bank write bursts -system.physmem.perBankWrBursts::5 7565 # Per bank write bursts -system.physmem.perBankWrBursts::6 7708 # Per bank write bursts -system.physmem.perBankWrBursts::7 7791 # Per bank write bursts -system.physmem.perBankWrBursts::8 7759 # Per bank write bursts -system.physmem.perBankWrBursts::9 7930 # Per bank write bursts -system.physmem.perBankWrBursts::10 7732 # Per bank write bursts -system.physmem.perBankWrBursts::11 7853 # Per bank write bursts -system.physmem.perBankWrBursts::12 8038 # Per bank write bursts -system.physmem.perBankWrBursts::13 8512 # Per bank write bursts -system.physmem.perBankWrBursts::14 8378 # Per bank write bursts -system.physmem.perBankWrBursts::15 8027 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 55287 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10087 # Per bank write bursts +system.physmem.perBankRdBursts::1 9529 # Per bank write bursts +system.physmem.perBankRdBursts::2 9814 # Per bank write bursts +system.physmem.perBankRdBursts::3 9652 # Per bank write bursts +system.physmem.perBankRdBursts::4 10130 # Per bank write bursts +system.physmem.perBankRdBursts::5 9950 # Per bank write bursts +system.physmem.perBankRdBursts::6 9317 # Per bank write bursts +system.physmem.perBankRdBursts::7 9200 # Per bank write bursts +system.physmem.perBankRdBursts::8 8918 # Per bank write bursts +system.physmem.perBankRdBursts::9 9357 # Per bank write bursts +system.physmem.perBankRdBursts::10 9066 # Per bank write bursts +system.physmem.perBankRdBursts::11 9331 # Per bank write bursts +system.physmem.perBankRdBursts::12 9713 # Per bank write bursts +system.physmem.perBankRdBursts::13 9915 # Per bank write bursts +system.physmem.perBankRdBursts::14 10131 # Per bank write bursts +system.physmem.perBankRdBursts::15 10131 # Per bank write bursts +system.physmem.perBankWrBursts::0 8252 # Per bank write bursts +system.physmem.perBankWrBursts::1 7742 # Per bank write bursts +system.physmem.perBankWrBursts::2 7578 # Per bank write bursts +system.physmem.perBankWrBursts::3 7566 # Per bank write bursts +system.physmem.perBankWrBursts::4 7987 # Per bank write bursts +system.physmem.perBankWrBursts::5 8326 # Per bank write bursts +system.physmem.perBankWrBursts::6 7980 # Per bank write bursts +system.physmem.perBankWrBursts::7 7858 # Per bank write bursts +system.physmem.perBankWrBursts::8 7446 # Per bank write bursts +system.physmem.perBankWrBursts::9 8118 # Per bank write bursts +system.physmem.perBankWrBursts::10 7706 # Per bank write bursts +system.physmem.perBankWrBursts::11 7948 # Per bank write bursts +system.physmem.perBankWrBursts::12 8417 # Per bank write bursts +system.physmem.perBankWrBursts::13 8510 # Per bank write bursts +system.physmem.perBankWrBursts::14 8023 # Per bank write bursts +system.physmem.perBankWrBursts::15 7877 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 5194921069000 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 5194978301500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 153570 # Read request sizes (log2) +system.physmem.readPktSize::6 154391 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 126163 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 150128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 47 # What read queue length does an incoming req see +system.physmem.writePktSize::6 127367 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151033 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2781 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -152,190 +156,192 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6125 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 6693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 8103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 8169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7071 # What write queue length does an incoming req see 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does an incoming req see -system.physmem.wrQLenPdf::42 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 55967 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 319.678668 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 191.248377 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.031309 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19371 34.61% 34.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 13720 24.51% 59.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6335 11.32% 70.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3428 6.13% 76.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2404 4.30% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1641 2.93% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1130 2.02% 85.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 964 1.72% 87.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6974 12.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 55967 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5838 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.276465 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 626.709863 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5837 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::59 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 56850 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 316.988566 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.998481 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.316521 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 20120 35.39% 35.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13756 24.20% 59.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6339 11.15% 70.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3490 6.14% 76.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2421 4.26% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1596 2.81% 83.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1162 2.04% 85.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 976 1.72% 87.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6990 12.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 56850 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5891 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.179766 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 623.896687 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5890 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5838 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5838 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.607400 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.425561 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.518520 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4794 82.12% 82.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 110 1.88% 84.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 38 0.65% 84.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 229 3.92% 88.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 28 0.48% 89.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 201 3.44% 92.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 72 1.23% 93.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.10% 93.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 12 0.21% 94.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 30 0.51% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.12% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.10% 94.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 233 3.99% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.09% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.07% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 31 0.53% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.05% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 16 0.27% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5838 # Writes before turning the bus around for reads -system.physmem.totQLat 1519267484 # Total ticks spent queuing -system.physmem.totMemAccLat 4395723734 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 767055000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9903.25 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5891 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5891 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.615006 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.434725 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.404388 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4837 82.11% 82.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 110 1.87% 83.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 36 0.61% 84.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 242 4.11% 88.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 18 0.31% 89.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 210 3.56% 92.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 69 1.17% 93.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.05% 93.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 13 0.22% 94.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 22 0.37% 94.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.14% 94.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.10% 94.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 244 4.14% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.08% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.07% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 27 0.46% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 18 0.31% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5891 # Writes before turning the bus around for reads +system.physmem.totQLat 1582264251 # Total ticks spent queuing +system.physmem.totMemAccLat 4474283001 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 771205000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10258.39 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28653.25 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.89 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.55 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.55 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29008.39 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.23 # Average write queue length when enqueuing -system.physmem.readRowHits 125316 # Number of row buffer hits during reads -system.physmem.writeRowHits 98271 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.69 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.89 # Row buffer hit rate for writes -system.physmem.avgGap 18570998.31 # Average gap between requests -system.physmem.pageHitRate 79.97 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 205775640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 112278375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 590093400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 401209200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 339306654960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 136710415665 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2997028284750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3474354711990 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.798995 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4985717890976 # Time in different power states -system.physmem_0.memoryStateTime::REF 173469660000 # Time in different power states +system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing +system.physmem.readRowHits 125535 # Number of row buffer hits during reads +system.physmem.writeRowHits 99190 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.39 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.88 # Row buffer hit rate for writes +system.physmem.avgGap 18437731.32 # Average gap between requests +system.physmem.pageHitRate 79.80 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 210712320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 114972000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 605896200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 410112720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 339310723440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 137072385045 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2996748141750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3474472943475 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.813734 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4985245725974 # Time in different power states +system.physmem_0.memoryStateTime::REF 173471480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35728632774 # Time in different power states +system.physmem_0.memoryStateTime::ACT 36261007776 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 217334880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 118585500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 606504600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 416203920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 339306654960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 137303660835 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2996507894250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3474476838945 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.822504 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4984854148228 # Time in different power states -system.physmem_1.memoryStateTime::REF 173469660000 # Time in different power states +system.physmem_1.actEnergy 219073680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 119534250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 597183600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 415011600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 339310723440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 137522699865 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2996353144500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3474537370935 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.826133 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4984581893484 # Time in different power states +system.physmem_1.memoryStateTime::REF 173471480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 36597272272 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36924866266 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10389842505 # number of cpu cycles simulated +system.cpu.numCycles 10389956725 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.committedInsts 128645145 # Number of instructions committed -system.cpu.committedOps 247968363 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232546069 # Number of integer alu accesses +system.cpu.committedInsts 128436556 # Number of instructions committed +system.cpu.committedOps 247559471 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232158304 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 2315361 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23194066 # number of instructions that are conditional controls -system.cpu.num_int_insts 232546069 # number of integer instructions +system.cpu.num_func_calls 2315823 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23152915 # number of instructions that are conditional controls +system.cpu.num_int_insts 232158304 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 435625855 # number of times the integer registers were read -system.cpu.num_int_register_writes 198317568 # number of times the integer registers were written +system.cpu.num_int_register_reads 434959162 # number of times the integer registers were read +system.cpu.num_int_register_writes 197962951 # number of times the integer registers were written system.cpu.num_fp_register_reads 48 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 133116486 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95666126 # number of times the CC registers were written -system.cpu.num_mem_refs 22339097 # number of memory refs -system.cpu.num_load_insts 13935932 # Number of load instructions -system.cpu.num_store_insts 8403165 # Number of store instructions -system.cpu.num_idle_cycles 9774871371.998117 # Number of idle cycles -system.cpu.num_busy_cycles 614971133.001882 # Number of busy cycles -system.cpu.not_idle_fraction 0.059190 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.940810 # Percentage of idle cycles -system.cpu.Branches 26367781 # Number of branches fetched -system.cpu.op_class::No_OpClass 172241 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 225200249 90.82% 90.89% # Class of executed instruction -system.cpu.op_class::IntMult 140056 0.06% 90.94% # Class of executed instruction -system.cpu.op_class::IntDiv 123237 0.05% 90.99% # Class of executed instruction +system.cpu.num_cc_register_reads 132872909 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95460932 # number of times the CC registers were written +system.cpu.num_mem_refs 22321110 # number of memory refs +system.cpu.num_load_insts 13911495 # Number of load instructions +system.cpu.num_store_insts 8409615 # Number of store instructions +system.cpu.num_idle_cycles 9773995534.086119 # Number of idle cycles +system.cpu.num_busy_cycles 615961190.913881 # Number of busy cycles +system.cpu.not_idle_fraction 0.059284 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.940716 # Percentage of idle cycles +system.cpu.Branches 26327381 # Number of branches fetched +system.cpu.op_class::No_OpClass 172225 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 224809718 90.81% 90.88% # Class of executed instruction +system.cpu.op_class::IntMult 140099 0.06% 90.94% # Class of executed instruction +system.cpu.op_class::IntDiv 122811 0.05% 90.99% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction @@ -362,213 +368,214 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction -system.cpu.op_class::MemRead 13930960 5.62% 96.61% # Class of executed instruction -system.cpu.op_class::MemWrite 8403165 3.39% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 13906523 5.62% 96.60% # Class of executed instruction +system.cpu.op_class::MemWrite 8409615 3.40% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 247969924 # Class of executed instruction -system.cpu.dcache.tags.replacements 1623328 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.995361 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20131141 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1623840 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.397244 # Average number of references to valid blocks. +system.cpu.op_class::total 247561007 # Class of executed instruction +system.cpu.dcache.tags.replacements 1623701 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.995481 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20139430 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1624213 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.399501 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 81561500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.995361 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.995481 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999991 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 284 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 123 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88683226 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88683226 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12000892 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12000892 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8069414 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8069414 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 58662 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 58662 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20070306 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20070306 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20128968 # number of overall hits -system.cpu.dcache.overall_hits::total 20128968 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 906883 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 906883 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 325772 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 325772 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 403210 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 403210 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1232655 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1232655 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1635865 # number of overall misses -system.cpu.dcache.overall_misses::total 1635865 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13550557000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13550557000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18295357977 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18295357977 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31845914977 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31845914977 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31845914977 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31845914977 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12907775 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12907775 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8395186 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8395186 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461872 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461872 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21302961 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21302961 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21764833 # number of overall (read+write) accesses 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accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12002647 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12002647 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8075474 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8075474 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 59092 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 59092 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20078121 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20078121 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20137213 # number of overall hits +system.cpu.dcache.overall_hits::total 20137213 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 907310 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 907310 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 326145 # number of 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accesses +system.cpu.dcache.demand_miss_rate::total 0.057877 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075149 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075149 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14947.894876 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14947.894876 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56563.781358 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56563.781358 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25951.793110 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25951.793110 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19563.226796 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19563.226796 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18014 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 441 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 511 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.226757 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.252446 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1540461 # number of writebacks -system.cpu.dcache.writebacks::total 1540461 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 292 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 292 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9470 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9470 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9762 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9762 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9762 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9762 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906591 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 906591 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316302 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 316302 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403174 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 403174 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1222893 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1222893 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1626067 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1626067 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 572954 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 572954 # number of ReadReq MSHR uncacheable +system.cpu.dcache.writebacks::writebacks 1540806 # number of writebacks +system.cpu.dcache.writebacks::total 1540806 # number of writebacks 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WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402763 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 402763 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1223692 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1223692 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1626455 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1626455 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 546346 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 546346 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13920 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 13920 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 586874 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 586874 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12641489000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12641489000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17000944477 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17000944477 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6508610000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6508610000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29642433477 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29642433477 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36151043477 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36151043477 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94684331000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94684331000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2622740500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2622740500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97307071500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 97307071500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070236 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070236 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037677 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037677 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.872913 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.872913 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057405 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057405 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074711 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074711 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13943.982457 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13943.982457 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53749.089405 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53749.089405 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16143.426907 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16143.426907 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24239.596986 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24239.596986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22232.197983 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22232.197983 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 165256.427218 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165256.427218 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188415.265805 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188415.265805 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 165805.729168 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 165805.729168 # average overall mshr uncacheable latency +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 560266 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 560266 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12653263500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12653263500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17148578471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17148578471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6516458500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6516458500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29801841971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29801841971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36318300471 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36318300471 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 95164003500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 95164003500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2786304500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2786304500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97950308000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 97950308000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070258 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070258 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037691 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037691 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871991 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871991 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057419 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057419 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074699 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074699 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13950.322649 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13950.322649 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54153.006676 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54153.006676 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16179.387133 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16179.387133 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24354.038411 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24354.038411 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22329.729670 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22329.729670 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 174182.667211 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174182.667211 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200165.553161 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200165.553161 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 174828.220881 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 174828.220881 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7724 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.052199 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13169 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7738 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.701861 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5166372049500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052199 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.replacements 7583 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.052194 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13349 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7599 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.756679 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5163389935000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052194 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315762 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315762 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 53153 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 53153 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13186 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13186 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13186 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13186 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13186 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13186 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8927 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8927 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8927 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8927 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8927 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8927 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97243000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97243000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97243000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 97243000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97243000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 97243000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22113 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22113 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22113 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22113 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22113 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22113 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403699 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403699 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403699 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403699 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403699 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403699 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10893.133191 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10893.133191 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10893.133191 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10893.133191 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10893.133191 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10893.133191 # average overall miss latency +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 53077 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 53077 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13349 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13349 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13349 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13349 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13349 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13349 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8793 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8793 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8793 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8793 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8793 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8793 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 96493000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 96493000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 96493000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 96493000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 96493000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 96493000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22142 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22142 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22142 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22142 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22142 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22142 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.397119 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.397119 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.397119 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.397119 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.397119 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.397119 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10973.842830 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10973.842830 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10973.842830 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10973.842830 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10973.842830 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10973.842830 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -577,86 +584,86 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2877 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2877 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8927 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8927 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8927 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8927 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8927 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8927 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 88316000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 88316000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 88316000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 88316000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 88316000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 88316000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.403699 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.403699 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.403699 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.403699 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.403699 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.403699 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9893.133191 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9893.133191 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9893.133191 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9893.133191 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9893.133191 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9893.133191 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2984 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2984 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8793 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8793 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8793 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8793 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8793 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8793 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 87700000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 87700000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 87700000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 87700000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 87700000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 87700000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.397119 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.397119 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.397119 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.397119 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.397119 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.397119 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9973.842830 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9973.842830 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9973.842830 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9973.842830 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9973.842830 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9973.842830 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 789867 # number of replacements -system.cpu.icache.tags.tagsinuse 510.214824 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 144930125 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 790379 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 183.367884 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 164495636500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.214824 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996513 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996513 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 790533 # number of replacements +system.cpu.icache.tags.tagsinuse 510.212427 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144635656 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 791045 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 182.841249 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 164582664500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.212427 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996509 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996509 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 292 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146510897 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146510897 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 144930125 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144930125 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144930125 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144930125 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144930125 # number of overall hits -system.cpu.icache.overall_hits::total 144930125 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 790386 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 790386 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 790386 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 790386 # number of demand (read+write) misses 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(read+write) accesses -system.cpu.icache.demand_accesses::total 145720511 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145720511 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145720511 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005424 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005424 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005424 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005424 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005424 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005424 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14972.069976 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14972.069976 # average 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overall hits +system.cpu.l2cache.overall_hits::total 2269013 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1406 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1406 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 113512 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 113512 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 12832 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 12832 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 1 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28510 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 28515 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 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UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 314123 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 314123 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 790373 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 790373 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 6514 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 3106 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1309075 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1318695 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6514 # number of demand (read+write) accesses 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# mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358630 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016302 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.001610 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.021779 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.021624 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001610 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.086967 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063575 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001610 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.086967 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063575 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71385.581062 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71385.581062 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 116872.015197 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 116872.015197 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121237.834692 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121237.834692 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.814600 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.814600 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.360990 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.360990 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016222 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016222 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000154 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.001748 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.021767 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.021618 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000154 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001748 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016222 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087470 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063883 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000154 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001748 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016222 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087470 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063883 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71413.584637 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71413.584637 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117230.869864 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117230.869864 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121856.452618 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121856.452618 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 137000 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 117500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121074.096808 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121073.470103 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121568.803959 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121568.631579 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 137000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121237.834692 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117720.683035 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118014.848689 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121856.452618 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118101.291495 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118412.586216 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 137000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121237.834692 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117720.683035 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118014.848689 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 152756.423727 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152756.423727 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176915.265805 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176915.265805 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 153329.444651 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 153329.444651 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121856.452618 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118101.291495 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118412.586216 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161682.658059 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161682.658059 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188665.409483 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188665.409483 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162353.053728 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 162353.053728 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4854729 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2424193 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12092 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1088 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1088 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4855760 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425141 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11068 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1020 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1020 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 572954 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2686987 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 546346 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2660535 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13920 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13920 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1670227 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2186 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2186 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 314129 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 314129 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 790386 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1324171 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1671932 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 790520 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 91754 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 314452 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 314452 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 791052 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1323668 # Transaction distribution system.cpu.toL2Bus.trans_dist::MessageReq 1654 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2370613 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6047740 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9205 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19678 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8447236 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50583872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204138427 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 244928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 601024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 255568251 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 188441 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5624579 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004514 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.080591 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2372611 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5995602 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8612 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19573 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8396398 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101219776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204103208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 232576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 605248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 306160808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 189298 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3174836 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004492 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.077863 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5604820 99.65% 99.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 14130 0.25% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 5629 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3163102 99.63% 99.63% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 9208 0.29% 99.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 2526 0.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5624579 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4271820500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3174836 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5050069000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 588787 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 571290 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1185579000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1186578000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3016848998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2990781992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6949500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6370500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13390500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 13189500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 226550 # Transaction distribution -system.iobus.trans_dist::ReadResp 226550 # Transaction distribution +system.iobus.trans_dist::ReadReq 216035 # Transaction distribution +system.iobus.trans_dist::ReadResp 216035 # Transaction distribution system.iobus.trans_dist::WriteReq 57726 # Transaction distribution system.iobus.trans_dist::WriteResp 57726 # Transaction distribution system.iobus.trans_dist::MessageReq 1654 # Transaction distribution @@ -1089,7 +1129,7 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 429188 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 408166 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) @@ -1099,12 +1139,12 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 473420 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95132 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95132 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 452398 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 571860 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 550830 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -1113,7 +1153,7 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 214594 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 204083 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) @@ -1123,96 +1163,96 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 242990 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 232479 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027280 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3276918 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3944816 # Layer occupancy (ticks) +system.iobus.pkt_size::total 3266375 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4013816 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10045000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 149500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 1094500 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 79000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 50500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 214595000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 306124500 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 1113000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) +system.iobus.reqLayer11.occupancy 177500 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 24284500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 240989862 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 240815899 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 1067000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 462414000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 441392000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 50044000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 50036000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47511 # number of replacements -system.iocache.tags.tagsinuse 0.108299 # Cycle average of tags in use +system.iocache.tags.replacements 47507 # number of replacements +system.iocache.tags.tagsinuse 0.108263 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47527 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47523 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5048321264000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108299 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006769 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006769 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5048362105000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108263 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006766 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006766 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428094 # Number of tag accesses -system.iocache.tags.data_accesses 428094 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 846 # number of ReadReq misses -system.iocache.ReadReq_misses::total 846 # number of ReadReq misses +system.iocache.tags.tag_accesses 428058 # Number of tag accesses +system.iocache.tags.data_accesses 428058 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 842 # number of ReadReq misses +system.iocache.ReadReq_misses::total 842 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 846 # number of demand (read+write) misses -system.iocache.demand_misses::total 846 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 846 # number of overall misses -system.iocache.overall_misses::total 846 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144199688 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 144199688 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6059543174 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 6059543174 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 144199688 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 144199688 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 144199688 # number of overall miss cycles -system.iocache.overall_miss_latency::total 144199688 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 846 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 846 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 842 # number of demand (read+write) misses +system.iocache.demand_misses::total 842 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 842 # number of overall misses +system.iocache.overall_misses::total 842 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141163690 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 141163690 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6072614209 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 6072614209 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 141163690 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 141163690 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 141163690 # number of overall miss cycles +system.iocache.overall_miss_latency::total 141163690 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 842 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 842 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 846 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 846 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 846 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 846 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 842 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 842 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 842 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 842 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1221,40 +1261,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170448.803783 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 170448.803783 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129699.126156 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129699.126156 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170448.803783 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 170448.803783 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170448.803783 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 170448.803783 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 693 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167652.838480 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 167652.838480 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129978.900021 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129978.900021 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167652.838480 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 167652.838480 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167652.838480 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 167652.838480 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 694 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 36 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 67 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 19.250000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.358209 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 846 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 846 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 842 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 842 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 846 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 846 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 846 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 846 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101899688 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 101899688 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3723543174 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3723543174 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 101899688 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 101899688 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 101899688 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 101899688 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 842 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 842 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 842 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 842 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99063690 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 99063690 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3736614209 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3736614209 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 99063690 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 99063690 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 99063690 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 99063690 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1263,73 +1303,73 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 120448.803783 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79699.126156 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79699.126156 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 120448.803783 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 120448.803783 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117652.838480 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 117652.838480 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79978.900021 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79978.900021 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117652.838480 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 117652.838480 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117652.838480 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 117652.838480 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 572954 # Transaction distribution -system.membus.trans_dist::ReadResp 615200 # Transaction distribution +system.membus.trans_dist::ReadReq 546346 # Transaction distribution +system.membus.trans_dist::ReadResp 588520 # Transaction distribution system.membus.trans_dist::WriteReq 13920 # Transaction distribution system.membus.trans_dist::WriteResp 13920 # Transaction distribution -system.membus.trans_dist::Writeback 126163 # Transaction distribution -system.membus.trans_dist::CleanEvict 7113 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2165 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1671 # Transaction distribution -system.membus.trans_dist::ReadExReq 112377 # Transaction distribution -system.membus.trans_dist::ReadExResp 112377 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 42246 # Transaction distribution +system.membus.trans_dist::WritebackDirty 127367 # Transaction distribution +system.membus.trans_dist::CleanEvict 6933 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1652 # Transaction distribution +system.membus.trans_dist::ReadExReq 113266 # Transaction distribution +system.membus.trans_dist::ReadExResp 113266 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 42174 # Transaction distribution system.membus.trans_dist::MessageReq 1654 # Transaction distribution system.membus.trans_dist::MessageResp 1654 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 473420 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 396961 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1570709 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141766 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141766 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1715783 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 452398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 668134 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 399599 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1520131 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1665201 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242990 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400653 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14887872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16531515 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 232479 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1336265 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15017472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16586216 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19553171 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1565 # Total snoops (count) -system.membus.snoop_fanout::samples 925791 # Request fanout histogram -system.membus.snoop_fanout::mean 1.001787 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.042230 # Request fanout histogram +system.membus.pkt_size::total 19607872 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1571 # Total snoops (count) +system.membus.snoop_fanout::samples 901008 # Request fanout histogram +system.membus.snoop_fanout::mean 1.001836 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.042806 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 924137 99.82% 99.82% # Request fanout histogram +system.membus.snoop_fanout::1 899354 99.82% 99.82% # Request fanout histogram system.membus.snoop_fanout::2 1654 0.18% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 925791 # Request fanout histogram -system.membus.reqLayer0.occupancy 359890000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 901008 # Request fanout histogram +system.membus.reqLayer0.occupancy 344294500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 527983500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 503567500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 4013184 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 843164843 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 852595093 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 2359184 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2152042345 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1928197366 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 85908558 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 85638132 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 58b2620bf..54de45ea3 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 21900500 # Number of ticks simulated final_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94413 # Simulator instruction rate (inst/s) -host_op_rate 94393 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 324370159 # Simulator tick rate (ticks/s) -host_mem_usage 297000 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 101932 # Simulator instruction rate (inst/s) +host_op_rate 101910 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 350189482 # Simulator tick rate (ticks/s) +host_mem_usage 296592 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index e7401ee31..d82a69683 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 32545500 # Number of ticks simulated -final_tick 32545500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000036 # Number of seconds simulated +sim_ticks 35667500 # Number of ticks simulated +final_tick 35667500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 507828 # Simulator instruction rate (inst/s) -host_op_rate 507304 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2581337246 # Simulator tick rate (ticks/s) -host_mem_usage 294696 # Number of bytes of host memory used +host_inst_rate 607241 # Simulator instruction rate (inst/s) +host_op_rate 606492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3381446720 # Simulator tick rate (ticks/s) +host_mem_usage 294520 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 546680801 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 330368254 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 877049054 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 546680801 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 546680801 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 546680801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 330368254 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 877049054 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 498829467 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 301450901 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 800280367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 498829467 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498829467 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 498829467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 301450901 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 800280367 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 65091 # number of cpu cycles simulated +system.cpu.numCycles 71335 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -82,7 +82,7 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 65091 # Number of busy cycles +system.cpu.num_busy_cycles 71335 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched @@ -122,17 +122,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.756988 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.427155 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.756988 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025331 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025331 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.427155 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025251 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025251 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses @@ -152,14 +152,14 @@ system.cpu.dcache.demand_misses::cpu.data 168 # n system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses system.cpu.dcache.overall_misses::total 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5890000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5890000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4526000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4526000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10416000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10416000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10416000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10416000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -176,14 +176,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,14 +200,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5130000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5130000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3942000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3942000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9072000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9072000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9072000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9072000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5795000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5795000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4453000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4453000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10248000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10248000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10248000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10248000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -216,27 +216,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 127.992231 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 127.519931 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 127.992231 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 127.519931 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062266 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062266 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 13081 # Number of tag accesses system.cpu.icache.tags.data_accesses 13081 # Number of data accesses @@ -252,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 279 # n system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses system.cpu.icache.overall_misses::total 279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15304500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15304500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15304500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15304500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15304500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15304500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17250500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17250500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17250500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17250500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17250500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17250500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses @@ -270,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54854.838710 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54854.838710 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54854.838710 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54854.838710 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54854.838710 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54854.838710 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61829.749104 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61829.749104 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61829.749104 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61829.749104 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -290,39 +290,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 279 system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15025500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15025500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15025500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15025500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15025500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15025500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16971500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16971500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16971500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16971500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16971500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16971500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53854.838710 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53854.838710 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53854.838710 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53854.838710 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53854.838710 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53854.838710 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60829.749104 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60829.749104 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.470347 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 183.843350 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.998222 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.472125 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003906 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001723 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.517941 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.325409 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003892 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001719 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005610 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses @@ -344,18 +344,18 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3832500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3832500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14595500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 14595500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4987500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4987500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8820000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23415500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8820000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23415500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4343500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4343500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5652500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5652500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9996000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 26537500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9996000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26537500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 279 # number of ReadCleanReq accesses(hits+misses) @@ -380,18 +380,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997763 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52501.121076 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52501.121076 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59501.121076 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59501.121076 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,18 +412,18 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3102500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3102500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11815500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11815500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4037500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4037500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11815500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7140000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18955500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11815500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7140000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18955500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3613500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3613500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4702500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4702500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8316000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22077500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8316000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22077500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadCleanReq accesses @@ -436,18 +436,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -479,11 +479,11 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadResp 373 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution @@ -504,8 +504,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 446 # Request fanout histogram system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2230500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.9 # Layer utilization (%) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2230000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index c4983f8bd..bedd68076 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000012 # Nu sim_ticks 12363500 # Number of ticks simulated final_tick 12363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79745 # Simulator instruction rate (inst/s) -host_op_rate 79707 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 412680664 # Simulator tick rate (ticks/s) -host_mem_usage 295680 # Number of bytes of host memory used +host_inst_rate 83593 # Simulator instruction rate (inst/s) +host_op_rate 83552 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 432562452 # Simulator tick rate (ticks/s) +host_mem_usage 295260 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 6bacfac4e..9e7b361e2 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16524500 # Number of ticks simulated -final_tick 16524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000018 # Number of seconds simulated +sim_ticks 18239500 # Number of ticks simulated +final_tick 18239500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 315037 # Simulator instruction rate (inst/s) -host_op_rate 314537 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2013954906 # Simulator tick rate (ticks/s) -host_mem_usage 293376 # Number of bytes of host memory used +host_inst_rate 407753 # Simulator instruction rate (inst/s) +host_op_rate 406852 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2874172707 # Simulator tick rate (ticks/s) +host_mem_usage 293212 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 10432 # Nu system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory system.physmem.num_reads::total 245 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 631305032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 317589034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 948894066 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 631305032 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 631305032 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 631305032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 317589034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 948894066 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 571945503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 287727186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 859672688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 571945503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 571945503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 571945503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 287727186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 859672688 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 33049 # number of cpu cycles simulated +system.cpu.numCycles 36479 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -82,7 +82,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 33049 # Number of busy cycles +system.cpu.num_busy_cycles 36479 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched @@ -122,17 +122,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 47.431392 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 47.277997 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 47.431392 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011580 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011580 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 47.277997 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011542 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011542 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses @@ -152,14 +152,14 @@ system.cpu.dcache.demand_misses::cpu.data 82 # n system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses system.cpu.dcache.overall_misses::total 82 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3410000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3410000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1674000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1674000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 5084000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 5084000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 5084000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 5084000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -176,14 +176,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,14 +200,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 82 system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2970000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2970000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1458000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1458000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4428000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4428000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4428000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4428000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3355000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3355000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1647000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1647000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5002000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5002000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5002000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5002000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses @@ -216,27 +216,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 80.038009 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 79.677134 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 80.038009 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.039081 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.039081 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 79.677134 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.038905 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.038905 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.079590 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 5335 # Number of tag accesses system.cpu.icache.tags.data_accesses 5335 # Number of data accesses @@ -252,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 163 # n system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses system.cpu.icache.overall_misses::total 163 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8965500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8965500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8965500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8965500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8965500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8965500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 10106500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 10106500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 10106500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 10106500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 10106500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 10106500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses @@ -270,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55003.067485 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55003.067485 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55003.067485 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55003.067485 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55003.067485 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55003.067485 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62003.067485 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62003.067485 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62003.067485 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62003.067485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62003.067485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62003.067485 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -290,39 +290,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 163 system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8802500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 8802500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8802500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 8802500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8802500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 8802500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9943500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9943500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9943500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9943500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9943500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9943500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54003.067485 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54003.067485 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54003.067485 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54003.067485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54003.067485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54003.067485 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61003.067485 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61003.067485 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61003.067485 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61003.067485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 107.126637 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 106.649585 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.141583 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 26.985054 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002446 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003269 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.770969 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 26.878617 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002434 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000820 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003255 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 218 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.006653 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2205 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2205 # Number of data accesses @@ -338,18 +338,18 @@ system.cpu.l2cache.demand_misses::total 245 # nu system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses system.cpu.l2cache.overall_misses::total 245 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1417500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1417500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8558000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 8558000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2887500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2887500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 8558000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4305000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12863000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 8558000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4305000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12863000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1606500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1606500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9699000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 9699000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3272500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3272500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9699000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4879000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14578000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9699000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4879000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14578000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 163 # number of ReadCleanReq accesses(hits+misses) @@ -374,18 +374,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52503.067485 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52503.067485 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52502.040816 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52502.040816 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.067485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.067485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.067485 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59502.040816 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.067485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59502.040816 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -406,18 +406,18 @@ system.cpu.l2cache.demand_mshr_misses::total 245 system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1147500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1147500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 6928000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 6928000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2337500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2337500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6928000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3485000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10413000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6928000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3485000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10413000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1336500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1336500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8069000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8069000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2722500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2722500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8069000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4059000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12128000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8069000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4059000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12128000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -430,18 +430,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42503.067485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42503.067485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42503.067485 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42502.040816 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.067485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42502.040816 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.067485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.067485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.067485 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49502.040816 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.067485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49502.040816 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -475,7 +475,7 @@ system.cpu.toL2Bus.snoop_fanout::total 245 # Re system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 244500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadResp 218 # Transaction distribution @@ -498,8 +498,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 245 # Request fanout histogram system.membus.reqLayer0.occupancy 245500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1225500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 7.4 # Layer utilization (%) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1225000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index ffa31a0bc..084d8789f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000030 # Nu sim_ticks 29949500 # Number of ticks simulated final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110305 # Simulator instruction rate (inst/s) -host_op_rate 129095 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 716958322 # Simulator tick rate (ticks/s) -host_mem_usage 313816 # Number of bytes of host memory used +host_inst_rate 117235 # Simulator instruction rate (inst/s) +host_op_rate 137200 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 761957462 # Simulator tick rate (ticks/s) +host_mem_usage 313960 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated @@ -567,6 +567,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 3 # number of writebacks +system.cpu.icache.writebacks::total 3 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses @@ -609,6 +611,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 253 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4181 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4181 # Number of data accesses +system.cpu.l2cache.WritebackClean_hits::writebacks 2 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 2 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 17 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits @@ -643,6 +647,8 @@ system.cpu.l2cache.demand_miss_latency::total 31692000 system.cpu.l2cache.overall_miss_latency::cpu.inst 22597500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 9094500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 31692000 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 2 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 2 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses) @@ -749,7 +755,7 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution @@ -757,22 +763,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20736 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30080 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 471 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.101911 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.302853 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.300891 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 423 89.81% 89.81% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 48 10.19% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 421 89.96% 89.96% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 47 10.04% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 471 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 238500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 0d7cf1bb4..120cb7565 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 17170000 # Number of ticks simulated final_tick 17170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50361 # Simulator instruction rate (inst/s) -host_op_rate 58973 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 188251031 # Simulator tick rate (ticks/s) -host_mem_usage 313812 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 54905 # Simulator instruction rate (inst/s) +host_op_rate 64292 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 205230571 # Simulator tick rate (ticks/s) +host_mem_usage 313448 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -979,6 +979,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 86.400000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 1 # number of writebacks +system.cpu.icache.writebacks::total 1 # number of writebacks system.cpu.icache.ReadReq_mshr_hits::cpu.inst 93 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 93 # number of demand (read+write) MSHR hits @@ -1178,18 +1180,18 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.102041 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.303046 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.100000 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.300341 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 396 89.80% 89.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 45 10.20% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 396 90.00% 90.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 44 10.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 221500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 8015f8322..985aedbbf 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 17778000 # Number of ticks simulated -final_tick 17778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000019 # Number of seconds simulated +sim_ticks 18741000 # Number of ticks simulated +final_tick 18741000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58925 # Simulator instruction rate (inst/s) -host_op_rate 69000 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 228057572 # Simulator tick rate (ticks/s) -host_mem_usage 310616 # Number of bytes of host memory used +host_inst_rate 59386 # Simulator instruction rate (inst/s) +host_op_rate 69540 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 242288300 # Simulator tick rate (ticks/s) +host_mem_usage 309720 # Number of bytes of host memory used host_seconds 0.08 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 18432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory -system.physmem.bytes_read::total 25984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28224 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 18432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 18432 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 288 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 126 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory -system.physmem.num_reads::total 406 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 975587805 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 388795140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 97198785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1461581730 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 975587805 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 975587805 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 975587805 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 388795140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 97198785 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1461581730 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 407 # Number of read requests accepted +system.physmem.num_reads::total 441 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 983512086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 430286538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 92204258 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1506002881 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 983512086 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 983512086 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 983512086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 430286538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 92204258 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1506002881 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 442 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 407 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 442 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26048 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 28288 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26048 # Total read bytes from the system interface side +system.physmem.bytesReadSys 28288 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 88 # Per bank write bursts -system.physmem.perBankRdBursts::1 45 # Per bank write bursts +system.physmem.perBankRdBursts::0 101 # Per bank write bursts +system.physmem.perBankRdBursts::1 48 # Per bank write bursts system.physmem.perBankRdBursts::2 19 # Per bank write bursts system.physmem.perBankRdBursts::3 44 # Per bank write bursts -system.physmem.perBankRdBursts::4 18 # Per bank write bursts -system.physmem.perBankRdBursts::5 32 # Per bank write bursts -system.physmem.perBankRdBursts::6 37 # Per bank write bursts +system.physmem.perBankRdBursts::4 19 # Per bank write bursts +system.physmem.perBankRdBursts::5 37 # Per bank write bursts +system.physmem.perBankRdBursts::6 46 # Per bank write bursts system.physmem.perBankRdBursts::7 10 # Per bank write bursts system.physmem.perBankRdBursts::8 4 # Per bank write bursts -system.physmem.perBankRdBursts::9 7 # Per bank write bursts -system.physmem.perBankRdBursts::10 26 # Per bank write bursts +system.physmem.perBankRdBursts::9 8 # Per bank write bursts +system.physmem.perBankRdBursts::10 27 # Per bank write bursts system.physmem.perBankRdBursts::11 47 # Per bank write bursts system.physmem.perBankRdBursts::12 17 # Per bank write bursts -system.physmem.perBankRdBursts::13 7 # Per bank write bursts +system.physmem.perBankRdBursts::13 8 # Per bank write bursts system.physmem.perBankRdBursts::14 0 # Per bank write bursts -system.physmem.perBankRdBursts::15 6 # Per bank write bursts +system.physmem.perBankRdBursts::15 7 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17764500 # Total gap between requests +system.physmem.totGap 18727500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 407 # Read request sizes (log2) +system.physmem.readPktSize::6 442 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,11 +94,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see @@ -190,79 +190,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 419.796610 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 279.431145 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 356.786751 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8 13.56% 13.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 32.20% 45.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 15.25% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 5.08% 66.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 3.39% 69.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 5.08% 74.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 5.08% 79.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.39% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 16.95% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation -system.physmem.totQLat 3121500 # Total ticks spent queuing -system.physmem.totMemAccLat 10752750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7669.53 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 425.650794 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 288.378165 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.476918 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21 33.33% 44.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 11.11% 68.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 5 7.94% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 1.59% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.17% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 12 19.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation +system.physmem.totQLat 3434000 # Total ticks spent queuing +system.physmem.totMemAccLat 11721500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2210000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7769.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26419.53 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1465.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26519.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1509.42 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1465.18 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1509.42 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.45 # Data bus utilization in percentage -system.physmem.busUtilRead 11.45 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.79 # Data bus utilization in percentage +system.physmem.busUtilRead 11.79 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.81 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 340 # Number of row buffer hits during reads +system.physmem.readRowHits 370 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43647.42 # Average gap between requests -system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined +system.physmem.avgGap 42369.91 # Average gap between requests +system.physmem.pageHitRate 83.71 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2160600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10769580 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 63750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14349765 # Total energy per rank (pJ) -system.physmem_0.averagePower 905.276555 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 315250 # Time in different power states +system.physmem_0.actBackEnergy 10786680 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 37500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14457615 # Total energy per rank (pJ) +system.physmem_0.averagePower 913.160587 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 7000 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15294250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15319250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 811200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10147140 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 598500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12757005 # Total energy per rank (pJ) -system.physmem_1.averagePower 805.747987 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 956000 # Time in different power states +system.physmem_1.actBackEnergy 9859005 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 851250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12737220 # Total energy per rank (pJ) +system.physmem_1.averagePower 804.498342 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2184750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14370250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 13949750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2336 # Number of BP lookups -system.cpu.branchPred.condPredicted 1386 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2341 # Number of BP lookups +system.cpu.branchPred.condPredicted 1389 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 508 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 837 # Number of BTB lookups -system.cpu.branchPred.BTBHits 442 # Number of BTB hits +system.cpu.branchPred.BTBLookups 838 # Number of BTB lookups +system.cpu.branchPred.BTBHits 447 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 52.807646 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 289 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 53.341289 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 290 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,84 +380,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 35557 # number of cpu cycles simulated +system.cpu.numCycles 37483 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6181 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11260 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2336 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 731 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 7643 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 6059 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11274 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2341 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 737 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 8204 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1059 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.MiscStallCycles 143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 322 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3826 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 175 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15133 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.869491 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.207772 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 363 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3834 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 177 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15601 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.845843 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.199579 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8934 59.04% 59.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2459 16.25% 75.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 521 3.44% 78.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3219 21.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9385 60.16% 60.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2463 15.79% 75.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 526 3.37% 79.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3227 20.68% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15133 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.065697 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.316675 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5932 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3662 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5040 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 368 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 15601 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.062455 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.300776 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5749 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4322 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5029 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 369 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 331 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 9865 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1623 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 368 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7001 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 962 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1967 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4096 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 739 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 8887 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 410 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full +system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 9880 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1586 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 369 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6811 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1118 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2339 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4089 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 875 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 8892 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 417 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 665 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9238 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 40311 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9765 # Number of integer rename lookups +system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 772 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9259 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40331 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9781 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3744 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 30 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 299 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1809 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1277 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3765 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 29 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1800 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1272 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8352 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsAdded 8358 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 7148 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 188 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3013 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7853 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15133 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.472345 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.858310 # Number of insts issued each cycle +system.cpu.iq.iqSquashedInstsIssued 184 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3018 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7856 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 15601 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.458176 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.848338 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10931 72.23% 72.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1952 12.90% 85.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1600 10.57% 95.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 604 3.99% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 46 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11391 73.01% 73.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1965 12.60% 85.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1598 10.24% 95.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 601 3.85% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 46 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -466,149 +465,149 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15133 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15601 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 412 28.91% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 465 32.63% 61.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 548 38.46% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 413 28.70% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 475 33.01% 61.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 551 38.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4470 62.53% 62.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1589 22.23% 84.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1081 15.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4480 62.67% 62.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1582 22.13% 84.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1078 15.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 7148 # Type of FU issued -system.cpu.iq.rate 0.201029 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1425 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.199356 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30998 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11395 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6553 # Number of integer instruction queue wakeup accesses +system.cpu.iq.rate 0.190700 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1439 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.201315 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31476 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11405 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6562 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8545 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8559 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 11 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 782 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 773 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 339 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 334 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 368 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 357 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8405 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 369 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 385 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 8410 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1809 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1277 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispLoadInsts 1800 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1272 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 67 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 361 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6744 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1404 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 6751 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1398 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 14 # number of nop insts executed -system.cpu.iew.exec_refs 2427 # number of memory reference insts executed -system.cpu.iew.exec_branches 1272 # Number of branches executed -system.cpu.iew.exec_stores 1023 # Number of stores executed -system.cpu.iew.exec_rate 0.189667 # Inst execution rate -system.cpu.iew.wb_sent 6611 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6569 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2977 # num instructions producing a value -system.cpu.iew.wb_consumers 5378 # num instructions consuming a value +system.cpu.iew.exec_refs 2419 # number of memory reference insts executed +system.cpu.iew.exec_branches 1275 # Number of branches executed +system.cpu.iew.exec_stores 1021 # Number of stores executed +system.cpu.iew.exec_rate 0.180108 # Inst execution rate +system.cpu.iew.wb_sent 6621 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6578 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2993 # num instructions producing a value +system.cpu.iew.wb_consumers 5408 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.184746 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.553552 # average fanout of values written-back +system.cpu.iew.wb_rate 0.175493 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.553439 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2574 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2586 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 347 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14591 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.368583 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.017117 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 348 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 15057 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.357176 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.003286 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11942 81.84% 81.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1388 9.51% 91.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 601 4.12% 95.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 293 2.01% 97.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 167 1.14% 98.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 78 0.53% 99.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 46 0.32% 99.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 33 0.23% 99.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12412 82.43% 82.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1386 9.21% 91.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 592 3.93% 95.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 296 1.97% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 173 1.15% 98.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 78 0.52% 99.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 45 0.30% 99.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 32 0.21% 99.71% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 43 0.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14591 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15057 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -655,242 +654,246 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22343 # The number of ROB reads -system.cpu.rob.rob_writes 16451 # The number of ROB writes -system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20424 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22821 # The number of ROB reads +system.cpu.rob.rob_writes 16478 # The number of ROB writes +system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21882 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.743249 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.743249 # CPI: Total CPI of All Threads -system.cpu.ipc 0.129145 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.129145 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6720 # number of integer regfile reads -system.cpu.int_regfile_writes 3747 # number of integer regfile writes +system.cpu.cpi 8.162674 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.162674 # CPI: Total CPI of All Threads +system.cpu.ipc 0.122509 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.122509 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6722 # number of integer regfile reads +system.cpu.int_regfile_writes 3755 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 23965 # number of cc regfile reads -system.cpu.cc_regfile_writes 2898 # number of cc regfile writes -system.cpu.misc_regfile_reads 2607 # number of misc regfile reads +system.cpu.cc_regfile_reads 23977 # number of cc regfile reads +system.cpu.cc_regfile_writes 2903 # number of cc regfile writes +system.cpu.misc_regfile_reads 2611 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.271040 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.485915 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 84.551975 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1908 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.342657 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.271040 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164592 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164592 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 84.551975 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.165141 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.165141 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.275391 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4692 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4692 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1173 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1173 # number of ReadReq hits +system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4677 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4677 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1166 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1166 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1895 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1895 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1895 # number of overall hits -system.cpu.dcache.overall_hits::total 1895 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 1888 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1888 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1888 # number of overall hits +system.cpu.dcache.overall_hits::total 1888 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses -system.cpu.dcache.overall_misses::total 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9210000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9210000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7717500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7717500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 125500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16927500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16927500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16927500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16927500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1340 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1340 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 357 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 357 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 357 # number of overall misses +system.cpu.dcache.overall_misses::total 357 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10689500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10689500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7727500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7727500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles 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# number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2253 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2253 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2253 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2253 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.124627 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.124627 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2245 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2245 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.124625 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.124625 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.158899 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.158899 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.158899 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.158899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55149.700599 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55149.700599 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40405.759162 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40405.759162 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47283.519553 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47283.519553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47283.519553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47283.519553 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.159020 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.159020 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.159020 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.159020 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64394.578313 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64394.578313 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40458.115183 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40458.115183 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51588.235294 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 51588.235294 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51588.235294 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 51588.235294 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 829 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 846 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 46.055556 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu.dcache.writebacks::total 1 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 215 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 215 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 215 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 213 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 213 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 213 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 213 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5839000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5839000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2454500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2454500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8293500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8293500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8293500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8293500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076119 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076119 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6989000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6989000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2447000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2447000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9436000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9436000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9436000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9436000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077327 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077327 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq 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average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57996.503497 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57996.503497 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57996.503497 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064143 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.064143 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064143 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.064143 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67854.368932 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67854.368932 # average ReadReq mshr miss latency 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count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.728814 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 43 # number of replacements +system.cpu.icache.tags.tagsinuse 137.647063 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3470 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 296 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.722973 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 136.212207 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.266039 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.266039 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 137.647063 # Average occupied blocks per requestor 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21574493 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21574493 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21574493 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21574493 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3824 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3824 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3824 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3824 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3824 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3824 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.095188 # miss rate for ReadReq accesses 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latency -system.cpu.icache.blocked_cycles::no_mshrs 8439 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 7960 # Number of tag accesses +system.cpu.icache.tags.data_accesses 7960 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 3470 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3470 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3470 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3470 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3470 # number of overall hits +system.cpu.icache.overall_hits::total 3470 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses 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Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7643 # Number of data accesses +system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 23 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 23 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 19 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 19 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 23 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 30 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 53 # number of demand (read+write) hits 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for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.813725 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.922297 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.790210 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.879271 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.922297 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.790210 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.879271 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77333.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77333.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67119.047619 # average ReadCleanReq miss latency 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ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67393.103448 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67393.103448 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 67475.247525 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 67475.247525 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67393.103448 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69679.389313 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68104.513064 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67393.103448 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69679.389313 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68104.513064 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1011,126 +1016,127 @@ system.cpu.l2cache.demand_mshr_hits::total 6 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 48 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 48 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 53 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 53 # number of HardPFReq MSHR misses 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MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 48 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 428 # number of overall MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 289 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 289 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 289 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 415 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 53 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 468 # number of overall MSHR misses system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1625926 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2140000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2140000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16642000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16642000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16642000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6928000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23570000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16642000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6928000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2133000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2133000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17760500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17760500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5946500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5946500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17760500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8079500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17760500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8079500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25195926 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27465926 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.918919 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.764706 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.865604 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.973064 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.932039 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.932039 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.941043 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.974943 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873.458333 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33873.458333 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71333.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71333.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61183.823529 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61183.823529 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61384.615385 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61384.615385 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61183.823529 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64148.148148 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62026.315789 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61183.823529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64148.148148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873.458333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58868.985981 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 1.061224 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 30677.849057 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 30677.849057 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71100 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71100 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61455.017301 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61455.017301 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61942.708333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61942.708333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61455.017301 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64123.015873 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62265.060241 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61455.017301 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64123.015873 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 30677.849057 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58687.876068 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 21 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 21 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 32 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 64 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_snoops 409 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 368 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 383 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 296 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 102 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 623 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 908 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 64 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 546 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.133700 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.340641 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 297 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 626 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 913 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 452 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 893 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.549832 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.582857 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 473 86.63% 86.63% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 73 13.37% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 443 49.61% 49.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 409 45.80% 95.41% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41 4.59% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 546 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 442999 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 215495 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 893 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 286500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 444499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 375 # Transaction distribution +system.membus.trans_dist::ReadResp 410 # Transaction distribution system.membus.trans_dist::ReadExReq 30 # Transaction distribution system.membus.trans_dist::ReadExResp 30 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 377 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 812 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 812 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25920 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 412 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 882 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 882 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 407 # Request fanout histogram +system.membus.snoop_fanout::samples 442 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 407 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 442 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 407 # Request fanout histogram -system.membus.reqLayer0.occupancy 514944 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2135000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.0 # Layer utilization (%) +system.membus.snoop_fanout::total 442 # Request fanout histogram +system.membus.reqLayer0.occupancy 559944 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 2320000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index d4b2570c8..26cb25dcb 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25848500 # Number of ticks simulated -final_tick 25848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000028 # Number of seconds simulated +sim_ticks 28298500 # Number of ticks simulated +final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 341128 # Simulator instruction rate (inst/s) -host_op_rate 397821 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1927554064 # Simulator tick rate (ticks/s) -host_mem_usage 312280 # Number of bytes of host memory used +host_inst_rate 321731 # Simulator instruction rate (inst/s) +host_op_rate 375194 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1990329160 # Simulator tick rate (ticks/s) +host_mem_usage 311896 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4566 # Number of instructions simulated sim_ops 5330 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 557092288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309495715 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 866588003 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 557092288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 557092288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 557092288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309495715 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 866588003 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 508860894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 282700496 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 791561390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 508860894 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 508860894 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 51697 # number of cpu cycles simulated +system.cpu.numCycles 56597 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4566 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 1965 # nu system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 51696.998000 # Number of busy cycles +system.cpu.num_busy_cycles 56596.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1008 # Number of branches fetched @@ -208,17 +208,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.887597 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.887597 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020236 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020236 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.647245 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020178 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020178 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_misses::cpu.data 141 # n system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses system.cpu.dcache.overall_misses::total 141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4734000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4734000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7099000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7099000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7099000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7099000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5308000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5308000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2666000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2666000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7974000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7974000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7974000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7974000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -270,14 +270,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48306.122449 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48306.122449 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 50347.517730 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 50347.517730 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54163.265306 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54163.265306 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56553.191489 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56553.191489 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -294,14 +294,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4636000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4636000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2322000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2322000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6958000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6958000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6958000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6958000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5210000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5210000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2623000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2623000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7833000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7833000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7833000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7833000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -310,27 +310,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47306.122449 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47306.122449 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.411093 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.411093 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055865 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055865 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055685 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses system.cpu.icache.tags.data_accesses 9453 # Number of data accesses @@ -346,12 +346,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12604500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12604500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12604500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12604500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12604500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12604500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14179500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14179500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14179500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14179500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14179500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14179500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses @@ -364,12 +364,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52300.829876 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52300.829876 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52300.829876 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52300.829876 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58836.099585 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 58836.099585 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 58836.099585 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 58836.099585 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -378,45 +378,47 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 1 # number of writebacks +system.cpu.icache.writebacks::total 1 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12363500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12363500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12363500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12363500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12363500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12363500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13938500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13938500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13938500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13938500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13938500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13938500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51300.829876 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51300.829876 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 153.806088 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.680973 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.125115 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003225 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004694 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003214 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001465 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004679 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses @@ -442,18 +444,18 @@ system.cpu.l2cache.demand_misses::total 350 # nu system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses system.cpu.l2cache.overall_misses::total 350 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2257500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2257500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11818000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 11818000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4305000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4305000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11818000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6562500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18380500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11818000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6562500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18380500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2558500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2558500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13393000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 13393000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4879000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4879000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13393000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7437500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20830500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13393000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7437500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20830500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 241 # number of ReadCleanReq accesses(hits+misses) @@ -478,18 +480,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916230 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52524.444444 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52515.714286 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52515.714286 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59524.444444 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59524.444444 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59515.714286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59515.714286 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -510,18 +512,18 @@ system.cpu.l2cache.demand_mshr_misses::total 350 system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1827500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1827500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9568000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9568000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3485000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3485000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9568000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5312500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14880500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9568000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5312500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14880500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2128500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2128500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11143000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11143000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4059000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4059000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11143000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6187500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17330500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11143000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6187500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17330500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadCleanReq accesses @@ -534,18 +536,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42524.444444 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42524.444444 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42524.444444 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42524.444444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49524.444444 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49524.444444 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -565,23 +567,23 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 383 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.086162 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.280970 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.083770 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.277405 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 350 91.38% 91.38% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 33 8.62% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 350 91.62% 91.62% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 32 8.38% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 383 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 191500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 192500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadResp 307 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution @@ -602,8 +604,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 350 # Request fanout histogram system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 1755500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.8 # Layer utilization (%) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1750000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index c52a652eb..b3842d82b 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 22451000 # Number of ticks simulated -final_tick 22451000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 22454000 # Number of ticks simulated +final_tick 22454000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76638 # Simulator instruction rate (inst/s) -host_op_rate 76622 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 344943613 # Simulator tick rate (ticks/s) -host_mem_usage 294148 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 82798 # Simulator instruction rate (inst/s) +host_op_rate 82780 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 372464129 # Simulator tick rate (ticks/s) +host_mem_usage 294232 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 4986 # Number of instructions simulated sim_ops 4986 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 20992 # Nu system.physmem.num_reads::cpu.inst 328 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 469 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 935014031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 401942007 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1336956038 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 935014031 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 935014031 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 935014031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 401942007 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1336956038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 934889107 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 401888305 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1336777412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 934889107 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 934889107 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 934889107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 401888305 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1336777412 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 469 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22364000 # Total gap between requests +system.physmem.totGap 22367000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -206,9 +206,9 @@ system.physmem.totBusLat 2345000 # To system.physmem.avgQLat 9606.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 28356.61 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1336.96 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBW 1336.78 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1336.96 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1336.78 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 10.44 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 355 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 75.69 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47684.43 # Average gap between requests +system.physmem.avgGap 47690.83 # Average gap between requests system.physmem.pageHitRate 75.69 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ) @@ -279,7 +279,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 44903 # number of cpu cycles simulated +system.cpu.numCycles 44909 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 8843 # Number of cycles fetch is stalled on an Icache miss @@ -308,8 +308,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 14261 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.045231 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.274547 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.045225 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.274511 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 8380 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 2677 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2707 # Number of cycles decode is running @@ -436,7 +436,7 @@ system.cpu.iq.FU_type_0::MemWrite 1068 13.46% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 7937 # Type of FU issued -system.cpu.iq.rate 0.176759 # Inst issue rate +system.cpu.iq.rate 0.176735 # Inst issue rate system.cpu.iq.fu_busy_cnt 176 # FU busy when requested system.cpu.iq.fu_busy_rate 0.022175 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 30327 # Number of integer instruction queue reads @@ -480,13 +480,13 @@ system.cpu.iew.exec_nop 1483 # nu system.cpu.iew.exec_refs 3098 # number of memory reference insts executed system.cpu.iew.exec_branches 1353 # Number of branches executed system.cpu.iew.exec_stores 1053 # Number of stores executed -system.cpu.iew.exec_rate 0.170835 # Inst execution rate +system.cpu.iew.exec_rate 0.170812 # Inst execution rate system.cpu.iew.wb_sent 7354 # cumulative count of insts sent to commit system.cpu.iew.wb_count 7279 # cumulative count of insts written-back system.cpu.iew.wb_producers 2832 # num instructions producing a value system.cpu.iew.wb_consumers 4198 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.162105 # insts written-back per cycle +system.cpu.iew.wb_rate 0.162083 # insts written-back per cycle system.cpu.iew.wb_fanout 0.674607 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 4505 # The number of squashed insts skipped by commit @@ -558,27 +558,27 @@ system.cpu.commit.bw_lim_events 116 # nu system.cpu.rob.rob_reads 23467 # The number of ROB reads system.cpu.rob.rob_writes 21056 # The number of ROB writes system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30642 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 30648 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4986 # Number of Instructions Simulated system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 9.005816 # CPI: Cycles Per Instruction -system.cpu.cpi_total 9.005816 # CPI: Total CPI of All Threads -system.cpu.ipc 0.111039 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.111039 # IPC: Total IPC of All Threads +system.cpu.cpi 9.007020 # CPI: Cycles Per Instruction +system.cpu.cpi_total 9.007020 # CPI: Total CPI of All Threads +system.cpu.ipc 0.111025 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.111025 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 10418 # number of integer regfile reads system.cpu.int_regfile_writes 5064 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 158 # number of misc regfile reads system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 90.670819 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 90.676519 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2302 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 16.326241 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 90.670819 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022136 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022136 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 90.676519 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022138 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022138 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id @@ -683,14 +683,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82822.687943 system.cpu.dcache.overall_avg_mshr_miss_latency::total 82822.687943 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 156.398029 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 156.413207 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1547 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 331 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4.673716 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 156.398029 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.076366 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.076366 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 156.413207 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.076374 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.076374 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id @@ -709,12 +709,12 @@ system.cpu.icache.demand_misses::cpu.inst 432 # n system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses system.cpu.icache.overall_misses::total 432 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32419500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32419500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32419500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32419500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32419500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32419500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32422500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32422500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32422500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32422500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32422500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32422500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1979 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1979 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1979 # number of demand (read+write) accesses @@ -727,12 +727,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.218292 system.cpu.icache.demand_miss_rate::total 0.218292 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.218292 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.218292 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75045.138889 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75045.138889 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75045.138889 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75045.138889 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75045.138889 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75045.138889 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75052.083333 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75052.083333 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75052.083333 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75052.083333 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75052.083333 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75052.083333 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -741,6 +741,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 17 # number of writebacks +system.cpu.icache.writebacks::total 17 # number of writebacks system.cpu.icache.ReadReq_mshr_hits::cpu.inst 101 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 101 # number of demand (read+write) MSHR hits @@ -753,33 +755,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 331 system.cpu.icache.demand_mshr_misses::total 331 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 331 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 331 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25901500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25901500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25901500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25901500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25901500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25901500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25904500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25904500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25904500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25904500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25904500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25904500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.167256 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.167256 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.167256 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78252.265861 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78252.265861 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78252.265861 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 78252.265861 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78252.265861 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 78252.265861 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78261.329305 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78261.329305 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78261.329305 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 78261.329305 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78261.329305 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 78261.329305 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 215.838012 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 215.857139 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 419 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.047733 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.321641 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.516370 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.337319 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.519820 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004832 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001755 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006587 # Average percentage of cache occupancy @@ -789,6 +791,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 235 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses +system.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -809,16 +813,18 @@ system.cpu.l2cache.overall_misses::cpu.data 141 # system.cpu.l2cache.overall_misses::total 469 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4007500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25373500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 25373500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25375000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 25375000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7455000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 7455000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25373500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25375000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 11462500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36836000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25373500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 36837500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25375000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 11462500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36836000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 36837500 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 331 # number of ReadCleanReq accesses(hits+misses) @@ -845,16 +851,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1 system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80150 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80150 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77358.231707 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77358.231707 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77362.804878 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77362.804878 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81923.076923 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81923.076923 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77358.231707 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77362.804878 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78541.577825 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77358.231707 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78544.776119 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77362.804878 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78541.577825 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78544.776119 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -877,16 +883,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 141 system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3507500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3507500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22093500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22093500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22095000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22095000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6545000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6545000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22093500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22095000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10052500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32146000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22093500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32147500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22095000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10052500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32146000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32147500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for ReadCleanReq accesses @@ -901,16 +907,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70150 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70150 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67358.231707 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67358.231707 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67362.804878 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67362.804878 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71923.076923 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71923.076923 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67358.231707 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67362.804878 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68541.577825 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67358.231707 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68544.776119 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67362.804878 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68541.577825 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68544.776119 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -919,7 +925,7 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 331 # Transaction distribution @@ -927,23 +933,23 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 91 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 679 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 961 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22272 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 31296 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 489 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 472 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 489 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 472 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 489 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 496500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) @@ -967,7 +973,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 469 # Request fanout histogram -system.membus.reqLayer0.occupancy 580000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 581500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) system.membus.respLayer1.occupancy 2493500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 11.1 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index d99d61508..d2f7b8e7a 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 30902500 # Number of ticks simulated -final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000034 # Number of seconds simulated +sim_ticks 33912500 # Number of ticks simulated +final_tick 33912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 459853 # Simulator instruction rate (inst/s) -host_op_rate 459290 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2521006690 # Simulator tick rate (ticks/s) -host_mem_usage 291832 # Number of bytes of host memory used +host_inst_rate 492168 # Simulator instruction rate (inst/s) +host_op_rate 491565 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2961014581 # Simulator tick rate (ticks/s) +host_mem_usage 292188 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 18752 # Nu system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.physmem.num_reads::total 430 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 606811747 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 283731090 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 890542836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 606811747 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 606811747 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 606811747 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 283731090 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 890542836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 552952451 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 258547733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 811500184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 552952451 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 552952451 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 552952451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 258547733 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 811500184 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -49,7 +49,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 61805 # number of cpu cycles simulated +system.cpu.numCycles 67825 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5624 # Number of instructions committed @@ -68,7 +68,7 @@ system.cpu.num_mem_refs 2034 # nu system.cpu.num_load_insts 1132 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 61805 # Number of busy cycles +system.cpu.num_busy_cycles 67825 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 883 # Number of branches fetched @@ -108,17 +108,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5625 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.152837 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.067027 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.152837 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021033 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021033 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.067027 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021012 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021012 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses @@ -138,14 +138,14 @@ system.cpu.dcache.demand_misses::cpu.data 137 # n system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses system.cpu.dcache.overall_misses::total 137 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5394000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5394000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3100000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3100000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8494000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8494000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8494000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8494000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) @@ -162,14 +162,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,14 +186,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 137 system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4698000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4698000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2700000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2700000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7398000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7398000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7398000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7398000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5307000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5307000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3050000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3050000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8357000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8357000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8357000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8357000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses @@ -202,27 +202,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 129.096971 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 129.022312 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5331 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.071186 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 129.096971 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063036 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063036 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 129.022312 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062999 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062999 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 11547 # Number of tag accesses system.cpu.icache.tags.data_accesses 11547 # Number of data accesses @@ -238,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst 295 # n system.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses system.cpu.icache.overall_misses::total 295 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16141500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16141500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16141500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16141500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16141500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18192500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18192500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18192500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18192500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18192500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18192500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses @@ -256,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052435 system.cpu.icache.demand_miss_rate::total 0.052435 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052435 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052435 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54716.949153 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54716.949153 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54716.949153 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54716.949153 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61669.491525 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61669.491525 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61669.491525 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61669.491525 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -270,48 +270,52 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 13 # number of writebacks +system.cpu.icache.writebacks::total 13 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15846500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15846500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15846500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15846500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15846500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15846500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17897500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17897500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17897500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17897500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17897500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17897500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052435 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052435 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052435 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53716.949153 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53716.949153 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53716.949153 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53716.949153 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53716.949153 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53716.949153 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60669.491525 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60669.491525 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.690355 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 183.581605 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.238740 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 53.451615 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003975 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001631 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005606 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.156658 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 53.424948 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003972 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005602 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3990 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3990 # Number of data accesses +system.cpu.l2cache.WritebackClean_hits::writebacks 13 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 13 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -330,18 +334,20 @@ system.cpu.l2cache.demand_misses::total 430 # nu system.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses system.cpu.l2cache.overall_misses::total 430 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2625000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2625000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15383000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 15383000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4567500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4567500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15383000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7192500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22575500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15383000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7192500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22575500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2975000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2975000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 17434000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 17434000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5176500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5176500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 17434000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8151500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 25585500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 17434000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8151500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 25585500 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 13 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 13 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 295 # number of ReadCleanReq accesses(hits+misses) @@ -366,18 +372,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.995370 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.706485 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.706485 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52501.162791 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52501.162791 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.706485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.706485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59501.162791 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59501.162791 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -398,18 +404,18 @@ system.cpu.l2cache.demand_mshr_misses::total 430 system.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2125000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2125000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12453000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12453000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3697500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3697500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12453000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5822500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18275500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12453000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5822500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18275500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2475000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2475000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14504000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14504000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4306500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4306500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14504000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6781500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21285500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14504000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6781500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21285500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadCleanReq accesses @@ -422,18 +428,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.706485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.706485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.706485 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.706485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.706485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.706485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -442,7 +448,7 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 13 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 295 # Transaction distribution @@ -450,27 +456,27 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 87 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 877 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19712 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 27648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28480 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 445 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 432 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 432 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 445 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 222500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 432 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) system.membus.trans_dist::ReadResp 380 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution @@ -491,8 +497,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 430 # Request fanout histogram system.membus.reqLayer0.occupancy 430500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2150500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 7.0 # Layer utilization (%) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2150000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 1b72b1558..685331601 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000020 # Nu sim_ticks 19923000 # Number of ticks simulated final_tick 19923000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93968 # Simulator instruction rate (inst/s) -host_op_rate 93947 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 323084408 # Simulator tick rate (ticks/s) -host_mem_usage 291680 # Number of bytes of host memory used +host_inst_rate 101947 # Simulator instruction rate (inst/s) +host_op_rate 101922 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 350504038 # Simulator tick rate (ticks/s) +host_mem_usage 292056 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index a369fae45..22edb2de4 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27803500 # Number of ticks simulated -final_tick 27803500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000031 # Number of seconds simulated +sim_ticks 30526500 # Number of ticks simulated +final_tick 30526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 506128 # Simulator instruction rate (inst/s) -host_op_rate 505504 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2635153066 # Simulator tick rate (ticks/s) -host_mem_usage 292480 # Number of bytes of host memory used +host_inst_rate 511867 # Simulator instruction rate (inst/s) +host_op_rate 511179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2925956101 # Simulator tick rate (ticks/s) +host_mem_usage 292840 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 16320 # Nu system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 389 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 586976460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 308450375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 895426835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 586976460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 586976460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 586976460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 308450375 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 895426835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 534617464 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 280936236 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 815553699 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 534617464 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 534617464 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 534617464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 280936236 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 815553699 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 55607 # number of cpu cycles simulated +system.cpu.numCycles 61053 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5327 # Number of instructions committed @@ -50,7 +50,7 @@ system.cpu.num_mem_refs 1401 # nu system.cpu.num_load_insts 723 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 55606.998000 # Number of busy cycles +system.cpu.num_busy_cycles 61052.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched @@ -90,17 +90,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.111103 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 81.961543 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.111103 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020047 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020047 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 81.961543 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020010 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020010 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses @@ -120,14 +120,14 @@ system.cpu.dcache.demand_misses::cpu.data 135 # n system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2929000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2929000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7384000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7384000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7384000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7384000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3300000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3300000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5022000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5022000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8322000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8322000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8322000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8322000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -144,14 +144,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54240.740741 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54240.740741 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54696.296296 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54696.296296 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54696.296296 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54696.296296 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61111.111111 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61111.111111 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61644.444444 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61644.444444 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61644.444444 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61644.444444 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -168,14 +168,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4374000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4374000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7249000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7249000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7249000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7249000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3246000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3246000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4941000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4941000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8187000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8187000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8187000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8187000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -184,27 +184,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53240.740741 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53240.740741 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53696.296296 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53696.296296 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53696.296296 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53696.296296 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60111.111111 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60111.111111 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 117.031458 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 116.865384 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 117.031458 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057144 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057144 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 116.865384 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057063 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057063 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses system.cpu.icache.tags.data_accesses 10999 # Number of data accesses @@ -220,12 +220,12 @@ system.cpu.icache.demand_misses::cpu.inst 257 # n system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses system.cpu.icache.overall_misses::total 257 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14053500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14053500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14053500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14053500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14053500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14053500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15838500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15838500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15838500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15838500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15838500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15838500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses @@ -238,12 +238,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54682.879377 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54682.879377 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54682.879377 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54682.879377 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54682.879377 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54682.879377 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61628.404669 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61628.404669 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61628.404669 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61628.404669 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61628.404669 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61628.404669 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -258,39 +258,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 257 system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13796500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13796500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13796500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13796500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13796500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13796500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15581500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15581500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15581500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15581500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15581500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15581500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53682.879377 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53682.879377 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53682.879377 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53682.879377 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53682.879377 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53682.879377 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60628.404669 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60628.404669 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 142.152541 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 141.950442 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.493414 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 25.659127 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003555 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004338 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.319383 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 25.631059 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003550 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000782 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004332 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses @@ -316,18 +316,18 @@ system.cpu.l2cache.demand_misses::total 389 # nu system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 389 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4252500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4252500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13388000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 13388000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2782500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2782500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13388000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20423000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13388000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20423000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4819500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4819500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15173000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 15173000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15173000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7973000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23146000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15173000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7973000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23146000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 257 # number of ReadCleanReq accesses(hits+misses) @@ -352,18 +352,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.992347 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.960784 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.960784 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52501.285347 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52501.285347 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.960784 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.960784 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.960784 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59501.285347 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.960784 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59501.285347 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -384,18 +384,18 @@ system.cpu.l2cache.demand_mshr_misses::total 389 system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3442500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3442500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10838000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10838000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2252500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2252500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10838000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5695000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16533000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10838000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5695000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16533000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4009500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4009500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12623000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12623000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12623000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19256000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12623000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19256000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadCleanReq accesses @@ -408,18 +408,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.960784 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.960784 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.960784 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.285347 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.960784 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.285347 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.960784 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.960784 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -451,9 +451,9 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadResp 308 # Transaction distribution @@ -476,8 +476,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 389 # Request fanout histogram system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 1945500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 7.0 # Layer utilization (%) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1945000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index b13c74560..73aebadd7 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000021 # Nu sim_ticks 20818000 # Number of ticks simulated final_tick 20818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48919 # Simulator instruction rate (inst/s) -host_op_rate 88616 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 189245943 # Simulator tick rate (ticks/s) -host_mem_usage 313416 # Number of bytes of host memory used +host_inst_rate 50154 # Simulator instruction rate (inst/s) +host_op_rate 90851 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 194020392 # Simulator tick rate (ticks/s) +host_mem_usage 314048 # Number of bytes of host memory used host_seconds 0.11 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index a52dc699f..c28a44ceb 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 28359500 # Number of ticks simulated -final_tick 28359500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000031 # Number of seconds simulated +sim_ticks 30886500 # Number of ticks simulated +final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 279983 # Simulator instruction rate (inst/s) -host_op_rate 506758 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1473373857 # Simulator tick rate (ticks/s) -host_mem_usage 311136 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 150745 # Simulator instruction rate (inst/s) +host_op_rate 272977 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 864611035 # Simulator tick rate (ticks/s) +host_mem_usage 310988 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,18 +21,18 @@ system.physmem.bytes_inst_read::total 14528 # Nu system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 512279836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 302403075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 814682910 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 512279836 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512279836 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 512279836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 302403075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 814682910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 470367313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 277661762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 748029074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 470367313 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 470367313 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 470367313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 277661762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 748029074 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 56719 # number of cpu cycles simulated +system.cpu.numCycles 61773 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed @@ -53,7 +53,7 @@ system.cpu.num_mem_refs 1988 # nu system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 56718.998000 # Number of busy cycles +system.cpu.num_busy_cycles 61772.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched @@ -93,17 +93,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 80.792611 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 80.558239 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 80.792611 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019725 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019725 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 80.558239 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019668 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019668 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses @@ -123,14 +123,14 @@ system.cpu.dcache.demand_misses::cpu.data 134 # n system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses system.cpu.dcache.overall_misses::total 134 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3410000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3410000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4898000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4898000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8308000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8308000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8308000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8308000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) @@ -147,14 +147,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -171,14 +171,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 134 system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2970000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2970000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4266000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4266000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7236000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7236000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7236000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7236000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3355000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3355000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4819000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4819000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8174000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8174000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8174000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8174000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses @@ -187,27 +187,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 105.543720 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 105.267613 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 105.543720 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.051535 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.051535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 105.267613 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.051400 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.051400 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses system.cpu.icache.tags.data_accesses 13956 # Number of data accesses @@ -223,12 +223,12 @@ system.cpu.icache.demand_misses::cpu.inst 228 # n system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses system.cpu.icache.overall_misses::total 228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12499500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12499500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12499500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12499500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12499500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12499500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14088500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14088500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14088500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14088500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14088500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14088500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses @@ -241,12 +241,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54822.368421 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54822.368421 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54822.368421 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54822.368421 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54822.368421 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54822.368421 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61791.666667 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61791.666667 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61791.666667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61791.666667 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -261,39 +261,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 228 system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12271500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12271500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12271500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12271500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12271500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12271500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13860500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13860500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13860500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13860500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13860500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13860500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53822.368421 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53822.368421 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53822.368421 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53822.368421 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53822.368421 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53822.368421 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60791.666667 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60791.666667 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 134.010901 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 133.672095 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.539859 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.471042 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.256135 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.415959 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003212 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000867 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004079 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses @@ -315,18 +315,18 @@ system.cpu.l2cache.demand_misses::total 361 # nu system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 361 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4147500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4147500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11918000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 11918000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2887500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2887500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11918000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18953000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11918000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18953000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4700500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4700500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13507000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 13507000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3272500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3272500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13507000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7973000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21480000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13507000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7973000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21480000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 228 # number of ReadCleanReq accesses(hits+misses) @@ -351,18 +351,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997238 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52502.202643 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52502.202643 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52501.385042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52501.385042 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59502.202643 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59502.202643 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59501.385042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59501.385042 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -383,18 +383,18 @@ system.cpu.l2cache.demand_mshr_misses::total 361 system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3357500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3357500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9648000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9648000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2337500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2337500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9648000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5695000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15343000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9648000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5695000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15343000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3910500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3910500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11237000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11237000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2722500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2722500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11237000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17870000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11237000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17870000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadCleanReq accesses @@ -407,18 +407,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42502.202643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42502.202643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42502.202643 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.385042 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.202643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.385042 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49502.202643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49502.202643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -452,7 +452,7 @@ system.cpu.toL2Bus.snoop_fanout::total 362 # Re system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadResp 282 # Transaction distribution @@ -477,8 +477,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 361 # Request fanout histogram system.membus.reqLayer0.occupancy 361500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1805500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.4 # Layer utilization (%) +system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1805000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt index 9d107898a..835d8659c 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu sim_ticks 24832500 # Number of ticks simulated final_tick 24832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79921 # Simulator instruction rate (inst/s) -host_op_rate 79915 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 155707227 # Simulator tick rate (ticks/s) -host_mem_usage 297588 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 76523 # Simulator instruction rate (inst/s) +host_op_rate 76517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 149086837 # Simulator tick rate (ticks/s) +host_mem_usage 297164 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 12744 # Number of instructions simulated sim_ops 12744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -905,6 +905,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 45.246753 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 8 # number of writebacks +system.cpu.icache.writebacks::total 8 # number of writebacks system.cpu.icache.ReadReq_mshr_hits::cpu.inst 301 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 301 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 301 # number of demand (read+write) MSHR hits @@ -955,6 +957,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 504 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025330 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 8864 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 8864 # Number of data accesses +system.cpu.l2cache.WritebackClean_hits::writebacks 8 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 8 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -985,6 +989,8 @@ system.cpu.l2cache.demand_miss_latency::total 80021500 system.cpu.l2cache.overall_miss_latency::cpu.inst 50583000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 29438500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 80021500 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 8 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 8 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 634 # number of ReadCleanReq accesses(hits+misses) @@ -1085,7 +1091,7 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 832 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 8 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 8 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 634 # Transaction distribution @@ -1093,22 +1099,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 198 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 1964 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41088 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 62592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 63104 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 986 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002028 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.045015 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 978 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002045 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045198 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 984 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 976 99.80% 99.80% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 2 0.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 986 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 493000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 978 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 501000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 951000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 3.8 # Layer utilization (%) diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index dca96be88..3046b3277 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000027 # Nu sim_ticks 26944000 # Number of ticks simulated final_tick 26944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95332 # Simulator instruction rate (inst/s) -host_op_rate 95323 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 177899852 # Simulator tick rate (ticks/s) -host_mem_usage 294468 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 77815 # Simulator instruction rate (inst/s) +host_op_rate 77809 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 145216229 # Simulator tick rate (ticks/s) +host_mem_usage 294808 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index b9f25890e..1f4758d3f 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000041 # Number of seconds simulated -sim_ticks 41370500 # Number of ticks simulated -final_tick 41370500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000044 # Number of seconds simulated +sim_ticks 44282500 # Number of ticks simulated +final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 454115 # Simulator instruction rate (inst/s) -host_op_rate 453939 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1238118753 # Simulator tick rate (ticks/s) -host_mem_usage 292408 # Number of bytes of host memory used +host_inst_rate 498046 # Simulator instruction rate (inst/s) +host_op_rate 497817 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1453362434 # Simulator tick rate (ticks/s) +host_mem_usage 292760 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated @@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 430064901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 213485455 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 643550356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 430064901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 430064901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 430064901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 213485455 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 643550356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 401784000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 199446734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 601230734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 401784000 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 401784000 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 401784000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 199446734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 601230734 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 82741 # number of cpu cycles simulated +system.cpu.numCycles 88565 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 15162 # Number of instructions committed @@ -50,7 +50,7 @@ system.cpu.num_mem_refs 3683 # nu system.cpu.num_load_insts 2231 # Number of load instructions system.cpu.num_store_insts 1452 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 82740.998000 # Number of busy cycles +system.cpu.num_busy_cycles 88564.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 3363 # Number of branches fetched @@ -90,14 +90,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 15207 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 97.990405 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 97.148649 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 97.990405 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.023923 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.023923 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 97.148649 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.023718 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.023718 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id @@ -122,14 +122,14 @@ system.cpu.dcache.demand_misses::cpu.data 138 # n system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3286000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3286000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5270000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5270000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8556000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8556000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8556000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8556000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -148,14 +148,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -172,14 +172,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2862000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2862000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4590000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4590000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7452000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7452000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7452000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7452000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3233000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3233000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5185000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5185000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8418000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8418000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8418000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8418000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -188,27 +188,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 153.774939 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 151.748662 # Cycle average of tags in use system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 153.774939 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.075085 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.075085 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 151.748662 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.074096 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.074096 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses system.cpu.icache.tags.data_accesses 30696 # Number of data accesses @@ -224,12 +224,12 @@ system.cpu.icache.demand_misses::cpu.inst 280 # n system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses system.cpu.icache.overall_misses::total 280 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15318500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15318500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15318500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15318500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15318500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15318500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17264500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17264500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17264500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17264500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17264500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17264500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses @@ -242,12 +242,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54708.928571 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54708.928571 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54708.928571 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54708.928571 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54708.928571 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54708.928571 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61658.928571 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61658.928571 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61658.928571 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61658.928571 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -262,39 +262,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 280 system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15038500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15038500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15038500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15038500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15038500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15038500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16984500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16984500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16984500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16984500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16984500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16984500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53708.928571 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53708.928571 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53708.928571 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53708.928571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53708.928571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53708.928571 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60658.928571 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60658.928571 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.610716 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 182.297739 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.093077 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.517640 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004672 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005634 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 151.068800 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.228940 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000953 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005563 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses @@ -316,18 +316,18 @@ system.cpu.l2cache.demand_misses::total 416 # nu system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 416 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4462500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4462500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14595500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 14595500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2782500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2782500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7245000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21840500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7245000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21840500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5057500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5057500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8211000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24752500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8211000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24752500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 280 # number of ReadCleanReq accesses(hits+misses) @@ -352,18 +352,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.995215 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52501.201923 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52501.201923 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59501.201923 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59501.201923 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -384,18 +384,18 @@ system.cpu.l2cache.demand_mshr_misses::total 416 system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3612500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3612500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11815500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11815500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2252500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2252500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11815500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5865000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17680500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11815500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5865000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17680500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4207500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4207500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles 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0.992857 # mshr miss rate for ReadCleanReq accesses @@ -408,18 +408,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -453,7 +453,7 @@ system.cpu.toL2Bus.snoop_fanout::total 418 # Re system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) system.membus.trans_dist::ReadResp 331 # Transaction distribution @@ -476,8 +476,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 416 # Request fanout histogram system.membus.reqLayer0.occupancy 416500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2080500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 5.0 # Layer utilization (%) +system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2080000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt index 5eff3b495..d2a255a74 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000062 # Nu sim_ticks 61610000 # Number of ticks simulated final_tick 61610000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 402374 # Simulator instruction rate (inst/s) -host_op_rate 402048 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3843418590 # Simulator tick rate (ticks/s) -host_mem_usage 682268 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 589960 # Simulator instruction rate (inst/s) +host_op_rate 589258 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5631112330 # Simulator tick rate (ticks/s) +host_mem_usage 681568 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 6440 # Number of instructions simulated sim_ops 6440 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -546,17 +546,17 @@ system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size::total 28736 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) -system.l2bus.snoop_fanout::samples 511 # Request fanout histogram -system.l2bus.snoop_fanout::mean 0.001957 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0.044237 # Request fanout histogram +system.l2bus.snoop_fanout::samples 449 # Request fanout histogram +system.l2bus.snoop_fanout::mean 0.002227 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0.047193 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 510 99.80% 99.80% # Request fanout histogram -system.l2bus.snoop_fanout::1 1 0.20% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 448 99.78% 99.78% # Request fanout histogram +system.l2bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram -system.l2bus.snoop_fanout::total 511 # Request fanout histogram +system.l2bus.snoop_fanout::total 449 # Request fanout histogram system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks) diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index 727647065..ab5d415d7 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000050 # Nu sim_ticks 49855000 # Number of ticks simulated final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 351391 # Simulator instruction rate (inst/s) -host_op_rate 406109 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3506224066 # Simulator tick rate (ticks/s) -host_mem_usage 699088 # Number of bytes of host memory used +host_inst_rate 371629 # Simulator instruction rate (inst/s) +host_op_rate 429475 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3707242713 # Simulator tick rate (ticks/s) +host_mem_usage 698952 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated @@ -640,17 +640,17 @@ system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) -system.l2bus.snoop_fanout::samples 461 # Request fanout histogram -system.l2bus.snoop_fanout::mean 0.095445 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0.294147 # Request fanout histogram +system.l2bus.snoop_fanout::samples 391 # Request fanout histogram +system.l2bus.snoop_fanout::mean 0.086957 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0.282132 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 417 90.46% 90.46% # Request fanout histogram -system.l2bus.snoop_fanout::1 44 9.54% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 357 91.30% 91.30% # Request fanout histogram +system.l2bus.snoop_fanout::1 34 8.70% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram -system.l2bus.snoop_fanout::total 461 # Request fanout histogram +system.l2bus.snoop_fanout::total 391 # Request fanout histogram system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) system.l2bus.respLayer0.occupancy 747000 # Layer occupancy (ticks) diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt index 5eab4cd6f..33e00fb70 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000059 # Nu sim_ticks 58892000 # Number of ticks simulated final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 489554 # Simulator instruction rate (inst/s) -host_op_rate 489001 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5114816745 # Simulator tick rate (ticks/s) -host_mem_usage 679136 # Number of bytes of host memory used +host_inst_rate 477419 # Simulator instruction rate (inst/s) +host_op_rate 476853 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4988311028 # Simulator tick rate (ticks/s) +host_mem_usage 679248 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated @@ -532,17 +532,17 @@ system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size::total 27776 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) -system.l2bus.snoop_fanout::samples 528 # Request fanout histogram +system.l2bus.snoop_fanout::samples 434 # Request fanout histogram system.l2bus.snoop_fanout::mean 0 # Request fanout histogram system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 528 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 434 100.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 0 # Request fanout histogram -system.l2bus.snoop_fanout::total 528 # Request fanout histogram +system.l2bus.snoop_fanout::total 434 # Request fanout histogram system.l2bus.reqLayer0.occupancy 528000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) system.l2bus.respLayer0.occupancy 891000 # Layer occupancy (ticks) diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt index 82b97827e..a3585592a 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000053 # Nu sim_ticks 53334000 # Number of ticks simulated final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 497623 # Simulator instruction rate (inst/s) -host_op_rate 497044 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4772617450 # Simulator tick rate (ticks/s) -host_mem_usage 679800 # Number of bytes of host memory used +host_inst_rate 408572 # Simulator instruction rate (inst/s) +host_op_rate 408151 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3919888285 # Simulator tick rate (ticks/s) +host_mem_usage 679628 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated @@ -519,17 +519,17 @@ system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) -system.l2bus.snoop_fanout::samples 468 # Request fanout histogram -system.l2bus.snoop_fanout::mean 0.008547 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0.092153 # Request fanout histogram +system.l2bus.snoop_fanout::samples 397 # Request fanout histogram +system.l2bus.snoop_fanout::mean 0.007557 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0.086709 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 464 99.15% 99.15% # Request fanout histogram -system.l2bus.snoop_fanout::1 4 0.85% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 394 99.24% 99.24% # Request fanout histogram +system.l2bus.snoop_fanout::1 3 0.76% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram -system.l2bus.snoop_fanout::total 468 # Request fanout histogram +system.l2bus.snoop_fanout::total 397 # Request fanout histogram system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) system.l2bus.respLayer0.occupancy 777000 # Layer occupancy (ticks) diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt index 29a5c5d19..e6ff8b326 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000056 # Nu sim_ticks 55844000 # Number of ticks simulated final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 284010 # Simulator instruction rate (inst/s) -host_op_rate 512497 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2773065846 # Simulator tick rate (ticks/s) -host_mem_usage 698700 # Number of bytes of host memory used +host_inst_rate 304186 # Simulator instruction rate (inst/s) +host_op_rate 548880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2969793661 # Simulator tick rate (ticks/s) +host_mem_usage 698284 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated @@ -518,17 +518,17 @@ system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size::total 23680 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) -system.l2bus.snoop_fanout::samples 428 # Request fanout histogram -system.l2bus.snoop_fanout::mean 0.002336 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0.048337 # Request fanout histogram +system.l2bus.snoop_fanout::samples 370 # Request fanout histogram +system.l2bus.snoop_fanout::mean 0.002703 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0.051988 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 427 99.77% 99.77% # Request fanout histogram -system.l2bus.snoop_fanout::1 1 0.23% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 369 99.73% 99.73% # Request fanout histogram +system.l2bus.snoop_fanout::1 1 0.27% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram -system.l2bus.snoop_fanout::total 428 # Request fanout histogram +system.l2bus.snoop_fanout::total 370 # Request fanout histogram system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks) diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 81d1f8ac8..088aacfd2 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.147041 # Number of seconds simulated -sim_ticks 147041346500 # Number of ticks simulated -final_tick 147041346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.147149 # Number of seconds simulated +sim_ticks 147148719500 # Number of ticks simulated +final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 870528 # Simulator instruction rate (inst/s) -host_op_rate 874854 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1413203999 # Simulator tick rate (ticks/s) -host_mem_usage 449664 # Number of bytes of host memory used -host_seconds 104.05 # Real time elapsed on the host +host_inst_rate 921343 # Simulator instruction rate (inst/s) +host_op_rate 925922 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1496788671 # Simulator tick rate (ticks/s) +host_mem_usage 449288 # Number of bytes of host memory used +host_seconds 98.31 # Real time elapsed on the host sim_insts 90576862 # Number of instructions simulated sim_ops 91026991 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 36928 # Nu system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 251140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6425621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6676761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 251140 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 251140 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 251140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6425621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6676761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 250957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6420933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6671890 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 250957 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 250957 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 250957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6420933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6671890 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 294082693 # number of cpu cycles simulated +system.cpu.numCycles 294297439 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90576862 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 27220755 # nu system.cpu.num_load_insts 22475911 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 294082692.998000 # Number of busy cycles +system.cpu.num_busy_cycles 294297438.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 18732305 # Number of branches fetched @@ -208,18 +208,18 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054081 # Class of executed instruction system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.593612 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3565.478025 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54410450500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593612 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 54453325500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.478025 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.870478 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.870478 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1355 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2550 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1357 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses @@ -248,14 +248,14 @@ system.cpu.dcache.demand_misses::cpu.data 946796 # n system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses system.cpu.dcache.overall_misses::total 946799 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711511000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11711511000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1217183500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1217183500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12928694500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12928694500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12928694500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12928694500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713009000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11713009000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1319019500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1319019500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13032028500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13032028500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13032028500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13032028500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) @@ -280,14 +280,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13010.086793 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13010.086793 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.206085 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13655.206085 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.162817 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13655.162817 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.750892 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.750892 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28299.673883 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28299.673883 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13764.346808 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13764.346808 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13764.303194 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13764.303194 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946795 system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10811285000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10811285000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1170574500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1170574500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 120000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 120000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981859500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11981859500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981979500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11981979500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812776000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812776000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1272410500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1272410500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 134000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 134000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12085186500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12085186500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12085320500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12085320500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses @@ -334,26 +334,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12010.056810 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12010.056810 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25114.773971 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25114.773971 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 40000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 40000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12655.178259 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12655.178259 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12655.264903 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12655.264903 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.713135 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.713135 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 510.120518 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.120518 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.249082 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.249082 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 510.111710 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.249078 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.249078 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id @@ -374,12 +374,12 @@ system.cpu.icache.demand_misses::cpu.inst 599 # n system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses system.cpu.icache.overall_misses::total 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32054000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32054000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32054000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32054000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32054000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32054000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 36093000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 36093000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 36093000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 36093000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 36093000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 36093000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses @@ -392,12 +392,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53512.520868 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53512.520868 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53512.520868 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53512.520868 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53512.520868 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53512.520868 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60255.425710 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 60255.425710 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 60255.425710 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 60255.425710 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -406,55 +406,59 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 2 # number of writebacks +system.cpu.icache.writebacks::total 2 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31455000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 31455000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31455000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 31455000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31455000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 31455000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35494000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 35494000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35494000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 35494000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35494000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 35494000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52512.520868 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52512.520868 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52512.520868 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52512.520868 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52512.520868 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52512.520868 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9567.853327 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8879.447332 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.172931 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 194.233064 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.270979 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 8876.269803 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.164592 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 194.224030 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.270882 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.005928 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.291988 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.005927 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.291890 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1468 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1473 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15181828 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15181828 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 942334 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942334 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits @@ -479,20 +483,22 @@ system.cpu.l2cache.demand_misses::total 15340 # nu system.cpu.l2cache.overall_misses::cpu.inst 577 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14763 # number of overall misses system.cpu.l2cache.overall_misses::total 15340 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764020500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 764020500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 30304500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 30304500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11289500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 11289500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 30304500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 775310000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 805614500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 30304500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 775310000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 805614500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 942334 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 942334 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 865856500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 865856500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34343500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 34343500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12794500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 12794500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 34343500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 878651000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 912994500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 34343500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 878651000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 912994500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 942334 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 942334 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 599 # number of ReadCleanReq accesses(hits+misses) @@ -517,18 +523,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016192 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963272 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52517.218862 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52517.218862 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52520.797227 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52520.797227 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52509.302326 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52509.302326 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52520.797227 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52517.103570 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52517.242503 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52520.797227 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52517.103570 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52517.242503 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59517.218862 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59517.218862 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59520.797227 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59520.797227 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59509.302326 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59509.302326 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59517.242503 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59517.242503 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -549,18 +555,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15340 system.cpu.l2cache.overall_mshr_misses::cpu.inst 577 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14763 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 618540500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 618540500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24534500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24534500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9139500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9139500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24534500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 627680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 652214500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24534500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 627680000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 652214500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 720376500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 720376500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 28573500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 28573500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10644500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10644500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28573500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 731021000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 759594500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28573500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 731021000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 759594500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for ReadCleanReq accesses @@ -573,18 +579,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42517.218862 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42517.218862 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42520.797227 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42520.797227 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42509.302326 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42509.302326 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42520.797227 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42517.103570 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42517.242503 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42520.797227 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42517.103570 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42517.242503 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49517.218862 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49517.218862 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49520.797227 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49520.797227 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49509.302326 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49509.302326 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -593,8 +599,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 256 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 255 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution @@ -602,22 +609,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1199 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836185 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2837384 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38400 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 120942848 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1890101 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000126 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.011244 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 947397 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000132 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.011486 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1889862 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 239 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 947272 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 125 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1890101 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1887384500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 947397 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -644,7 +651,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 15340 # Request fanout histogram system.membus.reqLayer0.occupancy 15604500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 76964500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 76700000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 053bb8ee0..beaa1a0e8 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000108 # Number of seconds simulated -sim_ticks 107711000 # Number of ticks simulated -final_tick 107711000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 107836000 # Number of ticks simulated +final_tick 107836000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152784 # Simulator instruction rate (inst/s) -host_op_rate 152784 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16568657 # Simulator tick rate (ticks/s) -host_mem_usage 311444 # Number of bytes of host memory used -host_seconds 6.50 # Real time elapsed on the host -sim_insts 993230 # Number of instructions simulated -sim_ops 993230 # Number of ops (including micro ops) simulated +host_inst_rate 166566 # Simulator instruction rate (inst/s) +host_op_rate 166565 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18067031 # Simulator tick rate (ticks/s) +host_mem_usage 311540 # Number of bytes of host memory used +host_seconds 5.97 # Real time elapsed on the host +sim_insts 994171 # Number of instructions simulated +sim_ops 994171 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory system.physmem.bytes_read::total 42560 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 448 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 83 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 665 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 213905729 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 100416856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 49317154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11883652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 2970913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7724374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1188365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7724374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 395131416 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213905729 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 49317154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 2970913 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1188365 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267382162 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213905729 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 100416856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 49317154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11883652 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 2970913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7724374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1188365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7724374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 395131416 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213657777 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 100300456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 47479506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11869876 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 1780481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7715420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 4154457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7715420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 394673393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213657777 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 47479506 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 1780481 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 4154457 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267072221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213657777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 100300456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 47479506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11869876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 1780481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7715420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 4154457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7715420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 394673393 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 666 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 666 # Number of DRAM read bursts, including those serviced by the write queue @@ -70,7 +70,7 @@ system.physmem.bytesReadSys 42624 # To system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 87 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 89 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 114 # Per bank write bursts system.physmem.perBankRdBursts::1 42 # Per bank write bursts system.physmem.perBankRdBursts::2 30 # Per bank write bursts @@ -105,7 +105,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 107683000 # Total gap between requests +system.physmem.totGap 107808000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -230,15 +230,15 @@ system.physmem.bytesPerActivate::768-895 2 1.38% 94.48% # By system.physmem.bytesPerActivate::896-1023 3 2.07% 96.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 3.45% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 145 # Bytes accessed per row activation -system.physmem.totQLat 6590000 # Total ticks spent queuing -system.physmem.totMemAccLat 19077500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 6565250 # Total ticks spent queuing +system.physmem.totMemAccLat 19052750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 3330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9894.89 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9857.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28644.89 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 395.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28607.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 395.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 395.73 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 395.27 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.09 # Data bus utilization in percentage @@ -250,133 +250,133 @@ system.physmem.readRowHits 510 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 161686.19 # Average gap between requests +system.physmem.avgGap 161873.87 # Average gap between requests system.physmem.pageHitRate 76.58 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 710640 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 387750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2769000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 38163780 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27411750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 76054200 # Total energy per rank (pJ) -system.physmem_0.averagePower 749.440907 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 47737250 # Time in different power states +system.physmem_0.actBackEnergy 38088540 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27477750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 76044960 # Total energy per rank (pJ) +system.physmem_0.averagePower 749.349855 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 47969250 # Time in different power states system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 52758750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 52649750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 2028000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 32134320 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32700750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 74023545 # Total energy per rank (pJ) -system.physmem_1.averagePower 729.430757 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57587750 # Time in different power states +system.physmem_1.actBackEnergy 32065065 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32761500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 74015040 # Total energy per rank (pJ) +system.physmem_1.averagePower 729.346948 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57811250 # Time in different power states system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 43903750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 43803750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 81565 # Number of BP lookups -system.cpu0.branchPred.condPredicted 78921 # Number of conditional branches predicted +system.cpu0.branchPred.lookups 81652 # Number of BP lookups +system.cpu0.branchPred.condPredicted 79008 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 1100 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 78897 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 76181 # Number of BTB hits +system.cpu0.branchPred.BTBLookups 78985 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 76270 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 96.557537 # BTB Hit Percentage +system.cpu0.branchPred.BTBHitPct 96.562638 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 645 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 215423 # number of cpu cycles simulated +system.cpu0.numCycles 215673 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 19725 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 482162 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 81565 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 76826 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 165719 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.icacheStallCycles 19729 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 482689 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 81652 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 76915 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 165939 # Number of cycles fetch has run and was not squashing or blocked system.cpu0.fetch.SquashCycles 2501 # Number of cycles fetch has spent squashing system.cpu0.fetch.TlbCycles 96 # Number of cycles fetch has spent waiting for tlb system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu0.fetch.PendingTrapStallCycles 1994 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 6733 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 620 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.CacheLines 6734 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 621 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 188787 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.554000 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.213947 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::samples 189011 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.553761 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.213837 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 30573 16.19% 16.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 78235 41.44% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 796 0.42% 58.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1203 0.64% 58.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 613 0.32% 59.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 73639 39.01% 98.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 671 0.36% 98.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 403 0.21% 98.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2654 1.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 30617 16.20% 16.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 78326 41.44% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 798 0.42% 58.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1203 0.64% 58.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 614 0.32% 59.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 73725 39.01% 98.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 672 0.36% 98.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 403 0.21% 98.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2653 1.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 188787 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.378627 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.238210 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 15472 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 18515 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 152899 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 651 # Number of cycles decode is unblocking +system.cpu0.fetch.rateDist::total 189011 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.378592 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.238059 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 15475 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 18570 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 153063 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 653 # Number of cycles decode is unblocking system.cpu0.decode.SquashCycles 1250 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 471677 # Number of instructions handled by decode +system.cpu0.decode.DecodedInsts 472193 # Number of instructions handled by decode system.cpu0.rename.SquashCycles 1250 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16075 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2062 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 15118 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 152899 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1383 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 468509 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full +system.cpu0.rename.IdleCycles 16079 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2117 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15116 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 153063 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1386 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 469016 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full system.cpu0.rename.SQFullEvents 883 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 320339 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 934389 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 705719 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 307267 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13072 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RenamedOperands 320676 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 935403 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 706479 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 307583 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13093 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 822 # count of serializing insts renamed system.cpu0.rename.tempSerializingInsts 832 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4372 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 149868 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 75788 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 73280 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 72874 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 391921 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.rename.skidInsts 4383 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 150037 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 75873 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 73364 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 72959 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 392343 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 889 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 388505 # Number of instructions issued +system.cpu0.iq.iqInstsIssued 388906 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 12295 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11684 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedInstsExamined 12322 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 11733 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 330 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 188787 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.057901 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.125475 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 189011 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.057584 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.125737 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33627 17.81% 17.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4227 2.24% 20.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 74093 39.25% 59.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 73707 39.04% 98.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1618 0.86% 99.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33687 17.82% 17.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4243 2.24% 20.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 74165 39.24% 59.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 73776 39.03% 98.34% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1622 0.86% 99.20% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::5 890 0.47% 99.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 402 0.21% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 405 0.21% 99.88% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 147 0.08% 99.96% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 76 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 188787 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 189011 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IntAlu 62 21.45% 21.45% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 0 0.00% 21.45% # attempts to use FU when none available @@ -412,7 +412,7 @@ system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # at system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 164238 42.27% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 164396 42.27% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.27% # Type of FU issued @@ -441,96 +441,96 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.27% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 149226 38.41% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 75041 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 149390 38.41% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 75120 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 388505 # Type of FU issued -system.cpu0.iq.rate 1.803452 # Inst issue rate +system.cpu0.iq.FU_type_0::total 388906 # Type of FU issued +system.cpu0.iq.rate 1.803221 # Inst issue rate system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000744 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 966117 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 405167 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 386653 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fu_busy_rate 0.000743 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 967143 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 405616 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 387054 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 388794 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 389195 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 72393 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 72474 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2645 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2656 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 63 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1670 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1676 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewSquashCycles 1250 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 2029 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 466388 # Number of instructions dispatched to IQ +system.cpu0.iew.iewBlockCycles 2081 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 466895 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 243 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 149868 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 75788 # Number of dispatched store instructions +system.cpu0.iew.iewDispLoadInsts 150037 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 75873 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 770 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 63 # Number of memory order violations system.cpu0.iew.predictedTakenIncorrect 318 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 991 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 1309 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 387494 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 148888 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1011 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 387894 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 149051 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 73578 # number of nop insts executed -system.cpu0.iew.exec_refs 223779 # number of memory reference insts executed -system.cpu0.iew.exec_branches 76909 # Number of branches executed -system.cpu0.iew.exec_stores 74891 # Number of stores executed -system.cpu0.iew.exec_rate 1.798759 # Inst execution rate -system.cpu0.iew.wb_sent 387061 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 386653 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 229361 # num instructions producing a value -system.cpu0.iew.wb_consumers 232407 # num instructions consuming a value +system.cpu0.iew.exec_nop 73663 # number of nop insts executed +system.cpu0.iew.exec_refs 224021 # number of memory reference insts executed +system.cpu0.iew.exec_branches 76988 # Number of branches executed +system.cpu0.iew.exec_stores 74970 # Number of stores executed +system.cpu0.iew.exec_rate 1.798528 # Inst execution rate +system.cpu0.iew.wb_sent 387462 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 387054 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 229603 # num instructions producing a value +system.cpu0.iew.wb_consumers 232649 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.794855 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.986894 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.794634 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.986907 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 13078 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 13111 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1100 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 186327 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.432562 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.148979 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 186547 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.432234 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.149146 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33862 18.17% 18.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 75972 40.77% 58.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1939 1.04% 59.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 672 0.36% 60.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 526 0.28% 60.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 72083 38.69% 99.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 527 0.28% 99.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33930 18.19% 18.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 76047 40.77% 58.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1940 1.04% 59.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 670 0.36% 60.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 524 0.28% 60.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 72154 38.68% 99.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 534 0.29% 99.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 265 0.14% 99.74% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::8 483 0.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 186327 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 453252 # Number of instructions committed -system.cpu0.commit.committedOps 453252 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 186547 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 453726 # Number of instructions committed +system.cpu0.commit.committedOps 453726 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 221341 # Number of memory references committed -system.cpu0.commit.loads 147223 # Number of loads committed +system.cpu0.commit.refs 221578 # Number of memory references committed +system.cpu0.commit.loads 147381 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 76005 # Number of branches committed +system.cpu0.commit.branches 76084 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 305598 # Number of committed integer instructions. +system.cpu0.commit.int_insts 305914 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 72737 16.05% 16.05% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 159090 35.10% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 72816 16.05% 16.05% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 159248 35.10% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction @@ -559,103 +559,103 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 147307 32.50% 83.65% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 74118 16.35% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 147465 32.50% 83.65% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 74197 16.35% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 453252 # Class of committed instruction +system.cpu0.commit.op_class_0::total 453726 # Class of committed instruction system.cpu0.commit.bw_lim_events 483 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 651013 # The number of ROB reads -system.cpu0.rob.rob_writes 935136 # The number of ROB writes +system.cpu0.rob.rob_reads 651740 # The number of ROB reads +system.cpu0.rob.rob_writes 936154 # The number of ROB writes system.cpu0.timesIdled 313 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26636 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 380431 # Number of Instructions Simulated -system.cpu0.committedOps 380431 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.566260 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.566260 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.765972 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.765972 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 693268 # number of integer regfile reads -system.cpu0.int_regfile_writes 312587 # number of integer regfile writes +system.cpu0.idleCycles 26662 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 380826 # Number of Instructions Simulated +system.cpu0.committedOps 380826 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.566330 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.566330 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.765756 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.765756 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 693989 # number of integer regfile reads +system.cpu0.int_regfile_writes 312909 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 225648 # number of misc regfile reads +system.cpu0.misc_regfile_reads 225890 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.123038 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 149358 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 141.137199 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 149509 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 873.438596 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 874.321637 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.123038 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275631 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.275631 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.137199 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275659 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.275659 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 602523 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 602523 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75889 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75889 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73521 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73521 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 603167 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 603167 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75961 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75961 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73598 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73598 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 149410 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 149410 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 149410 # number of overall hits -system.cpu0.dcache.overall_hits::total 149410 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 547 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 547 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 555 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 555 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 149559 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 149559 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 149559 # number of overall hits +system.cpu0.dcache.overall_hits::total 149559 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 557 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 557 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 557 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 557 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1102 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1102 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1102 # number of overall misses -system.cpu0.dcache.overall_misses::total 1102 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16913500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 16913500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34798980 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 34798980 # number of WriteReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 1114 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1114 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1114 # number of overall misses +system.cpu0.dcache.overall_misses::total 1114 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17293500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 17293500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34774980 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 34774980 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 472500 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 472500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 51712480 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 51712480 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 51712480 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 51712480 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 76436 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 76436 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74076 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74076 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 52068480 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 52068480 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 52068480 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 52068480 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 76518 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 76518 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74155 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74155 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 150512 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 150512 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 150512 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 150512 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007156 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.007156 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007492 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007492 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 150673 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 150673 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 150673 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 150673 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007279 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.007279 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007511 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007511 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007322 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.007322 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007322 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.007322 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30920.475320 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 30920.475320 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62700.864865 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 62700.864865 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007393 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.007393 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007393 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.007393 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31047.576302 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 31047.576302 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62432.639138 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 62432.639138 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18173.076923 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 18173.076923 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46926.025408 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 46926.025408 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46926.025408 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 46926.025408 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46740.107720 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 46740.107720 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46740.107720 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 46740.107720 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 891 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked @@ -666,14 +666,14 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 365 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 365 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 377 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 377 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 742 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 742 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 742 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 742 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 375 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 375 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 379 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 379 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 754 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 754 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 754 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 754 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 178 # number of WriteReq MSHR misses @@ -684,89 +684,89 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6860000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6860000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8493000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8493000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6892000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6892000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8487000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8487000 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 446500 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 446500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15353000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15353000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15353000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15353000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002381 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002381 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002403 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002403 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15379000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15379000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15379000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15379000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002379 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002379 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002400 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002400 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002392 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002392 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37692.307692 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37692.307692 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47713.483146 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47713.483146 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002389 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002389 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002389 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002389 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37868.131868 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37868.131868 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47679.775281 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47679.775281 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17173.076923 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17173.076923 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42647.222222 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42647.222222 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42647.222222 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42647.222222 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42719.444444 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42719.444444 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42719.444444 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42719.444444 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 315 # number of replacements -system.cpu0.icache.tags.tagsinuse 241.163907 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 5949 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 241.200073 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 5951 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 607 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.800659 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.803954 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.163907 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471023 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.471023 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.200073 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471094 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.471094 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.570312 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 7340 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 7340 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 5949 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5949 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5949 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5949 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5949 # number of overall hits -system.cpu0.icache.overall_hits::total 5949 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 784 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 784 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 784 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 784 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 784 # number of overall misses -system.cpu0.icache.overall_misses::total 784 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40406000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 40406000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 40406000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 40406000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 40406000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 40406000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6733 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6733 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6733 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6733 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6733 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6733 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116441 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.116441 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116441 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.116441 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116441 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.116441 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51538.265306 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 51538.265306 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51538.265306 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 51538.265306 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51538.265306 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 51538.265306 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 7341 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 7341 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 5951 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5951 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5951 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5951 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5951 # number of overall hits +system.cpu0.icache.overall_hits::total 5951 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 783 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 783 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 783 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 783 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 783 # number of overall misses +system.cpu0.icache.overall_misses::total 783 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40367500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 40367500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 40367500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 40367500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 40367500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 40367500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6734 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6734 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6734 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6734 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6734 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6734 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116276 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.116276 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116276 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.116276 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116276 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.116276 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51554.916986 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 51554.916986 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51554.916986 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 51554.916986 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51554.916986 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 51554.916986 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -775,411 +775,412 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs 4 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 176 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 176 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 176 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 176 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 176 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 176 # number of overall MSHR hits +system.cpu0.icache.writebacks::writebacks 315 # number of writebacks +system.cpu0.icache.writebacks::total 315 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 175 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 175 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 175 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 175 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 175 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 175 # number of overall MSHR hits system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 608 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 608 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 608 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 608 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 608 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 608 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31294000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 31294000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31294000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 31294000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31294000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 31294000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090302 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.090302 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.090302 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51470.394737 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 51470.394737 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 51470.394737 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31309500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 31309500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31309500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 31309500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31309500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 31309500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090288 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.090288 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.090288 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51495.888158 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 51495.888158 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 51495.888158 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 53924 # Number of BP lookups -system.cpu1.branchPred.condPredicted 50532 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1274 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 46687 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 45618 # Number of BTB hits +system.cpu1.branchPred.lookups 53782 # Number of BP lookups +system.cpu1.branchPred.condPredicted 50347 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1277 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 46315 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 45397 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 97.710283 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 909 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 98.017921 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 899 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.numCycles 162664 # number of cpu cycles simulated +system.cpu1.numCycles 162898 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 29507 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 300555 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 53924 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 46527 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 124688 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2705 # Number of cycles fetch has spent squashing +system.cpu1.fetch.icacheStallCycles 29679 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 299544 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 53782 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 46296 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 124703 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2711 # Number of cycles fetch has spent squashing system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from system.cpu1.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps system.cpu1.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20020 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 452 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 156656 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.918567 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.216659 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 20165 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 457 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 156846 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.909797 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.217375 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 52489 33.51% 33.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 52328 33.40% 66.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 5864 3.74% 70.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3542 2.26% 72.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 937 0.60% 73.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 35524 22.68% 96.19% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1237 0.79% 96.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 797 0.51% 97.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3938 2.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 53057 33.83% 33.83% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 52143 33.24% 67.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 5878 3.75% 70.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3526 2.25% 73.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 939 0.60% 73.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 35272 22.49% 96.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1247 0.80% 96.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 803 0.51% 97.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3981 2.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 156656 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.331505 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.847704 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 17844 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 50371 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 84089 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 2990 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1352 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 285365 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1352 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18555 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 22336 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13775 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 85993 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 14635 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 282118 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 13530 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full +system.cpu1.fetch.rateDist::total 156846 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.330158 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.838844 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 17882 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 51023 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 83554 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3022 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1355 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 284108 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 1355 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 18601 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 22664 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13899 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 84840 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 15477 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 280728 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 13732 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 199297 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 544091 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 423098 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 185456 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13841 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1187 # count of serializing insts renamed +system.cpu1.rename.RenamedOperands 198394 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 541219 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 420944 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 184552 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13842 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1192 # count of serializing insts renamed system.cpu1.rename.tempSerializingInsts 1257 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 19159 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 79883 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 38287 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 37783 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 33197 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 235383 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 5651 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 236419 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 14 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12945 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10680 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 703 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 156656 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.509160 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.379040 # Number of insts issued each cycle +system.cpu1.rename.skidInsts 20109 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 79403 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 38032 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 37516 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 32939 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 234221 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 5649 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 235400 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 7 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12841 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10393 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 661 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 156846 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.500835 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.378978 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 56139 35.84% 35.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 19247 12.29% 48.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 37725 24.08% 72.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 37266 23.79% 95.99% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3381 2.16% 98.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1595 1.02% 99.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 897 0.57% 99.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 205 0.13% 99.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 201 0.13% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 56627 36.10% 36.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 19405 12.37% 48.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 37510 23.92% 72.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 37026 23.61% 96.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3380 2.15% 98.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1607 1.02% 99.18% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 891 0.57% 99.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 204 0.13% 99.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 196 0.12% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 156656 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 156846 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 79 23.65% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 46 13.77% 37.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 209 62.57% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 79 24.38% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 36 11.11% 35.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 209 64.51% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 115374 48.80% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 83373 35.26% 84.07% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 37672 15.93% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 114995 48.85% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 82971 35.25% 84.10% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 37434 15.90% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 236419 # Type of FU issued -system.cpu1.iq.rate 1.453419 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 334 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001413 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 629842 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 254017 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 234890 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 235400 # Type of FU issued +system.cpu1.iq.rate 1.445076 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 324 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001376 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 627977 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 252747 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 233879 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 236753 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 235724 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 33006 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 32768 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2599 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2551 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1501 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1483 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1352 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6792 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 279653 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 149 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 79883 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 38287 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1135 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 1355 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6889 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 69 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 278263 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 133 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 79403 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 38032 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1130 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 444 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1061 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1505 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 235416 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 78826 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1003 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 36 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 442 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1069 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1511 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 234388 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 78381 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 38619 # number of nop insts executed -system.cpu1.iew.exec_refs 116410 # number of memory reference insts executed -system.cpu1.iew.exec_branches 48027 # Number of branches executed -system.cpu1.iew.exec_stores 37584 # Number of stores executed -system.cpu1.iew.exec_rate 1.447253 # Inst execution rate -system.cpu1.iew.wb_sent 235168 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 234890 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 134020 # num instructions producing a value -system.cpu1.iew.wb_consumers 140635 # num instructions consuming a value +system.cpu1.iew.exec_nop 38393 # number of nop insts executed +system.cpu1.iew.exec_refs 115730 # number of memory reference insts executed +system.cpu1.iew.exec_branches 47858 # Number of branches executed +system.cpu1.iew.exec_stores 37349 # Number of stores executed +system.cpu1.iew.exec_rate 1.438864 # Inst execution rate +system.cpu1.iew.wb_sent 234148 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 233879 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 133368 # num instructions producing a value +system.cpu1.iew.wb_consumers 139978 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.444020 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.952963 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.435739 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.952778 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13740 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 4948 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1274 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 154106 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.725163 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.084593 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13605 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 4988 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1277 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 154309 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.714761 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.081585 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60830 39.47% 39.47% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 44602 28.94% 68.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5225 3.39% 71.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 5769 3.74% 75.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1531 0.99% 76.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 33080 21.47% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 818 0.53% 98.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 941 0.61% 99.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1310 0.85% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 61394 39.79% 39.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 44430 28.79% 68.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5247 3.40% 71.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 5803 3.76% 75.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1533 0.99% 76.73% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 32828 21.27% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 824 0.53% 98.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 946 0.61% 99.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1304 0.85% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 154106 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 265858 # Number of instructions committed -system.cpu1.commit.committedOps 265858 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 154309 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 264603 # Number of instructions committed +system.cpu1.commit.committedOps 264603 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 114070 # Number of memory references committed -system.cpu1.commit.loads 77284 # Number of loads committed -system.cpu1.commit.membars 4232 # Number of memory barriers committed -system.cpu1.commit.branches 46981 # Number of branches committed +system.cpu1.commit.refs 113401 # Number of memory references committed +system.cpu1.commit.loads 76852 # Number of loads committed +system.cpu1.commit.membars 4272 # Number of memory barriers committed +system.cpu1.commit.branches 46786 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 183171 # Number of committed integer instructions. +system.cpu1.commit.int_insts 182306 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 37769 14.21% 14.21% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 109787 41.30% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 81516 30.66% 86.16% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 36786 13.84% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 37574 14.20% 14.20% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 109356 41.33% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 81124 30.66% 86.19% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 36549 13.81% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 265858 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1310 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 431808 # The number of ROB reads -system.cpu1.rob.rob_writes 561746 # The number of ROB writes -system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 6008 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 45259 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 223857 # Number of Instructions Simulated -system.cpu1.committedOps 223857 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.726642 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.726642 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.376193 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.376193 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 409049 # number of integer regfile reads -system.cpu1.int_regfile_writes 191377 # number of integer regfile writes +system.cpu1.commit.op_class_0::total 264603 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1304 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 430627 # The number of ROB reads +system.cpu1.rob.rob_writes 558953 # The number of ROB writes +system.cpu1.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 6052 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 45271 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 222757 # Number of Instructions Simulated +system.cpu1.committedOps 222757 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.731281 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.731281 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.367463 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.367463 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 407061 # number of integer regfile reads +system.cpu1.int_regfile_writes 190501 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 118040 # number of misc regfile reads +system.cpu1.misc_regfile_reads 117378 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 25.752806 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 42910 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1479.655172 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 25.769381 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 42560 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1520 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.752806 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050298 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.050298 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.769381 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050331 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.050331 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 330593 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 330593 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 45309 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 45309 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 36557 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 36557 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 15 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 81866 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 81866 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 81866 # number of overall hits -system.cpu1.dcache.overall_hits::total 81866 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 489 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 489 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 159 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 159 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 648 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 648 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 648 # number of overall misses -system.cpu1.dcache.overall_misses::total 648 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9556000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 9556000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3376000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3376000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 667000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 667000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 12932000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12932000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 12932000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12932000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 45798 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 45798 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 36716 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 36716 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 328816 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 328816 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 45076 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 45076 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 36319 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 36319 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 81395 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 81395 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 81395 # number of overall hits +system.cpu1.dcache.overall_hits::total 81395 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 515 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 515 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 160 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 160 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 675 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 675 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 675 # number of overall misses +system.cpu1.dcache.overall_misses::total 675 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 10357000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 10357000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3384000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3384000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 705000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 705000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13741000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13741000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13741000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13741000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 45591 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 45591 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 36479 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 36479 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 82514 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 82514 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 82514 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 82514 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010677 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.010677 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004331 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.004331 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.785714 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007853 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.007853 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007853 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.007853 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19541.922290 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19541.922290 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21232.704403 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21232.704403 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12127.272727 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 12127.272727 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19956.790123 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19956.790123 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19956.790123 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 19956.790123 # average overall miss latency +system.cpu1.dcache.demand_accesses::cpu1.data 82070 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 82070 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 82070 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 82070 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011296 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.011296 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004386 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004386 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.800000 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008225 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.008225 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008225 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.008225 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20110.679612 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 20110.679612 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21150 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21150 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12589.285714 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 12589.285714 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20357.037037 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20357.037037 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20357.037037 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20357.037037 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1188,517 +1189,520 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 325 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 325 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 349 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 349 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 378 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 378 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 378 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 378 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2051500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2051500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1754500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1754500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 612000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 612000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3806000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3806000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3806000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3806000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003581 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003581 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002887 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002887 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.785714 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003272 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003272 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003272 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003272 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12509.146341 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12509.146341 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16551.886792 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16551.886792 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11127.272727 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11127.272727 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14096.296296 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14096.296296 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14096.296296 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14096.296296 # average overall mshr miss latency +system.cpu1.dcache.demand_mshr_hits::cpu1.data 402 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 402 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 402 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 402 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 273 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 273 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 273 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2153500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2153500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1760500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1760500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 649000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 649000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3914000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3914000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3914000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3914000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003641 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003641 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002933 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002933 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003326 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003326 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003326 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003326 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12972.891566 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12972.891566 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16453.271028 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16453.271028 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11589.285714 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11589.285714 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14336.996337 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14336.996337 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14336.996337 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14336.996337 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 383 # number of replacements -system.cpu1.icache.tags.tagsinuse 84.461587 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 19439 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 84.449474 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 19585 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 496 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.191532 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.485887 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.461587 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164964 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.164964 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.449474 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164940 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.164940 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 20516 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 20516 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 19439 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 19439 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 19439 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 19439 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 19439 # number of overall hits -system.cpu1.icache.overall_hits::total 19439 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 581 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 581 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 581 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 581 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 581 # number of overall misses -system.cpu1.icache.overall_misses::total 581 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14331000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 14331000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 14331000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 14331000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 14331000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 14331000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 20020 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 20020 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 20020 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 20020 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 20020 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 20020 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029021 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.029021 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029021 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.029021 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029021 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.029021 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24666.092943 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 24666.092943 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24666.092943 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 24666.092943 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24666.092943 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 24666.092943 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 20661 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 20661 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 19585 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 19585 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 19585 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 19585 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 19585 # number of overall hits +system.cpu1.icache.overall_hits::total 19585 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 580 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 580 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 580 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 580 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 580 # number of overall misses +system.cpu1.icache.overall_misses::total 580 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14033000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 14033000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 14033000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 14033000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 14033000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 14033000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 20165 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 20165 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 20165 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 20165 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 20165 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 20165 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028763 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.028763 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028763 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.028763 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028763 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.028763 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24194.827586 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 24194.827586 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24194.827586 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 24194.827586 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24194.827586 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 24194.827586 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 64 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 85 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 85 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 85 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 85 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 85 # number of overall MSHR hits +system.cpu1.icache.writebacks::writebacks 383 # number of writebacks +system.cpu1.icache.writebacks::total 383 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 84 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 84 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 84 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 84 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 496 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 496 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 496 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 496 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11831000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 11831000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11831000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 11831000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11831000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 11831000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024775 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024775 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024775 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23852.822581 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 23852.822581 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 23852.822581 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11668000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 11668000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11668000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 11668000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11668000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 11668000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024597 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024597 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024597 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23524.193548 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 23524.193548 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 23524.193548 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 55489 # Number of BP lookups -system.cpu2.branchPred.condPredicted 52130 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1272 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 48168 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 47221 # Number of BTB hits +system.cpu2.branchPred.lookups 46151 # Number of BP lookups +system.cpu2.branchPred.condPredicted 42669 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1261 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 38744 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 37721 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 98.033964 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 905 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 97.359591 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 903 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.numCycles 162291 # number of cpu cycles simulated +system.cpu2.numCycles 162526 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 28975 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 310103 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 55489 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 48126 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 128617 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2701 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 35053 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 247865 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 46151 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 38624 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 123337 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2679 # Number of cycles fetch has spent squashing system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1166 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 20027 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 452 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 160121 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.936679 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.215928 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 26088 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 455 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 160896 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.540529 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.092892 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 52703 32.91% 32.91% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 53972 33.71% 66.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 5883 3.67% 70.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3530 2.20% 72.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 955 0.60% 73.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 37143 23.20% 96.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1222 0.76% 97.06% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 796 0.50% 97.55% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3917 2.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 69454 43.17% 43.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 47444 29.49% 72.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 8853 5.50% 78.16% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3439 2.14% 80.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 969 0.60% 80.90% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 24720 15.36% 96.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1203 0.75% 97.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 808 0.50% 97.51% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 4006 2.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 160121 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.341911 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.910784 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 17197 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 51483 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 87022 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 3059 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1350 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 295507 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 1350 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 17911 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 22825 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13935 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 88104 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 15986 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 292291 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 14001 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu2.fetch.rateDist::total 160896 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.283961 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.525079 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 17877 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 74268 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 63015 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4387 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1339 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 232406 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 1339 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 18566 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 36272 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13923 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 64728 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 26058 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 229231 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 23352 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full system.cpu2.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 205997 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 564188 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 438175 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 191932 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 14065 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1173 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 20395 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 83226 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 39943 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 39492 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 34851 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 243755 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 5682 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 244785 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13094 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10962 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 644 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 160121 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.528750 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.374157 # Number of insts issued each cycle +system.cpu2.rename.RenamedOperands 159189 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 426806 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 335096 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 145681 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 13508 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1198 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1266 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 30557 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 61312 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 27565 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 29913 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 22477 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 187400 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 8554 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 191519 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 13 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 12551 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10065 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 731 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 160896 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.190328 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.355636 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 56124 35.05% 35.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 19550 12.21% 47.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 39272 24.53% 71.79% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 38854 24.27% 96.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3402 2.12% 98.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1615 1.01% 99.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 887 0.55% 99.74% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 212 0.13% 99.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 205 0.13% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 73129 45.45% 45.45% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 27885 17.33% 62.78% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 27023 16.80% 79.58% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 26608 16.54% 96.11% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3367 2.09% 98.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1611 1.00% 99.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 866 0.54% 99.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 196 0.12% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 160121 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 160896 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 80 23.32% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 54 15.74% 39.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 209 60.93% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 80 24.02% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 44 13.21% 37.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 209 62.76% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 118682 48.48% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 86809 35.46% 83.95% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 39294 16.05% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 96792 50.54% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 67722 35.36% 85.90% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 27005 14.10% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 244785 # Type of FU issued -system.cpu2.iq.rate 1.508309 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 343 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001401 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 650053 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 262570 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 243225 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 191519 # Type of FU issued +system.cpu2.iq.rate 1.178390 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 333 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001739 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 544280 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 208542 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 190032 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 245128 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 191852 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 34614 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 22329 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2656 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2475 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1565 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1441 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1350 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 6752 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 289758 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 176 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 83226 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 39943 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1125 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 41 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 1339 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 9482 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 226726 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 191 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 61312 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 27565 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1142 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 39 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 446 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1057 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 243760 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 82166 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1025 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 430 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1052 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1482 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 190532 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 60316 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 987 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 40321 # number of nop insts executed -system.cpu2.iew.exec_refs 121366 # number of memory reference insts executed -system.cpu2.iew.exec_branches 49723 # Number of branches executed -system.cpu2.iew.exec_stores 39200 # Number of stores executed -system.cpu2.iew.exec_rate 1.501993 # Inst execution rate -system.cpu2.iew.wb_sent 243514 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 243225 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 138958 # num instructions producing a value -system.cpu2.iew.wb_consumers 145563 # num instructions consuming a value +system.cpu2.iew.exec_nop 30772 # number of nop insts executed +system.cpu2.iew.exec_refs 87235 # number of memory reference insts executed +system.cpu2.iew.exec_branches 40210 # Number of branches executed +system.cpu2.iew.exec_stores 26919 # Number of stores executed +system.cpu2.iew.exec_rate 1.172317 # Inst execution rate +system.cpu2.iew.wb_sent 190296 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 190032 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 104798 # num instructions producing a value +system.cpu2.iew.wb_consumers 111375 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.498697 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.954624 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.169241 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.940947 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 13911 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5038 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1272 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 157537 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.750713 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.089801 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 13298 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 7823 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1261 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 158397 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.347140 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.933730 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 60893 38.65% 38.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 46269 29.37% 68.02% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5250 3.33% 71.36% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5861 3.72% 75.08% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1535 0.97% 76.05% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 34623 21.98% 98.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 855 0.54% 98.57% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 943 0.60% 99.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1308 0.83% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 80708 50.95% 50.95% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 36780 23.22% 74.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5258 3.32% 77.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 8633 5.45% 82.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1531 0.97% 83.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 22393 14.14% 98.05% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 849 0.54% 98.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 955 0.60% 99.19% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1290 0.81% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 157537 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 275802 # Number of instructions committed -system.cpu2.commit.committedOps 275802 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 158397 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 213383 # Number of instructions committed +system.cpu2.commit.committedOps 213383 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 118948 # Number of memory references committed -system.cpu2.commit.loads 80570 # Number of loads committed -system.cpu2.commit.membars 4324 # Number of memory barriers committed -system.cpu2.commit.branches 48669 # Number of branches committed +system.cpu2.commit.refs 84961 # Number of memory references committed +system.cpu2.commit.loads 58837 # Number of loads committed +system.cpu2.commit.membars 7109 # Number of memory barriers committed +system.cpu2.commit.branches 39190 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 189737 # Number of committed integer instructions. +system.cpu2.commit.int_insts 146276 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 39459 14.31% 14.31% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 113071 41.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 84894 30.78% 86.08% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 38378 13.92% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 29980 14.05% 14.05% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 91333 42.80% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 65946 30.90% 87.76% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 26124 12.24% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 275802 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1308 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 445356 # The number of ROB reads -system.cpu2.rob.rob_writes 582010 # The number of ROB writes -system.cpu2.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 2170 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 45631 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 232019 # Number of Instructions Simulated -system.cpu2.committedOps 232019 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.699473 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.699473 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.429648 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.429648 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 423842 # number of integer regfile reads -system.cpu2.int_regfile_writes 197927 # number of integer regfile writes +system.cpu2.commit.op_class_0::total 213383 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1290 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 383202 # The number of ROB reads +system.cpu2.rob.rob_writes 455861 # The number of ROB writes +system.cpu2.timesIdled 213 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1630 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 45643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 176294 # Number of Instructions Simulated +system.cpu2.committedOps 176294 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.921903 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.921903 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.084713 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.084713 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 321409 # number of integer regfile reads +system.cpu2.int_regfile_writes 151400 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 122993 # number of misc regfile reads +system.cpu2.misc_regfile_reads 88848 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 24.276146 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 44407 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1585.964286 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 23.120660 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 32242 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1111.793103 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.276146 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.047414 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.047414 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.120660 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045158 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.045158 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 343879 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 343879 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 47002 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 47002 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 38151 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 38151 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 85153 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 85153 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 85153 # number of overall hits -system.cpu2.dcache.overall_hits::total 85153 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 527 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 527 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 159 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 159 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 686 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 686 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 686 # number of overall misses -system.cpu2.dcache.overall_misses::total 686 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 9963000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 9963000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 4178000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 4178000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 670500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 670500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 14141000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 14141000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 14141000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 14141000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 47529 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 47529 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 38310 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 38310 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 256599 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 256599 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 37491 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 37491 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 25903 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 25903 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 19 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 19 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 63394 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 63394 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 63394 # number of overall hits +system.cpu2.dcache.overall_hits::total 63394 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 473 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 473 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 153 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 153 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 49 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 49 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 626 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 626 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 626 # number of overall misses +system.cpu2.dcache.overall_misses::total 626 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7957500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 7957500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3701500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3701500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 605000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 605000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 11659000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 11659000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 11659000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 11659000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 37964 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 37964 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 26056 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 26056 # number of WriteReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 85839 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 85839 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 85839 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 85839 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.011088 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.011088 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004150 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.004150 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.823529 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.823529 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007992 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.007992 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007992 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.007992 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 18905.123340 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 18905.123340 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 26276.729560 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 26276.729560 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 11973.214286 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 11973.214286 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 20613.702624 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 20613.702624 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 20613.702624 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 20613.702624 # average overall miss latency +system.cpu2.dcache.demand_accesses::cpu2.data 64020 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 64020 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 64020 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 64020 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.012459 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.012459 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.005872 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.005872 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.720588 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.720588 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.009778 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.009778 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.009778 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.009778 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16823.467230 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 16823.467230 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24192.810458 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 24192.810458 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 12346.938776 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 12346.938776 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 18624.600639 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 18624.600639 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 18624.600639 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 18624.600639 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1707,106 +1711,106 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 367 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 367 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 51 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 51 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 418 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 418 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 418 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 418 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 160 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1620500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1620500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2159500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2159500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 614500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 614500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3780000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3780000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3780000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3780000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003366 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003366 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002819 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002819 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.823529 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.823529 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003122 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003122 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003122 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003122 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10128.125000 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10128.125000 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19995.370370 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19995.370370 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 10973.214286 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 10973.214286 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14104.477612 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14104.477612 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14104.477612 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14104.477612 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 311 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 50 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 50 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 361 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 361 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 361 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 361 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 103 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 49 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 49 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 265 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 265 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1647500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1647500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1967500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1967500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 556000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 556000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3615000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3615000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3615000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3615000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004267 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004267 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003953 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003953 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.720588 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.720588 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004139 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004139 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004139 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004139 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10169.753086 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10169.753086 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19101.941748 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19101.941748 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 11346.938776 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 11346.938776 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13641.509434 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13641.509434 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13641.509434 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13641.509434 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 386 # number of replacements -system.cpu2.icache.tags.tagsinuse 80.953803 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 19454 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 77.580266 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 25515 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 500 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 38.908000 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 51.030000 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 80.953803 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.158113 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.158113 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 77.580266 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.151524 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.151524 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 20527 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 20527 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 19454 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 19454 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 19454 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 19454 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 19454 # number of overall hits -system.cpu2.icache.overall_hits::total 19454 # number of overall hits +system.cpu2.icache.tags.tag_accesses 26588 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 26588 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 25515 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 25515 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 25515 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 25515 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 25515 # number of overall hits +system.cpu2.icache.overall_hits::total 25515 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 573 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 573 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 573 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 573 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 573 # number of overall misses system.cpu2.icache.overall_misses::total 573 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8014500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 8014500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 8014500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 8014500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 8014500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 8014500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 20027 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 20027 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 20027 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 20027 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 20027 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 20027 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.028611 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.028611 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.028611 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.028611 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.028611 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.028611 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13986.910995 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 13986.910995 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13986.910995 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 13986.910995 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13986.910995 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 13986.910995 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7955500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 7955500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 7955500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 7955500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 7955500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 7955500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 26088 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 26088 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 26088 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 26088 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 26088 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 26088 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.021964 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.021964 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.021964 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.021964 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.021964 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.021964 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13883.944154 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 13883.944154 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13883.944154 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 13883.944154 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13883.944154 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 13883.944154 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1815,6 +1819,8 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs 5 system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.writebacks::writebacks 386 # number of writebacks +system.cpu2.icache.writebacks::total 386 # number of writebacks system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 73 # number of ReadReq MSHR hits system.cpu2.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits system.cpu2.icache.demand_mshr_hits::cpu2.inst 73 # number of demand (read+write) MSHR hits @@ -1827,397 +1833,397 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 500 system.cpu2.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 500 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 500 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6952000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 6952000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6952000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 6952000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6952000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 6952000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024966 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.024966 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.024966 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13904 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13904 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13904 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 13904 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13904 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 13904 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6895000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 6895000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6895000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 6895000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6895000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 6895000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.019166 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.019166 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.019166 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13790 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13790 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13790 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 13790 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13790 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 13790 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 42820 # Number of BP lookups -system.cpu3.branchPred.condPredicted 39316 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1255 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 35479 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 34386 # Number of BTB hits +system.cpu3.branchPred.lookups 52678 # Number of BP lookups +system.cpu3.branchPred.condPredicted 49211 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1284 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 45275 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 44303 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 96.919304 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 900 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 97.853120 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 906 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.numCycles 161928 # number of cpu cycles simulated +system.cpu3.numCycles 162161 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 36909 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 226016 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 42820 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 35286 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 121156 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 2665 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 30846 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 291154 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 52678 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 45209 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 126827 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 2723 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 27941 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 455 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 160564 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.407638 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.031731 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.PendingTrapStallCycles 1166 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 21882 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 451 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 160213 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.817293 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.188011 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 74840 46.61% 46.61% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 45030 28.04% 74.66% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 9823 6.12% 80.77% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3413 2.13% 82.90% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 964 0.60% 83.50% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 20524 12.78% 96.28% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1162 0.72% 97.01% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 811 0.51% 97.51% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3997 2.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 57700 36.01% 36.01% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 51927 32.41% 68.43% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 6814 4.25% 72.68% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3535 2.21% 74.89% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 932 0.58% 75.47% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 33301 20.79% 96.25% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1242 0.78% 97.03% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 787 0.49% 97.52% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3975 2.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 160564 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.264439 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.395781 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 17966 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 81801 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 54656 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 4799 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1332 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 210555 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1332 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 18639 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 40771 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 13962 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 56374 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 29476 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 207391 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 26344 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full +system.cpu3.fetch.rateDist::total 160213 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.324850 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.795463 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 17433 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 58368 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 79576 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 3465 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1361 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 275763 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1361 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 18155 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 26788 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 14101 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 81078 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 18720 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 272367 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 16743 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 143048 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 379530 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 299622 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 129648 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 13400 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1181 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1248 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 33973 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 53782 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 23352 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 26620 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 18276 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 168080 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 9470 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 172966 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 9 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 12631 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10295 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 757 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 160564 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.077240 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.332251 # Number of insts issued each cycle +system.cpu3.rename.RenamedOperands 191251 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 520897 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 405695 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 177247 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 14004 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1196 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1267 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 23402 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 76309 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 36069 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 36463 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 30962 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 226032 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 6585 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 227862 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 13 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 13164 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10986 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 709 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 160213 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.422244 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.377526 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 78662 48.99% 48.99% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 30467 18.97% 67.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 22821 14.21% 82.18% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 22372 13.93% 96.11% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3353 2.09% 98.20% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1614 1.01% 99.21% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 863 0.54% 99.74% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 215 0.13% 99.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 197 0.12% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 61467 38.37% 38.37% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 22016 13.74% 52.11% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 35438 22.12% 74.23% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 35000 21.85% 96.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3395 2.12% 98.19% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1603 1.00% 99.19% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 883 0.55% 99.74% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 200 0.12% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 160564 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 160213 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 82 24.55% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 43 12.87% 37.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 209 62.57% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 82 24.12% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 49 14.41% 38.53% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 209 61.47% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 89169 51.55% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 61014 35.28% 86.83% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 22783 13.17% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 111773 49.05% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 80677 35.41% 84.46% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 35412 15.54% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 172966 # Type of FU issued -system.cpu3.iq.rate 1.068166 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 334 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001931 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 506839 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 190218 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 171502 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 227862 # Type of FU issued +system.cpu3.iq.rate 1.405159 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 340 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001492 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 616290 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 245818 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 226322 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 173300 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 228202 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 18096 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 30727 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2521 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2667 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu3.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1454 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedStores 1566 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1332 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 10558 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 75 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 205014 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 53782 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 23352 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1140 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 1361 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 7576 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 269910 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 166 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 76309 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 36069 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1148 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 41 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu3.iew.memOrderViolationEvents 37 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 429 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1047 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1476 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 171988 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 52726 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 978 # Number of squashed instructions skipped in execute +system.cpu3.iew.predictedTakenIncorrect 452 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1067 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1519 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 226838 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 75201 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1024 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 27464 # number of nop insts executed -system.cpu3.iew.exec_refs 75422 # number of memory reference insts executed -system.cpu3.iew.exec_branches 36861 # Number of branches executed -system.cpu3.iew.exec_stores 22696 # Number of stores executed -system.cpu3.iew.exec_rate 1.062126 # Inst execution rate -system.cpu3.iew.wb_sent 171762 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 171502 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 92998 # num instructions producing a value -system.cpu3.iew.wb_consumers 99577 # num instructions consuming a value +system.cpu3.iew.exec_nop 37293 # number of nop insts executed +system.cpu3.iew.exec_refs 110524 # number of memory reference insts executed +system.cpu3.iew.exec_branches 46686 # Number of branches executed +system.cpu3.iew.exec_stores 35323 # Number of stores executed +system.cpu3.iew.exec_rate 1.398844 # Inst execution rate +system.cpu3.iew.wb_sent 226605 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 226322 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 128132 # num instructions producing a value +system.cpu3.iew.wb_consumers 134738 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.059125 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.933931 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.395662 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.950972 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 13412 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 8713 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1255 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 158053 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.211980 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.860135 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 13998 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 5876 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1284 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 157615 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.623367 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.050526 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 87086 55.10% 55.10% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 33413 21.14% 76.24% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5238 3.31% 79.55% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 9506 6.01% 85.57% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1538 0.97% 86.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 18185 11.51% 98.05% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 832 0.53% 98.57% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 959 0.61% 99.18% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1296 0.82% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 67043 42.54% 42.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 43238 27.43% 69.97% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5262 3.34% 73.31% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 6673 4.23% 77.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1534 0.97% 78.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 30788 19.53% 98.05% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 827 0.52% 98.57% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 952 0.60% 99.18% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1298 0.82% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 158053 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 191557 # Number of instructions committed -system.cpu3.commit.committedOps 191557 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 157615 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 255867 # Number of instructions committed +system.cpu3.commit.committedOps 255867 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 73159 # Number of memory references committed -system.cpu3.commit.loads 51261 # Number of loads committed -system.cpu3.commit.membars 7996 # Number of memory barriers committed -system.cpu3.commit.branches 35851 # Number of branches committed +system.cpu3.commit.refs 108145 # Number of memory references committed +system.cpu3.commit.loads 73642 # Number of loads committed +system.cpu3.commit.membars 5159 # Number of memory barriers committed +system.cpu3.commit.branches 45627 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 131131 # Number of committed integer instructions. +system.cpu3.commit.int_insts 175889 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 26638 13.91% 13.91% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 83764 43.73% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 59257 30.93% 88.57% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 21898 11.43% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 36414 14.23% 14.23% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 106149 41.49% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.72% # Class of committed instruction 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committed instruction -system.cpu3.commit.bw_lim_events 1296 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 361140 # The number of ROB reads -system.cpu3.rob.rob_writes 412450 # The number of ROB writes -system.cpu3.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1364 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 45995 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 156923 # Number of Instructions Simulated -system.cpu3.committedOps 156923 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.031895 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.031895 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.969091 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.969091 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 285937 # number of integer regfile reads -system.cpu3.int_regfile_writes 135307 # number of integer regfile writes +system.cpu3.commit.op_class_0::total 255867 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1298 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 425596 # The number of ROB reads +system.cpu3.rob.rob_writes 542328 # The number of ROB writes +system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1948 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 46007 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 214294 # Number of Instructions Simulated +system.cpu3.committedOps 214294 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.756722 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.756722 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.321489 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.321489 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 391365 # number of integer regfile reads +system.cpu3.int_regfile_writes 183208 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 77019 # number of misc regfile reads +system.cpu3.misc_regfile_reads 112150 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 23.138417 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 27896 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 24.277315 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 40522 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 996.285714 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1447.214286 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.138417 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.045192 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.045192 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.277315 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047417 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.047417 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 226271 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 226271 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 34144 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 34144 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 21673 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 21673 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 55817 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 55817 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 55817 # number of overall hits -system.cpu3.dcache.overall_hits::total 55817 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 463 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 463 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 154 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 154 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 617 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 617 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 617 # number of overall misses -system.cpu3.dcache.overall_misses::total 617 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 7346500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 7346500 # number of ReadReq miss cycles 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of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 21827 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.tags.tag_accesses 316074 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 316074 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 43937 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 43937 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 34273 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 34273 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 78210 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 78210 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 78210 # number of overall hits +system.cpu3.dcache.overall_hits::total 78210 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 514 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 514 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 159 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 159 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 673 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 673 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 673 # number of overall misses +system.cpu3.dcache.overall_misses::total 673 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 9349000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 9349000 # number of ReadReq miss cycles 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of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 34432 # number of WriteReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 56434 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 56434 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 56434 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 56434 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.013379 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.013379 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007055 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.007055 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.732394 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.732394 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.010933 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.010933 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.010933 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.010933 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15867.170626 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 15867.170626 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21301.948052 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 21301.948052 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 12653.846154 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 12653.846154 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17223.662885 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 17223.662885 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17223.662885 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 17223.662885 # average overall miss latency +system.cpu3.dcache.demand_accesses::cpu3.data 78883 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 78883 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 78883 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 78883 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.011563 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.011563 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004618 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.004618 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008532 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.008532 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008532 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.008532 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 18188.715953 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 18188.715953 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23839.622642 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 23839.622642 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11938.596491 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 11938.596491 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 19523.774146 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 19523.774146 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 19523.774146 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 19523.774146 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2226,106 +2232,106 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 299 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 347 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 347 # number of ReadReq MSHR hits system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 52 # number of WriteReq MSHR hits system.cpu3.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 351 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 351 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 164 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 102 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 52 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 266 # number of demand (read+write) MSHR misses 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-system.cpu3.dcache.demand_mshr_miss_latency::total 3648500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3648500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3648500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004739 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004739 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.004673 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.004673 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.732394 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.732394 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004713 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.004713 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004713 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.004713 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10746.951220 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10746.951220 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 18490.196078 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 18490.196078 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 11653.846154 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 11653.846154 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13716.165414 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13716.165414 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13716.165414 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13716.165414 # average overall mshr miss latency +system.cpu3.dcache.demand_mshr_hits::cpu3.data 399 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 399 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 399 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 399 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 167 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 274 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 274 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1719000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1719000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2129500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2129500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 623500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 623500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3848500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3848500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3848500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3848500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003757 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003757 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003108 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003108 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003473 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003473 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003473 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003473 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10293.413174 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10293.413174 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19901.869159 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19901.869159 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 10938.596491 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 10938.596491 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14045.620438 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14045.620438 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14045.620438 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14045.620438 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 384 # number of replacements -system.cpu3.icache.tags.tagsinuse 77.554391 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 27370 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 81.046367 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 21310 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 54.959839 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 42.791165 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.554391 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151473 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.151473 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 81.046367 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.158294 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.158294 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 28439 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 28439 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 27370 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 27370 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 27370 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 27370 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 27370 # number of overall hits -system.cpu3.icache.overall_hits::total 27370 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 571 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 571 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 571 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 571 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 571 # number of overall misses -system.cpu3.icache.overall_misses::total 571 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7675000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 7675000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 7675000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 7675000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 7675000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 7675000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 27941 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 27941 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 27941 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 27941 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 27941 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 27941 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020436 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.020436 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020436 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.020436 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020436 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.020436 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13441.330998 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13441.330998 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13441.330998 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13441.330998 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13441.330998 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13441.330998 # average overall miss latency +system.cpu3.icache.tags.tag_accesses 22380 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 22380 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 21310 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 21310 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 21310 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 21310 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 21310 # number of overall hits +system.cpu3.icache.overall_hits::total 21310 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 572 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 572 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 572 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 572 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 572 # number of overall misses +system.cpu3.icache.overall_misses::total 572 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 8104500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 8104500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 8104500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 8104500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 8104500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 8104500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 21882 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 21882 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 21882 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 21882 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 21882 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 21882 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026140 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.026140 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026140 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.026140 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026140 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.026140 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14168.706294 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 14168.706294 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14168.706294 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 14168.706294 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14168.706294 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 14168.706294 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2334,77 +2340,81 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 73 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 73 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 73 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 73 # number of overall MSHR hits +system.cpu3.icache.writebacks::writebacks 384 # number of writebacks +system.cpu3.icache.writebacks::total 384 # number of writebacks +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 74 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 74 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 74 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 74 # number of overall MSHR hits system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6616000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 6616000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6616000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 6616000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6616000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 6616000 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017823 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.017823 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.017823 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13285.140562 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 13285.140562 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 13285.140562 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6912000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 6912000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6912000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 6912000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6912000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 6912000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.022758 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.022758 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.022758 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.022758 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.022758 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.022758 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13879.518072 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13879.518072 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13879.518072 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 13879.518072 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13879.518072 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 13879.518072 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 419.148333 # Cycle average of tags in use -system.l2c.tags.total_refs 2348 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 419.218954 # Cycle average of tags in use +system.l2c.tags.total_refs 2347 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 532 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.413534 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 4.411654 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.788271 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 288.012358 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.076849 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 62.302913 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 5.322223 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 3.076380 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.717940 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.174188 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.677210 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.788461 # Average occupied blocks per requestor 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WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 676 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 676 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu3.data 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 90 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 92 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) @@ -2544,16 +2556,16 @@ system.l2c.UpgradeReq_miss_rate::cpu0.data 0.900000 # system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.966667 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.967391 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss 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rate for ReadSharedReq accesses @@ -2562,55 +2574,55 @@ system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.083333 system.l2c.ReadSharedReq_miss_rate::total 0.724138 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.595395 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.175403 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.169355 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.020000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.018000 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.010040 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.018072 # miss rate for demand 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accesses system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.167339 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.010000 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.161290 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.014056 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_mshr_miss_rate::total 0.214558 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadSharedReq accesses @@ -2732,128 +2744,129 @@ system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.083333 system.l2c.ReadSharedReq_mshr_miss_rate::total 0.724138 # mshr miss rate for ReadSharedReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.167339 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161290 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.014056 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.283525 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.167339 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161290 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.014056 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.283525 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21722.222222 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21763.157895 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 21800 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 21809.380952 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21770.080460 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71053.191489 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21740.740741 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21850 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 21904.571429 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 21785.714286 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21814.561798 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70968.085106 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71461.538462 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 113791.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 84458.333333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 76236.641221 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72700 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 73000 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66278.270510 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69740 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 67214.285714 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 86500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 72500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69761.904762 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70470.414201 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69975 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72700 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 111692.307692 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 73000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 83538.461538 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 68676.426426 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70470.414201 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69975 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72700 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 111692.307692 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 83538.461538 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 68676.426426 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 90875 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 106583.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 76103.053435 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66068.750000 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73000 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 70785.714286 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66272.727273 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69753.333333 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 67142.857143 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 86500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69767.857143 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70428.994083 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66068.750000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69950 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 89461.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 70785.714286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 105038.461538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 68647.147147 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70428.994083 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66068.750000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69950 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 89461.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 70785.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 105038.461538 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 68647.147147 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 534 # Transaction distribution -system.membus.trans_dist::UpgradeReq 287 # Transaction distribution -system.membus.trans_dist::UpgradeResp 87 # Transaction distribution +system.membus.trans_dist::UpgradeReq 290 # Transaction distribution +system.membus.trans_dist::UpgradeResp 89 # Transaction distribution system.membus.trans_dist::ReadExReq 162 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution system.membus.trans_dist::ReadSharedReq 535 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1736 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1736 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1741 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1741 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42560 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 42560 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 231 # Total snoops (count) -system.membus.snoop_fanout::samples 984 # Request fanout histogram +system.membus.snoops 232 # Total snoops (count) +system.membus.snoop_fanout::samples 987 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 984 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 987 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 984 # Request fanout histogram -system.membus.reqLayer0.occupancy 923503 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 987 # Request fanout histogram +system.membus.reqLayer0.occupancy 936504 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 3708663 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3712661 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.4 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4928 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.tot_requests 4933 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 1339 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2358 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2364 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadResp 2773 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 678 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 394 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 394 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2778 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 676 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 293 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 293 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 391 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 391 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 2102 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 672 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 677 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1448 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 592 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1141 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 370 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1145 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 369 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1146 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 364 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6575 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 38848 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1140 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 374 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1151 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 360 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1140 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 376 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6581 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 53760 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31744 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41216 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 32000 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41664 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41088 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 150336 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1019 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4928 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.293425 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.231126 # Request fanout histogram +system.toL2Bus.pkt_size::total 193600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1022 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3463 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.289633 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.182691 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1910 38.76% 38.76% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 975 19.78% 58.54% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 730 14.81% 73.36% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 1313 26.64% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1230 35.52% 35.52% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 835 24.11% 59.63% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 563 16.26% 75.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 835 24.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram @@ -2862,24 +2875,24 @@ system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4928 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2484958 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 910999 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3463 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3953462 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 911498 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 505496 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 505495 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 745995 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 746495 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 435966 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 439455 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 752494 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 752991 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 426475 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 419474 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 748497 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 747998 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 424472 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 434475 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 9e7ba2833..374f2beb4 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1726221 # Simulator instruction rate (inst/s) -host_op_rate 1726160 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 223510854 # Simulator tick rate (ticks/s) -host_mem_usage 306324 # Number of bytes of host memory used -host_seconds 0.39 # Real time elapsed on the host +host_inst_rate 1763094 # Simulator instruction rate (inst/s) +host_op_rate 1763034 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 228285342 # Simulator tick rate (ticks/s) +host_mem_usage 306164 # Number of bytes of host memory used +host_seconds 0.38 # Real time elapsed on the host sim_insts 677333 # Number of instructions simulated sim_ops 677333 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -232,6 +232,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.writebacks::writebacks 215 # number of writebacks +system.cpu0.icache.writebacks::total 215 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 173297 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started @@ -401,6 +403,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.writebacks::writebacks 278 # number of writebacks +system.cpu1.icache.writebacks::total 278 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 173296 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started @@ -571,6 +575,8 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.writebacks::writebacks 278 # number of writebacks +system.cpu2.icache.writebacks::total 278 # number of writebacks system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 173297 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started @@ -740,6 +746,8 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed +system.cpu3.icache.writebacks::writebacks 279 # number of writebacks +system.cpu3.icache.writebacks::total 279 # number of writebacks system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.tagsinuse 366.582953 # Cycle average of tags in use @@ -772,8 +780,10 @@ system.l2c.tags.age_task_id_blocks_1024::1 373 # system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 19424 # Number of tag accesses system.l2c.tags.data_accesses 19424 # Number of data accesses -system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits -system.l2c.Writeback_hits::total 1 # number of Writeback hits +system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits system.l2c.ReadCleanReq_hits::cpu0.inst 185 # number of ReadCleanReq hits @@ -842,8 +852,10 @@ system.l2c.overall_misses::cpu2.data 13 # nu system.l2c.overall_misses::cpu3.inst 1 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses system.l2c.overall_misses::total 559 # number of overall misses -system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) @@ -957,8 +969,9 @@ system.toL2Bus.snoop_filter.tot_snoops 0 # To system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 496 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 495 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution @@ -974,15 +987,15 @@ system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 834 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 6229 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39040 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30720 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 30208 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 22976 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 30400 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 165888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 197568 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 0 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 1.246554 # Request fanout histogram diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index f34aec4c9..73bc4c073 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,199 +1,199 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000261 # Number of seconds simulated -sim_ticks 260712500 # Number of ticks simulated -final_tick 260712500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000265 # Number of seconds simulated +sim_ticks 264840500 # Number of ticks simulated +final_tick 264840500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1018019 # Simulator instruction rate (inst/s) -host_op_rate 1017997 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 401917302 # Simulator tick rate (ticks/s) -host_mem_usage 306320 # Number of bytes of host memory used +host_inst_rate 1022675 # Simulator instruction rate (inst/s) +host_op_rate 1022653 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 408888728 # Simulator tick rate (ticks/s) +host_mem_usage 306160 # Number of bytes of host memory used host_seconds 0.65 # Real time elapsed on the host -sim_insts 660333 # Number of instructions simulated -sim_ops 660333 # Number of ops (including micro ops) simulated +sim_insts 662366 # Number of instructions simulated +sim_ops 662366 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 3456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 3456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 3712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 54 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 58 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69962123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40504387 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 3436736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3927698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 13255981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 5400585 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 245481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3682217 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 140415208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69962123 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 3436736 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 13255981 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 245481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86900321 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69962123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40504387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 3436736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3927698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 13255981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 5400585 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 245481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3682217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 140415208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 68871642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 39873056 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 1691584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3624823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 14015983 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 5558062 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 966620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3624823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 138226593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 68871642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 1691584 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 14015983 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 966620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 85545829 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 68871642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 39873056 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 1691584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3624823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 14015983 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 5558062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 966620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3624823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 138226593 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 521425 # number of cpu cycles simulated +system.cpu0.numCycles 529681 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 157788 # Number of instructions committed -system.cpu0.committedOps 157788 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 108684 # Number of integer alu accesses +system.cpu0.committedInsts 158238 # Number of instructions committed +system.cpu0.committedOps 158238 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108984 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 25901 # number of instructions that are conditional controls -system.cpu0.num_int_insts 108684 # number of integer instructions +system.cpu0.num_conditional_control_insts 25976 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108984 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 314210 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110290 # number of times the integer registers were written +system.cpu0.num_int_register_reads 315110 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110590 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 73628 # number of memory refs -system.cpu0.num_load_insts 48745 # Number of load instructions -system.cpu0.num_store_insts 24883 # Number of store instructions +system.cpu0.num_mem_refs 73853 # number of memory refs +system.cpu0.num_load_insts 48895 # Number of load instructions +system.cpu0.num_store_insts 24958 # Number of store instructions system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 521424.998000 # Number of busy cycles +system.cpu0.num_busy_cycles 529680.998000 # Number of busy cycles system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 26766 # Number of branches fetched -system.cpu0.op_class::No_OpClass 23493 14.88% 14.88% # Class of executed instruction -system.cpu0.op_class::IntAlu 60645 38.42% 53.30% # Class of executed instruction -system.cpu0.op_class::IntMult 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::MemRead 48829 30.93% 84.24% # Class of executed instruction -system.cpu0.op_class::MemWrite 24883 15.76% 100.00% # Class of executed instruction +system.cpu0.Branches 26841 # Number of branches fetched +system.cpu0.op_class::No_OpClass 23568 14.89% 14.89% # Class of executed instruction +system.cpu0.op_class::IntAlu 60795 38.40% 53.29% # Class of executed instruction +system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::MemRead 48979 30.94% 84.23% # Class of executed instruction +system.cpu0.op_class::MemWrite 24958 15.77% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 157850 # Class of executed instruction +system.cpu0.op_class::total 158300 # Class of executed instruction system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 145.664312 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 73097 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 145.090849 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 73323 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 437.706587 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 439.059880 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.664312 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284501 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.284501 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.090849 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283381 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.283381 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 294744 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 294744 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 48566 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48566 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24649 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24649 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 295643 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 295643 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 48717 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48717 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24724 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24724 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73215 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73215 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73215 # number of overall hits -system.cpu0.dcache.overall_hits::total 73215 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 169 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 169 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 73441 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73441 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73441 # number of overall hits +system.cpu0.dcache.overall_hits::total 73441 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 168 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 168 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 352 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 352 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 352 # number of overall misses -system.cpu0.dcache.overall_misses::total 352 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4596500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4596500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7006000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7006000 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 359000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 359000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11602500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11602500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11602500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11602500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48735 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48735 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24832 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24832 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 351 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 351 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 351 # number of overall misses +system.cpu0.dcache.overall_misses::total 351 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5149000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5149000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7867000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7867000 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 395000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 395000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 13016000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 13016000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 13016000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 13016000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48885 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48885 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24907 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24907 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73567 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73567 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73567 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73567 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003468 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003468 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007370 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007370 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 73792 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73792 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73792 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73792 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003437 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007347 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007347 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004785 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004785 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004785 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004785 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27198.224852 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27198.224852 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38284.153005 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38284.153005 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13807.692308 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 13807.692308 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32961.647727 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 32961.647727 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32961.647727 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32961.647727 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004757 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004757 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004757 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004757 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30648.809524 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 30648.809524 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42989.071038 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42989.071038 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15192.307692 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 15192.307692 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37082.621083 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 37082.621083 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37082.621083 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 37082.621083 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -204,98 +204,98 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 169 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 168 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 168 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 352 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 352 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 352 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 352 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4427500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4427500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6823000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6823000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 333000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 333000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11250500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11250500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11250500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11250500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003468 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003468 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007370 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007370 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 351 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 351 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4981000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4981000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7684000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7684000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 369000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 369000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12665000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12665000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12665000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12665000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003437 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003437 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007347 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007347 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004785 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004785 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004785 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004785 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26198.224852 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26198.224852 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37284.153005 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37284.153005 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12807.692308 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12807.692308 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31961.647727 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31961.647727 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31961.647727 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31961.647727 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004757 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004757 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004757 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004757 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29648.809524 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29648.809524 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41989.071038 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41989.071038 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14192.307692 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14192.307692 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36082.621083 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 36082.621083 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36082.621083 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 36082.621083 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 212.605336 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 157384 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 211.456411 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 157834 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 337.010707 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 337.974304 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.605336 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415245 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.415245 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.456411 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.413001 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.413001 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 158318 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 158318 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 157384 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 157384 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 157384 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 157384 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 157384 # number of overall hits -system.cpu0.icache.overall_hits::total 157384 # number of overall hits +system.cpu0.icache.tags.tag_accesses 158768 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 158768 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 157834 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 157834 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 157834 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 157834 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 157834 # number of overall hits +system.cpu0.icache.overall_hits::total 157834 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18137000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18137000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18137000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18137000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18137000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18137000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 157851 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 157851 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 157851 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 157851 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 157851 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 157851 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002958 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002958 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002958 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002958 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002958 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002958 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38837.259101 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38837.259101 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38837.259101 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38837.259101 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38837.259101 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38837.259101 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20139500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 20139500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 20139500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 20139500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 20139500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 20139500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 158301 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 158301 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 158301 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 158301 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 158301 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 158301 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002950 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002950 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002950 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002950 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002950 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002950 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43125.267666 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 43125.267666 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43125.267666 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 43125.267666 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43125.267666 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 43125.267666 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -304,164 +304,166 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.writebacks::writebacks 215 # number of writebacks +system.cpu0.icache.writebacks::total 215 # number of writebacks system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17670000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17670000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17670000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17670000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17670000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17670000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002958 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37837.259101 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 37837.259101 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 37837.259101 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19672500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 19672500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19672500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 19672500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19672500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 19672500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002950 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002950 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42125.267666 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 42125.267666 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 42125.267666 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 521425 # number of cpu cycles simulated +system.cpu1.numCycles 529680 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 168182 # Number of instructions committed -system.cpu1.committedOps 168182 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 110851 # Number of integer alu accesses +system.cpu1.committedInsts 168829 # Number of instructions committed +system.cpu1.committedOps 168829 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 111193 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 32674 # number of instructions that are conditional controls -system.cpu1.num_int_insts 110851 # number of integer instructions +system.cpu1.num_conditional_control_insts 32827 # number of instructions that are conditional controls +system.cpu1.num_int_insts 111193 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 274889 # number of times the integer registers were read -system.cpu1.num_int_register_writes 104194 # number of times the integer registers were written +system.cpu1.num_int_register_reads 275699 # number of times the integer registers were read +system.cpu1.num_int_register_writes 104505 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 54346 # number of memory refs -system.cpu1.num_load_insts 41092 # Number of load instructions -system.cpu1.num_store_insts 13254 # Number of store instructions -system.cpu1.num_idle_cycles 67743.001740 # Number of idle cycles -system.cpu1.num_busy_cycles 453681.998260 # Number of busy cycles -system.cpu1.not_idle_fraction 0.870081 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.129919 # Percentage of idle cycles -system.cpu1.Branches 34327 # Number of branches fetched -system.cpu1.op_class::No_OpClass 25108 14.93% 14.93% # Class of executed instruction -system.cpu1.op_class::IntAlu 74636 44.37% 59.30% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::MemRead 55216 32.82% 92.12% # Class of executed instruction -system.cpu1.op_class::MemWrite 13254 7.88% 100.00% # Class of executed instruction +system.cpu1.num_mem_refs 54535 # number of memory refs +system.cpu1.num_load_insts 41264 # Number of load instructions +system.cpu1.num_store_insts 13271 # Number of store instructions +system.cpu1.num_idle_cycles 73879.862241 # Number of idle cycles +system.cpu1.num_busy_cycles 455800.137759 # Number of busy cycles +system.cpu1.not_idle_fraction 0.860520 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.139480 # Percentage of idle cycles +system.cpu1.Branches 34479 # Number of branches fetched +system.cpu1.op_class::No_OpClass 25261 14.96% 14.96% # Class of executed instruction +system.cpu1.op_class::IntAlu 74858 44.33% 59.29% # Class of executed instruction +system.cpu1.op_class::IntMult 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::MemRead 55471 32.85% 92.14% # Class of executed instruction +system.cpu1.op_class::MemWrite 13271 7.86% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 168214 # Class of executed instruction +system.cpu1.op_class::total 168861 # Class of executed instruction system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 26.819046 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 28734 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 990.827586 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 26.495164 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 28944 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 964.800000 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.819046 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.052381 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.052381 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.495164 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051748 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.051748 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 217604 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 217604 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 40921 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 40921 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 13075 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 13075 # number of WriteReq hits +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 218364 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 218364 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 41094 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 41094 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 13094 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 13094 # number of WriteReq hits system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 53996 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 53996 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 53996 # number of overall hits -system.cpu1.dcache.overall_hits::total 53996 # number of overall hits +system.cpu1.dcache.demand_hits::cpu1.data 54188 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 54188 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 54188 # number of overall hits +system.cpu1.dcache.overall_hits::total 54188 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 163 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 108 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 108 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 271 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 271 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 271 # number of overall misses -system.cpu1.dcache.overall_misses::total 271 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2627500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2627500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1987500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1987500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 248500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 248500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4615000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4615000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4615000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4615000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 41084 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 41084 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 13183 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 13183 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 54267 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 54267 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 54267 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 54267 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003967 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.003967 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008192 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.008192 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.811594 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004994 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.004994 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004994 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.004994 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16119.631902 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16119.631902 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18402.777778 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18402.777778 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4437.500000 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 4437.500000 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17029.520295 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17029.520295 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17029.520295 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17029.520295 # average overall miss latency +system.cpu1.dcache.WriteReq_misses::cpu1.data 107 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 107 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 270 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 270 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 270 # number of overall misses +system.cpu1.dcache.overall_misses::total 270 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2920000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2920000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2149500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2149500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 245500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 245500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5069500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5069500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5069500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5069500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 41257 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 41257 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 13201 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 13201 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 54458 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 54458 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 54458 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 54458 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003951 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.003951 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008105 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.008105 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.808824 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.808824 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004958 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.004958 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004958 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.004958 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17914.110429 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 17914.110429 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20088.785047 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20088.785047 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4463.636364 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 4463.636364 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18775.925926 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18775.925926 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18775.925926 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18775.925926 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,97 +474,97 @@ system.cpu1.dcache.fast_writes 0 # nu system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 271 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 271 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2464500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2464500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1879500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1879500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 192500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 192500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4344000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4344000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4344000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4344000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003967 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003967 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008192 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008192 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.811594 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004994 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.004994 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004994 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.004994 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15119.631902 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15119.631902 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17402.777778 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17402.777778 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3437.500000 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3437.500000 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16029.520295 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16029.520295 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16029.520295 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16029.520295 # average overall mshr miss latency +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2757000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2757000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2042500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2042500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 190500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 190500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4799500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4799500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4799500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4799500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003951 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003951 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008105 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008105 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.808824 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.808824 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004958 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.004958 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004958 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.004958 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16914.110429 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16914.110429 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19088.785047 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19088.785047 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3463.636364 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3463.636364 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17775.925926 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17775.925926 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17775.925926 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17775.925926 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 67.790334 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 167849 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 67.000483 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 168496 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 458.603825 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 460.371585 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 67.790334 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.132403 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.132403 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 67.000483 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130860 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.130860 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 168581 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 168581 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 167849 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 167849 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 167849 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 167849 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 167849 # number of overall hits -system.cpu1.icache.overall_hits::total 167849 # number of overall hits +system.cpu1.icache.tags.tag_accesses 169228 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 169228 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 168496 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 168496 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 168496 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 168496 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 168496 # number of overall hits +system.cpu1.icache.overall_hits::total 168496 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5586500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5586500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5586500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5586500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5586500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5586500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 168215 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 168215 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 168215 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 168215 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 168215 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 168215 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002176 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002176 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002176 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002176 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002176 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002176 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15263.661202 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15263.661202 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15263.661202 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15263.661202 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15263.661202 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15263.661202 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5681500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5681500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5681500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5681500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5681500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5681500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 168862 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 168862 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 168862 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 168862 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 168862 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 168862 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002167 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002167 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002167 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002167 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002167 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002167 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15523.224044 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15523.224044 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15523.224044 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15523.224044 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15523.224044 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15523.224044 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -571,164 +573,166 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.writebacks::writebacks 280 # number of writebacks +system.cpu1.icache.writebacks::total 280 # number of writebacks system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5220500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5220500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5220500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5220500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5220500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5220500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002176 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002176 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002176 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14263.661202 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 14263.661202 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 14263.661202 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5315500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5315500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5315500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5315500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5315500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5315500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002167 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002167 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002167 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14523.224044 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 14523.224044 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 14523.224044 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 521424 # number of cpu cycles simulated +system.cpu2.numCycles 529681 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 165155 # Number of instructions committed -system.cpu2.committedOps 165155 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 110249 # Number of integer alu accesses +system.cpu2.committedInsts 165415 # Number of instructions committed +system.cpu2.committedOps 165415 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 110386 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 31462 # number of instructions that are conditional controls -system.cpu2.num_int_insts 110249 # number of integer instructions +system.cpu2.num_conditional_control_insts 31522 # number of instructions that are conditional controls +system.cpu2.num_int_insts 110386 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 277329 # number of times the integer registers were read -system.cpu2.num_int_register_writes 105715 # number of times the integer registers were written +system.cpu2.num_int_register_reads 277687 # number of times the integer registers were read +system.cpu2.num_int_register_writes 105904 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 54956 # number of memory refs -system.cpu2.num_load_insts 40791 # Number of load instructions -system.cpu2.num_store_insts 14165 # Number of store instructions -system.cpu2.num_idle_cycles 67997.871331 # Number of idle cycles -system.cpu2.num_busy_cycles 453426.128669 # Number of busy cycles -system.cpu2.not_idle_fraction 0.869592 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.130408 # Percentage of idle cycles -system.cpu2.Branches 33115 # Number of branches fetched -system.cpu2.op_class::No_OpClass 23895 14.47% 14.47% # Class of executed instruction -system.cpu2.op_class::IntAlu 74335 45.00% 59.47% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::MemRead 52792 31.96% 91.42% # Class of executed instruction -system.cpu2.op_class::MemWrite 14165 8.58% 100.00% # Class of executed instruction +system.cpu2.num_mem_refs 55033 # number of memory refs +system.cpu2.num_load_insts 40858 # Number of load instructions +system.cpu2.num_store_insts 14175 # Number of store instructions +system.cpu2.num_idle_cycles 74150.001720 # Number of idle cycles +system.cpu2.num_busy_cycles 455530.998280 # Number of busy cycles +system.cpu2.not_idle_fraction 0.860010 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.139990 # Percentage of idle cycles +system.cpu2.Branches 33177 # Number of branches fetched +system.cpu2.op_class::No_OpClass 23956 14.48% 14.48% # Class of executed instruction +system.cpu2.op_class::IntAlu 74457 45.00% 59.48% # Class of executed instruction +system.cpu2.op_class::IntMult 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::IntDiv 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatAdd 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatCmp 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatCvt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatMult 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatDiv 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatSqrt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdAdd 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdAddAcc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdAlu 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdCmp 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdCvt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdMisc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdMult 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdMultAcc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdShift 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdSqrt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatMult 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::MemRead 52859 31.95% 91.43% # Class of executed instruction +system.cpu2.op_class::MemWrite 14175 8.57% 100.00% # Class of executed instruction system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 165187 # Class of executed instruction +system.cpu2.op_class::total 165447 # Class of executed instruction system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 27.775093 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 30556 # Total number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 27.486829 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 30625 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1053.655172 # Average number of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1056.034483 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.775093 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054248 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.054248 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.486829 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053685 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.053685 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 220041 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 220041 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 40622 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 40622 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 13986 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 13986 # number of WriteReq hits +system.cpu2.dcache.tags.tag_accesses 220352 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 220352 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 40687 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 40687 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 13994 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 13994 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 54608 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 54608 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 54608 # number of overall hits -system.cpu2.dcache.overall_hits::total 54608 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 161 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 161 # number of ReadReq misses +system.cpu2.dcache.demand_hits::cpu2.data 54681 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 54681 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 54681 # number of overall hits +system.cpu2.dcache.overall_hits::total 54681 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 163 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 163 # number of ReadReq misses system.cpu2.dcache.WriteReq_misses::cpu2.data 108 # number of WriteReq misses system.cpu2.dcache.WriteReq_misses::total 108 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses -system.cpu2.dcache.overall_misses::total 269 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2814500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 2814500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2046000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2046000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 249500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 249500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 4860500 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 4860500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 4860500 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 4860500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 40783 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 40783 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 14094 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 14094 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 54877 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 54877 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 54877 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 54877 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003948 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003948 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007663 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.007663 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004902 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004902 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004902 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004902 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17481.366460 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 17481.366460 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18944.444444 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 18944.444444 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4455.357143 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 4455.357143 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 18068.773234 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 18068.773234 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 18068.773234 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 18068.773234 # average overall miss latency +system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 271 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 271 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 271 # number of overall misses +system.cpu2.dcache.overall_misses::total 271 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3093500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 3093500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2328000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2328000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 260500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 260500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 5421500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 5421500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 5421500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 5421500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 40850 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 40850 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 14102 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 14102 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 54952 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 54952 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 54952 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 54952 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003990 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003990 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007658 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.007658 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.816901 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004932 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004932 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004932 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004932 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 18978.527607 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 18978.527607 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21555.555556 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 21555.555556 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4491.379310 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 4491.379310 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 20005.535055 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 20005.535055 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 20005.535055 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 20005.535055 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -737,99 +741,99 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 163 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 269 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 269 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2653500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2653500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1938000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1938000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 193500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 193500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4591500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 4591500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4591500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 4591500 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003948 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003948 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007663 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007663 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004902 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004902 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004902 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004902 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16481.366460 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16481.366460 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17944.444444 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17944.444444 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3455.357143 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3455.357143 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 17068.773234 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 17068.773234 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 17068.773234 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 17068.773234 # average overall mshr miss latency +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2930500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2930500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2220000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2220000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 202500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 202500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 5150500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 5150500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 5150500 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 5150500 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003990 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003990 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007658 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007658 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004932 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004932 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004932 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004932 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17978.527607 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 17978.527607 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 20555.555556 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 20555.555556 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3491.379310 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3491.379310 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 19005.535055 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19005.535055 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19005.535055 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19005.535055 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 70.166597 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 164822 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 69.407713 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 165082 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 450.333333 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 451.043716 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 70.166597 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.137044 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.137044 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.407713 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135562 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.135562 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 165554 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 165554 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 164822 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 164822 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 164822 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 164822 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 164822 # number of overall hits -system.cpu2.icache.overall_hits::total 164822 # number of overall hits +system.cpu2.icache.tags.tag_accesses 165814 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 165814 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 165082 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 165082 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 165082 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 165082 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 165082 # number of overall hits +system.cpu2.icache.overall_hits::total 165082 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7626500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 7626500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 7626500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 7626500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 7626500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 7626500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 165188 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 165188 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 165188 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 165188 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 165188 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 165188 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002216 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002216 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002216 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002216 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002216 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002216 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20837.431694 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 20837.431694 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20837.431694 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 20837.431694 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20837.431694 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 20837.431694 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8101000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 8101000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 8101000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 8101000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 8101000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 8101000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 165448 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 165448 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 165448 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 165448 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 165448 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 165448 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002212 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002212 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002212 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002212 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002212 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002212 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22133.879781 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 22133.879781 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22133.879781 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 22133.879781 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22133.879781 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 22133.879781 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -838,164 +842,166 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.writebacks::writebacks 280 # number of writebacks +system.cpu2.icache.writebacks::total 280 # number of writebacks system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7260500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 7260500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7260500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 7260500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7260500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 7260500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002216 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002216 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002216 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19837.431694 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 19837.431694 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 19837.431694 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7735000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 7735000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7735000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 7735000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7735000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 7735000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002212 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002212 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002212 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21133.879781 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 21133.879781 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 21133.879781 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 521424 # number of cpu cycles simulated +system.cpu3.numCycles 529680 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 169208 # Number of instructions committed -system.cpu3.committedOps 169208 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 110441 # Number of integer alu accesses +system.cpu3.committedInsts 169884 # Number of instructions committed +system.cpu3.committedOps 169884 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 110793 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 33391 # number of instructions that are conditional controls -system.cpu3.num_int_insts 110441 # number of integer instructions +system.cpu3.num_conditional_control_insts 33553 # number of instructions that are conditional controls +system.cpu3.num_int_insts 110793 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 270379 # number of times the integer registers were read -system.cpu3.num_int_register_writes 102142 # number of times the integer registers were written +system.cpu3.num_int_register_reads 271193 # number of times the integer registers were read +system.cpu3.num_int_register_writes 102450 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 53219 # number of memory refs -system.cpu3.num_load_insts 40883 # Number of load instructions -system.cpu3.num_store_insts 12336 # Number of store instructions -system.cpu3.num_idle_cycles 68253.870839 # Number of idle cycles -system.cpu3.num_busy_cycles 453170.129161 # Number of busy cycles -system.cpu3.not_idle_fraction 0.869101 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.130899 # Percentage of idle cycles -system.cpu3.Branches 35047 # Number of branches fetched -system.cpu3.op_class::No_OpClass 25824 15.26% 15.26% # Class of executed instruction -system.cpu3.op_class::IntAlu 74433 43.98% 59.24% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::MemRead 56647 33.47% 92.71% # Class of executed instruction -system.cpu3.op_class::MemWrite 12336 7.29% 100.00% # Class of executed instruction +system.cpu3.num_mem_refs 53409 # number of memory refs +system.cpu3.num_load_insts 41060 # Number of load instructions +system.cpu3.num_store_insts 12349 # Number of store instructions +system.cpu3.num_idle_cycles 74420.861217 # Number of idle cycles +system.cpu3.num_busy_cycles 455259.138783 # Number of busy cycles +system.cpu3.not_idle_fraction 0.859498 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.140502 # Percentage of idle cycles +system.cpu3.Branches 35208 # Number of branches fetched +system.cpu3.op_class::No_OpClass 25987 15.29% 15.29% # Class of executed instruction +system.cpu3.op_class::IntAlu 74660 43.94% 59.23% # Class of executed instruction +system.cpu3.op_class::IntMult 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::IntDiv 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::FloatAdd 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::FloatCmp 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::FloatCvt 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::FloatMult 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::FloatDiv 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::FloatSqrt 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdAdd 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdAddAcc 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdAlu 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdCmp 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdCvt 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdMisc 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdMult 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdMultAcc 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdShift 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdSqrt 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdFloatMult 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::MemRead 56920 33.50% 92.73% # Class of executed instruction +system.cpu3.op_class::MemWrite 12349 7.27% 100.00% # Class of executed instruction system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 169240 # Class of executed instruction +system.cpu3.op_class::total 169916 # Class of executed instruction system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 25.991280 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 27009 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 900.300000 # Average number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 25.679518 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 26969 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 929.965517 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.991280 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050764 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.050764 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.679518 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050155 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.050155 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 213096 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 213096 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 40712 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 40712 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 12155 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 12155 # number of WriteReq hits +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 213856 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 213856 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 40892 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 40892 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 12169 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 12169 # number of WriteReq hits system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 52867 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 52867 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 52867 # number of overall hits -system.cpu3.dcache.overall_hits::total 52867 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 163 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 163 # number of ReadReq misses +system.cpu3.dcache.demand_hits::cpu3.data 53061 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 53061 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 53061 # number of overall hits +system.cpu3.dcache.overall_hits::total 53061 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 161 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 161 # number of ReadReq misses system.cpu3.dcache.WriteReq_misses::cpu3.data 107 # number of WriteReq misses system.cpu3.dcache.WriteReq_misses::total 107 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 270 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 270 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 270 # number of overall misses -system.cpu3.dcache.overall_misses::total 270 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2676500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 2676500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1989500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 1989500 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 259000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 259000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 4666000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 4666000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 4666000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 4666000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 40875 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 40875 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 12262 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 12262 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 53137 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 53137 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 53137 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 53137 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003988 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003988 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008726 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.008726 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805556 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.805556 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005081 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.005081 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005081 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.005081 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16420.245399 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 16420.245399 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18593.457944 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 18593.457944 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4465.517241 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 4465.517241 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17281.481481 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 17281.481481 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17281.481481 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 17281.481481 # average overall miss latency +system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses +system.cpu3.dcache.overall_misses::total 268 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2856500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 2856500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2210000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2210000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 258500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 258500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 5066500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 5066500 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 5066500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 5066500 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41053 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41053 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 12276 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 12276 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 53329 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 53329 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 53329 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 53329 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003922 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003922 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008716 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.008716 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005025 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.005025 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005025 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005025 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17742.236025 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 17742.236025 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20654.205607 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 20654.205607 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4535.087719 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 4535.087719 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18904.850746 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 18904.850746 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18904.850746 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 18904.850746 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1004,99 +1010,99 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 161 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 270 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 270 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2513500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2513500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1882500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1882500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 201000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 201000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4396000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 4396000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4396000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 4396000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003988 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003988 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008726 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008726 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805556 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805556 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005081 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.005081 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005081 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.005081 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15420.245399 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15420.245399 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17593.457944 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17593.457944 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3465.517241 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3465.517241 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16281.481481 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16281.481481 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16281.481481 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16281.481481 # average overall mshr miss latency +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2695500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2695500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2103000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2103000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 201500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 201500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4798500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 4798500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4798500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 4798500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003922 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003922 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008716 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008716 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005025 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.005025 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005025 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.005025 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16742.236025 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16742.236025 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19654.205607 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19654.205607 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3535.087719 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3535.087719 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 17904.850746 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 17904.850746 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 17904.850746 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 17904.850746 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 281 # number of replacements -system.cpu3.icache.tags.tagsinuse 65.768661 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 168874 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 64.991831 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 169550 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 460.147139 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 461.989101 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.768661 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128454 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.128454 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.991831 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126937 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.126937 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 169608 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 169608 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 168874 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 168874 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 168874 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 168874 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 168874 # number of overall hits -system.cpu3.icache.overall_hits::total 168874 # number of overall hits +system.cpu3.icache.tags.tag_accesses 170284 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 170284 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 169550 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 169550 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 169550 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 169550 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 169550 # number of overall hits +system.cpu3.icache.overall_hits::total 169550 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses system.cpu3.icache.overall_misses::total 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5371500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5371500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5371500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5371500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5371500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5371500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 169241 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 169241 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 169241 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 169241 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 169241 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 169241 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 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system.l2c.overall_hits::cpu0.inst 182 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits system.l2c.overall_hits::cpu1.inst 352 # number of overall hits system.l2c.overall_hits::cpu1.data 9 # number of overall hits -system.l2c.overall_hits::cpu2.inst 302 # number of overall hits +system.l2c.overall_hits::cpu2.inst 301 # number of overall hits system.l2c.overall_hits::cpu2.data 3 # number of overall hits -system.l2c.overall_hits::cpu3.inst 358 # number of overall hits +system.l2c.overall_hits::cpu3.inst 357 # number of overall hits system.l2c.overall_hits::cpu3.data 9 # number of overall hits -system.l2c.overall_hits::total 1220 # number of overall hits +system.l2c.overall_hits::total 1218 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses 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-system.l2c.ReadCleanReq_miss_rate::total 0.237548 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.177596 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.027248 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.238825 # miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.727273 # miss rate for ReadSharedReq accesses @@ -1328,53 +1340,53 @@ system.l2c.demand_miss_rate::cpu0.inst 0.610278 # mi system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.640000 # miss rate for demand accesses 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0 # number of cycles access was blocked @@ -1383,25 +1395,28 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 10 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 8 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2.data 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 7 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 7 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 6 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::total 20 # number of ReadCleanReq MSHR hits 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+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49522.807018 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 49512.121212 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 50214.285714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50100 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 49517.241379 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 49652.173913 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 49750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 49966.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 49561.188811 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49522.807018 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 49512.121212 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 50214.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50100 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49517.241379 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 49652.173913 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49966.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 49561.188811 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 430 # Transaction distribution system.membus.trans_dist::UpgradeReq 271 # Transaction distribution @@ -1563,62 +1578,63 @@ system.membus.pkt_count::total 1557 # Pa system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 261 # Total snoops (count) -system.membus.snoop_fanout::samples 913 # Request fanout histogram +system.membus.snoop_fanout::samples 915 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 913 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 915 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 913 # Request fanout histogram -system.membus.reqLayer0.occupancy 664148 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 915 # Request fanout histogram +system.membus.reqLayer0.occupancy 677632 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2946008 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2936000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 3982 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1114 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 3980 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1113 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadResp 2222 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 496 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2221 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 495 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 273 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 273 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 428 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 428 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 656 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 655 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 848 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 579 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 853 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 369 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5311 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 852 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5309 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39040 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30912 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 30912 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31040 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1034 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3982 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.291562 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.219091 # Request fanout histogram +system.toL2Bus.pkt_size::total 147712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1032 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2922 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.269678 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.154527 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1499 37.64% 37.64% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 871 21.87% 59.52% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 564 14.16% 73.68% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 1048 26.32% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1002 34.29% 34.29% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 787 26.93% 61.23% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 476 16.29% 77.52% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 657 22.48% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram @@ -1627,24 +1643,24 @@ system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3982 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1996990 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2922 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3050992 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 700999 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 501990 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 495500 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 549000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 552489 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 431977 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 432972 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 553988 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 552491 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 427478 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 434474 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 554487 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 553492 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 432477 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 427974 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt index a10945c4f..099024f7a 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.010063 # Number of seconds simulated -sim_ticks 10063247 # Number of ticks simulated -final_tick 10063247 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.010022 # Number of seconds simulated +sim_ticks 10021833 # Number of ticks simulated +final_tick 10021833 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 101901 # Simulator tick rate (ticks/s) -host_mem_usage 533376 # Number of bytes of host memory used -host_seconds 98.76 # Real time elapsed on the host +host_tick_rate 186642 # Simulator tick rate (ticks/s) +host_mem_usage 462200 # Number of bytes of host memory used +host_seconds 53.70 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39727680 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 39727680 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14278528 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 14278528 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 620745 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 620745 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 223102 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 223102 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 3947799353 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 3947799353 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1418878817 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1418878817 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 5366678171 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 5366678171 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 620746 # Number of read requests accepted -system.mem_ctrls.writeReqs 223102 # Number of write requests accepted -system.mem_ctrls.readBursts 620746 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 223102 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 39328832 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 398912 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 14151168 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 39727744 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 14278528 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 6233 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 1970 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39622272 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 39622272 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14218944 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 14218944 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 619098 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 619098 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 222171 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 222171 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 3953595315 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 3953595315 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1418796741 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1418796741 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 5372392056 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 5372392056 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 619101 # Number of read requests accepted +system.mem_ctrls.writeReqs 222171 # Number of write requests accepted +system.mem_ctrls.readBursts 619101 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 222171 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 39234688 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 387776 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 14090496 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 39622464 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 14218944 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 6059 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 1977 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 76987 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 76875 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 76834 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 76304 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 76781 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 76790 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 76930 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 77012 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 76712 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 76619 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 76862 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 76984 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 76352 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 76556 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 76570 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 76387 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts @@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 27724 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 27471 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 27707 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 27397 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 27728 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 27814 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 27530 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 27741 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 27545 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 27285 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 27557 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 27826 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 27514 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 27565 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 27642 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 27230 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts @@ -69,29 +69,29 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 10063228 # Total gap between requests +system.mem_ctrls.totGap 10021798 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 620746 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 619101 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 223102 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 222171 # Write request sizes (log2) system.mem_ctrls.rdQLenPdf::0 32087 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 65790 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 105631 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 136536 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 129546 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 85237 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 43922 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 15764 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 65566 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 105076 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 135661 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 128982 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 85695 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 43990 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 15985 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see @@ -131,36 +131,36 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 15 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 61 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 1639 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 5258 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 9594 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 12657 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 14464 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 15595 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 16062 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 16123 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 15972 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 15753 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 15290 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 14922 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 14865 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 14792 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 15022 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 15406 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 4416 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 1895 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 813 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 323 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 122 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 10 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 4 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 16 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 68 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 1655 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 5385 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 9439 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 12632 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 14319 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 15430 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 15929 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 16152 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 15943 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 15642 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 15180 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 14917 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 14784 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 14795 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 14883 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 15369 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 4463 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 1876 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 780 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 324 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 113 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 50 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 19 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 10 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -180,169 +180,170 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 334200 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 160.021257 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 125.929223 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 125.831339 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 136007 40.70% 40.70% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 126202 37.76% 78.46% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 44342 13.27% 91.73% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 17534 5.25% 96.97% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 6577 1.97% 98.94% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 2267 0.68% 99.62% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 844 0.25% 99.87% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 285 0.09% 99.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 142 0.04% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 334200 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 13810 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 44.496959 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 43.460780 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 9.596020 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::8-11 2 0.01% 0.01% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-19 16 0.12% 0.13% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-23 59 0.43% 0.56% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::24-27 259 1.88% 2.43% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::28-31 691 5.00% 7.44% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::32-35 1388 10.05% 17.49% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-39 1899 13.75% 31.24% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::40-43 2398 17.36% 48.60% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::44-47 2268 16.42% 65.03% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::48-51 1790 12.96% 77.99% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::52-55 1284 9.30% 87.28% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::56-59 833 6.03% 93.32% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::60-63 471 3.41% 96.73% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::64-67 226 1.64% 98.36% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::68-71 131 0.95% 99.31% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::72-75 52 0.38% 99.69% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::76-79 27 0.20% 99.88% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-83 10 0.07% 99.96% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::84-87 2 0.01% 99.97% # Reads before turning the bus around for writes +system.mem_ctrls.bytesPerActivate::samples 333023 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 160.121361 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 125.956156 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 126.041045 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 135519 40.69% 40.69% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 125870 37.80% 78.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 44087 13.24% 91.73% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 17315 5.20% 96.93% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 6630 1.99% 98.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 2388 0.72% 99.64% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 800 0.24% 99.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 268 0.08% 99.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 146 0.04% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 333023 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 13749 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 44.585133 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 43.567355 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 9.556105 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-15 1 0.01% 0.01% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-19 13 0.09% 0.10% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-23 50 0.36% 0.47% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::24-27 236 1.72% 2.18% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::28-31 654 4.76% 6.94% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::32-35 1404 10.21% 17.15% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-39 1971 14.34% 31.49% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::40-43 2304 16.76% 48.24% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::44-47 2255 16.40% 64.64% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::48-51 1821 13.24% 77.89% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::52-55 1248 9.08% 86.97% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::56-59 870 6.33% 93.29% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::60-63 460 3.35% 96.64% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::64-67 257 1.87% 98.51% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::68-71 103 0.75% 99.26% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::72-75 53 0.39% 99.64% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::76-79 28 0.20% 99.85% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::80-83 12 0.09% 99.93% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::84-87 5 0.04% 99.97% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::88-91 1 0.01% 99.98% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::92-95 1 0.01% 99.99% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::96-99 1 0.01% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::100-103 1 0.01% 99.99% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::116-119 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 13810 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 13810 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.011007 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.010210 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.170265 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 13731 99.43% 99.43% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 38 0.28% 99.70% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 22 0.16% 99.86% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 11 0.08% 99.94% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 5 0.04% 99.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 1 0.01% 99.99% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 2 0.01% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 13810 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 29144143 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 40819890 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3072565 # Total ticks spent in databus transfers +system.mem_ctrls.rdPerTurnAround::total 13749 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 13749 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.013092 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.012104 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.190256 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 13662 99.37% 99.37% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 31 0.23% 99.59% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 36 0.26% 99.85% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 11 0.08% 99.93% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 5 0.04% 99.97% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 1 0.01% 99.98% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 2 0.01% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 1 0.01% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 13749 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 29074956 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 40722754 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3065210 # Total ticks spent in databus transfers system.mem_ctrls.avgQLat 47.43 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst system.mem_ctrls.avgMemAccLat 66.43 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 3908.17 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 1406.22 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 3947.81 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1418.88 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgRdBW 3914.92 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1405.98 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 3953.61 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1418.80 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 41.52 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 30.53 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 10.99 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 5.49 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 26.50 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 286541 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 214878 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 46.63 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 97.17 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 11.93 # Average gap between requests -system.mem_ctrls.pageHitRate 60.00 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 2525743080 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 1403190600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 7666351680 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 2291493888 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 657059520 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 6856125984 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 21726000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 21421690752 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 2129.438017 # Core power per rank (mW) +system.mem_ctrls.busUtil 41.57 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 30.59 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 10.98 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 5.50 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 26.51 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 286090 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 214085 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 46.67 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 97.23 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 11.91 # Average gap between requests +system.mem_ctrls.pageHitRate 60.03 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 2517434640 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 1398574800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7649928000 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2282494464 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 654516720 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 6829590204 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 21655800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 21354194628 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 2130.971273 # Core power per rank (mW) system.mem_ctrls_0.memoryStateTime::IDLE 18 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 335920 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 334620 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 9723862 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 9686250 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 657059520 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 217397088 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 5845155600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 6719612208 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 667.969568 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 9723852 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 335920 # Time in different power states +system.mem_ctrls_1.refreshEnergy 654516720 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 216555768 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 5822535600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 6693608088 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.969562 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 9686222 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 334620 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 1 # Clock period in ticks -system.cpu0.num_reads 100000 # number of read accesses completed -system.cpu0.num_writes 55281 # number of write accesses completed -system.cpu1.num_reads 99949 # number of read accesses completed -system.cpu1.num_writes 55072 # number of write accesses completed -system.cpu2.num_reads 99624 # number of read accesses completed -system.cpu2.num_writes 55443 # number of write accesses completed -system.cpu3.num_reads 99109 # number of read accesses completed -system.cpu3.num_writes 54950 # number of write accesses completed -system.cpu4.num_reads 99489 # number of read accesses completed -system.cpu4.num_writes 55162 # number of write accesses completed -system.cpu5.num_reads 99504 # number of read accesses completed -system.cpu5.num_writes 55000 # number of write accesses completed -system.cpu6.num_reads 99322 # number of read accesses completed -system.cpu6.num_writes 55464 # number of write accesses completed -system.cpu7.num_reads 99224 # number of read accesses completed -system.cpu7.num_writes 55901 # number of write accesses completed +system.cpu0.num_reads 99423 # number of read accesses completed +system.cpu0.num_writes 55170 # number of write accesses completed +system.cpu1.num_reads 98761 # number of read accesses completed +system.cpu1.num_writes 54523 # number of write accesses completed +system.cpu2.num_reads 100000 # number of read accesses completed +system.cpu2.num_writes 55115 # number of write accesses completed +system.cpu3.num_reads 99531 # number of read accesses completed +system.cpu3.num_writes 55151 # number of write accesses completed +system.cpu4.num_reads 99248 # number of read accesses completed +system.cpu4.num_writes 55036 # number of write accesses completed +system.cpu5.num_reads 99097 # number of read accesses completed +system.cpu5.num_writes 55621 # number of write accesses completed +system.cpu6.num_reads 99456 # number of read accesses completed +system.cpu6.num_writes 55200 # number of write accesses completed +system.cpu7.num_reads 99560 # number of read accesses completed +system.cpu7.num_writes 55285 # number of write accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 32 # delay histogram for all message system.ruby.delayHist::max_bucket 319 # delay histogram for all message -system.ruby.delayHist::samples 4996019 # delay histogram for all message -system.ruby.delayHist::mean 6.440399 # delay histogram for all message -system.ruby.delayHist::stdev 17.465456 # delay histogram for all message -system.ruby.delayHist | 4687892 93.83% 93.83% | 148183 2.97% 96.80% | 120739 2.42% 99.22% | 34268 0.69% 99.90% | 4051 0.08% 99.98% | 661 0.01% 100.00% | 184 0.00% 100.00% | 36 0.00% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 4996019 # delay histogram for all message +system.ruby.delayHist::samples 4985028 # delay histogram for all message +system.ruby.delayHist::mean 6.537266 # delay histogram for all message +system.ruby.delayHist::stdev 17.581596 # delay histogram for all message +system.ruby.delayHist | 4675734 93.80% 93.80% | 147874 2.97% 96.76% | 121251 2.43% 99.19% | 34910 0.70% 99.89% | 4283 0.09% 99.98% | 711 0.01% 99.99% | 211 0.00% 100.00% | 36 0.00% 100.00% | 16 0.00% 100.00% | 2 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 4985028 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 626530 -system.ruby.outstanding_req_hist::mean 15.998463 -system.ruby.outstanding_req_hist::gmean 15.997199 -system.ruby.outstanding_req_hist::stdev 0.125840 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 19 0.00% 0.02% | 626407 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 626530 +system.ruby.outstanding_req_hist::samples 624868 +system.ruby.outstanding_req_hist::mean 15.998456 +system.ruby.outstanding_req_hist::gmean 15.997188 +system.ruby.outstanding_req_hist::stdev 0.126020 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 21 0.00% 0.02% | 624743 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 624868 system.ruby.latency_hist::bucket_size 1024 system.ruby.latency_hist::max_bucket 10239 -system.ruby.latency_hist::samples 626402 -system.ruby.latency_hist::mean 2056.065891 -system.ruby.latency_hist::gmean 1570.991925 -system.ruby.latency_hist::stdev 1229.216136 -system.ruby.latency_hist | 170336 27.19% 27.19% | 149314 23.84% 51.03% | 146612 23.41% 74.43% | 133427 21.30% 95.74% | 26424 4.22% 99.95% | 289 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 626402 +system.ruby.latency_hist::samples 624741 +system.ruby.latency_hist::mean 2053.034201 +system.ruby.latency_hist::gmean 1585.285080 +system.ruby.latency_hist::stdev 1206.859039 +system.ruby.latency_hist | 164671 26.36% 26.36% | 154480 24.73% 51.09% | 150906 24.15% 75.24% | 129850 20.78% 96.02% | 24588 3.94% 99.96% | 246 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 624741 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 6 +system.ruby.hit_latency_hist::samples 10 system.ruby.hit_latency_hist::mean 1 system.ruby.hit_latency_hist::gmean 1 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 6 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 6 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 10 system.ruby.miss_latency_hist::bucket_size 1024 system.ruby.miss_latency_hist::max_bucket 10239 -system.ruby.miss_latency_hist::samples 626396 -system.ruby.miss_latency_hist::mean 2056.085575 -system.ruby.miss_latency_hist::gmean 1571.102673 -system.ruby.miss_latency_hist::stdev 1229.205568 -system.ruby.miss_latency_hist | 170330 27.19% 27.19% | 149314 23.84% 51.03% | 146612 23.41% 74.43% | 133427 21.30% 95.74% | 26424 4.22% 99.95% | 289 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 626396 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 78404 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78405 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 624731 +system.ruby.miss_latency_hist::mean 2053.067048 +system.ruby.miss_latency_hist::gmean 1585.472070 +system.ruby.miss_latency_hist::stdev 1206.840773 +system.ruby.miss_latency_hist | 164661 26.36% 26.36% | 154480 24.73% 51.08% | 150906 24.16% 75.24% | 129850 20.78% 96.02% | 24588 3.94% 99.96% | 246 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 624731 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 78237 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78237 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -355,9 +356,9 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl1.L1Dcache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 78190 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78190 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 3 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 77673 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 77676 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -371,8 +372,8 @@ system.ruby.l1_cntrl1.prefetcher.partial_hits 0 system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed system.ruby.l1_cntrl2.L1Dcache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 78457 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78458 # Number of cache demand accesses +system.ruby.l1_cntrl2.L1Dcache.demand_misses 78377 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78378 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -385,9 +386,9 @@ system.ruby.l1_cntrl2.prefetcher.hits 0 # nu system.ruby.l1_cntrl2.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl2.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl2.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl3.L1Dcache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 78022 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78022 # Number of cache demand accesses +system.ruby.l1_cntrl3.L1Dcache.demand_hits 1 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 78097 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78098 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -400,9 +401,9 @@ system.ruby.l1_cntrl3.prefetcher.hits 0 # nu system.ruby.l1_cntrl3.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl3.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl3.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl4.L1Dcache.demand_hits 2 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Dcache.demand_misses 78555 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78557 # Number of cache demand accesses +system.ruby.l1_cntrl4.L1Dcache.demand_hits 1 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Dcache.demand_misses 78248 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78249 # Number of cache demand accesses system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -415,9 +416,9 @@ system.ruby.l1_cntrl4.prefetcher.hits 0 # nu system.ruby.l1_cntrl4.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl4.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl4.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl5.L1Dcache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Dcache.demand_misses 78114 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78115 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Dcache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Dcache.demand_misses 77823 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Dcache.demand_accesses 77823 # Number of cache demand accesses system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -430,9 +431,9 @@ system.ruby.l1_cntrl5.prefetcher.hits 0 # nu system.ruby.l1_cntrl5.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl5.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl5.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl6.L1Dcache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Dcache.demand_misses 78297 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78297 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Dcache.demand_hits 2 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Dcache.demand_misses 78233 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78235 # Number of cache demand accesses system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -445,9 +446,9 @@ system.ruby.l1_cntrl6.prefetcher.hits 0 # nu system.ruby.l1_cntrl6.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl6.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl6.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl7.L1Dcache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Dcache.demand_misses 78384 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78385 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Dcache.demand_hits 2 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Dcache.demand_misses 78071 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78073 # Number of cache demand accesses system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -460,759 +461,762 @@ system.ruby.l1_cntrl7.prefetcher.hits 0 # nu system.ruby.l1_cntrl7.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl7.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl7.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l2_cntrl0.L2cache.demand_hits 31 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 626370 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 626401 # Number of cache demand accesses +system.ruby.l2_cntrl0.L2cache.demand_hits 35 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 624702 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 624737 # Number of cache demand accesses system.ruby.l2_cntrl0.fully_busy_cycles 3 # cycles for which number of transistions == max transitions system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers00.percent_links_utilized 4.070923 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+system.ruby.network.routers10.throttle2.msg_bytes.Response_Control::1 330040 +system.ruby.network.routers10.throttle3.link_utilization 4.092196 +system.ruby.network.routers10.throttle3.msg_count.Request_Control::2 76565 +system.ruby.network.routers10.throttle3.msg_count.Response_Data::1 78093 +system.ruby.network.routers10.throttle3.msg_count.Response_Control::1 40824 +system.ruby.network.routers10.throttle3.msg_bytes.Request_Control::2 612520 +system.ruby.network.routers10.throttle3.msg_bytes.Response_Data::1 5622696 +system.ruby.network.routers10.throttle3.msg_bytes.Response_Control::1 326592 +system.ruby.network.routers10.throttle4.link_utilization 4.100772 +system.ruby.network.routers10.throttle4.msg_count.Request_Control::2 76737 +system.ruby.network.routers10.throttle4.msg_count.Response_Data::1 78244 +system.ruby.network.routers10.throttle4.msg_count.Response_Control::1 41012 +system.ruby.network.routers10.throttle4.msg_bytes.Request_Control::2 613896 +system.ruby.network.routers10.throttle4.msg_bytes.Response_Data::1 5633568 +system.ruby.network.routers10.throttle4.msg_bytes.Response_Control::1 328096 +system.ruby.network.routers10.throttle5.link_utilization 4.077592 +system.ruby.network.routers10.throttle5.msg_count.Request_Control::2 76343 +system.ruby.network.routers10.throttle5.msg_count.Response_Data::1 77820 +system.ruby.network.routers10.throttle5.msg_count.Response_Control::1 40576 +system.ruby.network.routers10.throttle5.msg_bytes.Request_Control::2 610744 +system.ruby.network.routers10.throttle5.msg_bytes.Response_Data::1 5603040 +system.ruby.network.routers10.throttle5.msg_bytes.Response_Control::1 324608 +system.ruby.network.routers10.throttle6.link_utilization 4.100642 +system.ruby.network.routers10.throttle6.msg_count.Request_Control::2 76715 +system.ruby.network.routers10.throttle6.msg_count.Response_Data::1 78229 +system.ruby.network.routers10.throttle6.msg_count.Response_Control::1 41143 +system.ruby.network.routers10.throttle6.msg_bytes.Request_Control::2 613720 +system.ruby.network.routers10.throttle6.msg_bytes.Response_Data::1 5632488 +system.ruby.network.routers10.throttle6.msg_bytes.Response_Control::1 329144 +system.ruby.network.routers10.throttle7.link_utilization 4.091138 +system.ruby.network.routers10.throttle7.msg_count.Request_Control::2 76560 +system.ruby.network.routers10.throttle7.msg_count.Response_Data::1 78068 +system.ruby.network.routers10.throttle7.msg_count.Response_Control::1 40842 +system.ruby.network.routers10.throttle7.msg_bytes.Request_Control::2 612480 +system.ruby.network.routers10.throttle7.msg_bytes.Response_Data::1 5620896 +system.ruby.network.routers10.throttle7.msg_bytes.Response_Control::1 326736 +system.ruby.network.routers10.throttle8.link_utilization 63.142461 +system.ruby.network.routers10.throttle8.msg_count.Control::0 624759 +system.ruby.network.routers10.throttle8.msg_count.Response_Data::1 620345 +system.ruby.network.routers10.throttle8.msg_count.Response_Control::1 812188 +system.ruby.network.routers10.throttle8.msg_count.Response_Control::2 619667 +system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::0 117713 +system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::1 416384 +system.ruby.network.routers10.throttle8.msg_count.Writeback_Control::0 209480 +system.ruby.network.routers10.throttle8.msg_bytes.Control::0 4998072 +system.ruby.network.routers10.throttle8.msg_bytes.Response_Data::1 44664840 +system.ruby.network.routers10.throttle8.msg_bytes.Response_Control::1 6497504 +system.ruby.network.routers10.throttle8.msg_bytes.Response_Control::2 4957336 +system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::0 8475336 +system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::1 29979648 +system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Control::0 1675840 +system.ruby.network.routers10.throttle9.link_utilization 15.044962 +system.ruby.network.routers10.throttle9.msg_count.Control::0 619101 +system.ruby.network.routers10.throttle9.msg_count.Response_Data::1 222171 +system.ruby.network.routers10.throttle9.msg_count.Response_Control::1 396922 +system.ruby.network.routers10.throttle9.msg_bytes.Control::0 4952808 +system.ruby.network.routers10.throttle9.msg_bytes.Response_Data::1 15996312 +system.ruby.network.routers10.throttle9.msg_bytes.Response_Control::1 3175376 system.ruby.delayVCHist.vnet_0::bucket_size 32 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 319 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 1575058 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 16.499518 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 28.066605 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 1267495 80.47% 80.47% | 147619 9.37% 89.85% | 120739 7.67% 97.51% | 34268 2.18% 99.69% | 4051 0.26% 99.94% | 661 0.04% 99.99% | 184 0.01% 100.00% | 36 0.00% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 1575058 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 1571585 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 16.631308 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 28.252150 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 1262919 80.36% 80.36% | 147246 9.37% 89.73% | 121251 7.72% 97.44% | 34910 2.22% 99.67% | 4283 0.27% 99.94% | 711 0.05% 99.98% | 211 0.01% 100.00% | 36 0.00% 100.00% | 16 0.00% 100.00% | 2 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 1571585 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 8 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 79 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 2807147 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 2.202665 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 4.138703 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 2450377 87.29% 87.29% | 292281 10.41% 97.70% | 56101 2.00% 99.70% | 7824 0.28% 99.98% | 540 0.02% 100.00% | 23 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 2807147 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 2800862 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 2.301244 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 4.225794 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 2428288 86.70% 86.70% | 302747 10.81% 97.51% | 60957 2.18% 99.68% | 8242 0.29% 99.98% | 602 0.02% 100.00% | 25 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 2800862 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 613814 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.008885 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.133109 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 611089 99.56% 99.56% | 0 0.00% 99.56% | 2723 0.44% 100.00% | 0 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 613814 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 612581 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.008929 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.133339 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 609846 99.55% 99.55% | 0 0.00% 99.55% | 2735 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 612581 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 1024 system.ruby.LD.latency_hist::max_bucket 10239 -system.ruby.LD.latency_hist::samples 402652 -system.ruby.LD.latency_hist::mean 2058.156706 -system.ruby.LD.latency_hist::gmean 1573.125397 -system.ruby.LD.latency_hist::stdev 1229.056134 -system.ruby.LD.latency_hist | 109272 27.14% 27.14% | 96049 23.85% 50.99% | 93972 23.34% 74.33% | 86268 21.42% 95.76% | 16904 4.20% 99.95% | 187 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 402652 +system.ruby.LD.latency_hist::samples 401903 +system.ruby.LD.latency_hist::mean 2053.043401 +system.ruby.LD.latency_hist::gmean 1585.283402 +system.ruby.LD.latency_hist::stdev 1206.884955 +system.ruby.LD.latency_hist | 106001 26.37% 26.37% | 99372 24.73% 51.10% | 97044 24.15% 75.25% | 83497 20.78% 96.02% | 15842 3.94% 99.96% | 147 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 401903 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 4 +system.ruby.LD.hit_latency_hist::samples 7 system.ruby.LD.hit_latency_hist::mean 1 system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 4 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 7 system.ruby.LD.miss_latency_hist::bucket_size 1024 system.ruby.LD.miss_latency_hist::max_bucket 10239 -system.ruby.LD.miss_latency_hist::samples 402648 -system.ruby.LD.miss_latency_hist::mean 2058.177142 -system.ruby.LD.miss_latency_hist::gmean 1573.240435 -system.ruby.LD.miss_latency_hist::stdev 1229.045136 -system.ruby.LD.miss_latency_hist | 109268 27.14% 27.14% | 96049 23.85% 50.99% | 93972 23.34% 74.33% | 86268 21.43% 95.76% | 16904 4.20% 99.95% | 187 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 402648 +system.ruby.LD.miss_latency_hist::samples 401896 +system.ruby.LD.miss_latency_hist::mean 2053.079142 +system.ruby.LD.miss_latency_hist::gmean 1585.486872 +system.ruby.LD.miss_latency_hist::stdev 1206.865080 +system.ruby.LD.miss_latency_hist | 105994 26.37% 26.37% | 99372 24.73% 51.10% | 97044 24.15% 75.25% | 83497 20.78% 96.02% | 15842 3.94% 99.96% | 147 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 401896 system.ruby.ST.latency_hist::bucket_size 1024 system.ruby.ST.latency_hist::max_bucket 10239 -system.ruby.ST.latency_hist::samples 223750 -system.ruby.ST.latency_hist::mean 2052.303339 -system.ruby.ST.latency_hist::gmean 1567.159894 -system.ruby.ST.latency_hist::stdev 1229.497806 -system.ruby.ST.latency_hist | 61064 27.29% 27.29% | 53265 23.81% 51.10% | 52640 23.53% 74.62% | 47159 21.08% 95.70% | 9520 4.25% 99.95% | 102 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 223750 +system.ruby.ST.latency_hist::samples 222838 +system.ruby.ST.latency_hist::mean 2053.017609 +system.ruby.ST.latency_hist::gmean 1585.288106 +system.ruby.ST.latency_hist::stdev 1206.815003 +system.ruby.ST.latency_hist | 58670 26.33% 26.33% | 55108 24.73% 51.06% | 53862 24.17% 75.23% | 46353 20.80% 96.03% | 8746 3.92% 99.96% | 99 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 222838 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 2 +system.ruby.ST.hit_latency_hist::samples 3 system.ruby.ST.hit_latency_hist::mean 1 system.ruby.ST.hit_latency_hist::gmean 1 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 2 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 3 system.ruby.ST.miss_latency_hist::bucket_size 1024 system.ruby.ST.miss_latency_hist::max_bucket 10239 -system.ruby.ST.miss_latency_hist::samples 223748 -system.ruby.ST.miss_latency_hist::mean 2052.321674 -system.ruby.ST.miss_latency_hist::gmean 1567.262957 -system.ruby.ST.miss_latency_hist::stdev 1229.488005 -system.ruby.ST.miss_latency_hist | 61062 27.29% 27.29% | 53265 23.81% 51.10% | 52640 23.53% 74.62% | 47159 21.08% 95.70% | 9520 4.25% 99.95% | 102 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 223748 -system.ruby.Directory_Controller.Fetch 620746 0.00% 0.00% -system.ruby.Directory_Controller.Data 223102 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 620744 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 223102 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 397635 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 620746 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 223102 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 397635 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 620744 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 223102 0.00% 0.00% -system.ruby.L1Cache_Controller.Load | 50393 12.51% 12.51% | 50416 12.52% 25.03% | 50363 12.51% 37.54% | 50237 12.48% 50.02% | 50645 12.58% 62.59% | 50325 12.50% 75.09% | 50093 12.44% 87.53% | 50207 12.47% 100.00% -system.ruby.L1Cache_Controller.Load::total 402679 -system.ruby.L1Cache_Controller.Store | 28016 12.52% 12.52% | 27777 12.41% 24.93% | 28096 12.56% 37.49% | 27785 12.42% 49.91% | 27912 12.47% 62.38% | 27792 12.42% 74.80% | 28205 12.60% 87.41% | 28180 12.59% 100.00% -system.ruby.L1Cache_Controller.Store::total 223763 -system.ruby.L1Cache_Controller.Inv | 76429 12.51% 12.51% | 76212 12.48% 24.99% | 76536 12.53% 37.53% | 76087 12.46% 49.99% | 76620 12.55% 62.53% | 76246 12.48% 75.02% | 76271 12.49% 87.51% | 76303 12.49% 100.00% -system.ruby.L1Cache_Controller.Inv::total 610704 -system.ruby.L1Cache_Controller.L1_Replacement | 550317 12.45% 12.45% | 551277 12.47% 24.93% | 553788 12.53% 37.46% | 552456 12.50% 49.96% | 552412 12.50% 62.46% | 551088 12.47% 74.93% | 552554 12.50% 87.43% | 555396 12.57% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 4419288 -system.ruby.L1Cache_Controller.Fwd_GETX | 222 12.19% 12.19% | 243 13.34% 25.54% | 235 12.90% 38.44% | 235 12.90% 51.35% | 227 12.47% 63.81% | 224 12.30% 76.11% | 222 12.19% 88.30% | 213 11.70% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 1821 -system.ruby.L1Cache_Controller.Fwd_GETS | 169 13.11% 13.11% | 152 11.79% 24.90% | 145 11.25% 36.15% | 167 12.96% 49.11% | 162 12.57% 61.68% | 154 11.95% 73.62% | 186 14.43% 88.05% | 154 11.95% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 1289 -system.ruby.L1Cache_Controller.Data | 2 18.18% 18.18% | 1 9.09% 27.27% | 1 9.09% 36.36% | 1 9.09% 45.45% | 1 9.09% 54.55% | 1 9.09% 63.64% | 3 27.27% 90.91% | 1 9.09% 100.00% -system.ruby.L1Cache_Controller.Data::total 11 -system.ruby.L1Cache_Controller.Data_Exclusive | 49617 12.52% 12.52% | 49601 12.51% 25.03% | 49567 12.51% 37.54% | 49439 12.47% 50.01% | 49824 12.57% 62.58% | 49575 12.51% 75.09% | 49312 12.44% 87.53% | 49406 12.47% 100.00% -system.ruby.L1Cache_Controller.Data_Exclusive::total 396341 -system.ruby.L1Cache_Controller.DataS_fromL1 | 158 12.26% 12.26% | 179 13.89% 26.14% | 152 11.79% 37.94% | 164 12.72% 50.66% | 171 13.27% 63.93% | 151 11.71% 75.64% | 165 12.80% 88.44% | 149 11.56% 100.00% -system.ruby.L1Cache_Controller.DataS_fromL1::total 1289 -system.ruby.L1Cache_Controller.Data_all_Acks | 28623 12.51% 12.51% | 28405 12.42% 24.93% | 28733 12.56% 37.49% | 28414 12.42% 49.91% | 28556 12.48% 62.39% | 28383 12.41% 74.80% | 28815 12.60% 87.40% | 28826 12.60% 100.00% -system.ruby.L1Cache_Controller.Data_all_Acks::total 228755 -system.ruby.L1Cache_Controller.Ack | 2 18.18% 18.18% | 1 9.09% 27.27% | 1 9.09% 36.36% | 1 9.09% 45.45% | 1 9.09% 54.55% | 1 9.09% 63.64% | 3 27.27% 90.91% | 1 9.09% 100.00% -system.ruby.L1Cache_Controller.Ack::total 11 -system.ruby.L1Cache_Controller.Ack_all | 2 18.18% 18.18% | 1 9.09% 27.27% | 1 9.09% 36.36% | 1 9.09% 45.45% | 1 9.09% 54.55% | 1 9.09% 63.64% | 3 27.27% 90.91% | 1 9.09% 100.00% -system.ruby.L1Cache_Controller.Ack_all::total 11 -system.ruby.L1Cache_Controller.WB_Ack | 41099 12.56% 12.56% | 40747 12.45% 25.01% | 41179 12.58% 37.59% | 40659 12.42% 50.01% | 41184 12.58% 62.60% | 40696 12.43% 75.03% | 40814 12.47% 87.50% | 40902 12.50% 100.00% -system.ruby.L1Cache_Controller.WB_Ack::total 327280 -system.ruby.L1Cache_Controller.NP.Load | 50382 12.51% 12.51% | 50404 12.52% 25.03% | 50351 12.51% 37.54% | 50231 12.48% 50.02% | 50629 12.58% 62.59% | 50312 12.50% 75.09% | 50084 12.44% 87.53% | 50197 12.47% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 402590 -system.ruby.L1Cache_Controller.NP.Store | 28007 12.52% 12.52% | 27774 12.41% 24.93% | 28092 12.56% 37.49% | 27781 12.42% 49.91% | 27904 12.47% 62.38% | 27786 12.42% 74.80% | 28200 12.61% 87.41% | 28171 12.59% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 223715 -system.ruby.L1Cache_Controller.NP.Inv | 206 12.54% 12.54% | 200 12.17% 24.71% | 198 12.05% 36.76% | 211 12.84% 49.60% | 206 12.54% 62.14% | 193 11.75% 73.89% | 237 14.42% 88.31% | 192 11.69% 100.00% -system.ruby.L1Cache_Controller.NP.Inv::total 1643 -system.ruby.L1Cache_Controller.I.Load | 8 10.67% 10.67% | 9 12.00% 22.67% | 10 13.33% 36.00% | 6 8.00% 44.00% | 15 20.00% 64.00% | 10 13.33% 77.33% | 9 12.00% 89.33% | 8 10.67% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 75 -system.ruby.L1Cache_Controller.I.Store | 7 16.28% 16.28% | 3 6.98% 23.26% | 4 9.30% 32.56% | 4 9.30% 41.86% | 7 16.28% 58.14% | 6 13.95% 72.09% | 4 9.30% 81.40% | 8 18.60% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 43 -system.ruby.L1Cache_Controller.I.L1_Replacement | 37146 12.47% 12.47% | 37282 12.52% 24.99% | 37125 12.46% 37.45% | 37212 12.49% 49.95% | 37204 12.49% 62.44% | 37260 12.51% 74.95% | 37293 12.52% 87.47% | 37327 12.53% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 297849 -system.ruby.L1Cache_Controller.S.Inv | 594 12.78% 12.78% | 608 13.08% 25.86% | 578 12.44% 38.30% | 580 12.48% 50.77% | 596 12.82% 63.60% | 541 11.64% 75.24% | 559 12.03% 87.26% | 592 12.74% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 4648 -system.ruby.L1Cache_Controller.S.L1_Replacement | 138 12.21% 12.21% | 141 12.48% 24.69% | 133 11.77% 36.46% | 135 11.95% 48.41% | 139 12.30% 60.71% | 137 12.12% 72.83% | 173 15.31% 88.14% | 134 11.86% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 1130 -system.ruby.L1Cache_Controller.E.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% -system.ruby.L1Cache_Controller.E.Load::total 3 -system.ruby.L1Cache_Controller.E.Store | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::samples 222835 +system.ruby.ST.miss_latency_hist::mean 2053.045235 +system.ruby.ST.miss_latency_hist::gmean 1585.445376 +system.ruby.ST.miss_latency_hist::stdev 1206.799639 +system.ruby.ST.miss_latency_hist | 58667 26.33% 26.33% | 55108 24.73% 51.06% | 53862 24.17% 75.23% | 46353 20.80% 96.03% | 8746 3.92% 99.96% | 99 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 222835 +system.ruby.Directory_Controller.Fetch 619101 0.00% 0.00% +system.ruby.Directory_Controller.Data 222171 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 619097 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 222171 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 396922 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 619101 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 222171 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 396922 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 619097 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 222171 0.00% 0.00% +system.ruby.L1Cache_Controller.Load | 50255 12.50% 12.50% | 50036 12.45% 24.95% | 50411 12.54% 37.49% | 50415 12.54% 50.04% | 50500 12.56% 62.60% | 49698 12.36% 74.97% | 50454 12.55% 87.52% | 50164 12.48% 100.00% +system.ruby.L1Cache_Controller.Load::total 401933 +system.ruby.L1Cache_Controller.Store | 27984 12.56% 12.56% | 27641 12.40% 24.96% | 27968 12.55% 37.51% | 27685 12.42% 49.93% | 27750 12.45% 62.39% | 28127 12.62% 75.01% | 27782 12.47% 87.47% | 27912 12.53% 100.00% +system.ruby.L1Cache_Controller.Store::total 222849 +system.ruby.L1Cache_Controller.Inv | 76332 12.52% 12.52% | 75835 12.44% 24.97% | 76387 12.53% 37.50% | 76173 12.50% 50.00% | 76356 12.53% 62.52% | 75957 12.46% 74.98% | 76316 12.52% 87.51% | 76157 12.49% 100.00% +system.ruby.L1Cache_Controller.Inv::total 609513 +system.ruby.L1Cache_Controller.L1_Replacement | 552371 12.53% 12.53% | 550621 12.49% 25.01% | 551224 12.50% 37.51% | 552517 12.53% 50.04% | 551365 12.50% 62.54% | 548546 12.44% 74.98% | 551692 12.51% 87.49% | 551725 12.51% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 4410061 +system.ruby.L1Cache_Controller.Fwd_GETX | 234 12.86% 12.86% | 193 10.60% 23.46% | 223 12.25% 35.71% | 228 12.53% 48.24% | 227 12.47% 60.71% | 241 13.24% 73.96% | 236 12.97% 86.92% | 238 13.08% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 1820 +system.ruby.L1Cache_Controller.Fwd_GETS | 157 12.58% 12.58% | 144 11.54% 24.12% | 156 12.50% 36.62% | 164 13.14% 49.76% | 154 12.34% 62.10% | 145 11.62% 73.72% | 163 13.06% 86.78% | 165 13.22% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 1248 +system.ruby.L1Cache_Controller.Data | 2 11.76% 11.76% | 3 17.65% 29.41% | 3 17.65% 47.06% | 2 11.76% 58.82% | 4 23.53% 82.35% | 1 5.88% 88.24% | 1 5.88% 94.12% | 1 5.88% 100.00% +system.ruby.L1Cache_Controller.Data::total 17 +system.ruby.L1Cache_Controller.Data_Exclusive | 49438 12.50% 12.50% | 49246 12.45% 24.95% | 49647 12.55% 37.50% | 49605 12.54% 50.04% | 49712 12.57% 62.60% | 48909 12.36% 74.97% | 49665 12.55% 87.52% | 49363 12.48% 100.00% +system.ruby.L1Cache_Controller.Data_Exclusive::total 395585 +system.ruby.L1Cache_Controller.DataS_fromL1 | 172 13.78% 13.78% | 145 11.62% 25.40% | 152 12.18% 37.58% | 161 12.90% 50.48% | 163 13.06% 63.54% | 168 13.46% 77.00% | 147 11.78% 88.78% | 140 11.22% 100.00% +system.ruby.L1Cache_Controller.DataS_fromL1::total 1248 +system.ruby.L1Cache_Controller.Data_all_Acks | 28621 12.56% 12.56% | 28275 12.41% 24.97% | 28573 12.54% 37.51% | 28325 12.43% 49.94% | 28365 12.45% 62.38% | 28742 12.61% 75.00% | 28416 12.47% 87.47% | 28564 12.53% 100.00% +system.ruby.L1Cache_Controller.Data_all_Acks::total 227881 +system.ruby.L1Cache_Controller.Ack | 2 11.76% 11.76% | 3 17.65% 29.41% | 3 17.65% 47.06% | 2 11.76% 58.82% | 4 23.53% 82.35% | 1 5.88% 88.24% | 1 5.88% 94.12% | 1 5.88% 100.00% +system.ruby.L1Cache_Controller.Ack::total 17 +system.ruby.L1Cache_Controller.Ack_all | 2 11.76% 11.76% | 3 17.65% 29.41% | 3 17.65% 47.06% | 2 11.76% 58.82% | 4 23.53% 82.35% | 1 5.88% 88.24% | 1 5.88% 94.12% | 1 5.88% 100.00% +system.ruby.L1Cache_Controller.Ack_all::total 17 +system.ruby.L1Cache_Controller.WB_Ack | 41127 12.57% 12.57% | 40427 12.36% 24.93% | 41249 12.61% 37.53% | 40820 12.48% 50.01% | 41004 12.53% 62.54% | 40574 12.40% 74.94% | 41141 12.57% 87.52% | 40840 12.48% 100.00% +system.ruby.L1Cache_Controller.WB_Ack::total 327182 +system.ruby.L1Cache_Controller.NP.Load | 50249 12.50% 12.50% | 50019 12.45% 24.95% | 50402 12.54% 37.49% | 50402 12.54% 50.04% | 50493 12.57% 62.60% | 49692 12.37% 74.97% | 50442 12.55% 87.52% | 50154 12.48% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 401853 +system.ruby.L1Cache_Controller.NP.Store | 27983 12.56% 12.56% | 27632 12.40% 24.96% | 27961 12.55% 37.51% | 27680 12.42% 49.93% | 27747 12.45% 62.39% | 28122 12.62% 75.01% | 27776 12.47% 87.48% | 27901 12.52% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 222802 +system.ruby.L1Cache_Controller.NP.Inv | 218 13.12% 13.12% | 171 10.30% 23.42% | 208 12.52% 35.94% | 206 12.40% 48.34% | 219 13.18% 61.53% | 202 12.16% 73.69% | 218 13.12% 86.82% | 219 13.18% 100.00% +system.ruby.L1Cache_Controller.NP.Inv::total 1661 +system.ruby.L1Cache_Controller.I.Load | 5 7.81% 7.81% | 13 20.31% 28.12% | 7 10.94% 39.06% | 10 15.62% 54.69% | 7 10.94% 65.62% | 5 7.81% 73.44% | 11 17.19% 90.62% | 6 9.38% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 64 +system.ruby.L1Cache_Controller.I.Store | 0 0.00% 0.00% | 9 22.50% 22.50% | 7 17.50% 40.00% | 5 12.50% 52.50% | 1 2.50% 55.00% | 4 10.00% 65.00% | 4 10.00% 75.00% | 10 25.00% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 40 +system.ruby.L1Cache_Controller.I.L1_Replacement | 36955 12.47% 12.47% | 37106 12.52% 24.99% | 36973 12.48% 37.47% | 37122 12.53% 50.00% | 37081 12.51% 62.51% | 37099 12.52% 75.03% | 36939 12.47% 87.49% | 37064 12.51% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 296339 +system.ruby.L1Cache_Controller.S.Inv | 576 12.71% 12.71% | 579 12.77% 25.48% | 543 11.98% 37.46% | 579 12.77% 50.23% | 549 12.11% 62.34% | 556 12.27% 74.61% | 580 12.80% 87.40% | 571 12.60% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 4533 +system.ruby.L1Cache_Controller.S.L1_Replacement | 144 13.20% 13.20% | 112 10.27% 23.46% | 137 12.56% 36.02% | 134 12.28% 48.30% | 149 13.66% 61.96% | 137 12.56% 74.52% | 133 12.19% 86.71% | 145 13.29% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 1091 +system.ruby.L1Cache_Controller.E.Load | 0 0.00% 0.00% | 2 40.00% 40.00% | 1 20.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% +system.ruby.L1Cache_Controller.E.Load::total 5 +system.ruby.L1Cache_Controller.E.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.E.Store::total 2 -system.ruby.L1Cache_Controller.E.Inv | 23331 12.49% 12.49% | 23358 12.50% 24.99% | 23341 12.49% 37.48% | 23267 12.45% 49.93% | 23444 12.55% 62.48% | 23417 12.53% 75.01% | 23300 12.47% 87.49% | 23382 12.51% 100.00% -system.ruby.L1Cache_Controller.E.Inv::total 186840 -system.ruby.L1Cache_Controller.E.L1_Replacement | 26209 12.54% 12.54% | 26174 12.53% 25.07% | 26158 12.52% 37.59% | 26101 12.49% 50.09% | 26317 12.60% 62.68% | 26077 12.48% 75.16% | 25938 12.41% 87.58% | 25953 12.42% 100.00% -system.ruby.L1Cache_Controller.E.L1_Replacement::total 208927 -system.ruby.L1Cache_Controller.E.Fwd_GETX | 62 12.35% 12.35% | 66 13.15% 25.50% | 60 11.95% 37.45% | 65 12.95% 50.40% | 56 11.16% 61.55% | 72 14.34% 75.90% | 60 11.95% 87.85% | 61 12.15% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETX::total 502 -system.ruby.L1Cache_Controller.E.Fwd_GETS | 14 20.00% 20.00% | 3 4.29% 24.29% | 8 11.43% 35.71% | 6 8.57% 44.29% | 6 8.57% 52.86% | 9 12.86% 65.71% | 14 20.00% 85.71% | 10 14.29% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETS::total 70 -system.ruby.L1Cache_Controller.M.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 1 -system.ruby.L1Cache_Controller.M.Inv | 13036 12.46% 12.46% | 13096 12.52% 24.97% | 12978 12.40% 37.38% | 13136 12.55% 49.93% | 12951 12.38% 62.31% | 13083 12.50% 74.81% | 13211 12.63% 87.44% | 13143 12.56% 100.00% -system.ruby.L1Cache_Controller.M.Inv::total 104634 -system.ruby.L1Cache_Controller.M.L1_Replacement | 14892 12.58% 12.58% | 14577 12.32% 24.90% | 15023 12.69% 37.59% | 14560 12.30% 49.89% | 14869 12.56% 62.45% | 14620 12.35% 74.80% | 14876 12.57% 87.37% | 14950 12.63% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 118367 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 25 9.65% 9.65% | 34 13.13% 22.78% | 43 16.60% 39.38% | 35 13.51% 52.90% | 26 10.04% 62.93% | 28 10.81% 73.75% | 41 15.83% 89.58% | 27 10.42% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 259 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 59 12.04% 12.04% | 69 14.08% 26.12% | 52 10.61% 36.73% | 53 10.82% 47.55% | 63 12.86% 60.41% | 60 12.24% 72.65% | 75 15.31% 87.96% | 59 12.04% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 490 -system.ruby.L1Cache_Controller.IS.Inv | 113 10.38% 10.38% | 132 12.12% 22.50% | 139 12.76% 35.26% | 139 12.76% 48.03% | 154 14.14% 62.17% | 135 12.40% 74.56% | 137 12.58% 87.14% | 140 12.86% 100.00% -system.ruby.L1Cache_Controller.IS.Inv::total 1089 -system.ruby.L1Cache_Controller.IS.L1_Replacement | 303918 12.46% 12.46% | 305385 12.52% 24.99% | 304615 12.49% 37.48% | 306232 12.56% 50.04% | 305451 12.53% 62.56% | 304922 12.50% 75.07% | 303754 12.46% 87.52% | 304236 12.48% 100.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement::total 2438513 -system.ruby.L1Cache_Controller.IS.Data_Exclusive | 49617 12.52% 12.52% | 49601 12.51% 25.03% | 49567 12.51% 37.54% | 49439 12.47% 50.01% | 49824 12.57% 62.58% | 49575 12.51% 75.09% | 49312 12.44% 87.53% | 49406 12.47% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 396341 -system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 158 12.26% 12.26% | 179 13.89% 26.14% | 152 11.79% 37.94% | 164 12.72% 50.66% | 171 13.27% 63.93% | 151 11.71% 75.64% | 165 12.80% 88.44% | 149 11.56% 100.00% -system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 1289 -system.ruby.L1Cache_Controller.IS.Data_all_Acks | 501 12.75% 12.75% | 498 12.67% 25.43% | 499 12.70% 38.13% | 492 12.52% 50.65% | 495 12.60% 63.25% | 458 11.66% 74.90% | 478 12.17% 87.07% | 508 12.93% 100.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 3929 -system.ruby.L1Cache_Controller.IM.L1_Replacement | 168014 12.40% 12.40% | 167718 12.38% 24.79% | 170734 12.60% 37.39% | 168216 12.42% 49.81% | 168432 12.43% 62.25% | 168072 12.41% 74.65% | 170520 12.59% 87.24% | 172796 12.76% 100.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement::total 1354502 -system.ruby.L1Cache_Controller.IM.Data | 2 18.18% 18.18% | 1 9.09% 27.27% | 1 9.09% 36.36% | 1 9.09% 45.45% | 1 9.09% 54.55% | 1 9.09% 63.64% | 3 27.27% 90.91% | 1 9.09% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 11 -system.ruby.L1Cache_Controller.IM.Data_all_Acks | 28009 12.52% 12.52% | 27775 12.41% 24.93% | 28095 12.56% 37.49% | 27783 12.42% 49.91% | 27907 12.47% 62.38% | 27790 12.42% 74.80% | 28200 12.60% 87.41% | 28178 12.59% 100.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 223737 -system.ruby.L1Cache_Controller.SM.Ack | 2 18.18% 18.18% | 1 9.09% 27.27% | 1 9.09% 36.36% | 1 9.09% 45.45% | 1 9.09% 54.55% | 1 9.09% 63.64% | 3 27.27% 90.91% | 1 9.09% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 11 -system.ruby.L1Cache_Controller.SM.Ack_all | 2 18.18% 18.18% | 1 9.09% 27.27% | 1 9.09% 36.36% | 1 9.09% 45.45% | 1 9.09% 54.55% | 1 9.09% 63.64% | 3 27.27% 90.91% | 1 9.09% 100.00% -system.ruby.L1Cache_Controller.SM.Ack_all::total 11 -system.ruby.L1Cache_Controller.IS_I.Data_all_Acks | 113 10.38% 10.38% | 132 12.12% 22.50% | 139 12.76% 35.26% | 139 12.76% 48.03% | 154 14.14% 62.17% | 135 12.40% 74.56% | 137 12.58% 87.14% | 140 12.86% 100.00% -system.ruby.L1Cache_Controller.IS_I.Data_all_Acks::total 1089 -system.ruby.L1Cache_Controller.M_I.Load | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M_I.Load::total 1 -system.ruby.L1Cache_Controller.M_I.Inv | 39121 12.55% 12.55% | 38797 12.45% 25.00% | 39282 12.61% 37.61% | 38722 12.43% 50.03% | 39243 12.59% 62.63% | 38848 12.47% 75.09% | 38794 12.45% 87.54% | 38827 12.46% 100.00% -system.ruby.L1Cache_Controller.M_I.Inv::total 311634 -system.ruby.L1Cache_Controller.M_I.Fwd_GETX | 135 12.74% 12.74% | 143 13.49% 26.23% | 132 12.45% 38.68% | 135 12.74% 51.42% | 145 13.68% 65.09% | 124 11.70% 76.79% | 121 11.42% 88.21% | 125 11.79% 100.00% -system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total 1060 -system.ruby.L1Cache_Controller.M_I.Fwd_GETS | 96 13.17% 13.17% | 80 10.97% 24.14% | 85 11.66% 35.80% | 108 14.81% 50.62% | 93 12.76% 63.37% | 85 11.66% 75.03% | 97 13.31% 88.34% | 85 11.66% 100.00% -system.ruby.L1Cache_Controller.M_I.Fwd_GETS::total 729 -system.ruby.L1Cache_Controller.M_I.WB_Ack | 1748 12.60% 12.60% | 1729 12.47% 25.07% | 1682 12.13% 37.20% | 1696 12.23% 49.43% | 1705 12.29% 61.72% | 1640 11.83% 73.55% | 1802 12.99% 86.54% | 1866 13.46% 100.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack::total 13868 -system.ruby.L1Cache_Controller.SINK_WB_ACK.Load | 2 22.22% 22.22% | 3 33.33% 55.56% | 1 11.11% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 22.22% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.Load::total 9 -system.ruby.L1Cache_Controller.SINK_WB_ACK.Store | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.E.Inv | 23003 12.40% 12.40% | 23352 12.58% 24.98% | 23212 12.51% 37.49% | 23319 12.57% 50.05% | 23269 12.54% 62.59% | 23047 12.42% 75.01% | 23189 12.50% 87.51% | 23179 12.49% 100.00% +system.ruby.L1Cache_Controller.E.Inv::total 185570 +system.ruby.L1Cache_Controller.E.L1_Replacement | 26368 12.59% 12.59% | 25847 12.34% 24.93% | 26370 12.59% 37.51% | 26213 12.51% 50.03% | 26377 12.59% 62.62% | 25796 12.31% 74.93% | 26413 12.61% 87.54% | 26096 12.46% 100.00% +system.ruby.L1Cache_Controller.E.L1_Replacement::total 209480 +system.ruby.L1Cache_Controller.E.Fwd_GETX | 64 13.31% 13.31% | 40 8.32% 21.62% | 55 11.43% 33.06% | 67 13.93% 46.99% | 60 12.47% 59.46% | 63 13.10% 72.56% | 54 11.23% 83.78% | 78 16.22% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETX::total 481 +system.ruby.L1Cache_Controller.E.Fwd_GETS | 3 6.00% 6.00% | 7 14.00% 20.00% | 8 16.00% 36.00% | 6 12.00% 48.00% | 5 10.00% 58.00% | 3 6.00% 64.00% | 8 16.00% 80.00% | 10 20.00% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETS::total 50 +system.ruby.L1Cache_Controller.M.Load | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 2 +system.ruby.L1Cache_Controller.M.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 1 +system.ruby.L1Cache_Controller.M.Inv | 13117 12.56% 12.56% | 12975 12.43% 24.99% | 13007 12.46% 37.45% | 12982 12.43% 49.89% | 13030 12.48% 62.37% | 13257 12.70% 75.07% | 12964 12.42% 87.48% | 13067 12.52% 100.00% +system.ruby.L1Cache_Controller.M.Inv::total 104399 +system.ruby.L1Cache_Controller.M.L1_Replacement | 14761 12.54% 12.54% | 14582 12.39% 24.93% | 14879 12.64% 37.57% | 14609 12.41% 49.98% | 14629 12.43% 62.41% | 14778 12.55% 74.96% | 14729 12.51% 87.47% | 14746 12.53% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 117713 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 46 17.10% 17.10% | 26 9.67% 26.77% | 22 8.18% 34.94% | 35 13.01% 47.96% | 31 11.52% 59.48% | 33 12.27% 71.75% | 39 14.50% 86.25% | 37 13.75% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 269 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 58 12.72% 12.72% | 58 12.72% 25.44% | 59 12.94% 38.38% | 58 12.72% 51.10% | 58 12.72% 63.82% | 58 12.72% 76.54% | 47 10.31% 86.84% | 60 13.16% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 456 +system.ruby.L1Cache_Controller.IS.Inv | 154 12.91% 12.91% | 156 13.08% 25.98% | 148 12.41% 38.39% | 155 12.99% 51.38% | 150 12.57% 63.96% | 153 12.82% 76.78% | 128 10.73% 87.51% | 149 12.49% 100.00% +system.ruby.L1Cache_Controller.IS.Inv::total 1193 +system.ruby.L1Cache_Controller.IS.L1_Replacement | 304731 12.52% 12.52% | 304693 12.51% 25.03% | 304216 12.49% 37.53% | 306147 12.57% 50.10% | 305838 12.56% 62.66% | 299900 12.32% 74.98% | 305125 12.53% 87.51% | 304082 12.49% 100.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement::total 2434732 +system.ruby.L1Cache_Controller.IS.Data_Exclusive | 49438 12.50% 12.50% | 49246 12.45% 24.95% | 49647 12.55% 37.50% | 49605 12.54% 50.04% | 49712 12.57% 62.60% | 48909 12.36% 74.97% | 49665 12.55% 87.52% | 49363 12.48% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 395585 +system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 172 13.78% 13.78% | 145 11.62% 25.40% | 152 12.18% 37.58% | 161 12.90% 50.48% | 163 13.06% 63.54% | 168 13.46% 77.00% | 147 11.78% 88.78% | 140 11.22% 100.00% +system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 1248 +system.ruby.L1Cache_Controller.IS.Data_all_Acks | 487 12.58% 12.58% | 481 12.43% 25.01% | 461 11.91% 36.93% | 488 12.61% 49.53% | 472 12.20% 61.73% | 464 11.99% 73.72% | 511 13.20% 86.93% | 506 13.07% 100.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 3870 +system.ruby.L1Cache_Controller.IM.L1_Replacement | 169412 12.54% 12.54% | 168281 12.46% 25.00% | 168649 12.49% 37.49% | 168292 12.46% 49.95% | 167291 12.39% 62.33% | 170836 12.65% 74.98% | 168353 12.46% 87.44% | 169592 12.56% 100.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement::total 1350706 +system.ruby.L1Cache_Controller.IM.Data | 2 11.76% 11.76% | 3 17.65% 29.41% | 3 17.65% 47.06% | 2 11.76% 58.82% | 4 23.53% 82.35% | 1 5.88% 88.24% | 1 5.88% 94.12% | 1 5.88% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 17 +system.ruby.L1Cache_Controller.IM.Data_all_Acks | 27980 12.56% 12.56% | 27638 12.40% 24.96% | 27964 12.55% 37.51% | 27682 12.42% 49.93% | 27743 12.45% 62.39% | 28125 12.62% 75.01% | 27777 12.47% 87.47% | 27909 12.53% 100.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 222818 +system.ruby.L1Cache_Controller.SM.Ack | 2 11.76% 11.76% | 3 17.65% 29.41% | 3 17.65% 47.06% | 2 11.76% 58.82% | 4 23.53% 82.35% | 1 5.88% 88.24% | 1 5.88% 94.12% | 1 5.88% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 17 +system.ruby.L1Cache_Controller.SM.Ack_all | 2 11.76% 11.76% | 3 17.65% 29.41% | 3 17.65% 47.06% | 2 11.76% 58.82% | 4 23.53% 82.35% | 1 5.88% 88.24% | 1 5.88% 94.12% | 1 5.88% 100.00% +system.ruby.L1Cache_Controller.SM.Ack_all::total 17 +system.ruby.L1Cache_Controller.IS_I.Data_all_Acks | 154 12.91% 12.91% | 156 13.08% 25.98% | 148 12.41% 38.39% | 155 12.99% 51.38% | 150 12.57% 63.96% | 153 12.82% 76.78% | 128 10.73% 87.51% | 149 12.49% 100.00% +system.ruby.L1Cache_Controller.IS_I.Data_all_Acks::total 1193 +system.ruby.L1Cache_Controller.M_I.Load | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% +system.ruby.L1Cache_Controller.M_I.Load::total 2 +system.ruby.L1Cache_Controller.M_I.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M_I.Store::total 1 +system.ruby.L1Cache_Controller.M_I.Inv | 39242 12.58% 12.58% | 38582 12.37% 24.94% | 39251 12.58% 37.53% | 38904 12.47% 50.00% | 39118 12.54% 62.53% | 38723 12.41% 74.95% | 39214 12.57% 87.52% | 38951 12.48% 100.00% +system.ruby.L1Cache_Controller.M_I.Inv::total 311985 +system.ruby.L1Cache_Controller.M_I.Fwd_GETX | 124 11.59% 11.59% | 127 11.87% 23.46% | 146 13.64% 37.10% | 126 11.78% 48.88% | 136 12.71% 61.59% | 145 13.55% 75.14% | 143 13.36% 88.50% | 123 11.50% 100.00% +system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total 1070 +system.ruby.L1Cache_Controller.M_I.Fwd_GETS | 96 12.94% 12.94% | 79 10.65% 23.58% | 89 11.99% 35.58% | 100 13.48% 49.06% | 91 12.26% 61.32% | 84 11.32% 72.64% | 108 14.56% 87.20% | 95 12.80% 100.00% +system.ruby.L1Cache_Controller.M_I.Fwd_GETS::total 742 +system.ruby.L1Cache_Controller.M_I.WB_Ack | 1667 12.44% 12.44% | 1641 12.25% 24.69% | 1763 13.16% 37.85% | 1692 12.63% 50.49% | 1661 12.40% 62.88% | 1622 12.11% 74.99% | 1677 12.52% 87.51% | 1673 12.49% 100.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack::total 13396 +system.ruby.L1Cache_Controller.SINK_WB_ACK.Load | 1 14.29% 14.29% | 0 0.00% 14.29% | 1 14.29% 28.57% | 2 28.57% 57.14% | 0 0.00% 57.14% | 1 14.29% 71.43% | 0 0.00% 71.43% | 2 28.57% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.Load::total 7 +system.ruby.L1Cache_Controller.SINK_WB_ACK.Store | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.SINK_WB_ACK.Store::total 3 -system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv | 28 12.96% 12.96% | 21 9.72% 22.69% | 20 9.26% 31.94% | 32 14.81% 46.76% | 26 12.04% 58.80% | 29 13.43% 72.22% | 33 15.28% 87.50% | 27 12.50% 100.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv::total 216 -system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack | 39351 12.56% 12.56% | 39018 12.45% 25.01% | 39497 12.60% 37.61% | 38963 12.43% 50.04% | 39479 12.60% 62.64% | 39056 12.46% 75.10% | 39012 12.45% 87.54% | 39036 12.46% 100.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total 313412 -system.ruby.L2Cache_Controller.L1_GETS 404299 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 226040 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 15894 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX_old 317733 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 6562 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 4972783 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 620744 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 620737 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 217912 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 199643 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack 3793 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 190620 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 1289 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 620088 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 398837 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 221912 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_PUTX_old 309665 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 4 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 11 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_PUTX 522 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_PUTX_old 5 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 1205 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 2576 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 9 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 7 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 5190 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 8661 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETS 1289 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETX 1821 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 13868 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX_old 799 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement 7 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 603102 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.L1_GETS 17 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.L1_GETX 19 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 1853 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 620737 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.L1_PUTX_old 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.WB_Data 5 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.Ack_all 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.L1_GETS 52 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.L1_GETX 56 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 4837 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 216700 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 199561 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 186837 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack 2584 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 2576 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack 1209 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack_all 1205 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L1_GETS 2503 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L1_GETX 1381 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L1_PUTX_old 282 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 2223370 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 396332 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.L1_GETS 8 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.L1_GETX 5 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 14743 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 2503 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L1_GETS 1420 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L1_GETX 752 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L1_PUTX_old 285 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 1246257 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 221909 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_PUTX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L2_Replacement_clean 11 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 11 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETS 156 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETX 74 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 900 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L2_Replacement 12 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 870972 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 620077 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_GETS 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_GETX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX 601 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX_old 5 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L2_Replacement_clean 3062 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data 997 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 55 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.Unblock 237 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.L1_PUTX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.L2_Replacement_clean 19 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data 210 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 27 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.L2_Replacement 148 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.L2_Replacement_clean 10 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.Unblock 1052 0.00% 0.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv | 22 12.79% 12.79% | 20 11.63% 24.42% | 18 10.47% 34.88% | 28 16.28% 51.16% | 21 12.21% 63.37% | 19 11.05% 74.42% | 23 13.37% 87.79% | 21 12.21% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv::total 172 +system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack | 39460 12.58% 12.58% | 38786 12.36% 24.94% | 39486 12.58% 37.52% | 39128 12.47% 49.99% | 39343 12.54% 62.53% | 38952 12.41% 74.94% | 39464 12.58% 87.52% | 39167 12.48% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total 313786 +system.ruby.L2Cache_Controller.L1_GETS 403525 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 225164 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 15509 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX_old 317752 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 6260 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 4973424 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 619096 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 619092 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 217296 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 200336 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack 3770 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 189325 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 1248 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 618418 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 398107 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 220994 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_PUTX_old 310098 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 6 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 17 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_PUTX 585 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_PUTX_old 1 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 1182 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 2573 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 6 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 6 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 4880 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 8504 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETS 1248 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETX 1820 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 13396 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX_old 802 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement 8 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 601946 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.L1_GETS 31 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.L1_GETX 22 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 1745 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 619092 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.WB_Data 7 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.Ack_all 1 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.L1_GETS 44 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.L1_GETX 53 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 4549 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data 216101 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 200276 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.Ack_all 185569 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack 2583 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 2573 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack 1187 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack_all 1182 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L1_GETS 2524 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L1_GETX 1390 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L1_PUTX_old 243 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 2228535 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 395579 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L1_GETS 9 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L1_GETX 3 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L1_PUTX_old 2 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 14781 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 2524 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L1_GETS 1430 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L1_GETX 771 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L1_PUTX_old 309 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 1244298 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 220993 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_PUTX 3 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L2_Replacement 11 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L2_Replacement_clean 44 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 17 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETS 115 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETX 83 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 915 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old 2 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 869948 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 618401 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L1_GETS 5 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L1_GETX 5 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX 609 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX_old 1 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L2_Replacement_clean 2783 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data 1008 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 46 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.Unblock 194 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.L2_Replacement_clean 12 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data 180 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 14 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.L1_PUTX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.L2_Replacement 179 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.Unblock 1054 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index 1f113b5af..114a3df3b 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.007450 # Number of seconds simulated -sim_ticks 7450335 # Number of ticks simulated -final_tick 7450335 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.007437 # Number of seconds simulated +sim_ticks 7436579 # Number of ticks simulated +final_tick 7436579 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 44748 # Simulator tick rate (ticks/s) -host_mem_usage 535492 # Number of bytes of host memory used -host_seconds 166.50 # Real time elapsed on the host +host_tick_rate 78938 # Simulator tick rate (ticks/s) +host_mem_usage 462744 # Number of bytes of host memory used +host_seconds 94.21 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39503232 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 39503232 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14194176 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 14194176 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 617238 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 617238 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 221784 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 221784 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 5302208827 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 5302208827 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1905172855 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1905172855 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 7207381681 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 7207381681 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 617238 # Number of read requests accepted -system.mem_ctrls.writeReqs 221784 # Number of write requests accepted -system.mem_ctrls.readBursts 617238 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 221784 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 39015296 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 487936 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 14108480 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 39503232 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 14194176 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 7624 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 1314 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39411840 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 39411840 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14207680 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 14207680 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 615810 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 615810 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 221995 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 221995 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 5299727200 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 5299727200 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1910512885 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1910512885 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 7210240085 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 7210240085 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 615810 # Number of read requests accepted +system.mem_ctrls.writeReqs 221995 # Number of write requests accepted +system.mem_ctrls.readBursts 615810 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 221995 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 38929216 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 482624 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 14125184 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 39411840 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 14207680 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 7541 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 1261 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 76468 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 76168 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 76258 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 76300 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 75967 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 75936 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 76245 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 76272 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 76231 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 76213 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 75957 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 75931 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 76493 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 75719 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 75833 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 75892 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts @@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 27688 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 27707 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 27571 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 27765 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 27388 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 27514 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 27619 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 27193 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 27537 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 27586 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 27586 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 27772 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 27583 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 27668 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 27492 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 27482 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts @@ -69,53 +69,53 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 7450249 # Total gap between requests +system.mem_ctrls.totGap 7436498 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 617238 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 615810 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 221784 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 30351 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 21642 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 21175 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 21038 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 21013 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 20994 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 21066 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 21037 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 21065 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 21095 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 21098 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 21130 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 21132 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 21102 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 21089 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 20989 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 20897 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 20827 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 21383 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 23358 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 20515 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 20498 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 20677 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 21227 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 19570 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 18765 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 17478 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 15176 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 11553 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 7171 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 2963 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 540 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 221995 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 30449 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 21561 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 21067 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 21018 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 20984 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 20961 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 20980 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 20969 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 21010 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 21084 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 21146 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 21129 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 21110 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 21093 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 21035 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 20973 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 20827 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 20851 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 21366 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 23438 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 20522 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 20526 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 20692 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 21175 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 19524 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 18773 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 17374 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 14929 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 11206 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 6963 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 2993 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 541 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -131,48 +131,48 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 1553 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 1647 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 2987 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 4458 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 5875 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 7231 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 8291 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 9328 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 10227 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 11116 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 12977 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 44701 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 22149 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 13767 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 13570 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 13598 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 13601 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 13593 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 1719 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 1018 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 900 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 831 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 771 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 688 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 620 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 558 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 493 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 433 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 369 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 305 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 263 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 219 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 171 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 130 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 103 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 71 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 48 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 31 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 22 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 12 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 4 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 1535 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 1606 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 2940 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 4414 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 5795 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 7172 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 8185 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 9155 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 10156 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 11124 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 12920 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 44902 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 22210 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 13816 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 13613 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 13742 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 13679 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 13617 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 1792 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 1038 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 879 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 821 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 762 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 704 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 635 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 574 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 527 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 442 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 381 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 322 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 271 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 227 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 184 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 155 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 123 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 96 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 66 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 50 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 35 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 28 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 17 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 9 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see @@ -180,1239 +180,1247 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 217818 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 243.887429 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 202.500481 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 149.546588 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 27528 12.64% 12.64% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 89594 41.13% 53.77% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 57727 26.50% 80.27% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 26380 12.11% 92.38% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 10665 4.90% 97.28% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 3943 1.81% 99.09% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1360 0.62% 99.71% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 433 0.20% 99.91% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 188 0.09% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 217818 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 13300 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 45.833308 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 16.067198 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-7 15 0.11% 0.11% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::8-15 35 0.26% 0.38% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-23 109 0.82% 1.20% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::24-31 4761 35.80% 36.99% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::32-39 1393 10.47% 47.47% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::40-47 165 1.24% 48.71% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::48-55 647 4.86% 53.57% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::56-63 5508 41.41% 94.98% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::64-71 350 2.63% 97.62% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::72-79 69 0.52% 98.14% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-87 128 0.96% 99.10% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::88-95 115 0.86% 99.96% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::96-103 2 0.02% 99.98% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::104-111 2 0.02% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.bytesPerActivate::samples 217346 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 244.098166 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 202.416903 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 150.509893 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 27506 12.66% 12.66% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 89777 41.31% 53.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 57089 26.27% 80.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 26035 11.98% 92.21% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 10776 4.96% 97.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 4097 1.89% 99.05% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1420 0.65% 99.70% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 436 0.20% 99.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 210 0.10% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 217346 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 13325 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 45.646679 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 42.587501 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 16.167834 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-7 23 0.17% 0.17% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::8-15 31 0.23% 0.41% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-23 111 0.83% 1.24% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::24-31 4805 36.06% 37.30% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::32-39 1443 10.83% 48.13% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::40-47 177 1.33% 49.46% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::48-55 620 4.65% 54.11% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::56-63 5467 41.03% 95.14% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::64-71 305 2.29% 97.43% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::72-79 81 0.61% 98.03% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::80-87 128 0.96% 98.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::88-95 130 0.98% 99.97% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::96-103 3 0.02% 99.99% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::168-175 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 13300 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 13300 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.574812 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.531569 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.272266 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 10416 78.32% 78.32% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 436 3.28% 81.59% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 1086 8.17% 89.76% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 895 6.73% 96.49% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 251 1.89% 98.38% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 107 0.80% 99.18% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 40 0.30% 99.48% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 32 0.24% 99.72% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 14 0.11% 99.83% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 8 0.06% 99.89% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 7 0.05% 99.94% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 5 0.04% 99.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 1 0.01% 99.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 1 0.01% 99.99% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::31 1 0.01% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 13300 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 70140821 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 81723487 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3048070 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 115.06 # Average queueing delay per DRAM burst +system.mem_ctrls.rdPerTurnAround::total 13325 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 13325 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.563302 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.520349 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.274530 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 10488 78.71% 78.71% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 442 3.32% 82.03% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 1047 7.86% 89.88% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 903 6.78% 96.66% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 233 1.75% 98.41% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 111 0.83% 99.24% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 54 0.41% 99.65% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 14 0.11% 99.75% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 9 0.07% 99.82% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 4 0.03% 99.85% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 6 0.05% 99.89% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 4 0.03% 99.92% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::28 3 0.02% 99.95% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::29 2 0.02% 99.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::30 2 0.02% 99.98% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::32 2 0.02% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::34 1 0.01% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 13325 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 69903381 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 81460492 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3041345 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 114.92 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 134.06 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 5236.72 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 1893.67 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 5302.21 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1905.17 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 133.92 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 5234.83 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1899.42 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 5299.73 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1910.51 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 55.71 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 40.91 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 14.79 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 20.99 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 27.77 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 398292 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 213942 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 65.34 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 97.04 # Row buffer hit rate for writes +system.mem_ctrls.busUtil 55.74 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 40.90 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 14.84 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 20.93 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 27.84 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 397576 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 214045 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 65.36 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 96.97 # Row buffer hit rate for writes system.mem_ctrls.avgGap 8.88 # Average gap between requests -system.mem_ctrls.pageHitRate 73.76 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 1645229880 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 914016600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 7600894080 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 2283510528 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 486183360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 5072981076 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 16222200 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 18019037724 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 2420.717630 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 76 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 248560 # Time in different power states +system.mem_ctrls.pageHitRate 73.78 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1642961880 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 912756600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7590311040 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2287948032 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 485674800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 5067708804 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 16181400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 18003542556 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 2421.165233 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 104 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 248300 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 7195054 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 7187510 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 486183360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 160860384 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 4325091600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 4972135344 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 667.968984 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 7195116 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 248560 # Time in different power states +system.mem_ctrls_1.refreshEnergy 485674800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 160692120 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 4320567600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 4966934520 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.968982 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 7187590 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 248300 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 1 # Clock period in ticks -system.cpu0.num_reads 99719 # number of read accesses completed -system.cpu0.num_writes 55019 # number of write accesses completed -system.cpu1.num_reads 99960 # number of read accesses completed -system.cpu1.num_writes 55278 # number of write accesses completed -system.cpu2.num_reads 99469 # number of read accesses completed -system.cpu2.num_writes 55712 # number of write accesses completed -system.cpu3.num_reads 99320 # number of read accesses completed -system.cpu3.num_writes 55175 # number of write accesses completed -system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 55545 # number of write accesses completed -system.cpu5.num_reads 99058 # number of read accesses completed -system.cpu5.num_writes 55373 # number of write accesses completed -system.cpu6.num_reads 99422 # number of read accesses completed -system.cpu6.num_writes 55005 # number of write accesses completed -system.cpu7.num_reads 99226 # number of read accesses completed -system.cpu7.num_writes 55176 # number of write accesses completed +system.cpu0.num_reads 99533 # number of read accesses completed +system.cpu0.num_writes 55594 # number of write accesses completed +system.cpu1.num_reads 99397 # number of read accesses completed +system.cpu1.num_writes 55662 # number of write accesses completed +system.cpu2.num_reads 99976 # number of read accesses completed +system.cpu2.num_writes 55789 # number of write accesses completed +system.cpu3.num_reads 99413 # number of read accesses completed +system.cpu3.num_writes 55629 # number of write accesses completed +system.cpu4.num_reads 99342 # number of read accesses completed +system.cpu4.num_writes 55223 # number of write accesses completed +system.cpu5.num_reads 100000 # number of read accesses completed +system.cpu5.num_writes 55687 # number of write accesses completed +system.cpu6.num_reads 99314 # number of read accesses completed +system.cpu6.num_writes 55046 # number of write accesses completed +system.cpu7.num_reads 99437 # number of read accesses completed +system.cpu7.num_writes 55128 # number of write accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 628543 -system.ruby.outstanding_req_hist::mean 15.998447 -system.ruby.outstanding_req_hist::gmean 15.997186 -system.ruby.outstanding_req_hist::stdev 0.125720 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 32 0.01% 0.02% | 628407 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 628543 -system.ruby.latency_hist::bucket_size 4096 -system.ruby.latency_hist::max_bucket 40959 -system.ruby.latency_hist::samples 628415 -system.ruby.latency_hist::mean 1517.183250 -system.ruby.latency_hist::gmean 957.723931 -system.ruby.latency_hist::stdev 1635.952449 -system.ruby.latency_hist | 579052 92.14% 92.14% | 44560 7.09% 99.24% | 4463 0.71% 99.95% | 320 0.05% 100.00% | 18 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 628415 +system.ruby.outstanding_req_hist::samples 627422 +system.ruby.outstanding_req_hist::mean 15.998440 +system.ruby.outstanding_req_hist::gmean 15.997176 +system.ruby.outstanding_req_hist::stdev 0.125852 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 35 0.01% 0.02% | 627283 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 627422 +system.ruby.latency_hist::bucket_size 2048 +system.ruby.latency_hist::max_bucket 20479 +system.ruby.latency_hist::samples 627294 +system.ruby.latency_hist::mean 1517.095464 +system.ruby.latency_hist::gmean 959.020860 +system.ruby.latency_hist::stdev 1631.310093 +system.ruby.latency_hist | 473909 75.55% 75.55% | 104367 16.64% 92.19% | 33291 5.31% 97.49% | 11023 1.76% 99.25% | 3421 0.55% 99.80% | 948 0.15% 99.95% | 243 0.04% 99.99% | 74 0.01% 100.00% | 12 0.00% 100.00% | 6 0.00% 100.00% +system.ruby.latency_hist::total 627294 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 120 +system.ruby.hit_latency_hist::samples 141 system.ruby.hit_latency_hist::mean 1 system.ruby.hit_latency_hist::gmean 1 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 120 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 120 -system.ruby.miss_latency_hist::bucket_size 4096 -system.ruby.miss_latency_hist::max_bucket 40959 -system.ruby.miss_latency_hist::samples 628295 -system.ruby.miss_latency_hist::mean 1517.472830 -system.ruby.miss_latency_hist::gmean 958.980411 -system.ruby.miss_latency_hist::stdev 1635.974461 -system.ruby.miss_latency_hist | 578932 92.14% 92.14% | 44560 7.09% 99.24% | 4463 0.71% 99.95% | 320 0.05% 100.00% | 18 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 628295 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 14 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 78658 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78672 # Number of cache demand accesses +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 141 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 141 +system.ruby.miss_latency_hist::bucket_size 2048 +system.ruby.miss_latency_hist::max_bucket 20479 +system.ruby.miss_latency_hist::samples 627153 +system.ruby.miss_latency_hist::mean 1517.436321 +system.ruby.miss_latency_hist::gmean 960.502379 +system.ruby.miss_latency_hist::stdev 1631.335046 +system.ruby.miss_latency_hist | 473768 75.54% 75.54% | 104367 16.64% 92.18% | 33291 5.31% 97.49% | 11023 1.76% 99.25% | 3421 0.55% 99.80% | 948 0.15% 99.95% | 243 0.04% 99.99% | 74 0.01% 100.00% | 12 0.00% 100.00% | 6 0.00% 100.00% +system.ruby.miss_latency_hist::total 627153 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 22 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 78254 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78276 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Dcache.demand_hits 12 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 78504 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78516 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 9 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 78372 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78381 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl2.L1Dcache.demand_hits 12 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 78447 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78459 # Number of cache demand accesses +system.ruby.l1_cntrl2.L1Dcache.demand_hits 19 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Dcache.demand_misses 78709 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78728 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl3.L1Dcache.demand_hits 19 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 78745 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78764 # Number of cache demand accesses +system.ruby.l1_cntrl3.L1Dcache.demand_hits 17 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 78281 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78298 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl4.L1Dcache.demand_hits 20 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Dcache.demand_misses 78661 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78681 # Number of cache demand accesses +system.ruby.l1_cntrl4.L1Dcache.demand_hits 23 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Dcache.demand_misses 78290 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78313 # Number of cache demand accesses system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl5.L1Dcache.demand_hits 8 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Dcache.demand_misses 78410 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78418 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Dcache.demand_hits 11 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Dcache.demand_misses 78570 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78581 # Number of cache demand accesses system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl6.L1Dcache.demand_hits 17 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Dcache.demand_misses 78434 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78451 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Dcache.demand_hits 23 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Dcache.demand_misses 78475 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78498 # Number of cache demand accesses system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl7.L1Dcache.demand_hits 18 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Dcache.demand_misses 78459 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78477 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Dcache.demand_hits 17 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Dcache.demand_misses 78224 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78241 # Number of cache demand accesses system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l2_cntrl0.L2cache.demand_hits 4503 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 623799 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 628302 # Number of cache demand accesses +system.ruby.l2_cntrl0.L2cache.demand_hits 4647 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 622511 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 627158 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers00.percent_links_utilized 5.807272 -system.ruby.network.routers00.msg_count.Request_Control::0 78658 -system.ruby.network.routers00.msg_count.Response_Data::2 77284 -system.ruby.network.routers00.msg_count.ResponseL2hit_Data::2 571 -system.ruby.network.routers00.msg_count.ResponseLocal_Data::2 1597 -system.ruby.network.routers00.msg_count.Response_Control::2 590 -system.ruby.network.routers00.msg_count.Writeback_Data::2 77627 -system.ruby.network.routers00.msg_count.Writeback_Control::0 157246 -system.ruby.network.routers00.msg_count.Forwarded_Control::0 796 -system.ruby.network.routers00.msg_count.Invalidate_Control::0 231 -system.ruby.network.routers00.msg_count.Unblock_Control::2 79413 -system.ruby.network.routers00.msg_bytes.Request_Control::0 629264 -system.ruby.network.routers00.msg_bytes.Response_Data::2 5564448 -system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::2 41112 -system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::2 114984 -system.ruby.network.routers00.msg_bytes.Response_Control::2 4720 -system.ruby.network.routers00.msg_bytes.Writeback_Data::2 5589144 -system.ruby.network.routers00.msg_bytes.Writeback_Control::0 1257968 -system.ruby.network.routers00.msg_bytes.Forwarded_Control::0 6368 -system.ruby.network.routers00.msg_bytes.Invalidate_Control::0 1848 -system.ruby.network.routers00.msg_bytes.Unblock_Control::2 635304 -system.ruby.network.routers01.percent_links_utilized 5.796192 -system.ruby.network.routers01.msg_count.Request_Control::0 78504 -system.ruby.network.routers01.msg_count.Response_Data::2 77157 -system.ruby.network.routers01.msg_count.ResponseL2hit_Data::2 518 -system.ruby.network.routers01.msg_count.ResponseLocal_Data::2 1667 -system.ruby.network.routers01.msg_count.Response_Control::2 595 -system.ruby.network.routers01.msg_count.Writeback_Data::2 77433 -system.ruby.network.routers01.msg_count.Writeback_Control::0 156912 -system.ruby.network.routers01.msg_count.Forwarded_Control::0 842 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77119 -system.ruby.network.routers02.msg_count.ResponseL2hit_Data::2 539 -system.ruby.network.routers02.msg_count.ResponseLocal_Data::2 1632 -system.ruby.network.routers02.msg_count.Response_Control::2 550 -system.ruby.network.routers02.msg_count.Writeback_Data::2 77366 -system.ruby.network.routers02.msg_count.Writeback_Control::0 156784 -system.ruby.network.routers02.msg_count.Forwarded_Control::0 846 -system.ruby.network.routers02.msg_count.Invalidate_Control::0 215 -system.ruby.network.routers02.msg_count.Unblock_Control::2 79250 -system.ruby.network.routers02.msg_bytes.Request_Control::0 627576 -system.ruby.network.routers02.msg_bytes.Response_Data::2 5552568 -system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::2 38808 -system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::2 117504 -system.ruby.network.routers02.msg_bytes.Response_Control::2 4400 -system.ruby.network.routers02.msg_bytes.Writeback_Data::2 5570352 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1640 -system.ruby.network.routers04.msg_count.Response_Control::2 675 -system.ruby.network.routers04.msg_count.Writeback_Data::2 77561 -system.ruby.network.routers04.msg_count.Writeback_Control::0 157206 -system.ruby.network.routers04.msg_count.Forwarded_Control::0 779 -system.ruby.network.routers04.msg_count.Invalidate_Control::0 254 -system.ruby.network.routers04.msg_count.Unblock_Control::2 79436 -system.ruby.network.routers04.msg_bytes.Request_Control::0 629272 -system.ruby.network.routers04.msg_bytes.Response_Data::2 5557464 -system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::2 43848 -system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::2 118080 -system.ruby.network.routers04.msg_bytes.Response_Control::2 5400 -system.ruby.network.routers04.msg_bytes.Writeback_Data::2 5584392 -system.ruby.network.routers04.msg_bytes.Writeback_Control::0 1257648 -system.ruby.network.routers04.msg_bytes.Forwarded_Control::0 6232 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1234467 -system.ruby.network.routers10.msg_count.ResponseL2hit_Data::2 4503 -system.ruby.network.routers10.msg_count.ResponseLocal_Data::2 6561 -system.ruby.network.routers10.msg_count.Response_Control::2 3061 -system.ruby.network.routers10.msg_count.Writeback_Data::2 841687 -system.ruby.network.routers10.msg_count.Writeback_Control::0 1255878 -system.ruby.network.routers10.msg_count.Writeback_Control::1 443578 -system.ruby.network.routers10.msg_count.Forwarded_Control::0 6561 -system.ruby.network.routers10.msg_count.Invalidate_Control::0 1843 -system.ruby.network.routers10.msg_count.Unblock_Control::2 1251653 -system.ruby.network.routers10.msg_bytes.Request_Control::0 5026416 -system.ruby.network.routers10.msg_bytes.Request_Control::1 4937904 -system.ruby.network.routers10.msg_bytes.Response_Data::2 88881624 -system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::2 324216 -system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::2 472392 -system.ruby.network.routers10.msg_bytes.Response_Control::2 24488 -system.ruby.network.routers10.msg_bytes.Writeback_Data::2 60601464 -system.ruby.network.routers10.msg_bytes.Writeback_Control::0 10047024 -system.ruby.network.routers10.msg_bytes.Writeback_Control::1 3548624 -system.ruby.network.routers10.msg_bytes.Forwarded_Control::0 52488 -system.ruby.network.routers10.msg_bytes.Invalidate_Control::0 14744 -system.ruby.network.routers10.msg_bytes.Unblock_Control::2 10013224 -system.ruby.network.msg_count.Request_Control 3736634 -system.ruby.network.msg_count.Response_Data 3703403 -system.ruby.network.msg_count.ResponseL2hit_Data 13509 -system.ruby.network.msg_count.ResponseLocal_Data 19683 -system.ruby.network.msg_count.Response_Control 9183 -system.ruby.network.msg_count.Writeback_Data 2525061 -system.ruby.network.msg_count.Writeback_Control 5098392 -system.ruby.network.msg_count.Forwarded_Control 19683 -system.ruby.network.msg_count.Invalidate_Control 5528 -system.ruby.network.msg_count.Unblock_Control 3754969 -system.ruby.network.msg_byte.Request_Control 29893072 -system.ruby.network.msg_byte.Response_Data 266645016 -system.ruby.network.msg_byte.ResponseL2hit_Data 972648 -system.ruby.network.msg_byte.ResponseLocal_Data 1417176 -system.ruby.network.msg_byte.Response_Control 73464 -system.ruby.network.msg_byte.Writeback_Data 181804392 -system.ruby.network.msg_byte.Writeback_Control 40787136 -system.ruby.network.msg_byte.Forwarded_Control 157464 -system.ruby.network.msg_byte.Invalidate_Control 44224 -system.ruby.network.msg_byte.Unblock_Control 30039752 -system.ruby.network.routers00.throttle0.link_utilization 5.287769 -system.ruby.network.routers00.throttle0.msg_count.Response_Data::2 77284 -system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::2 571 -system.ruby.network.routers00.throttle0.msg_count.ResponseLocal_Data::2 801 -system.ruby.network.routers00.throttle0.msg_count.Response_Control::2 359 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-system.ruby.network.routers01.throttle0.msg_count.ResponseLocal_Data::2 825 -system.ruby.network.routers01.throttle0.msg_count.Response_Control::2 350 -system.ruby.network.routers01.throttle0.msg_count.Writeback_Control::0 78454 -system.ruby.network.routers01.throttle0.msg_count.Forwarded_Control::0 842 -system.ruby.network.routers01.throttle0.msg_count.Invalidate_Control::0 245 -system.ruby.network.routers01.throttle0.msg_bytes.Response_Data::2 5555304 -system.ruby.network.routers01.throttle0.msg_bytes.ResponseL2hit_Data::2 37296 -system.ruby.network.routers01.throttle0.msg_bytes.ResponseLocal_Data::2 59400 -system.ruby.network.routers01.throttle0.msg_bytes.Response_Control::2 2800 -system.ruby.network.routers01.throttle0.msg_bytes.Writeback_Control::0 627632 -system.ruby.network.routers01.throttle0.msg_bytes.Forwarded_Control::0 6736 -system.ruby.network.routers01.throttle0.msg_bytes.Invalidate_Control::0 1960 -system.ruby.network.routers01.throttle1.link_utilization 6.314830 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-system.ruby.network.routers10.throttle6.msg_count.Forwarded_Control::0 870 -system.ruby.network.routers10.throttle6.msg_count.Invalidate_Control::0 227 -system.ruby.network.routers10.throttle6.msg_bytes.Response_Data::2 5547528 -system.ruby.network.routers10.throttle6.msg_bytes.ResponseL2hit_Data::2 42408 -system.ruby.network.routers10.throttle6.msg_bytes.ResponseLocal_Data::2 57168 -system.ruby.network.routers10.throttle6.msg_bytes.Response_Control::2 3232 -system.ruby.network.routers10.throttle6.msg_bytes.Writeback_Control::0 627104 -system.ruby.network.routers10.throttle6.msg_bytes.Forwarded_Control::0 6960 -system.ruby.network.routers10.throttle6.msg_bytes.Invalidate_Control::0 1816 -system.ruby.network.routers10.throttle7.link_utilization 5.274273 -system.ruby.network.routers10.throttle7.msg_count.Response_Data::2 77063 -system.ruby.network.routers10.throttle7.msg_count.ResponseL2hit_Data::2 573 -system.ruby.network.routers10.throttle7.msg_count.ResponseLocal_Data::2 823 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-system.ruby.network.routers10.throttle8.msg_count.Response_Data::2 617235 -system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::2 619903 -system.ruby.network.routers10.throttle8.msg_count.Writeback_Control::0 627939 -system.ruby.network.routers10.throttle8.msg_count.Writeback_Control::1 221784 -system.ruby.network.routers10.throttle8.msg_count.Unblock_Control::2 634436 -system.ruby.network.routers10.throttle8.msg_bytes.Request_Control::0 5026416 -system.ruby.network.routers10.throttle8.msg_bytes.Response_Data::2 44440920 -system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::2 44633016 -system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Control::0 5023512 -system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Control::1 1774272 -system.ruby.network.routers10.throttle8.msg_bytes.Unblock_Control::2 5075488 -system.ruby.network.routers10.throttle9.link_utilization 23.168790 -system.ruby.network.routers10.throttle9.msg_count.Request_Control::1 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100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 404685 +system.ruby.network.routers00.percent_links_utilized 5.789295 +system.ruby.network.routers00.msg_count.Request_Control::0 78254 +system.ruby.network.routers00.msg_count.Response_Data::2 76885 +system.ruby.network.routers00.msg_count.ResponseL2hit_Data::2 587 +system.ruby.network.routers00.msg_count.ResponseLocal_Data::2 1652 +system.ruby.network.routers00.msg_count.Response_Control::2 604 +system.ruby.network.routers00.msg_count.Writeback_Data::2 77175 +system.ruby.network.routers00.msg_count.Writeback_Control::0 156408 +system.ruby.network.routers00.msg_count.Forwarded_Control::0 873 +system.ruby.network.routers00.msg_count.Invalidate_Control::0 239 +system.ruby.network.routers00.msg_count.Unblock_Control::2 79033 +system.ruby.network.routers00.msg_bytes.Request_Control::0 626032 +system.ruby.network.routers00.msg_bytes.Response_Data::2 5535720 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77261 +system.ruby.network.routers01.msg_count.Writeback_Control::0 156637 +system.ruby.network.routers01.msg_count.Forwarded_Control::0 897 +system.ruby.network.routers01.msg_count.Invalidate_Control::0 228 +system.ruby.network.routers01.msg_count.Unblock_Control::2 79196 +system.ruby.network.routers01.msg_bytes.Request_Control::0 626976 +system.ruby.network.routers01.msg_bytes.Response_Data::2 5537880 +system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::2 42840 +system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::2 126576 +system.ruby.network.routers01.msg_bytes.Response_Control::2 5088 +system.ruby.network.routers01.msg_bytes.Writeback_Data::2 5562792 +system.ruby.network.routers01.msg_bytes.Writeback_Control::0 1253096 +system.ruby.network.routers01.msg_bytes.Forwarded_Control::0 7176 +system.ruby.network.routers01.msg_bytes.Invalidate_Control::0 1824 +system.ruby.network.routers01.msg_bytes.Unblock_Control::2 633568 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76878 +system.ruby.network.routers04.msg_count.ResponseL2hit_Data::2 592 +system.ruby.network.routers04.msg_count.ResponseLocal_Data::2 1671 +system.ruby.network.routers04.msg_count.Response_Control::2 602 +system.ruby.network.routers04.msg_count.Writeback_Data::2 77230 +system.ruby.network.routers04.msg_count.Writeback_Control::0 156495 +system.ruby.network.routers04.msg_count.Forwarded_Control::0 853 +system.ruby.network.routers04.msg_count.Invalidate_Control::0 215 +system.ruby.network.routers04.msg_count.Unblock_Control::2 79085 +system.ruby.network.routers04.msg_bytes.Request_Control::0 626320 +system.ruby.network.routers04.msg_bytes.Response_Data::2 5535216 +system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::2 42624 +system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::2 120312 +system.ruby.network.routers04.msg_bytes.Response_Control::2 4816 +system.ruby.network.routers04.msg_bytes.Writeback_Data::2 5560560 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1654 +system.ruby.network.routers06.msg_count.Response_Control::2 595 +system.ruby.network.routers06.msg_count.Writeback_Data::2 77412 +system.ruby.network.routers06.msg_count.Writeback_Control::0 156860 +system.ruby.network.routers06.msg_count.Forwarded_Control::0 823 +system.ruby.network.routers06.msg_count.Invalidate_Control::0 222 +system.ruby.network.routers06.msg_count.Unblock_Control::2 79261 +system.ruby.network.routers06.msg_bytes.Request_Control::0 627800 +system.ruby.network.routers06.msg_bytes.Response_Data::2 5549832 +system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::2 40248 +system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::2 119088 +system.ruby.network.routers06.msg_bytes.Response_Control::2 4760 +system.ruby.network.routers06.msg_bytes.Writeback_Data::2 5573664 +system.ruby.network.routers06.msg_bytes.Writeback_Control::0 1254880 +system.ruby.network.routers06.msg_bytes.Forwarded_Control::0 6584 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840575 +system.ruby.network.routers08.msg_count.Writeback_Control::0 1253590 +system.ruby.network.routers08.msg_count.Writeback_Control::1 443999 +system.ruby.network.routers08.msg_count.Forwarded_Control::0 6701 +system.ruby.network.routers08.msg_count.Invalidate_Control::0 1852 +system.ruby.network.routers08.msg_count.Unblock_Control::2 1249240 +system.ruby.network.routers08.msg_bytes.Request_Control::0 5017264 +system.ruby.network.routers08.msg_bytes.Request_Control::1 4926480 +system.ruby.network.routers08.msg_bytes.Response_Data::2 88676064 +system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::2 334584 +system.ruby.network.routers08.msg_bytes.Response_Control::2 9544 +system.ruby.network.routers08.msg_bytes.Writeback_Data::2 60521400 +system.ruby.network.routers08.msg_bytes.Writeback_Control::0 10028720 +system.ruby.network.routers08.msg_bytes.Writeback_Control::1 3551992 +system.ruby.network.routers08.msg_bytes.Forwarded_Control::0 53608 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1808 +system.ruby.network.routers10.throttle8.link_utilization 88.877366 +system.ruby.network.routers10.throttle8.msg_count.Request_Control::0 627158 +system.ruby.network.routers10.throttle8.msg_count.Response_Data::2 615806 +system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::2 618580 +system.ruby.network.routers10.throttle8.msg_count.Writeback_Control::0 626795 +system.ruby.network.routers10.throttle8.msg_count.Writeback_Control::1 221995 +system.ruby.network.routers10.throttle8.msg_count.Unblock_Control::2 633449 +system.ruby.network.routers10.throttle8.msg_bytes.Request_Control::0 5017264 +system.ruby.network.routers10.throttle8.msg_bytes.Response_Data::2 44338032 +system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::2 44537760 +system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Control::0 5014360 +system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Control::1 1775960 +system.ruby.network.routers10.throttle8.msg_bytes.Unblock_Control::2 5067592 +system.ruby.network.routers10.throttle9.link_utilization 23.206638 +system.ruby.network.routers10.throttle9.msg_count.Request_Control::1 615810 +system.ruby.network.routers10.throttle9.msg_count.Writeback_Data::2 221995 +system.ruby.network.routers10.throttle9.msg_count.Writeback_Control::1 222004 +system.ruby.network.routers10.throttle9.msg_count.Unblock_Control::2 615791 +system.ruby.network.routers10.throttle9.msg_bytes.Request_Control::1 4926480 +system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Data::2 15983640 +system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Control::1 1776032 +system.ruby.network.routers10.throttle9.msg_bytes.Unblock_Control::2 4926328 +system.ruby.LD.latency_hist::bucket_size 2048 +system.ruby.LD.latency_hist::max_bucket 20479 +system.ruby.LD.latency_hist::samples 403304 +system.ruby.LD.latency_hist::mean 1518.773717 +system.ruby.LD.latency_hist::gmean 957.355041 +system.ruby.LD.latency_hist::stdev 1636.976329 +system.ruby.LD.latency_hist | 304613 75.53% 75.53% | 66895 16.59% 92.12% | 21521 5.34% 97.45% | 7222 1.79% 99.24% | 2199 0.55% 99.79% | 636 0.16% 99.95% | 153 0.04% 99.98% | 51 0.01% 100.00% | 10 0.00% 100.00% | 4 0.00% 100.00% +system.ruby.LD.latency_hist::total 403304 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 99 +system.ruby.LD.hit_latency_hist::samples 106 system.ruby.LD.hit_latency_hist::mean 1 system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 99 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 99 -system.ruby.LD.miss_latency_hist::bucket_size 4096 -system.ruby.LD.miss_latency_hist::max_bucket 40959 -system.ruby.LD.miss_latency_hist::samples 404586 -system.ruby.LD.miss_latency_hist::mean 1516.105515 -system.ruby.LD.miss_latency_hist::gmean 956.810233 -system.ruby.LD.miss_latency_hist::stdev 1635.021809 -system.ruby.LD.miss_latency_hist | 372777 92.14% 92.14% | 28739 7.10% 99.24% | 2856 0.71% 99.95% | 198 0.05% 100.00% | 15 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 404586 -system.ruby.ST.latency_hist::bucket_size 4096 -system.ruby.ST.latency_hist::max_bucket 40959 -system.ruby.ST.latency_hist::samples 223730 -system.ruby.ST.latency_hist::mean 1519.803097 -system.ruby.ST.latency_hist::gmean 962.297042 -system.ruby.ST.latency_hist::stdev 1637.685967 -system.ruby.ST.latency_hist | 206176 92.15% 92.15% | 15821 7.07% 99.23% | 1607 0.72% 99.94% | 122 0.05% 100.00% | 3 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 223730 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 106 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 106 +system.ruby.LD.miss_latency_hist::bucket_size 2048 +system.ruby.LD.miss_latency_hist::max_bucket 20479 +system.ruby.LD.miss_latency_hist::samples 403198 +system.ruby.LD.miss_latency_hist::mean 1519.172736 +system.ruby.LD.miss_latency_hist::gmean 959.084223 +system.ruby.LD.miss_latency_hist::stdev 1637.006477 +system.ruby.LD.miss_latency_hist | 304507 75.52% 75.52% | 66895 16.59% 92.11% | 21521 5.34% 97.45% | 7222 1.79% 99.24% | 2199 0.55% 99.79% | 636 0.16% 99.95% | 153 0.04% 99.98% | 51 0.01% 100.00% | 10 0.00% 100.00% | 4 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 403198 +system.ruby.ST.latency_hist::bucket_size 2048 +system.ruby.ST.latency_hist::max_bucket 20479 +system.ruby.ST.latency_hist::samples 223990 +system.ruby.ST.latency_hist::mean 1514.073695 +system.ruby.ST.latency_hist::gmean 962.027552 +system.ruby.ST.latency_hist::stdev 1621.057112 +system.ruby.ST.latency_hist | 169296 75.58% 75.58% | 37472 16.73% 92.31% | 11770 5.25% 97.57% | 3801 1.70% 99.26% | 1222 0.55% 99.81% | 312 0.14% 99.95% | 90 0.04% 99.99% | 23 0.01% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% +system.ruby.ST.latency_hist::total 223990 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 21 +system.ruby.ST.hit_latency_hist::samples 35 system.ruby.ST.hit_latency_hist::mean 1 system.ruby.ST.hit_latency_hist::gmean 1 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 21 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 21 -system.ruby.ST.miss_latency_hist::bucket_size 4096 -system.ruby.ST.miss_latency_hist::max_bucket 40959 -system.ruby.ST.miss_latency_hist::samples 223709 -system.ruby.ST.miss_latency_hist::mean 1519.945670 -system.ruby.ST.miss_latency_hist::gmean 962.917767 -system.ruby.ST.miss_latency_hist::stdev 1637.696715 -system.ruby.ST.miss_latency_hist | 206155 92.15% 92.15% | 15821 7.07% 99.23% | 1607 0.72% 99.94% | 122 0.05% 100.00% | 3 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 223709 -system.ruby.Directory_Controller.GETX 221811 0.00% 0.00% -system.ruby.Directory_Controller.GETS 395429 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 221694 0.00% 0.00% -system.ruby.Directory_Controller.PUTO_SHARERS 100 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 143423 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 251993 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 221801 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 221784 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 617238 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 221784 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 79576 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 143429 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 221511 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 142233 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 252000 0.00% 0.00% -system.ruby.Directory_Controller.S.Memory_Ack 100 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 221694 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTO_SHARERS 100 0.00% 0.00% -system.ruby.Directory_Controller.IS.Unblock 143423 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 143429 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Ack 109 0.00% 0.00% -system.ruby.Directory_Controller.SS.GETX 1 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 251993 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 252000 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 221801 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 221809 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Ack 64 0.00% 0.00% -system.ruby.Directory_Controller.MI.GETX 1 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 221684 0.00% 0.00% -system.ruby.Directory_Controller.MIS.Dirty_Writeback 100 0.00% 0.00% -system.ruby.L1Cache_Controller.Load | 50975 12.59% 12.59% | 50686 12.52% 25.11% | 50265 12.42% 37.53% | 50687 12.52% 50.05% | 50708 12.53% 62.58% | 50292 12.42% 75.00% | 50642 12.51% 87.51% | 50559 12.49% 100.00% -system.ruby.L1Cache_Controller.Load::total 404814 -system.ruby.L1Cache_Controller.Store | 27723 12.39% 12.39% | 27833 12.44% 24.83% | 28209 12.61% 37.43% | 28121 12.57% 50.00% | 27986 12.51% 62.51% | 28145 12.58% 75.09% | 27813 12.43% 87.51% | 27938 12.49% 100.00% -system.ruby.L1Cache_Controller.Store::total 223768 -system.ruby.L1Cache_Controller.L1_Replacement | 9449872 12.49% 12.49% | 9450863 12.50% 24.99% | 9457169 12.50% 37.50% | 9449931 12.49% 49.99% | 9452722 12.50% 62.49% | 9458219 12.51% 74.99% | 9456663 12.50% 87.50% | 9455445 12.50% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 75630884 -system.ruby.L1Cache_Controller.Fwd_GETX | 160 12.08% 12.08% | 162 12.24% 24.32% | 196 14.80% 39.12% | 176 13.29% 52.42% | 158 11.93% 64.35% | 165 12.46% 76.81% | 169 12.76% 89.58% | 138 10.42% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 1324 -system.ruby.L1Cache_Controller.Fwd_GETS | 667 12.00% 12.00% | 715 12.86% 24.86% | 691 12.43% 37.29% | 687 12.36% 49.65% | 656 11.80% 61.45% | 702 12.63% 74.08% | 752 13.53% 87.61% | 689 12.39% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 5559 -system.ruby.L1Cache_Controller.Inv | 231 12.53% 12.53% | 245 13.29% 25.83% | 215 11.67% 37.49% | 234 12.70% 50.19% | 254 13.78% 63.97% | 239 12.97% 76.94% | 227 12.32% 89.26% | 198 10.74% 100.00% -system.ruby.L1Cache_Controller.Inv::total 1843 -system.ruby.L1Cache_Controller.Ack | 359 11.73% 11.73% | 350 11.43% 23.16% | 335 10.94% 34.11% | 406 13.26% 47.37% | 421 13.75% 61.12% | 405 13.23% 74.35% | 404 13.20% 87.55% | 381 12.45% 100.00% -system.ruby.L1Cache_Controller.Ack::total 3061 -system.ruby.L1Cache_Controller.Data | 50755 12.59% 12.59% | 50486 12.52% 25.12% | 50068 12.42% 37.54% | 50475 12.52% 50.06% | 50468 12.52% 62.58% | 50087 12.43% 75.00% | 50433 12.51% 87.52% | 50322 12.48% 100.00% -system.ruby.L1Cache_Controller.Data::total 403094 -system.ruby.L1Cache_Controller.Exclusive_Data | 27901 12.39% 12.39% | 28014 12.44% 24.83% | 28376 12.60% 37.43% | 28266 12.55% 49.98% | 28189 12.52% 62.50% | 28320 12.58% 75.07% | 27999 12.43% 87.51% | 28136 12.49% 100.00% -system.ruby.L1Cache_Controller.Exclusive_Data::total 225201 -system.ruby.L1Cache_Controller.Writeback_Ack | 623 12.31% 12.31% | 636 12.57% 24.89% | 642 12.69% 37.58% | 640 12.65% 50.23% | 656 12.97% 63.19% | 622 12.29% 75.49% | 608 12.02% 87.51% | 632 12.49% 100.00% -system.ruby.L1Cache_Controller.Writeback_Ack::total 5059 -system.ruby.L1Cache_Controller.Writeback_Ack_Data | 77761 12.52% 12.52% | 77567 12.49% 25.01% | 77530 12.48% 37.50% | 77833 12.53% 50.03% | 77685 12.51% 62.54% | 77496 12.48% 75.02% | 77548 12.49% 87.51% | 77576 12.49% 100.00% -system.ruby.L1Cache_Controller.Writeback_Ack_Data::total 620996 -system.ruby.L1Cache_Controller.Writeback_Nack | 239 12.69% 12.69% | 251 13.32% 26.01% | 219 11.62% 37.63% | 233 12.37% 50.00% | 261 13.85% 63.85% | 238 12.63% 76.49% | 232 12.31% 88.80% | 211 11.20% 100.00% -system.ruby.L1Cache_Controller.Writeback_Nack::total 1884 -system.ruby.L1Cache_Controller.All_acks | 27718 12.39% 12.39% | 27829 12.44% 24.83% | 28204 12.61% 37.44% | 28102 12.56% 50.00% | 27980 12.51% 62.51% | 28140 12.58% 75.09% | 27807 12.43% 87.52% | 27929 12.48% 100.00% -system.ruby.L1Cache_Controller.All_acks::total 223709 -system.ruby.L1Cache_Controller.Use_Timeout | 27901 12.39% 12.39% | 28014 12.44% 24.83% | 28376 12.60% 37.43% | 28266 12.55% 49.98% | 28189 12.52% 62.50% | 28319 12.58% 75.07% | 27999 12.43% 87.51% | 28134 12.49% 100.00% -system.ruby.L1Cache_Controller.Use_Timeout::total 225198 -system.ruby.L1Cache_Controller.I.Load | 50939 12.59% 12.59% | 50672 12.52% 25.11% | 50242 12.42% 37.53% | 50641 12.52% 50.05% | 50680 12.53% 62.57% | 50268 12.42% 75.00% | 50626 12.51% 87.51% | 50529 12.49% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 404597 -system.ruby.L1Cache_Controller.I.Store | 27715 12.39% 12.39% | 27826 12.44% 24.83% | 28197 12.61% 37.44% | 28101 12.56% 50.00% | 27976 12.51% 62.51% | 28140 12.58% 75.09% | 27806 12.43% 87.52% | 27924 12.48% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 223685 -system.ruby.L1Cache_Controller.I.L1_Replacement | 44 10.78% 10.78% | 51 12.50% 23.28% | 54 13.24% 36.52% | 38 9.31% 45.83% | 57 13.97% 59.80% | 58 14.22% 74.02% | 58 14.22% 88.24% | 48 11.76% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 408 -system.ruby.L1Cache_Controller.S.Load | 7 14.29% 14.29% | 6 12.24% 26.53% | 2 4.08% 30.61% | 6 12.24% 42.86% | 9 18.37% 61.22% | 3 6.12% 67.35% | 8 16.33% 83.67% | 8 16.33% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 49 -system.ruby.L1Cache_Controller.S.Store | 4 11.11% 11.11% | 6 16.67% 27.78% | 8 22.22% 50.00% | 3 8.33% 58.33% | 5 13.89% 72.22% | 2 5.56% 77.78% | 2 5.56% 83.33% | 6 16.67% 100.00% -system.ruby.L1Cache_Controller.S.Store::total 36 -system.ruby.L1Cache_Controller.S.L1_Replacement | 50741 12.59% 12.59% | 50473 12.52% 25.12% | 50051 12.42% 37.54% | 50462 12.52% 50.06% | 50458 12.52% 62.58% | 50072 12.43% 75.00% | 50417 12.51% 87.52% | 50311 12.48% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 402985 -system.ruby.L1Cache_Controller.S.Fwd_GETS | 48 14.12% 14.12% | 34 10.00% 24.12% | 44 12.94% 37.06% | 48 14.12% 51.18% | 34 10.00% 61.18% | 40 11.76% 72.94% | 47 13.82% 86.76% | 45 13.24% 100.00% -system.ruby.L1Cache_Controller.S.Fwd_GETS::total 340 -system.ruby.L1Cache_Controller.S.Inv | 9 13.24% 13.24% | 7 10.29% 23.53% | 8 11.76% 35.29% | 10 14.71% 50.00% | 5 7.35% 57.35% | 13 19.12% 76.47% | 12 17.65% 94.12% | 4 5.88% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 68 -system.ruby.L1Cache_Controller.O.L1_Replacement | 1 25.00% 25.00% | 0 0.00% 25.00% | 2 50.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.O.L1_Replacement::total 4 -system.ruby.L1Cache_Controller.M.Load | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 1 -system.ruby.L1Cache_Controller.M.L1_Replacement | 182 12.25% 12.25% | 185 12.45% 24.70% | 170 11.44% 36.14% | 164 11.04% 47.17% | 209 14.06% 61.24% | 179 12.05% 73.28% | 190 12.79% 86.07% | 207 13.93% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 1486 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 2 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 1 25.00% 25.00% | 0 0.00% 25.00% | 2 50.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 4 -system.ruby.L1Cache_Controller.M_W.L1_Replacement | 618 15.54% 15.54% | 612 15.38% 30.92% | 440 11.06% 41.98% | 556 13.98% 55.96% | 512 12.87% 68.83% | 422 10.61% 79.44% | 281 7.06% 86.50% | 537 13.50% 100.00% -system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 3978 -system.ruby.L1Cache_Controller.M_W.Fwd_GETS | 2 50.00% 50.00% | 0 0.00% 50.00% | 2 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M_W.Fwd_GETS::total 4 -system.ruby.L1Cache_Controller.M_W.Use_Timeout | 183 12.27% 12.27% | 185 12.40% 24.66% | 172 11.53% 36.19% | 164 10.99% 47.18% | 209 14.01% 61.19% | 180 12.06% 73.26% | 192 12.87% 86.13% | 207 13.87% 100.00% -system.ruby.L1Cache_Controller.M_W.Use_Timeout::total 1492 -system.ruby.L1Cache_Controller.MM.Load | 0 0.00% 0.00% | 1 8.33% 8.33% | 0 0.00% 8.33% | 5 41.67% 50.00% | 2 16.67% 66.67% | 0 0.00% 66.67% | 3 25.00% 91.67% | 1 8.33% 100.00% -system.ruby.L1Cache_Controller.MM.Load::total 12 -system.ruby.L1Cache_Controller.MM.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 20.00% 20.00% | 1 20.00% 40.00% | 1 20.00% 60.00% | 1 20.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.MM.Store::total 5 -system.ruby.L1Cache_Controller.MM.L1_Replacement | 27682 12.39% 12.39% | 27785 12.44% 24.83% | 28158 12.61% 37.44% | 28074 12.57% 50.01% | 27928 12.50% 62.51% | 28094 12.58% 75.09% | 27763 12.43% 87.52% | 27883 12.48% 100.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement::total 223367 -system.ruby.L1Cache_Controller.MM.Fwd_GETX | 16 13.11% 13.11% | 17 13.93% 27.05% | 21 17.21% 44.26% | 12 9.84% 54.10% | 15 12.30% 66.39% | 16 13.11% 79.51% | 16 13.11% 92.62% | 9 7.38% 100.00% -system.ruby.L1Cache_Controller.MM.Fwd_GETX::total 122 -system.ruby.L1Cache_Controller.MM.Fwd_GETS | 19 8.80% 8.80% | 27 12.50% 21.30% | 25 11.57% 32.87% | 16 7.41% 40.28% | 37 17.13% 57.41% | 29 13.43% 70.83% | 28 12.96% 83.80% | 35 16.20% 100.00% -system.ruby.L1Cache_Controller.MM.Fwd_GETS::total 216 -system.ruby.L1Cache_Controller.MM_W.Load | 5 13.51% 13.51% | 4 10.81% 24.32% | 8 21.62% 45.95% | 5 13.51% 59.46% | 6 16.22% 75.68% | 3 8.11% 83.78% | 4 10.81% 94.59% | 2 5.41% 100.00% -system.ruby.L1Cache_Controller.MM_W.Load::total 37 -system.ruby.L1Cache_Controller.MM_W.Store | 2 12.50% 12.50% | 0 0.00% 12.50% | 1 6.25% 18.75% | 2 12.50% 31.25% | 2 12.50% 43.75% | 1 6.25% 50.00% | 1 6.25% 56.25% | 7 43.75% 100.00% -system.ruby.L1Cache_Controller.MM_W.Store::total 16 -system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 606977 12.33% 12.33% | 615803 12.51% 24.84% | 623715 12.67% 37.51% | 616598 12.52% 50.03% | 615980 12.51% 62.54% | 618118 12.56% 75.10% | 608400 12.36% 87.45% | 617675 12.55% 100.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 4923266 -system.ruby.L1Cache_Controller.MM_W.Fwd_GETX | 10 9.43% 9.43% | 11 10.38% 19.81% | 11 10.38% 30.19% | 19 17.92% 48.11% | 18 16.98% 65.09% | 11 10.38% 75.47% | 12 11.32% 86.79% | 14 13.21% 100.00% -system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total 106 -system.ruby.L1Cache_Controller.MM_W.Fwd_GETS | 19 8.96% 8.96% | 24 11.32% 20.28% | 28 13.21% 33.49% | 30 14.15% 47.64% | 17 8.02% 55.66% | 22 10.38% 66.04% | 39 18.40% 84.43% | 33 15.57% 100.00% -system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total 212 -system.ruby.L1Cache_Controller.MM_W.Use_Timeout | 27718 12.39% 12.39% | 27829 12.44% 24.83% | 28204 12.61% 37.44% | 28102 12.56% 50.00% | 27980 12.51% 62.51% | 28139 12.58% 75.09% | 27807 12.43% 87.52% | 27927 12.48% 100.00% -system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total 223706 -system.ruby.L1Cache_Controller.IM.L1_Replacement | 3104942 12.38% 12.38% | 3112814 12.41% 24.80% | 3156163 12.59% 37.38% | 3151707 12.57% 49.95% | 3133278 12.50% 62.45% | 3159725 12.60% 75.05% | 3112202 12.41% 87.46% | 3144126 12.54% 100.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement::total 25074957 -system.ruby.L1Cache_Controller.IM.Ack | 136 11.13% 11.13% | 143 11.70% 22.83% | 126 10.31% 33.14% | 160 13.09% 46.24% | 158 12.93% 59.17% | 169 13.83% 73.00% | 162 13.26% 86.25% | 168 13.75% 100.00% -system.ruby.L1Cache_Controller.IM.Ack::total 1222 -system.ruby.L1Cache_Controller.IM.Exclusive_Data | 27714 12.39% 12.39% | 27823 12.44% 24.83% | 28196 12.61% 37.44% | 28099 12.56% 50.00% | 27975 12.51% 62.51% | 28138 12.58% 75.09% | 27805 12.43% 87.52% | 27923 12.48% 100.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 223673 -system.ruby.L1Cache_Controller.SM.L1_Replacement | 771 12.50% 12.50% | 1568 25.41% 37.91% | 1253 20.31% 58.22% | 163 2.64% 60.86% | 597 9.68% 70.53% | 603 9.77% 80.31% | 118 1.91% 82.22% | 1097 17.78% 100.00% -system.ruby.L1Cache_Controller.SM.L1_Replacement::total 6170 -system.ruby.L1Cache_Controller.SM.Exclusive_Data | 4 11.11% 11.11% | 6 16.67% 27.78% | 8 22.22% 50.00% | 3 8.33% 58.33% | 5 13.89% 72.22% | 2 5.56% 77.78% | 2 5.56% 83.33% | 6 16.67% 100.00% -system.ruby.L1Cache_Controller.SM.Exclusive_Data::total 36 -system.ruby.L1Cache_Controller.OM.L1_Replacement | 22113 12.42% 12.42% | 21338 11.99% 24.41% | 22521 12.65% 37.05% | 21572 12.12% 49.17% | 23207 13.03% 62.21% | 22805 12.81% 75.02% | 22735 12.77% 87.78% | 21748 12.22% 100.00% -system.ruby.L1Cache_Controller.OM.L1_Replacement::total 178039 -system.ruby.L1Cache_Controller.OM.Ack | 223 12.13% 12.13% | 207 11.26% 23.38% | 209 11.36% 34.75% | 246 13.38% 48.12% | 263 14.30% 62.43% | 236 12.83% 75.26% | 242 13.16% 88.42% | 213 11.58% 100.00% -system.ruby.L1Cache_Controller.OM.Ack::total 1839 -system.ruby.L1Cache_Controller.OM.All_acks | 27718 12.39% 12.39% | 27829 12.44% 24.83% | 28204 12.61% 37.44% | 28102 12.56% 50.00% | 27980 12.51% 62.51% | 28140 12.58% 75.09% | 27807 12.43% 87.52% | 27929 12.48% 100.00% -system.ruby.L1Cache_Controller.OM.All_acks::total 223709 -system.ruby.L1Cache_Controller.IS.L1_Replacement | 5635801 12.58% 12.58% | 5620234 12.54% 25.12% | 5574642 12.44% 37.55% | 5580597 12.45% 50.01% | 5600496 12.50% 62.50% | 5578142 12.45% 74.95% | 5634499 12.57% 87.52% | 5591813 12.48% 100.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement::total 44816224 -system.ruby.L1Cache_Controller.IS.Data | 50755 12.59% 12.59% | 50486 12.52% 25.12% | 50068 12.42% 37.54% | 50475 12.52% 50.06% | 50468 12.52% 62.58% | 50087 12.43% 75.00% | 50433 12.51% 87.52% | 50322 12.48% 100.00% -system.ruby.L1Cache_Controller.IS.Data::total 403094 -system.ruby.L1Cache_Controller.IS.Exclusive_Data | 183 12.27% 12.27% | 185 12.40% 24.66% | 172 11.53% 36.19% | 164 10.99% 47.18% | 209 14.01% 61.19% | 180 12.06% 73.26% | 192 12.87% 86.13% | 207 13.87% 100.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 1492 -system.ruby.L1Cache_Controller.SI.Load | 15 20.27% 20.27% | 2 2.70% 22.97% | 11 14.86% 37.84% | 29 39.19% 77.03% | 11 14.86% 91.89% | 4 5.41% 97.30% | 1 1.35% 98.65% | 1 1.35% 100.00% -system.ruby.L1Cache_Controller.SI.Load::total 74 -system.ruby.L1Cache_Controller.SI.Store | 1 4.17% 4.17% | 1 4.17% 8.33% | 2 8.33% 16.67% | 14 58.33% 75.00% | 2 8.33% 83.33% | 1 4.17% 87.50% | 2 8.33% 95.83% | 1 4.17% 100.00% -system.ruby.L1Cache_Controller.SI.Store::total 24 -system.ruby.L1Cache_Controller.SI.Fwd_GETS | 325 11.43% 11.43% | 384 13.51% 24.94% | 351 12.35% 37.28% | 352 12.38% 49.67% | 342 12.03% 61.70% | 351 12.35% 74.04% | 393 13.82% 87.86% | 345 12.14% 100.00% -system.ruby.L1Cache_Controller.SI.Fwd_GETS::total 2843 -system.ruby.L1Cache_Controller.SI.Inv | 222 12.51% 12.51% | 238 13.41% 25.92% | 207 11.66% 37.58% | 224 12.62% 50.20% | 249 14.03% 64.23% | 226 12.73% 76.96% | 215 12.11% 89.07% | 194 10.93% 100.00% -system.ruby.L1Cache_Controller.SI.Inv::total 1775 -system.ruby.L1Cache_Controller.SI.Writeback_Ack | 623 12.33% 12.33% | 634 12.54% 24.87% | 642 12.70% 37.57% | 639 12.64% 50.22% | 656 12.98% 63.20% | 622 12.31% 75.50% | 607 12.01% 87.51% | 631 12.49% 100.00% -system.ruby.L1Cache_Controller.SI.Writeback_Ack::total 5054 -system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data | 49896 12.60% 12.60% | 49599 12.52% 25.12% | 49200 12.42% 37.54% | 49596 12.52% 50.06% | 49549 12.51% 62.56% | 49222 12.43% 74.99% | 49595 12.52% 87.51% | 49486 12.49% 100.00% -system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total 396143 -system.ruby.L1Cache_Controller.OI.Fwd_GETX | 1 20.00% 20.00% | 0 0.00% 20.00% | 2 40.00% 60.00% | 1 20.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OI.Fwd_GETX::total 5 -system.ruby.L1Cache_Controller.OI.Fwd_GETS | 5 71.43% 71.43% | 1 14.29% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 1 14.29% 100.00% -system.ruby.L1Cache_Controller.OI.Fwd_GETS::total 7 -system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data | 248 12.84% 12.84% | 245 12.68% 25.52% | 239 12.37% 37.89% | 240 12.42% 50.31% | 225 11.65% 61.96% | 260 13.46% 75.41% | 245 12.68% 88.10% | 230 11.90% 100.00% -system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total 1932 -system.ruby.L1Cache_Controller.OI.Writeback_Nack | 17 15.04% 15.04% | 15 13.27% 28.32% | 12 10.62% 38.94% | 10 8.85% 47.79% | 11 9.73% 57.52% | 12 10.62% 68.14% | 18 15.93% 84.07% | 18 15.93% 100.00% -system.ruby.L1Cache_Controller.OI.Writeback_Nack::total 113 -system.ruby.L1Cache_Controller.MI.Load | 9 20.45% 20.45% | 0 0.00% 20.45% | 2 4.55% 25.00% | 1 2.27% 27.27% | 0 0.00% 27.27% | 14 31.82% 59.09% | 0 0.00% 59.09% | 18 40.91% 100.00% -system.ruby.L1Cache_Controller.MI.Load::total 44 -system.ruby.L1Cache_Controller.MI.Store | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.MI.Store::total 2 -system.ruby.L1Cache_Controller.MI.Fwd_GETX | 133 12.21% 12.21% | 134 12.30% 24.52% | 162 14.88% 39.39% | 144 13.22% 52.62% | 124 11.39% 64.00% | 138 12.67% 76.68% | 139 12.76% 89.44% | 115 10.56% 100.00% -system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 1089 -system.ruby.L1Cache_Controller.MI.Fwd_GETS | 248 12.83% 12.83% | 245 12.67% 25.50% | 239 12.36% 37.87% | 241 12.47% 50.34% | 226 11.69% 62.03% | 259 13.40% 75.43% | 245 12.67% 88.10% | 230 11.90% 100.00% -system.ruby.L1Cache_Controller.MI.Fwd_GETS::total 1933 -system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data | 27483 12.39% 12.39% | 27589 12.44% 24.83% | 27927 12.59% 37.42% | 27852 12.56% 49.97% | 27787 12.53% 62.50% | 27876 12.57% 75.06% | 27569 12.43% 87.49% | 27745 12.51% 100.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total 221828 -system.ruby.L1Cache_Controller.II.Writeback_Ack | 0 0.00% 0.00% | 2 40.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 1 20.00% 80.00% | 1 20.00% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Ack::total 5 -system.ruby.L1Cache_Controller.II.Writeback_Ack_Data | 134 12.26% 12.26% | 134 12.26% 24.52% | 164 15.00% 39.52% | 145 13.27% 52.79% | 124 11.34% 64.14% | 138 12.63% 76.76% | 139 12.72% 89.48% | 115 10.52% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Ack_Data::total 1093 -system.ruby.L1Cache_Controller.II.Writeback_Nack | 222 12.54% 12.54% | 236 13.33% 25.86% | 207 11.69% 37.55% | 223 12.59% 50.14% | 250 14.12% 64.26% | 226 12.76% 77.02% | 214 12.08% 89.10% | 193 10.90% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Nack::total 1771 -system.ruby.L2Cache_Controller.L1_GETS 502566 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 277256 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTO 133 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 260463 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTS_only 477991 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTS 24694 0.00% 0.00% -system.ruby.L2Cache_Controller.All_Acks 221808 0.00% 0.00% -system.ruby.L2Cache_Controller.Data 617234 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBCLEANDATA 396143 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 223760 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Ack 221784 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 409238 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 225198 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 690238 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 395429 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 218564 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_GETS 3183 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_GETX 1859 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 392962 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_PUTS 3181 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_GETS 2153 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_GETX 1213 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_PUTX 222920 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_PUTS 1767 0.00% 0.00% +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 35 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 35 +system.ruby.ST.miss_latency_hist::bucket_size 2048 +system.ruby.ST.miss_latency_hist::max_bucket 20479 +system.ruby.ST.miss_latency_hist::samples 223955 +system.ruby.ST.miss_latency_hist::mean 1514.310161 +system.ruby.ST.miss_latency_hist::gmean 963.060847 +system.ruby.ST.miss_latency_hist::stdev 1621.073408 +system.ruby.ST.miss_latency_hist | 169261 75.58% 75.58% | 37472 16.73% 92.31% | 11770 5.26% 97.57% | 3801 1.70% 99.26% | 1222 0.55% 99.81% | 312 0.14% 99.95% | 90 0.04% 99.99% | 23 0.01% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 223955 +system.ruby.Directory_Controller.GETX 222027 0.00% 0.00% +system.ruby.Directory_Controller.GETS 393786 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 221899 0.00% 0.00% +system.ruby.Directory_Controller.PUTO_SHARERS 105 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 143585 0.00% 0.00% +system.ruby.Directory_Controller.Last_Unblock 250191 0.00% 0.00% +system.ruby.Directory_Controller.Exclusive_Unblock 222014 0.00% 0.00% +system.ruby.Directory_Controller.Dirty_Writeback 221995 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 615809 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 221995 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 79646 0.00% 0.00% +system.ruby.Directory_Controller.I.GETS 143590 0.00% 0.00% +system.ruby.Directory_Controller.I.Memory_Ack 221718 0.00% 0.00% +system.ruby.Directory_Controller.S.GETX 142378 0.00% 0.00% +system.ruby.Directory_Controller.S.GETS 250196 0.00% 0.00% +system.ruby.Directory_Controller.S.Memory_Ack 105 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 221899 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTO_SHARERS 105 0.00% 0.00% +system.ruby.Directory_Controller.IS.Unblock 143585 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Data 143590 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Ack 112 0.00% 0.00% +system.ruby.Directory_Controller.SS.GETX 3 0.00% 0.00% +system.ruby.Directory_Controller.SS.Last_Unblock 250191 0.00% 0.00% +system.ruby.Directory_Controller.SS.Memory_Data 250195 0.00% 0.00% +system.ruby.Directory_Controller.MM.Exclusive_Unblock 222014 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Data 222024 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Ack 60 0.00% 0.00% +system.ruby.Directory_Controller.MI.Dirty_Writeback 221890 0.00% 0.00% +system.ruby.Directory_Controller.MIS.Dirty_Writeback 105 0.00% 0.00% +system.ruby.L1Cache_Controller.Load | 50374 12.49% 12.49% | 50325 12.48% 24.96% | 50647 12.56% 37.52% | 50182 12.44% 49.96% | 50433 12.50% 62.46% | 50587 12.54% 75.00% | 50571 12.54% 87.54% | 50265 12.46% 100.00% +system.ruby.L1Cache_Controller.Load::total 403384 +system.ruby.L1Cache_Controller.Store | 27948 12.47% 12.47% | 28058 12.52% 25.00% | 28087 12.54% 37.53% | 28119 12.55% 50.08% | 27905 12.45% 62.54% | 28006 12.50% 75.04% | 27945 12.47% 87.51% | 27982 12.49% 100.00% +system.ruby.L1Cache_Controller.Store::total 224050 +system.ruby.L1Cache_Controller.L1_Replacement | 9444943 12.51% 12.51% | 9438529 12.50% 25.01% | 9427861 12.49% 37.50% | 9443150 12.51% 50.00% | 9440429 12.50% 62.51% | 9432698 12.49% 75.00% | 9432851 12.49% 87.49% | 9442432 12.51% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 75502893 +system.ruby.L1Cache_Controller.Fwd_GETX | 175 13.50% 13.50% | 165 12.73% 26.23% | 169 13.04% 39.27% | 177 13.66% 52.93% | 160 12.35% 65.28% | 143 11.03% 76.31% | 171 13.19% 89.51% | 136 10.49% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 1296 +system.ruby.L1Cache_Controller.Fwd_GETS | 752 13.09% 13.09% | 775 13.49% 26.58% | 721 12.55% 39.12% | 733 12.76% 51.88% | 720 12.53% 64.41% | 672 11.70% 76.11% | 694 12.08% 88.18% | 679 11.82% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 5746 +system.ruby.L1Cache_Controller.Inv | 239 12.86% 12.86% | 228 12.27% 25.13% | 240 12.92% 38.05% | 224 12.06% 50.11% | 215 11.57% 61.68% | 264 14.21% 75.89% | 222 11.95% 87.84% | 226 12.16% 100.00% +system.ruby.L1Cache_Controller.Inv::total 1858 +system.ruby.L1Cache_Controller.Ack | 365 11.96% 11.96% | 408 13.37% 25.34% | 380 12.45% 37.79% | 394 12.91% 50.70% | 387 12.68% 63.39% | 379 12.42% 75.81% | 373 12.23% 88.04% | 365 11.96% 100.00% +system.ruby.L1Cache_Controller.Ack::total 3051 +system.ruby.L1Cache_Controller.Data | 50182 12.49% 12.49% | 50097 12.47% 24.96% | 50442 12.56% 37.52% | 49978 12.44% 49.96% | 50201 12.50% 62.46% | 50372 12.54% 75.00% | 50365 12.54% 87.54% | 50046 12.46% 100.00% +system.ruby.L1Cache_Controller.Data::total 401683 +system.ruby.L1Cache_Controller.Exclusive_Data | 28069 12.45% 12.45% | 28274 12.54% 24.99% | 28264 12.54% 37.52% | 28299 12.55% 50.08% | 28087 12.46% 62.53% | 28195 12.50% 75.04% | 28106 12.47% 87.50% | 28176 12.50% 100.00% +system.ruby.L1Cache_Controller.Exclusive_Data::total 225470 +system.ruby.L1Cache_Controller.Writeback_Ack | 637 12.18% 12.18% | 690 13.19% 25.36% | 632 12.08% 37.44% | 666 12.73% 50.17% | 656 12.54% 62.71% | 638 12.19% 74.90% | 639 12.21% 87.12% | 674 12.88% 100.00% +system.ruby.L1Cache_Controller.Writeback_Ack::total 5232 +system.ruby.L1Cache_Controller.Writeback_Ack_Data | 77320 12.48% 12.48% | 77396 12.49% 24.97% | 77782 12.55% 37.52% | 77329 12.48% 50.00% | 77371 12.49% 62.49% | 77618 12.53% 75.01% | 77563 12.52% 87.53% | 77279 12.47% 100.00% +system.ruby.L1Cache_Controller.Writeback_Ack_Data::total 619658 +system.ruby.L1Cache_Controller.Writeback_Nack | 246 12.91% 12.91% | 232 12.18% 25.09% | 249 13.07% 38.16% | 233 12.23% 50.39% | 220 11.55% 61.94% | 263 13.81% 75.75% | 227 11.92% 87.66% | 235 12.34% 100.00% +system.ruby.L1Cache_Controller.Writeback_Nack::total 1905 +system.ruby.L1Cache_Controller.All_acks | 27913 12.46% 12.46% | 28056 12.53% 24.99% | 28076 12.54% 37.53% | 28112 12.55% 50.08% | 27887 12.45% 62.53% | 27999 12.50% 75.03% | 27936 12.47% 87.51% | 27976 12.49% 100.00% +system.ruby.L1Cache_Controller.All_acks::total 223955 +system.ruby.L1Cache_Controller.Use_Timeout | 28069 12.45% 12.45% | 28272 12.54% 24.99% | 28263 12.54% 37.52% | 28299 12.55% 50.08% | 28087 12.46% 62.53% | 28195 12.51% 75.04% | 28106 12.47% 87.50% | 28175 12.50% 100.00% +system.ruby.L1Cache_Controller.Use_Timeout::total 225466 +system.ruby.L1Cache_Controller.I.Load | 50341 12.49% 12.49% | 50316 12.48% 24.96% | 50632 12.56% 37.52% | 50168 12.44% 49.96% | 50401 12.50% 62.46% | 50569 12.54% 75.00% | 50536 12.53% 87.54% | 50248 12.46% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 403211 +system.ruby.L1Cache_Controller.I.Store | 27912 12.46% 12.46% | 28052 12.53% 24.99% | 28073 12.54% 37.53% | 28110 12.55% 50.08% | 27883 12.45% 62.53% | 28000 12.50% 75.03% | 27934 12.47% 87.51% | 27974 12.49% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 223938 +system.ruby.L1Cache_Controller.I.L1_Replacement | 62 14.80% 14.80% | 57 13.60% 28.40% | 54 12.89% 41.29% | 60 14.32% 55.61% | 45 10.74% 66.35% | 54 12.89% 79.24% | 45 10.74% 89.98% | 42 10.02% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 419 +system.ruby.L1Cache_Controller.S.Load | 7 13.46% 13.46% | 6 11.54% 25.00% | 5 9.62% 34.62% | 5 9.62% 44.23% | 9 17.31% 61.54% | 4 7.69% 69.23% | 8 15.38% 84.62% | 8 15.38% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 52 +system.ruby.L1Cache_Controller.S.Store | 1 3.85% 3.85% | 4 15.38% 19.23% | 4 15.38% 34.62% | 3 11.54% 46.15% | 6 23.08% 69.23% | 1 3.85% 73.08% | 5 19.23% 92.31% | 2 7.69% 100.00% +system.ruby.L1Cache_Controller.S.Store::total 26 +system.ruby.L1Cache_Controller.S.L1_Replacement | 50169 12.49% 12.49% | 50086 12.47% 24.96% | 50429 12.56% 37.52% | 49967 12.44% 49.96% | 50185 12.50% 62.46% | 50360 12.54% 75.00% | 50354 12.54% 87.54% | 50040 12.46% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 401590 +system.ruby.L1Cache_Controller.S.Fwd_GETS | 33 9.38% 9.38% | 53 15.06% 24.43% | 45 12.78% 37.22% | 42 11.93% 49.15% | 49 13.92% 63.07% | 42 11.93% 75.00% | 44 12.50% 87.50% | 44 12.50% 100.00% +system.ruby.L1Cache_Controller.S.Fwd_GETS::total 352 +system.ruby.L1Cache_Controller.S.Inv | 11 17.74% 17.74% | 6 9.68% 27.42% | 9 14.52% 41.94% | 8 12.90% 54.84% | 8 12.90% 67.74% | 10 16.13% 83.87% | 6 9.68% 93.55% | 4 6.45% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 62 +system.ruby.L1Cache_Controller.O.L1_Replacement | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% +system.ruby.L1Cache_Controller.O.L1_Replacement::total 6 +system.ruby.L1Cache_Controller.M.L1_Replacement | 153 10.15% 10.15% | 217 14.39% 24.54% | 188 12.47% 37.00% | 186 12.33% 49.34% | 200 13.26% 62.60% | 196 13.00% 75.60% | 170 11.27% 86.87% | 198 13.13% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 1508 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 1 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 6 +system.ruby.L1Cache_Controller.M_W.L1_Replacement | 567 12.42% 12.42% | 715 15.67% 28.09% | 542 11.88% 39.96% | 587 12.86% 52.83% | 335 7.34% 60.17% | 455 9.97% 70.14% | 721 15.80% 85.93% | 642 14.07% 100.00% +system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 4564 +system.ruby.L1Cache_Controller.M_W.Fwd_GETS | 4 57.14% 57.14% | 2 28.57% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 1 14.29% 100.00% +system.ruby.L1Cache_Controller.M_W.Fwd_GETS::total 7 +system.ruby.L1Cache_Controller.M_W.Use_Timeout | 156 10.30% 10.30% | 218 14.39% 24.69% | 188 12.41% 37.10% | 187 12.34% 49.44% | 200 13.20% 62.64% | 196 12.94% 75.58% | 170 11.22% 86.80% | 200 13.20% 100.00% +system.ruby.L1Cache_Controller.M_W.Use_Timeout::total 1515 +system.ruby.L1Cache_Controller.MM.Load | 1 7.14% 7.14% | 1 7.14% 14.29% | 2 14.29% 28.57% | 1 7.14% 35.71% | 3 21.43% 57.14% | 0 0.00% 57.14% | 3 21.43% 78.57% | 3 21.43% 100.00% +system.ruby.L1Cache_Controller.MM.Load::total 14 +system.ruby.L1Cache_Controller.MM.Store | 3 25.00% 25.00% | 1 8.33% 33.33% | 2 16.67% 50.00% | 1 8.33% 58.33% | 1 8.33% 66.67% | 0 0.00% 66.67% | 3 25.00% 91.67% | 1 8.33% 100.00% +system.ruby.L1Cache_Controller.MM.Store::total 12 +system.ruby.L1Cache_Controller.MM.L1_Replacement | 27862 12.46% 12.46% | 28003 12.52% 24.99% | 28030 12.54% 37.52% | 28061 12.55% 50.07% | 27850 12.46% 62.53% | 27955 12.50% 75.03% | 27897 12.48% 87.51% | 27936 12.49% 100.00% +system.ruby.L1Cache_Controller.MM.L1_Replacement::total 223594 +system.ruby.L1Cache_Controller.MM.Fwd_GETX | 13 11.61% 11.61% | 18 16.07% 27.68% | 15 13.39% 41.07% | 20 17.86% 58.93% | 13 11.61% 70.54% | 16 14.29% 84.82% | 5 4.46% 89.29% | 12 10.71% 100.00% +system.ruby.L1Cache_Controller.MM.Fwd_GETX::total 112 +system.ruby.L1Cache_Controller.MM.Fwd_GETS | 38 15.57% 15.57% | 33 13.52% 29.10% | 30 12.30% 41.39% | 31 12.70% 54.10% | 24 9.84% 63.93% | 28 11.48% 75.41% | 34 13.93% 89.34% | 26 10.66% 100.00% +system.ruby.L1Cache_Controller.MM.Fwd_GETS::total 244 +system.ruby.L1Cache_Controller.MM_W.Load | 5 12.50% 12.50% | 0 0.00% 12.50% | 5 12.50% 25.00% | 6 15.00% 40.00% | 8 20.00% 60.00% | 5 12.50% 72.50% | 7 17.50% 90.00% | 4 10.00% 100.00% +system.ruby.L1Cache_Controller.MM_W.Load::total 40 +system.ruby.L1Cache_Controller.MM_W.Store | 6 26.09% 26.09% | 1 4.35% 30.43% | 5 21.74% 52.17% | 4 17.39% 69.57% | 2 8.70% 78.26% | 2 8.70% 86.96% | 2 8.70% 95.65% | 1 4.35% 100.00% +system.ruby.L1Cache_Controller.MM_W.Store::total 23 +system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 618993 12.55% 12.55% | 615472 12.48% 25.04% | 618093 12.54% 37.57% | 615714 12.49% 50.06% | 613249 12.44% 62.50% | 615741 12.49% 74.99% | 616966 12.51% 87.50% | 616397 12.50% 100.00% +system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 4930625 +system.ruby.L1Cache_Controller.MM_W.Fwd_GETX | 17 16.50% 16.50% | 12 11.65% 28.16% | 18 17.48% 45.63% | 20 19.42% 65.05% | 5 4.85% 69.90% | 4 3.88% 73.79% | 14 13.59% 87.38% | 13 12.62% 100.00% +system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total 103 +system.ruby.L1Cache_Controller.MM_W.Fwd_GETS | 33 14.29% 14.29% | 29 12.55% 26.84% | 40 17.32% 44.16% | 30 12.99% 57.14% | 22 9.52% 66.67% | 26 11.26% 77.92% | 28 12.12% 90.04% | 23 9.96% 100.00% +system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total 231 +system.ruby.L1Cache_Controller.MM_W.Use_Timeout | 27913 12.46% 12.46% | 28054 12.53% 24.99% | 28075 12.54% 37.53% | 28112 12.55% 50.08% | 27887 12.45% 62.53% | 27999 12.50% 75.03% | 27936 12.47% 87.51% | 27975 12.49% 100.00% +system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total 223951 +system.ruby.L1Cache_Controller.IM.L1_Replacement | 3111214 12.42% 12.42% | 3124415 12.47% 24.89% | 3120162 12.45% 37.34% | 3163564 12.63% 49.97% | 3121043 12.46% 62.43% | 3124051 12.47% 74.89% | 3147596 12.56% 87.46% | 3142627 12.54% 100.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement::total 25054672 +system.ruby.L1Cache_Controller.IM.Ack | 130 10.89% 10.89% | 165 13.82% 24.71% | 151 12.65% 37.35% | 153 12.81% 50.17% | 141 11.81% 61.98% | 157 13.15% 75.13% | 151 12.65% 87.77% | 146 12.23% 100.00% +system.ruby.L1Cache_Controller.IM.Ack::total 1194 +system.ruby.L1Cache_Controller.IM.Exclusive_Data | 27912 12.46% 12.46% | 28052 12.53% 24.99% | 28072 12.54% 37.53% | 28109 12.55% 50.08% | 27881 12.45% 62.53% | 27998 12.50% 75.03% | 27931 12.47% 87.51% | 27974 12.49% 100.00% +system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 223929 +system.ruby.L1Cache_Controller.SM.L1_Replacement | 481 11.34% 11.34% | 642 15.13% 26.47% | 663 15.63% 42.10% | 403 9.50% 51.60% | 896 21.12% 72.73% | 30 0.71% 73.43% | 885 20.86% 94.30% | 242 5.70% 100.00% +system.ruby.L1Cache_Controller.SM.L1_Replacement::total 4242 +system.ruby.L1Cache_Controller.SM.Exclusive_Data | 1 3.85% 3.85% | 4 15.38% 19.23% | 4 15.38% 34.62% | 3 11.54% 46.15% | 6 23.08% 69.23% | 1 3.85% 73.08% | 5 19.23% 92.31% | 2 7.69% 100.00% +system.ruby.L1Cache_Controller.SM.Exclusive_Data::total 26 +system.ruby.L1Cache_Controller.OM.L1_Replacement | 22139 12.48% 12.48% | 23425 13.21% 25.69% | 21656 12.21% 37.90% | 22952 12.94% 50.84% | 22585 12.73% 63.57% | 21353 12.04% 75.61% | 22440 12.65% 88.26% | 20828 11.74% 100.00% +system.ruby.L1Cache_Controller.OM.L1_Replacement::total 177378 +system.ruby.L1Cache_Controller.OM.Ack | 235 12.65% 12.65% | 243 13.09% 25.74% | 229 12.33% 38.07% | 241 12.98% 51.05% | 246 13.25% 64.30% | 222 11.95% 76.25% | 222 11.95% 88.21% | 219 11.79% 100.00% +system.ruby.L1Cache_Controller.OM.Ack::total 1857 +system.ruby.L1Cache_Controller.OM.All_acks | 27913 12.46% 12.46% | 28056 12.53% 24.99% | 28076 12.54% 37.53% | 28112 12.55% 50.08% | 27887 12.45% 62.53% | 27999 12.50% 75.03% | 27936 12.47% 87.51% | 27976 12.49% 100.00% +system.ruby.L1Cache_Controller.OM.All_acks::total 223955 +system.ruby.L1Cache_Controller.IS.L1_Replacement | 5613300 12.56% 12.56% | 5595496 12.52% 25.07% | 5588044 12.50% 37.57% | 5561656 12.44% 50.01% | 5604041 12.54% 62.55% | 5592503 12.51% 75.06% | 5565777 12.45% 87.51% | 5583478 12.49% 100.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement::total 44704295 +system.ruby.L1Cache_Controller.IS.Data | 50182 12.49% 12.49% | 50097 12.47% 24.96% | 50442 12.56% 37.52% | 49978 12.44% 49.96% | 50201 12.50% 62.46% | 50372 12.54% 75.00% | 50365 12.54% 87.54% | 50046 12.46% 100.00% +system.ruby.L1Cache_Controller.IS.Data::total 401683 +system.ruby.L1Cache_Controller.IS.Exclusive_Data | 156 10.30% 10.30% | 218 14.39% 24.69% | 188 12.41% 37.10% | 187 12.34% 49.44% | 200 13.20% 62.64% | 196 12.94% 75.58% | 170 11.22% 86.80% | 200 13.20% 100.00% +system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 1515 +system.ruby.L1Cache_Controller.SI.Load | 11 26.19% 26.19% | 1 2.38% 28.57% | 2 4.76% 33.33% | 1 2.38% 35.71% | 1 2.38% 38.10% | 9 21.43% 59.52% | 16 38.10% 97.62% | 1 2.38% 100.00% +system.ruby.L1Cache_Controller.SI.Load::total 42 +system.ruby.L1Cache_Controller.SI.Store | 15 41.67% 41.67% | 0 0.00% 41.67% | 2 5.56% 47.22% | 1 2.78% 50.00% | 13 36.11% 86.11% | 1 2.78% 88.89% | 0 0.00% 88.89% | 4 11.11% 100.00% +system.ruby.L1Cache_Controller.SI.Store::total 36 +system.ruby.L1Cache_Controller.SI.Fwd_GETS | 394 13.59% 13.59% | 405 13.97% 27.56% | 386 13.31% 40.88% | 361 12.45% 53.33% | 355 12.25% 65.57% | 314 10.83% 76.41% | 339 11.69% 88.10% | 345 11.90% 100.00% +system.ruby.L1Cache_Controller.SI.Fwd_GETS::total 2899 +system.ruby.L1Cache_Controller.SI.Inv | 228 12.69% 12.69% | 222 12.36% 25.06% | 231 12.86% 37.92% | 216 12.03% 49.94% | 207 11.53% 61.47% | 254 14.14% 75.61% | 216 12.03% 87.64% | 222 12.36% 100.00% +system.ruby.L1Cache_Controller.SI.Inv::total 1796 +system.ruby.L1Cache_Controller.SI.Writeback_Ack | 637 12.19% 12.19% | 688 13.17% 25.36% | 631 12.08% 37.44% | 665 12.73% 50.16% | 655 12.54% 62.70% | 637 12.19% 74.89% | 639 12.23% 87.12% | 673 12.88% 100.00% +system.ruby.L1Cache_Controller.SI.Writeback_Ack::total 5225 +system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data | 49302 12.50% 12.50% | 49175 12.46% 24.96% | 49565 12.56% 37.52% | 49084 12.44% 49.96% | 49323 12.50% 62.46% | 49467 12.54% 75.00% | 49498 12.55% 87.54% | 49145 12.46% 100.00% +system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total 394559 +system.ruby.L1Cache_Controller.OI.Fwd_GETX | 0 0.00% 0.00% | 1 25.00% 25.00% | 2 50.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OI.Fwd_GETX::total 4 +system.ruby.L1Cache_Controller.OI.Fwd_GETS | 0 0.00% 0.00% | 2 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 3 50.00% 100.00% +system.ruby.L1Cache_Controller.OI.Fwd_GETS::total 6 +system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data | 250 12.48% 12.48% | 250 12.48% 24.96% | 218 10.88% 35.85% | 269 13.43% 49.28% | 269 13.43% 62.71% | 262 13.08% 75.79% | 248 12.38% 88.17% | 237 11.83% 100.00% +system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total 2003 +system.ruby.L1Cache_Controller.OI.Writeback_Nack | 18 15.79% 15.79% | 12 10.53% 26.32% | 19 16.67% 42.98% | 18 15.79% 58.77% | 13 11.40% 70.18% | 10 8.77% 78.95% | 10 8.77% 87.72% | 14 12.28% 100.00% +system.ruby.L1Cache_Controller.OI.Writeback_Nack::total 114 +system.ruby.L1Cache_Controller.MI.Load | 9 36.00% 36.00% | 1 4.00% 40.00% | 1 4.00% 44.00% | 1 4.00% 48.00% | 11 44.00% 92.00% | 0 0.00% 92.00% | 1 4.00% 96.00% | 1 4.00% 100.00% +system.ruby.L1Cache_Controller.MI.Load::total 25 +system.ruby.L1Cache_Controller.MI.Store | 10 71.43% 71.43% | 0 0.00% 71.43% | 1 7.14% 78.57% | 0 0.00% 78.57% | 0 0.00% 78.57% | 2 14.29% 92.86% | 1 7.14% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.MI.Store::total 14 +system.ruby.L1Cache_Controller.MI.Fwd_GETX | 145 13.48% 13.48% | 134 12.45% 25.93% | 134 12.45% 38.38% | 136 12.64% 51.02% | 142 13.20% 64.22% | 123 11.43% 75.65% | 151 14.03% 89.68% | 111 10.32% 100.00% +system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 1076 +system.ruby.L1Cache_Controller.MI.Fwd_GETS | 247 12.34% 12.34% | 250 12.49% 24.84% | 220 10.99% 35.83% | 269 13.44% 49.28% | 269 13.44% 62.72% | 262 13.09% 75.81% | 249 12.44% 88.26% | 235 11.74% 100.00% +system.ruby.L1Cache_Controller.MI.Fwd_GETS::total 2001 +system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data | 27623 12.44% 12.44% | 27836 12.54% 24.98% | 27863 12.55% 37.53% | 27840 12.54% 50.07% | 27638 12.45% 62.52% | 27766 12.51% 75.02% | 27666 12.46% 87.48% | 27786 12.52% 100.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total 222018 +system.ruby.L1Cache_Controller.II.Store | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.II.Store::total 1 +system.ruby.L1Cache_Controller.II.Writeback_Ack | 0 0.00% 0.00% | 2 28.57% 28.57% | 1 14.29% 42.86% | 1 14.29% 57.14% | 1 14.29% 71.43% | 1 14.29% 85.71% | 0 0.00% 85.71% | 1 14.29% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Ack::total 7 +system.ruby.L1Cache_Controller.II.Writeback_Ack_Data | 145 13.45% 13.45% | 135 12.52% 25.97% | 136 12.62% 38.59% | 136 12.62% 51.21% | 141 13.08% 64.29% | 123 11.41% 75.70% | 151 14.01% 89.70% | 111 10.30% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Ack_Data::total 1078 +system.ruby.L1Cache_Controller.II.Writeback_Nack | 228 12.73% 12.73% | 220 12.28% 25.01% | 230 12.84% 37.86% | 215 12.00% 49.86% | 207 11.56% 61.42% | 253 14.13% 75.54% | 217 12.12% 87.66% | 221 12.34% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Nack::total 1791 +system.ruby.L2Cache_Controller.L1_GETS 505918 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 279265 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTO 147 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 260754 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTS_only 476678 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTS 26071 0.00% 0.00% +system.ruby.L2Cache_Controller.All_Acks 222022 0.00% 0.00% +system.ruby.L2Cache_Controller.Data 615806 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_WBCLEANDATA 394559 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 224021 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_Ack 221995 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 407986 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 225463 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 692184 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 393786 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 218821 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_GETS 3251 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_GETX 1863 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 391321 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_PUTS 3238 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_GETS 2251 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_GETX 1189 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_PUTO 1 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_PUTX 223094 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_PUTS 1786 0.00% 0.00% system.ruby.L2Cache_Controller.ILOX.L1_GETS 3 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOX.L1_PUTO 110 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOX.L1_PUTX 113 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOX.L1_PUTS 1 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_GETS 4 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_GETX 5 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_PUTO 7 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_PUTX 1816 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_PUTS_only 113 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOX.L1_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOX.L1_PUTO 115 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOX.L1_PUTX 114 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_GETS 3 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_GETX 3 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_PUTO 4 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_PUTX 1886 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_PUTS_only 119 0.00% 0.00% system.ruby.L2Cache_Controller.ILOSX.L1_PUTS 5 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETS 2518 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETX 1376 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 392259 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L1_GETS 2609 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L1_GETX 1332 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L2_Replacement 390668 0.00% 0.00% system.ruby.L2Cache_Controller.OLSX.L1_GETS 7 0.00% 0.00% system.ruby.L2Cache_Controller.OLSX.L1_GETX 4 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L1_PUTS_only 1718 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L1_PUTS_only 1779 0.00% 0.00% system.ruby.L2Cache_Controller.OLSX.L1_PUTS 11 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L2_Replacement 100 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_GETS 16 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_GETX 10 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 3195 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_PUTS 17 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L2_Replacement 2494 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1276 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 682 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L2_Replacement 105 0.00% 0.00% +system.ruby.L2Cache_Controller.SLS.L1_GETS 19 0.00% 0.00% +system.ruby.L2Cache_Controller.SLS.L1_GETX 8 0.00% 0.00% +system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 3291 0.00% 0.00% +system.ruby.L2Cache_Controller.SLS.L1_PUTS 27 0.00% 0.00% +system.ruby.L2Cache_Controller.SLS.L2_Replacement 2548 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1271 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 737 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_PUTX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_PUTS 2 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 221694 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_GETS 34 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_PUTX 1526 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_PUTS 14 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_WBDIRTYDATA 110 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.Unblock 113 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_GETS 27 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_GETX 29 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_PUTX 55 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS_only 4213 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS 25 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_WBDIRTYDATA 1822 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.Unblock 6 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSW.L1_PUTS 46 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSW.Unblock 17 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSW.L2_Replacement 170 0.00% 0.00% -system.ruby.L2Cache_Controller.ILSW.L1_GETS 85 0.00% 0.00% -system.ruby.L2Cache_Controller.ILSW.L1_GETX 50 0.00% 0.00% -system.ruby.L2Cache_Controller.ILSW.L1_PUTS 11624 0.00% 0.00% -system.ruby.L2Cache_Controller.ILSW.L1_WBCLEANDATA 3181 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_GETS 16711 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_GETX 8904 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 392962 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.L1_GETS 84 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.L1_GETX 85 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.Unblock 3195 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.L2_Replacement 21848 0.00% 0.00% -system.ruby.L2Cache_Controller.OXW.L1_GETS 33 0.00% 0.00% -system.ruby.L2Cache_Controller.OXW.L1_GETX 7 0.00% 0.00% -system.ruby.L2Cache_Controller.OXW.Unblock 1718 0.00% 0.00% -system.ruby.L2Cache_Controller.OXW.L2_Replacement 8808 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXW.L1_PUTS 42 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_PUTS 3 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 221899 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_GETS 44 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_GETX 13 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_PUTO 21 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_PUTX 1591 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_WBDIRTYDATA 115 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.Unblock 119 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_GETS 31 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_GETX 20 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_PUTX 49 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS_only 4911 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS 39 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_WBDIRTYDATA 1888 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.Unblock 7 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSW.L1_PUTS 64 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSW.Unblock 27 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSW.L2_Replacement 207 0.00% 0.00% +system.ruby.L2Cache_Controller.ILSW.L1_GETS 123 0.00% 0.00% +system.ruby.L2Cache_Controller.ILSW.L1_GETX 47 0.00% 0.00% +system.ruby.L2Cache_Controller.ILSW.L1_PUTS 12315 0.00% 0.00% +system.ruby.L2Cache_Controller.ILSW.L1_WBCLEANDATA 3238 0.00% 0.00% +system.ruby.L2Cache_Controller.IW.L1_GETS 16878 0.00% 0.00% +system.ruby.L2Cache_Controller.IW.L1_GETX 8637 0.00% 0.00% +system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 391321 0.00% 0.00% +system.ruby.L2Cache_Controller.SW.L1_GETS 72 0.00% 0.00% +system.ruby.L2Cache_Controller.SW.L1_GETX 87 0.00% 0.00% +system.ruby.L2Cache_Controller.SW.Unblock 3291 0.00% 0.00% +system.ruby.L2Cache_Controller.SW.L2_Replacement 23701 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.L1_GETS 55 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.L1_GETX 9 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.Unblock 1779 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.L2_Replacement 9622 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXW.L1_PUTS_only 6 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXW.L1_PUTS 36 0.00% 0.00% system.ruby.L2Cache_Controller.OLSXW.Unblock 11 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXW.L2_Replacement 80 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_GETS 6015 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_GETX 3112 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_PUTX 1468 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_PUTS 18 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 221828 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.Unblock 1092 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.L1_GETS 129 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.L1_GETX 78 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.L1_PUTS_only 28060 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.L1_PUTS 119 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.Unblock 3183 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOX.L1_PUTO 16 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOX.L1_PUTS_only 33 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXW.L2_Replacement 100 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_GETS 6543 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_GETX 3771 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_PUTX 1449 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_PUTS 29 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 222018 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.Unblock 1076 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLS.L1_GETS 210 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLS.L1_GETX 110 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLS.L1_PUTS_only 28110 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLS.L1_PUTS 313 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLS.Unblock 3251 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOX.L1_PUTX 15 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOX.L1_PUTS_only 48 0.00% 0.00% system.ruby.L2Cache_Controller.IFLOX.Unblock 3 0.00% 0.00% system.ruby.L2Cache_Controller.IFLOX.Exclusive_Unblock 4 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_GETS 212 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_GETX 122 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_PUTX 32391 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_PUTS 93 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.Unblock 1937 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.Exclusive_Unblock 1429 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOSX.L1_PUTX 32 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOSX.L1_PUTS_only 3 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOSX.Unblock 4 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLXO.L1_PUTX 56 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLXO.L1_PUTS_only 30 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLXO.Exclusive_Unblock 5 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.L1_GETS 47271 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.L1_GETX 26146 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.L1_PUTS 7681 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Data 395426 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Unblock 395418 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.L1_GETS 20848 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.L1_GETX 11573 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.Data 219939 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.L1_GETS 323 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.L1_GETX 84 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.L1_PUTS_only 30451 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.Data 1869 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_GETS 5322 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_GETX 2911 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_PUTX 85 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_PUTS_only 16785 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_PUTS 1 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.All_Acks 221808 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 221802 0.00% 0.00% -system.ruby.L2Cache_Controller.MM.L1_GETS 13 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_GETS 222 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_GETX 77 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_PUTO 6 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_PUTX 32390 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_PUTS 148 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.Unblock 2007 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.Exclusive_Unblock 1434 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOSX.L1_PUTX 21 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOSX.L1_PUTS_only 2 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOSX.Unblock 3 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLXO.L1_PUTX 30 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLXO.L1_PUTS_only 20 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLXO.Exclusive_Unblock 3 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.L1_GETS 49192 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.L1_GETX 27678 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.L1_PUTS 7782 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.Data 393784 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.Unblock 393777 0.00% 0.00% +system.ruby.L2Cache_Controller.IGM.L1_GETS 22557 0.00% 0.00% +system.ruby.L2Cache_Controller.IGM.L1_GETX 11373 0.00% 0.00% +system.ruby.L2Cache_Controller.IGM.Data 220151 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMLS.L1_GETS 194 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMLS.L1_GETX 129 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMLS.L1_PUTS_only 29583 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMLS.L1_PUTS 113 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMLS.Data 1871 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_GETS 5723 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_GETX 2924 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_PUTX 114 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_PUTS_only 17056 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_PUTS 123 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.All_Acks 222022 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 222014 0.00% 0.00% +system.ruby.L2Cache_Controller.MM.L1_GETS 25 0.00% 0.00% system.ruby.L2Cache_Controller.MM.L1_GETX 3 0.00% 0.00% -system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 682 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 89 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 48 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_PUTS 47 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.Unblock 2518 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 30996 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.L1_GETS 31 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.L1_GETX 20 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 1276 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.L2_Replacement 11661 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXS.L1_PUTS_only 10 0.00% 0.00% +system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 737 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 75 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 44 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_PUTS 24 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.Unblock 2609 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 30888 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.L1_GETS 27 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.L1_GETX 19 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 1271 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.L2_Replacement 12369 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXS.L1_PUTS_only 20 0.00% 0.00% system.ruby.L2Cache_Controller.OLSXS.Unblock 7 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSS.L1_PUTS_only 51 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSS.Unblock 16 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSS.L2_Replacement 128 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.L1_GETS 750 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.L1_GETX 371 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.Writeback_Ack 221684 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSI.L1_PUTS_only 367 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSI.Writeback_Ack 100 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXS.L2_Replacement 2 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSS.L1_PUTS_only 83 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSS.Unblock 19 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSS.L2_Replacement 75 0.00% 0.00% +system.ruby.L2Cache_Controller.MI.L1_GETS 747 0.00% 0.00% +system.ruby.L2Cache_Controller.MI.L1_GETX 366 0.00% 0.00% +system.ruby.L2Cache_Controller.MI.Writeback_Ack 221890 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSI.L1_PUTS_only 329 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSI.L1_PUTS 15 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSI.Writeback_Ack 105 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index ef23dc4f3..c1a93ea1f 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.006094 # Number of seconds simulated -sim_ticks 6094458 # Number of ticks simulated -final_tick 6094458 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.006099 # Number of seconds simulated +sim_ticks 6099346 # Number of ticks simulated +final_tick 6099346 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 58915 # Simulator tick rate (ticks/s) -host_mem_usage 544772 # Number of bytes of host memory used -host_seconds 103.45 # Real time elapsed on the host +host_tick_rate 86189 # Simulator tick rate (ticks/s) +host_mem_usage 466764 # Number of bytes of host memory used +host_seconds 70.77 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39764032 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 39764032 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 19451264 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 19451264 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 621313 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 621313 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 303926 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 303926 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 6524621550 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 6524621550 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 3191631479 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 3191631479 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 9716253029 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 9716253029 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 621333 # Number of read requests accepted -system.mem_ctrls.writeReqs 303926 # Number of write requests accepted -system.mem_ctrls.readBursts 621333 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 303926 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 39132480 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 632192 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 19235456 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 39765312 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 19451264 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 9878 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 3352 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39765376 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 39765376 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 19455168 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 19455168 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 621334 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 621334 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 303987 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 303987 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 6519613086 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 6519613086 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 3189713782 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 3189713782 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 9709326869 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 9709326869 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 621353 # Number of read requests accepted +system.mem_ctrls.writeReqs 303987 # Number of write requests accepted +system.mem_ctrls.readBursts 621353 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 303987 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 39135936 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 630016 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 19233536 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 39766592 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 19455168 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 9844 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 3445 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 76884 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 76513 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 76369 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 76611 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 76482 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 76084 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 76357 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 76145 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 76431 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 76127 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 76543 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 76671 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 76481 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 76370 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 76529 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 76347 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts @@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 38021 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 37717 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 37434 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 37597 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 37617 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 37600 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 37306 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 37262 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 37966 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 37270 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 37672 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 37851 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 37319 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 37564 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 37461 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 37421 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts @@ -68,54 +68,54 @@ system.mem_ctrls.perBankWrBursts::13 0 # Pe system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 4 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 6094364 # Total gap between requests +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 6099263 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 621333 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 621353 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 303926 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 9143 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 12614 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 16926 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 20366 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 24924 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 30287 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 35331 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 37577 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 36100 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 32063 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 28594 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 26472 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 25440 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 24994 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 24297 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 23452 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 22114 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 20959 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 20085 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 19573 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 19246 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 18919 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 18483 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 17384 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 15463 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 12615 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 9072 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 5403 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 2490 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 852 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 194 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 23 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 303987 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 9205 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 12803 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 17020 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 20322 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 24896 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 30274 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 35013 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 37548 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 36271 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 32061 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 28288 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 26271 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 25434 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 24827 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 24316 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 23513 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 22261 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 21004 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 20162 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 19561 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 19244 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 18852 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 18407 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 17373 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 15506 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 12631 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 9097 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 5499 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 2677 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 929 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 214 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 30 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -131,1005 +131,1012 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 24 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 80 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 310 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 806 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 1525 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 2881 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 4887 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 7333 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 10281 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 32 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 89 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 308 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 808 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 1648 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 2932 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 4835 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 7227 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 10026 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 13120 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 16621 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 19689 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 17477 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 18689 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 19714 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 20349 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 21128 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 21781 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 12862 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 11204 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 9770 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 8766 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 7847 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 6903 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 5981 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 5331 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 4754 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 4259 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 3842 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 3387 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 3113 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 2634 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 2352 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 2047 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 1787 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 1566 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 1320 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 1180 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 999 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 856 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 521 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 288 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 134 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 81 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 33 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 16528 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 20274 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 17895 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 19060 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 20080 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 20633 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 21139 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 21648 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 12617 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 11019 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 9715 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 8816 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 7624 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 6699 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 5864 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 5356 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 4652 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 4249 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 3709 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 3432 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 3063 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 2763 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 2448 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 2048 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 1790 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 1460 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 1286 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 1101 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 924 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 776 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 451 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 197 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 92 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 50 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 23 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::60 17 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 13 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 10 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 252796 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 230.887704 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 185.257710 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 157.538914 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 45820 18.13% 18.13% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 103869 41.09% 59.21% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 56524 22.36% 81.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 26591 10.52% 92.09% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 12053 4.77% 96.86% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 5022 1.99% 98.85% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1879 0.74% 99.59% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 667 0.26% 99.85% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 371 0.15% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 252796 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 18205 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 33.585663 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 30.328772 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 11.770408 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-7 955 5.25% 5.25% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::8-15 90 0.49% 5.74% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-23 53 0.29% 6.03% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::24-31 5978 32.84% 38.87% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::32-39 8627 47.39% 86.26% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::40-47 1420 7.80% 94.06% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::48-55 150 0.82% 94.88% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::56-63 324 1.78% 96.66% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::64-71 363 1.99% 98.65% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::72-79 136 0.75% 99.40% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-87 41 0.23% 99.63% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::88-95 36 0.20% 99.82% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::96-103 14 0.08% 99.90% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::104-111 13 0.07% 99.97% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::112-119 3 0.02% 99.99% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::120-127 1 0.01% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.wrQLenPdf::61 3 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 253833 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 229.950243 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 184.650902 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 156.806564 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 46155 18.18% 18.18% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 104846 41.31% 59.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 56523 22.27% 81.76% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 26583 10.47% 92.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 12002 4.73% 96.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 4847 1.91% 98.87% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1822 0.72% 99.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 638 0.25% 99.84% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 417 0.16% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 253833 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 18189 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 33.618066 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 30.320455 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 11.847126 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-7 973 5.35% 5.35% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::8-15 91 0.50% 5.85% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-23 51 0.28% 6.13% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::24-31 5842 32.12% 38.25% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::32-39 8693 47.79% 86.04% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::40-47 1435 7.89% 93.93% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::48-55 149 0.82% 94.75% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::56-63 362 1.99% 96.74% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::64-71 347 1.91% 98.65% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::72-79 138 0.76% 99.41% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::80-87 42 0.23% 99.64% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::88-95 22 0.12% 99.76% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::96-103 20 0.11% 99.87% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::104-111 15 0.08% 99.95% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::112-119 8 0.04% 99.99% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::152-159 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 18205 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 18205 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.509420 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.442130 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.668297 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 15874 87.20% 87.20% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 492 2.70% 89.90% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 406 2.23% 92.13% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 320 1.76% 93.89% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 297 1.63% 95.52% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 221 1.21% 96.73% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 199 1.09% 97.82% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 123 0.68% 98.50% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 96 0.53% 99.03% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 59 0.32% 99.35% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 35 0.19% 99.54% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 33 0.18% 99.73% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 22 0.12% 99.85% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 13 0.07% 99.92% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::30 9 0.05% 99.97% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::31 5 0.03% 99.99% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::32 1 0.01% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 18205 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 65625909 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 77243364 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3057225 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 107.33 # Average queueing delay per DRAM burst +system.mem_ctrls.rdPerTurnAround::total 18189 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 18189 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.522294 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.453355 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.687354 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 15819 86.97% 86.97% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 514 2.83% 89.80% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 386 2.12% 91.92% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 307 1.69% 93.61% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 291 1.60% 95.21% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 250 1.37% 96.58% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 208 1.14% 97.72% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 134 0.74% 98.46% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 105 0.58% 99.04% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 62 0.34% 99.38% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 47 0.26% 99.64% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 24 0.13% 99.77% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::28 18 0.10% 99.87% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::29 10 0.05% 99.92% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::30 5 0.03% 99.95% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::31 4 0.02% 99.97% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::32 3 0.02% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::33 1 0.01% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::36 1 0.01% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 18189 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 65720985 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 77339466 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3057495 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 107.47 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 126.33 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 6420.99 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 3156.22 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 6524.83 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 3191.63 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 126.47 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 6416.42 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 3153.38 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 6519.81 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 3189.71 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 74.82 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 50.16 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 24.66 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 15.57 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 32.13 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 364864 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 294336 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 59.67 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 97.92 # Row buffer hit rate for writes +system.mem_ctrls.busUtil 74.76 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 50.13 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 24.64 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 15.58 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 32.06 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 364001 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 294185 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 59.53 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 97.88 # Row buffer hit rate for writes system.mem_ctrls.avgGap 6.59 # Average gap between requests -system.mem_ctrls.pageHitRate 72.28 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 1909232640 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 1060684800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 7623545280 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 3113116416 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 397693920 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 4149780804 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 13210200 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 18267264060 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 3000.068987 # Core power per rank (mW) +system.mem_ctrls.pageHitRate 72.17 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1918206360 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 1065670200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7628499840 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 3114474624 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 398202480 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 4155129684 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 13188000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 18293371188 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 3000.521294 # Core power per rank (mW) system.mem_ctrls_0.memoryStateTime::IDLE 21 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 203320 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 203580 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 5885621 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 5893144 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 397693920 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 131582448 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3537915600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 4067191968 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 667.968484 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 5885592 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 203320 # Time in different power states +system.mem_ctrls_1.refreshEnergy 398202480 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 131750712 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3542439600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 4072392792 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.968488 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 5893118 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 203580 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 1 # Clock period in ticks -system.cpu0.num_reads 99235 # number of read accesses completed -system.cpu0.num_writes 55276 # number of write accesses completed -system.cpu1.num_reads 99504 # number of read accesses completed -system.cpu1.num_writes 55438 # number of write accesses completed -system.cpu2.num_reads 99803 # number of read accesses completed -system.cpu2.num_writes 55490 # number of write accesses completed -system.cpu3.num_reads 99664 # number of read accesses completed -system.cpu3.num_writes 55571 # number of write accesses completed -system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 55141 # number of write accesses completed -system.cpu5.num_reads 98993 # number of read accesses completed -system.cpu5.num_writes 55521 # number of write accesses completed -system.cpu6.num_reads 98704 # number of read accesses completed -system.cpu6.num_writes 55280 # number of write accesses completed -system.cpu7.num_reads 99571 # number of read accesses completed -system.cpu7.num_writes 55135 # number of write accesses completed +system.cpu0.num_reads 99731 # number of read accesses completed +system.cpu0.num_writes 55103 # number of write accesses completed +system.cpu1.num_reads 99468 # number of read accesses completed +system.cpu1.num_writes 55228 # number of write accesses completed +system.cpu2.num_reads 100000 # number of read accesses completed +system.cpu2.num_writes 55518 # number of write accesses completed +system.cpu3.num_reads 99696 # number of read accesses completed +system.cpu3.num_writes 55953 # number of write accesses completed +system.cpu4.num_reads 98851 # number of read accesses completed +system.cpu4.num_writes 55227 # number of write accesses completed +system.cpu5.num_reads 98859 # number of read accesses completed +system.cpu5.num_writes 55313 # number of write accesses completed +system.cpu6.num_reads 99329 # number of read accesses completed +system.cpu6.num_writes 55461 # number of write accesses completed +system.cpu7.num_reads 99244 # number of read accesses completed +system.cpu7.num_writes 55110 # number of write accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 626635 -system.ruby.outstanding_req_hist::mean 15.998458 -system.ruby.outstanding_req_hist::gmean 15.997194 -system.ruby.outstanding_req_hist::stdev 0.125848 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 22 0.00% 0.02% | 626509 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 626635 +system.ruby.outstanding_req_hist::samples 626716 +system.ruby.outstanding_req_hist::mean 15.998460 +system.ruby.outstanding_req_hist::gmean 15.997196 +system.ruby.outstanding_req_hist::stdev 0.125834 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 21 0.00% 0.02% | 626591 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 626716 system.ruby.latency_hist::bucket_size 512 system.ruby.latency_hist::max_bucket 5119 -system.ruby.latency_hist::samples 626507 -system.ruby.latency_hist::mean 1244.945150 -system.ruby.latency_hist::gmean 1011.314987 -system.ruby.latency_hist::stdev 668.400305 -system.ruby.latency_hist | 108851 17.37% 17.37% | 146909 23.45% 40.82% | 142986 22.82% 63.65% | 142296 22.71% 86.36% | 76007 12.13% 98.49% | 9399 1.50% 99.99% | 59 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 626507 +system.ruby.latency_hist::samples 626588 +system.ruby.latency_hist::mean 1245.772554 +system.ruby.latency_hist::gmean 1012.769806 +system.ruby.latency_hist::stdev 668.694211 +system.ruby.latency_hist | 107920 17.22% 17.22% | 148908 23.76% 40.99% | 141299 22.55% 63.54% | 142667 22.77% 86.31% | 76272 12.17% 98.48% | 9413 1.50% 99.98% | 107 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 626588 system.ruby.hit_latency_hist::bucket_size 512 system.ruby.hit_latency_hist::max_bucket 5119 -system.ruby.hit_latency_hist::samples 2863 -system.ruby.hit_latency_hist::mean 1132.518687 -system.ruby.hit_latency_hist::gmean 620.916073 -system.ruby.hit_latency_hist::stdev 708.964831 -system.ruby.hit_latency_hist | 672 23.47% 23.47% | 629 21.97% 45.44% | 656 22.91% 68.35% | 578 20.19% 88.54% | 301 10.51% 99.06% | 27 0.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 2863 +system.ruby.hit_latency_hist::samples 2961 +system.ruby.hit_latency_hist::mean 1105.733874 +system.ruby.hit_latency_hist::gmean 581.668757 +system.ruby.hit_latency_hist::stdev 707.726656 +system.ruby.hit_latency_hist | 739 24.96% 24.96% | 664 22.42% 47.38% | 645 21.78% 69.17% | 594 20.06% 89.23% | 287 9.69% 98.92% | 32 1.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 2961 system.ruby.miss_latency_hist::bucket_size 512 system.ruby.miss_latency_hist::max_bucket 5119 -system.ruby.miss_latency_hist::samples 623644 -system.ruby.miss_latency_hist::mean 1245.461273 -system.ruby.miss_latency_hist::gmean 1013.582286 -system.ruby.miss_latency_hist::stdev 668.165388 -system.ruby.miss_latency_hist | 108179 17.35% 17.35% | 146280 23.46% 40.80% | 142330 22.82% 63.62% | 141718 22.72% 86.35% | 75706 12.14% 98.49% | 9372 1.50% 99.99% | 59 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 623644 -system.ruby.L1Cache.incomplete_times 2147 -system.ruby.Directory.incomplete_times 621494 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 21 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 78427 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78448 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 623627 +system.ruby.miss_latency_hist::mean 1246.437462 +system.ruby.miss_latency_hist::gmean 1015.439930 +system.ruby.miss_latency_hist::stdev 668.434071 +system.ruby.miss_latency_hist | 107181 17.19% 17.19% | 148244 23.77% 40.96% | 140654 22.55% 63.51% | 142073 22.78% 86.29% | 75985 12.18% 98.48% | 9381 1.50% 99.98% | 107 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 623627 +system.ruby.L1Cache.incomplete_times 2150 +system.ruby.Directory.incomplete_times 621474 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 20 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 78435 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78455 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl0.fully_busy_cycles 9 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl1.L1Dcache.demand_hits 20 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 78366 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78386 # Number of cache demand accesses +system.ruby.l1_cntrl0.fully_busy_cycles 12 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl1.L1Dcache.demand_hits 26 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 78293 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78319 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl1.fully_busy_cycles 7 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl2.L1Dcache.demand_hits 17 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 78090 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78107 # Number of cache demand accesses +system.ruby.l1_cntrl1.fully_busy_cycles 8 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl2.L1Dcache.demand_hits 21 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Dcache.demand_misses 78389 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78410 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl2.fully_busy_cycles 13 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl3.L1Dcache.demand_hits 19 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 78331 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78350 # Number of cache demand accesses +system.ruby.l1_cntrl2.fully_busy_cycles 6 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl3.L1Dcache.demand_hits 20 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 78553 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78573 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl3.fully_busy_cycles 5 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl3.fully_busy_cycles 6 # cycles for which number of transistions == max transitions system.ruby.l1_cntrl4.L1Dcache.demand_hits 24 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Dcache.demand_misses 78332 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78356 # Number of cache demand accesses +system.ruby.l1_cntrl4.L1Dcache.demand_misses 78168 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78192 # Number of cache demand accesses system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl4.fully_busy_cycles 7 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl5.L1Dcache.demand_hits 16 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Dcache.demand_misses 78475 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78491 # Number of cache demand accesses +system.ruby.l1_cntrl4.fully_busy_cycles 12 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl5.L1Dcache.demand_hits 31 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Dcache.demand_misses 78418 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78449 # Number of cache demand accesses system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl5.fully_busy_cycles 11 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl6.L1Dcache.demand_hits 22 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Dcache.demand_misses 77984 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78006 # Number of cache demand accesses +system.ruby.l1_cntrl5.fully_busy_cycles 8 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl6.L1Dcache.demand_hits 32 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Dcache.demand_misses 78003 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78035 # Number of cache demand accesses system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl6.fully_busy_cycles 11 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl7.L1Dcache.demand_hits 26 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Dcache.demand_misses 78363 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78389 # Number of cache demand accesses +system.ruby.l1_cntrl6.fully_busy_cycles 7 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl7.L1Dcache.demand_hits 24 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Dcache.demand_misses 78156 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78180 # Number of cache demand accesses system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl7.fully_busy_cycles 8 # cycles for which number of transistions == max transitions -system.ruby.l2_cntrl0.L2cache.demand_hits 1668 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 624699 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 626367 # Number of cache demand accesses +system.ruby.l1_cntrl7.fully_busy_cycles 7 # cycles for which number of transistions == max transitions +system.ruby.l2_cntrl0.L2cache.demand_hits 1651 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 624764 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 626415 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers00.percent_links_utilized 11.231610 -system.ruby.network.routers00.msg_count.Request_Control::1 78427 -system.ruby.network.routers00.msg_count.Response_Data::4 81678 -system.ruby.network.routers00.msg_count.ResponseL2hit_Data::4 213 -system.ruby.network.routers00.msg_count.ResponseLocal_Data::4 169 -system.ruby.network.routers00.msg_count.Response_Control::4 118 -system.ruby.network.routers00.msg_count.Writeback_Data::4 107515 -system.ruby.network.routers00.msg_count.Broadcast_Control::1 626367 -system.ruby.network.routers00.msg_count.Persistent_Control::3 326936 -system.ruby.network.routers00.msg_bytes.Request_Control::1 627416 -system.ruby.network.routers00.msg_bytes.Response_Data::4 5880816 -system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::4 15336 -system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::4 12168 -system.ruby.network.routers00.msg_bytes.Response_Control::4 944 -system.ruby.network.routers00.msg_bytes.Writeback_Data::4 7741080 -system.ruby.network.routers00.msg_bytes.Broadcast_Control::1 5010936 -system.ruby.network.routers00.msg_bytes.Persistent_Control::3 2615488 -system.ruby.network.routers01.percent_links_utilized 11.222233 -system.ruby.network.routers01.msg_count.Request_Control::1 78366 -system.ruby.network.routers01.msg_count.Response_Data::4 81679 -system.ruby.network.routers01.msg_count.ResponseL2hit_Data::4 220 -system.ruby.network.routers01.msg_count.ResponseLocal_Data::4 167 -system.ruby.network.routers01.msg_count.Response_Control::4 116 -system.ruby.network.routers01.msg_count.Writeback_Data::4 107261 -system.ruby.network.routers01.msg_count.Broadcast_Control::1 626367 -system.ruby.network.routers01.msg_count.Persistent_Control::3 326945 -system.ruby.network.routers01.msg_bytes.Request_Control::1 626928 -system.ruby.network.routers01.msg_bytes.Response_Data::4 5880888 -system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::4 15840 -system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::4 12024 -system.ruby.network.routers01.msg_bytes.Response_Control::4 928 -system.ruby.network.routers01.msg_bytes.Writeback_Data::4 7722792 -system.ruby.network.routers01.msg_bytes.Broadcast_Control::1 5010936 -system.ruby.network.routers01.msg_bytes.Persistent_Control::3 2615560 -system.ruby.network.routers02.percent_links_utilized 11.193288 -system.ruby.network.routers02.msg_count.Request_Control::1 78090 -system.ruby.network.routers02.msg_count.Response_Data::4 81339 -system.ruby.network.routers02.msg_count.ResponseL2hit_Data::4 226 -system.ruby.network.routers02.msg_count.ResponseLocal_Data::4 199 -system.ruby.network.routers02.msg_count.Response_Control::4 143 -system.ruby.network.routers02.msg_count.Writeback_Data::4 106812 -system.ruby.network.routers02.msg_count.Broadcast_Control::1 626367 -system.ruby.network.routers02.msg_count.Persistent_Control::3 326897 -system.ruby.network.routers02.msg_bytes.Request_Control::1 624720 -system.ruby.network.routers02.msg_bytes.Response_Data::4 5856408 -system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::4 16272 -system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::4 14328 -system.ruby.network.routers02.msg_bytes.Response_Control::4 1144 -system.ruby.network.routers02.msg_bytes.Writeback_Data::4 7690464 -system.ruby.network.routers02.msg_bytes.Broadcast_Control::1 5010936 -system.ruby.network.routers02.msg_bytes.Persistent_Control::3 2615176 -system.ruby.network.routers03.percent_links_utilized 11.227565 -system.ruby.network.routers03.msg_count.Request_Control::1 78331 -system.ruby.network.routers03.msg_count.Response_Data::4 81572 -system.ruby.network.routers03.msg_count.ResponseL2hit_Data::4 242 -system.ruby.network.routers03.msg_count.ResponseLocal_Data::4 184 -system.ruby.network.routers03.msg_count.Response_Control::4 136 -system.ruby.network.routers03.msg_count.Writeback_Data::4 107465 -system.ruby.network.routers03.msg_count.Broadcast_Control::1 626367 -system.ruby.network.routers03.msg_count.Persistent_Control::3 327036 -system.ruby.network.routers03.msg_bytes.Request_Control::1 626648 -system.ruby.network.routers03.msg_bytes.Response_Data::4 5873184 -system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::4 17424 -system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::4 13248 -system.ruby.network.routers03.msg_bytes.Response_Control::4 1088 -system.ruby.network.routers03.msg_bytes.Writeback_Data::4 7737480 -system.ruby.network.routers03.msg_bytes.Broadcast_Control::1 5010936 -system.ruby.network.routers03.msg_bytes.Persistent_Control::3 2616288 -system.ruby.network.routers04.percent_links_utilized 11.207941 -system.ruby.network.routers04.msg_count.Request_Control::1 78332 -system.ruby.network.routers04.msg_count.Response_Data::4 81536 -system.ruby.network.routers04.msg_count.ResponseL2hit_Data::4 225 -system.ruby.network.routers04.msg_count.ResponseLocal_Data::4 192 -system.ruby.network.routers04.msg_count.Response_Control::4 134 -system.ruby.network.routers04.msg_count.Writeback_Data::4 107022 -system.ruby.network.routers04.msg_count.Writeback_Control::4 1 -system.ruby.network.routers04.msg_count.Broadcast_Control::1 626367 -system.ruby.network.routers04.msg_count.Persistent_Control::3 326647 -system.ruby.network.routers04.msg_bytes.Request_Control::1 626656 -system.ruby.network.routers04.msg_bytes.Response_Data::4 5870592 -system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::4 16200 -system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::4 13824 -system.ruby.network.routers04.msg_bytes.Response_Control::4 1072 -system.ruby.network.routers04.msg_bytes.Writeback_Data::4 7705584 -system.ruby.network.routers04.msg_bytes.Writeback_Control::4 8 -system.ruby.network.routers04.msg_bytes.Broadcast_Control::1 5010936 -system.ruby.network.routers04.msg_bytes.Persistent_Control::3 2613176 -system.ruby.network.routers05.percent_links_utilized 11.239334 -system.ruby.network.routers05.msg_count.Request_Control::1 78475 -system.ruby.network.routers05.msg_count.Response_Data::4 81608 -system.ruby.network.routers05.msg_count.ResponseL2hit_Data::4 226 -system.ruby.network.routers05.msg_count.ResponseLocal_Data::4 173 -system.ruby.network.routers05.msg_count.Response_Control::4 127 -system.ruby.network.routers05.msg_count.Writeback_Data::4 107742 -system.ruby.network.routers05.msg_count.Broadcast_Control::1 626368 -system.ruby.network.routers05.msg_count.Persistent_Control::3 327195 -system.ruby.network.routers05.msg_bytes.Request_Control::1 627800 -system.ruby.network.routers05.msg_bytes.Response_Data::4 5875776 -system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::4 16272 -system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::4 12456 -system.ruby.network.routers05.msg_bytes.Response_Control::4 1016 -system.ruby.network.routers05.msg_bytes.Writeback_Data::4 7757424 -system.ruby.network.routers05.msg_bytes.Broadcast_Control::1 5010944 -system.ruby.network.routers05.msg_bytes.Persistent_Control::3 2617560 -system.ruby.network.routers06.percent_links_utilized 11.179157 -system.ruby.network.routers06.msg_count.Request_Control::1 77984 -system.ruby.network.routers06.msg_count.Response_Data::4 81120 -system.ruby.network.routers06.msg_count.ResponseL2hit_Data::4 212 -system.ruby.network.routers06.msg_count.ResponseLocal_Data::4 173 -system.ruby.network.routers06.msg_count.Response_Control::4 140 -system.ruby.network.routers06.msg_count.Writeback_Data::4 106745 -system.ruby.network.routers06.msg_count.Broadcast_Control::1 626367 -system.ruby.network.routers06.msg_count.Persistent_Control::3 326495 -system.ruby.network.routers06.msg_bytes.Request_Control::1 623872 -system.ruby.network.routers06.msg_bytes.Response_Data::4 5840640 -system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::4 15264 -system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::4 12456 -system.ruby.network.routers06.msg_bytes.Response_Control::4 1120 -system.ruby.network.routers06.msg_bytes.Writeback_Data::4 7685640 -system.ruby.network.routers06.msg_bytes.Broadcast_Control::1 5010936 -system.ruby.network.routers06.msg_bytes.Persistent_Control::3 2611960 -system.ruby.network.routers07.percent_links_utilized 11.220542 -system.ruby.network.routers07.msg_count.Request_Control::1 78363 -system.ruby.network.routers07.msg_count.Response_Data::4 81698 -system.ruby.network.routers07.msg_count.ResponseL2hit_Data::4 207 -system.ruby.network.routers07.msg_count.ResponseLocal_Data::4 169 -system.ruby.network.routers07.msg_count.Response_Control::4 166 -system.ruby.network.routers07.msg_count.Writeback_Data::4 107207 -system.ruby.network.routers07.msg_count.Broadcast_Control::1 626367 -system.ruby.network.routers07.msg_count.Persistent_Control::3 326900 -system.ruby.network.routers07.msg_bytes.Request_Control::1 626904 -system.ruby.network.routers07.msg_bytes.Response_Data::4 5882256 -system.ruby.network.routers07.msg_bytes.ResponseL2hit_Data::4 14904 -system.ruby.network.routers07.msg_bytes.ResponseLocal_Data::4 12168 -system.ruby.network.routers07.msg_bytes.Response_Control::4 1328 -system.ruby.network.routers07.msg_bytes.Writeback_Data::4 7718904 -system.ruby.network.routers07.msg_bytes.Broadcast_Control::1 5010936 -system.ruby.network.routers07.msg_bytes.Persistent_Control::3 2615200 -system.ruby.network.routers08.percent_links_utilized 42.069721 -system.ruby.network.routers08.msg_count.Request_Control::1 626368 -system.ruby.network.routers08.msg_count.Request_Control::2 624699 -system.ruby.network.routers08.msg_count.Response_Data::4 14860 -system.ruby.network.routers08.msg_count.ResponseL2hit_Data::4 1670 -system.ruby.network.routers08.msg_count.Response_Control::4 1055 -system.ruby.network.routers08.msg_count.Writeback_Data::4 916229 -system.ruby.network.routers08.msg_count.Writeback_Control::4 318172 -system.ruby.network.routers08.msg_count.Persistent_Control::3 290561 -system.ruby.network.routers08.msg_bytes.Request_Control::1 5010944 -system.ruby.network.routers08.msg_bytes.Request_Control::2 4997592 -system.ruby.network.routers08.msg_bytes.Response_Data::4 1069920 -system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::4 120240 -system.ruby.network.routers08.msg_bytes.Response_Control::4 8440 -system.ruby.network.routers08.msg_bytes.Writeback_Data::4 65968488 -system.ruby.network.routers08.msg_bytes.Writeback_Control::4 2545376 -system.ruby.network.routers08.msg_bytes.Persistent_Control::3 2324488 -system.ruby.network.routers09.percent_links_utilized 39.417693 -system.ruby.network.routers09.msg_count.Request_Control::2 624699 -system.ruby.network.routers09.msg_count.Response_Data::4 635313 -system.ruby.network.routers09.msg_count.ResponseL2hit_Data::4 101 +system.ruby.network.routers00.percent_links_utilized 11.233413 +system.ruby.network.routers00.msg_count.Request_Control::1 78435 +system.ruby.network.routers00.msg_count.Response_Data::4 81785 +system.ruby.network.routers00.msg_count.ResponseL2hit_Data::4 210 +system.ruby.network.routers00.msg_count.ResponseLocal_Data::4 180 +system.ruby.network.routers00.msg_count.Response_Control::4 122 +system.ruby.network.routers00.msg_count.Writeback_Data::4 107529 +system.ruby.network.routers00.msg_count.Broadcast_Control::1 626415 +system.ruby.network.routers00.msg_count.Persistent_Control::3 328351 +system.ruby.network.routers00.msg_bytes.Request_Control::1 627480 +system.ruby.network.routers00.msg_bytes.Response_Data::4 5888520 +system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::4 15120 +system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::4 12960 +system.ruby.network.routers00.msg_bytes.Response_Control::4 976 +system.ruby.network.routers00.msg_bytes.Writeback_Data::4 7742088 +system.ruby.network.routers00.msg_bytes.Broadcast_Control::1 5011320 +system.ruby.network.routers00.msg_bytes.Persistent_Control::3 2626808 +system.ruby.network.routers01.percent_links_utilized 11.216772 +system.ruby.network.routers01.msg_count.Request_Control::1 78293 +system.ruby.network.routers01.msg_count.Response_Data::4 81463 +system.ruby.network.routers01.msg_count.ResponseL2hit_Data::4 217 +system.ruby.network.routers01.msg_count.ResponseLocal_Data::4 171 +system.ruby.network.routers01.msg_count.Response_Control::4 101 +system.ruby.network.routers01.msg_count.Writeback_Data::4 107414 +system.ruby.network.routers01.msg_count.Broadcast_Control::1 626415 +system.ruby.network.routers01.msg_count.Persistent_Control::3 328405 +system.ruby.network.routers01.msg_bytes.Request_Control::1 626344 +system.ruby.network.routers01.msg_bytes.Response_Data::4 5865336 +system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::4 15624 +system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::4 12312 +system.ruby.network.routers01.msg_bytes.Response_Control::4 808 +system.ruby.network.routers01.msg_bytes.Writeback_Data::4 7733808 +system.ruby.network.routers01.msg_bytes.Broadcast_Control::1 5011320 +system.ruby.network.routers01.msg_bytes.Persistent_Control::3 2627240 +system.ruby.network.routers02.percent_links_utilized 11.235213 +system.ruby.network.routers02.msg_count.Request_Control::1 78389 +system.ruby.network.routers02.msg_count.Response_Data::4 81630 +system.ruby.network.routers02.msg_count.ResponseL2hit_Data::4 212 +system.ruby.network.routers02.msg_count.ResponseLocal_Data::4 166 +system.ruby.network.routers02.msg_count.Response_Control::4 134 +system.ruby.network.routers02.msg_count.Writeback_Data::4 107712 +system.ruby.network.routers02.msg_count.Broadcast_Control::1 626415 +system.ruby.network.routers02.msg_count.Persistent_Control::3 328681 +system.ruby.network.routers02.msg_bytes.Request_Control::1 627112 +system.ruby.network.routers02.msg_bytes.Response_Data::4 5877360 +system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::4 15264 +system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::4 11952 +system.ruby.network.routers02.msg_bytes.Response_Control::4 1072 +system.ruby.network.routers02.msg_bytes.Writeback_Data::4 7755264 +system.ruby.network.routers02.msg_bytes.Broadcast_Control::1 5011320 +system.ruby.network.routers02.msg_bytes.Persistent_Control::3 2629448 +system.ruby.network.routers03.percent_links_utilized 11.269241 +system.ruby.network.routers03.msg_count.Request_Control::1 78553 +system.ruby.network.routers03.msg_count.Response_Data::4 82027 +system.ruby.network.routers03.msg_count.ResponseL2hit_Data::4 206 +system.ruby.network.routers03.msg_count.ResponseLocal_Data::4 173 +system.ruby.network.routers03.msg_count.Response_Control::4 127 +system.ruby.network.routers03.msg_count.Writeback_Data::4 108198 +system.ruby.network.routers03.msg_count.Broadcast_Control::1 626415 +system.ruby.network.routers03.msg_count.Persistent_Control::3 328869 +system.ruby.network.routers03.msg_bytes.Request_Control::1 628424 +system.ruby.network.routers03.msg_bytes.Response_Data::4 5905944 +system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::4 14832 +system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::4 12456 +system.ruby.network.routers03.msg_bytes.Response_Control::4 1016 +system.ruby.network.routers03.msg_bytes.Writeback_Data::4 7790256 +system.ruby.network.routers03.msg_bytes.Broadcast_Control::1 5011320 +system.ruby.network.routers03.msg_bytes.Persistent_Control::3 2630952 +system.ruby.network.routers04.percent_links_utilized 11.220096 +system.ruby.network.routers04.msg_count.Request_Control::1 78168 +system.ruby.network.routers04.msg_count.Response_Data::4 81565 +system.ruby.network.routers04.msg_count.ResponseL2hit_Data::4 202 +system.ruby.network.routers04.msg_count.ResponseLocal_Data::4 179 +system.ruby.network.routers04.msg_count.Response_Control::4 149 +system.ruby.network.routers04.msg_count.Writeback_Data::4 107413 +system.ruby.network.routers04.msg_count.Broadcast_Control::1 626415 +system.ruby.network.routers04.msg_count.Persistent_Control::3 328447 +system.ruby.network.routers04.msg_bytes.Request_Control::1 625344 +system.ruby.network.routers04.msg_bytes.Response_Data::4 5872680 +system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::4 14544 +system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::4 12888 +system.ruby.network.routers04.msg_bytes.Response_Control::4 1192 +system.ruby.network.routers04.msg_bytes.Writeback_Data::4 7733736 +system.ruby.network.routers04.msg_bytes.Broadcast_Control::1 5011320 +system.ruby.network.routers04.msg_bytes.Persistent_Control::3 2627576 +system.ruby.network.routers05.percent_links_utilized 11.228085 +system.ruby.network.routers05.msg_count.Request_Control::1 78418 +system.ruby.network.routers05.msg_count.Response_Data::4 81763 +system.ruby.network.routers05.msg_count.ResponseL2hit_Data::4 205 +system.ruby.network.routers05.msg_count.ResponseLocal_Data::4 183 +system.ruby.network.routers05.msg_count.Response_Control::4 151 +system.ruby.network.routers05.msg_count.Writeback_Data::4 107403 +system.ruby.network.routers05.msg_count.Writeback_Control::4 2 +system.ruby.network.routers05.msg_count.Broadcast_Control::1 626415 +system.ruby.network.routers05.msg_count.Persistent_Control::3 328387 +system.ruby.network.routers05.msg_bytes.Request_Control::1 627344 +system.ruby.network.routers05.msg_bytes.Response_Data::4 5886936 +system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::4 14760 +system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::4 13176 +system.ruby.network.routers05.msg_bytes.Response_Control::4 1208 +system.ruby.network.routers05.msg_bytes.Writeback_Data::4 7733016 +system.ruby.network.routers05.msg_bytes.Writeback_Control::4 16 +system.ruby.network.routers05.msg_bytes.Broadcast_Control::1 5011320 +system.ruby.network.routers05.msg_bytes.Persistent_Control::3 2627096 +system.ruby.network.routers06.percent_links_utilized 11.201853 +system.ruby.network.routers06.msg_count.Request_Control::1 78003 +system.ruby.network.routers06.msg_count.Response_Data::4 81441 +system.ruby.network.routers06.msg_count.ResponseL2hit_Data::4 248 +system.ruby.network.routers06.msg_count.ResponseLocal_Data::4 180 +system.ruby.network.routers06.msg_count.Response_Control::4 133 +system.ruby.network.routers06.msg_count.Writeback_Data::4 107026 +system.ruby.network.routers06.msg_count.Broadcast_Control::1 626415 +system.ruby.network.routers06.msg_count.Persistent_Control::3 328353 +system.ruby.network.routers06.msg_bytes.Request_Control::1 624024 +system.ruby.network.routers06.msg_bytes.Response_Data::4 5863752 +system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::4 17856 +system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::4 12960 +system.ruby.network.routers06.msg_bytes.Response_Control::4 1064 +system.ruby.network.routers06.msg_bytes.Writeback_Data::4 7705872 +system.ruby.network.routers06.msg_bytes.Broadcast_Control::1 5011320 +system.ruby.network.routers06.msg_bytes.Persistent_Control::3 2626824 +system.ruby.network.routers07.percent_links_utilized 11.201172 +system.ruby.network.routers07.msg_count.Request_Control::1 78156 +system.ruby.network.routers07.msg_count.Response_Data::4 81436 +system.ruby.network.routers07.msg_count.ResponseL2hit_Data::4 242 +system.ruby.network.routers07.msg_count.ResponseLocal_Data::4 192 +system.ruby.network.routers07.msg_count.Response_Control::4 146 +system.ruby.network.routers07.msg_count.Writeback_Data::4 107013 +system.ruby.network.routers07.msg_count.Broadcast_Control::1 626415 +system.ruby.network.routers07.msg_count.Persistent_Control::3 328129 +system.ruby.network.routers07.msg_bytes.Request_Control::1 625248 +system.ruby.network.routers07.msg_bytes.Response_Data::4 5863392 +system.ruby.network.routers07.msg_bytes.ResponseL2hit_Data::4 17424 +system.ruby.network.routers07.msg_bytes.ResponseLocal_Data::4 13824 +system.ruby.network.routers07.msg_bytes.Response_Control::4 1168 +system.ruby.network.routers07.msg_bytes.Writeback_Data::4 7704936 +system.ruby.network.routers07.msg_bytes.Broadcast_Control::1 5011320 +system.ruby.network.routers07.msg_bytes.Persistent_Control::3 2625032 +system.ruby.network.routers08.percent_links_utilized 42.049426 +system.ruby.network.routers08.msg_count.Request_Control::1 626415 +system.ruby.network.routers08.msg_count.Request_Control::2 624764 +system.ruby.network.routers08.msg_count.Response_Data::4 15075 +system.ruby.network.routers08.msg_count.ResponseL2hit_Data::4 1651 +system.ruby.network.routers08.msg_count.Response_Control::4 1042 +system.ruby.network.routers08.msg_count.Writeback_Data::4 916236 +system.ruby.network.routers08.msg_count.Writeback_Control::4 318123 +system.ruby.network.routers08.msg_count.Persistent_Control::3 291958 +system.ruby.network.routers08.msg_bytes.Request_Control::1 5011320 +system.ruby.network.routers08.msg_bytes.Request_Control::2 4998112 +system.ruby.network.routers08.msg_bytes.Response_Data::4 1085400 +system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::4 118872 +system.ruby.network.routers08.msg_bytes.Response_Control::4 8336 +system.ruby.network.routers08.msg_bytes.Writeback_Data::4 65968992 +system.ruby.network.routers08.msg_bytes.Writeback_Control::4 2544984 +system.ruby.network.routers08.msg_bytes.Persistent_Control::3 2335664 +system.ruby.network.routers09.percent_links_utilized 39.472142 +system.ruby.network.routers09.msg_count.Request_Control::2 624764 +system.ruby.network.routers09.msg_count.Response_Data::4 635954 +system.ruby.network.routers09.msg_count.ResponseL2hit_Data::4 91 system.ruby.network.routers09.msg_count.Response_Control::4 9 -system.ruby.network.routers09.msg_count.Writeback_Data::4 295224 -system.ruby.network.routers09.msg_count.Writeback_Control::4 318173 -system.ruby.network.routers09.msg_count.Persistent_Control::3 290561 -system.ruby.network.routers09.msg_bytes.Request_Control::2 4997592 -system.ruby.network.routers09.msg_bytes.Response_Data::4 45742536 -system.ruby.network.routers09.msg_bytes.ResponseL2hit_Data::4 7272 +system.ruby.network.routers09.msg_count.Writeback_Data::4 296768 +system.ruby.network.routers09.msg_count.Writeback_Control::4 318125 +system.ruby.network.routers09.msg_count.Persistent_Control::3 291958 +system.ruby.network.routers09.msg_bytes.Request_Control::2 4998112 +system.ruby.network.routers09.msg_bytes.Response_Data::4 45788688 +system.ruby.network.routers09.msg_bytes.ResponseL2hit_Data::4 6552 system.ruby.network.routers09.msg_bytes.Response_Control::4 72 -system.ruby.network.routers09.msg_bytes.Writeback_Data::4 21256128 -system.ruby.network.routers09.msg_bytes.Writeback_Control::4 2545384 -system.ruby.network.routers09.msg_bytes.Persistent_Control::3 2324488 -system.ruby.network.routers10.percent_links_utilized 19.496901 -system.ruby.network.routers10.msg_count.Request_Control::1 626368 -system.ruby.network.routers10.msg_count.Request_Control::2 624699 -system.ruby.network.routers10.msg_count.Response_Data::4 651201 -system.ruby.network.routers10.msg_count.ResponseL2hit_Data::4 1771 -system.ruby.network.routers10.msg_count.ResponseLocal_Data::4 713 -system.ruby.network.routers10.msg_count.Response_Control::4 1072 -system.ruby.network.routers10.msg_count.Writeback_Data::4 1034611 -system.ruby.network.routers10.msg_count.Writeback_Control::4 318173 -system.ruby.network.routers10.msg_count.Broadcast_Control::1 4384575 -system.ruby.network.routers10.msg_count.Persistent_Control::3 2615058 -system.ruby.network.routers10.msg_bytes.Request_Control::1 5010944 -system.ruby.network.routers10.msg_bytes.Request_Control::2 4997592 -system.ruby.network.routers10.msg_bytes.Response_Data::4 46886472 -system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::4 127512 -system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::4 51336 -system.ruby.network.routers10.msg_bytes.Response_Control::4 8576 -system.ruby.network.routers10.msg_bytes.Writeback_Data::4 74491992 -system.ruby.network.routers10.msg_bytes.Writeback_Control::4 2545384 -system.ruby.network.routers10.msg_bytes.Broadcast_Control::1 35076600 -system.ruby.network.routers10.msg_bytes.Persistent_Control::3 20920464 -system.ruby.network.msg_count.Request_Control 3753201 -system.ruby.network.msg_count.Response_Data 1953604 -system.ruby.network.msg_count.ResponseL2hit_Data 5313 -system.ruby.network.msg_count.ResponseLocal_Data 2139 -system.ruby.network.msg_count.Response_Control 3216 -system.ruby.network.msg_count.Writeback_Data 3103833 -system.ruby.network.msg_count.Writeback_Control 954519 -system.ruby.network.msg_count.Broadcast_Control 9395512 -system.ruby.network.msg_count.Persistent_Control 5811231 -system.ruby.network.msg_byte.Request_Control 30025608 -system.ruby.network.msg_byte.Response_Data 140659488 -system.ruby.network.msg_byte.ResponseL2hit_Data 382536 -system.ruby.network.msg_byte.ResponseLocal_Data 154008 -system.ruby.network.msg_byte.Response_Control 25728 -system.ruby.network.msg_byte.Writeback_Data 223475976 -system.ruby.network.msg_byte.Writeback_Control 7636152 -system.ruby.network.msg_byte.Broadcast_Control 75164096 -system.ruby.network.msg_byte.Persistent_Control 46489848 -system.ruby.network.routers00.throttle0.link_utilization 13.875688 -system.ruby.network.routers00.throttle0.msg_count.Response_Data::4 79822 -system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::4 200 -system.ruby.network.routers00.throttle0.msg_count.ResponseLocal_Data::4 94 -system.ruby.network.routers00.throttle0.msg_count.Writeback_Data::4 14639 -system.ruby.network.routers00.throttle0.msg_count.Broadcast_Control::1 547940 -system.ruby.network.routers00.throttle0.msg_count.Persistent_Control::3 290561 -system.ruby.network.routers00.throttle0.msg_bytes.Response_Data::4 5747184 -system.ruby.network.routers00.throttle0.msg_bytes.ResponseL2hit_Data::4 14400 -system.ruby.network.routers00.throttle0.msg_bytes.ResponseLocal_Data::4 6768 -system.ruby.network.routers00.throttle0.msg_bytes.Writeback_Data::4 1054008 -system.ruby.network.routers00.throttle0.msg_bytes.Broadcast_Control::1 4383520 -system.ruby.network.routers00.throttle0.msg_bytes.Persistent_Control::3 2324488 -system.ruby.network.routers00.throttle1.link_utilization 8.587531 -system.ruby.network.routers00.throttle1.msg_count.Request_Control::1 78427 -system.ruby.network.routers00.throttle1.msg_count.Response_Data::4 1856 -system.ruby.network.routers00.throttle1.msg_count.ResponseL2hit_Data::4 13 -system.ruby.network.routers00.throttle1.msg_count.ResponseLocal_Data::4 75 -system.ruby.network.routers00.throttle1.msg_count.Response_Control::4 118 -system.ruby.network.routers00.throttle1.msg_count.Writeback_Data::4 92876 -system.ruby.network.routers00.throttle1.msg_count.Broadcast_Control::1 78427 -system.ruby.network.routers00.throttle1.msg_count.Persistent_Control::3 36375 -system.ruby.network.routers00.throttle1.msg_bytes.Request_Control::1 627416 -system.ruby.network.routers00.throttle1.msg_bytes.Response_Data::4 133632 -system.ruby.network.routers00.throttle1.msg_bytes.ResponseL2hit_Data::4 936 -system.ruby.network.routers00.throttle1.msg_bytes.ResponseLocal_Data::4 5400 -system.ruby.network.routers00.throttle1.msg_bytes.Response_Control::4 944 -system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Data::4 6687072 -system.ruby.network.routers00.throttle1.msg_bytes.Broadcast_Control::1 627416 -system.ruby.network.routers00.throttle1.msg_bytes.Persistent_Control::3 291000 -system.ruby.network.routers01.throttle0.link_utilization 13.867197 -system.ruby.network.routers01.throttle0.msg_count.Response_Data::4 79803 -system.ruby.network.routers01.throttle0.msg_count.ResponseL2hit_Data::4 200 -system.ruby.network.routers01.throttle0.msg_count.ResponseLocal_Data::4 94 +system.ruby.network.routers09.msg_bytes.Writeback_Data::4 21367296 +system.ruby.network.routers09.msg_bytes.Writeback_Control::4 2545000 +system.ruby.network.routers09.msg_bytes.Persistent_Control::3 2335664 +system.ruby.network.routers10.percent_links_utilized 19.510945 +system.ruby.network.routers10.msg_count.Request_Control::1 626415 +system.ruby.network.routers10.msg_count.Request_Control::2 624764 +system.ruby.network.routers10.msg_count.Response_Data::4 652070 +system.ruby.network.routers10.msg_count.ResponseL2hit_Data::4 1742 +system.ruby.network.routers10.msg_count.ResponseLocal_Data::4 712 +system.ruby.network.routers10.msg_count.Response_Control::4 1057 +system.ruby.network.routers10.msg_count.Writeback_Data::4 1036356 +system.ruby.network.routers10.msg_count.Writeback_Control::4 318125 +system.ruby.network.routers10.msg_count.Broadcast_Control::1 4384905 +system.ruby.network.routers10.msg_count.Persistent_Control::3 2627622 +system.ruby.network.routers10.msg_bytes.Request_Control::1 5011320 +system.ruby.network.routers10.msg_bytes.Request_Control::2 4998112 +system.ruby.network.routers10.msg_bytes.Response_Data::4 46949040 +system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::4 125424 +system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::4 51264 +system.ruby.network.routers10.msg_bytes.Response_Control::4 8456 +system.ruby.network.routers10.msg_bytes.Writeback_Data::4 74617632 +system.ruby.network.routers10.msg_bytes.Writeback_Control::4 2545000 +system.ruby.network.routers10.msg_bytes.Broadcast_Control::1 35079240 +system.ruby.network.routers10.msg_bytes.Persistent_Control::3 21020976 +system.ruby.network.msg_count.Request_Control 3753537 +system.ruby.network.msg_count.Response_Data 1956209 +system.ruby.network.msg_count.ResponseL2hit_Data 5226 +system.ruby.network.msg_count.ResponseLocal_Data 2136 +system.ruby.network.msg_count.Response_Control 3171 +system.ruby.network.msg_count.Writeback_Data 3109068 +system.ruby.network.msg_count.Writeback_Control 954375 +system.ruby.network.msg_count.Broadcast_Control 9396225 +system.ruby.network.msg_count.Persistent_Control 5839160 +system.ruby.network.msg_byte.Request_Control 30028296 +system.ruby.network.msg_byte.Response_Data 140847048 +system.ruby.network.msg_byte.ResponseL2hit_Data 376272 +system.ruby.network.msg_byte.ResponseLocal_Data 153792 +system.ruby.network.msg_byte.Response_Control 25368 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5735592 +system.ruby.network.routers10.throttle1.msg_bytes.ResponseL2hit_Data::4 14760 +system.ruby.network.routers10.throttle1.msg_bytes.ResponseLocal_Data::4 6192 system.ruby.network.routers10.throttle1.msg_bytes.Response_Control::4 8 -system.ruby.network.routers10.throttle1.msg_bytes.Writeback_Data::4 1046592 -system.ruby.network.routers10.throttle1.msg_bytes.Broadcast_Control::1 4384016 -system.ruby.network.routers10.throttle1.msg_bytes.Persistent_Control::3 2033432 -system.ruby.network.routers10.throttle2.link_utilization 13.542591 -system.ruby.network.routers10.throttle2.msg_count.Response_Data::4 79478 -system.ruby.network.routers10.throttle2.msg_count.ResponseL2hit_Data::4 213 -system.ruby.network.routers10.throttle2.msg_count.ResponseLocal_Data::4 94 -system.ruby.network.routers10.throttle2.msg_count.Response_Control::4 4 -system.ruby.network.routers10.throttle2.msg_count.Writeback_Data::4 14458 -system.ruby.network.routers10.throttle2.msg_count.Broadcast_Control::1 548278 -system.ruby.network.routers10.throttle2.msg_count.Persistent_Control::3 254226 -system.ruby.network.routers10.throttle2.msg_bytes.Response_Data::4 5722416 -system.ruby.network.routers10.throttle2.msg_bytes.ResponseL2hit_Data::4 15336 -system.ruby.network.routers10.throttle2.msg_bytes.ResponseLocal_Data::4 6768 -system.ruby.network.routers10.throttle2.msg_bytes.Response_Control::4 32 -system.ruby.network.routers10.throttle2.msg_bytes.Writeback_Data::4 1040976 -system.ruby.network.routers10.throttle2.msg_bytes.Broadcast_Control::1 4386224 -system.ruby.network.routers10.throttle2.msg_bytes.Persistent_Control::3 2033808 -system.ruby.network.routers10.throttle3.link_utilization 13.572692 -system.ruby.network.routers10.throttle3.msg_count.Response_Data::4 79695 -system.ruby.network.routers10.throttle3.msg_count.ResponseL2hit_Data::4 229 -system.ruby.network.routers10.throttle3.msg_count.ResponseLocal_Data::4 92 -system.ruby.network.routers10.throttle3.msg_count.Response_Control::4 3 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-system.ruby.network.routers10.throttle6.msg_bytes.Writeback_Data::4 1045152 -system.ruby.network.routers10.throttle6.msg_bytes.Broadcast_Control::1 4387072 -system.ruby.network.routers10.throttle6.msg_bytes.Persistent_Control::3 2037024 -system.ruby.network.routers10.throttle7.link_utilization 13.565997 -system.ruby.network.routers10.throttle7.msg_count.Response_Data::4 79768 -system.ruby.network.routers10.throttle7.msg_count.ResponseL2hit_Data::4 193 -system.ruby.network.routers10.throttle7.msg_count.ResponseLocal_Data::4 70 -system.ruby.network.routers10.throttle7.msg_count.Response_Control::4 1 -system.ruby.network.routers10.throttle7.msg_count.Writeback_Data::4 14560 -system.ruby.network.routers10.throttle7.msg_count.Broadcast_Control::1 548005 -system.ruby.network.routers10.throttle7.msg_count.Persistent_Control::3 254223 -system.ruby.network.routers10.throttle7.msg_bytes.Response_Data::4 5743296 -system.ruby.network.routers10.throttle7.msg_bytes.ResponseL2hit_Data::4 13896 -system.ruby.network.routers10.throttle7.msg_bytes.ResponseLocal_Data::4 5040 -system.ruby.network.routers10.throttle7.msg_bytes.Response_Control::4 8 -system.ruby.network.routers10.throttle7.msg_bytes.Writeback_Data::4 1048320 -system.ruby.network.routers10.throttle7.msg_bytes.Broadcast_Control::1 4384040 -system.ruby.network.routers10.throttle7.msg_bytes.Persistent_Control::3 2033784 -system.ruby.network.routers10.throttle8.link_utilization 53.700961 -system.ruby.network.routers10.throttle8.msg_count.Request_Control::1 626368 -system.ruby.network.routers10.throttle8.msg_count.Response_Control::4 1052 -system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::4 625287 -system.ruby.network.routers10.throttle8.msg_count.Persistent_Control::3 290562 -system.ruby.network.routers10.throttle8.msg_bytes.Request_Control::1 5010944 -system.ruby.network.routers10.throttle8.msg_bytes.Response_Control::4 8416 -system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::4 45020664 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91905 22.79% 86.38% | 48739 12.09% 98.47% | 6121 1.52% 99.98% | 64 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 403224 system.ruby.LD.hit_latency_hist::bucket_size 512 system.ruby.LD.hit_latency_hist::max_bucket 5119 -system.ruby.LD.hit_latency_hist::samples 1840 -system.ruby.LD.hit_latency_hist::mean 1146.420652 -system.ruby.LD.hit_latency_hist::gmean 647.348793 -system.ruby.LD.hit_latency_hist::stdev 705.858079 -system.ruby.LD.hit_latency_hist | 416 22.61% 22.61% | 409 22.23% 44.84% | 432 23.48% 68.32% | 368 20.00% 88.32% | 194 10.54% 98.86% | 21 1.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 1840 +system.ruby.LD.hit_latency_hist::samples 1892 +system.ruby.LD.hit_latency_hist::mean 1091.609408 +system.ruby.LD.hit_latency_hist::gmean 566.194555 +system.ruby.LD.hit_latency_hist::stdev 701.385932 +system.ruby.LD.hit_latency_hist | 479 25.32% 25.32% | 427 22.57% 47.89% | 425 22.46% 70.35% | 371 19.61% 89.96% | 172 9.09% 99.05% | 18 0.95% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 1892 system.ruby.LD.miss_latency_hist::bucket_size 512 system.ruby.LD.miss_latency_hist::max_bucket 5119 -system.ruby.LD.miss_latency_hist::samples 400850 -system.ruby.LD.miss_latency_hist::mean 1245.988053 -system.ruby.LD.miss_latency_hist::gmean 1014.091147 -system.ruby.LD.miss_latency_hist::stdev 668.086740 -system.ruby.LD.miss_latency_hist | 69390 17.31% 17.31% | 93921 23.43% 40.74% | 91634 22.86% 63.60% | 91222 22.76% 86.36% | 48558 12.11% 98.47% | 6089 1.52% 99.99% | 36 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 400850 +system.ruby.LD.miss_latency_hist::samples 401332 +system.ruby.LD.miss_latency_hist::mean 1245.595128 +system.ruby.LD.miss_latency_hist::gmean 1014.893956 +system.ruby.LD.miss_latency_hist::stdev 667.922999 +system.ruby.LD.miss_latency_hist | 68911 17.17% 17.17% | 95606 23.82% 40.99% | 90547 22.56% 63.55% | 91534 22.81% 86.36% | 48567 12.10% 98.46% | 6103 1.52% 99.98% | 64 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 401332 system.ruby.ST.latency_hist::bucket_size 512 system.ruby.ST.latency_hist::max_bucket 5119 -system.ruby.ST.latency_hist::samples 223817 -system.ruby.ST.latency_hist::mean 1243.887310 -system.ruby.ST.latency_hist::gmean 1010.059619 -system.ruby.ST.latency_hist::stdev 668.586332 -system.ruby.ST.latency_hist | 39045 17.45% 17.45% | 52579 23.49% 40.94% | 50920 22.75% 63.69% | 50706 22.66% 86.34% | 27255 12.18% 98.52% | 3289 1.47% 99.99% | 23 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 223817 +system.ruby.ST.latency_hist::samples 223364 +system.ruby.ST.latency_hist::mean 1247.397181 +system.ruby.ST.latency_hist::gmean 1013.946431 +system.ruby.ST.latency_hist::stdev 669.645339 +system.ruby.ST.latency_hist | 38530 17.25% 17.25% | 52875 23.67% 40.92% | 50327 22.53% 63.45% | 50762 22.73% 86.18% | 27533 12.33% 98.51% | 3292 1.47% 99.98% | 43 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 223364 system.ruby.ST.hit_latency_hist::bucket_size 512 system.ruby.ST.hit_latency_hist::max_bucket 5119 -system.ruby.ST.hit_latency_hist::samples 1023 -system.ruby.ST.hit_latency_hist::mean 1107.514174 -system.ruby.ST.hit_latency_hist::gmean 576.060221 -system.ruby.ST.hit_latency_hist::stdev 714.183785 -system.ruby.ST.hit_latency_hist | 256 25.02% 25.02% | 220 21.51% 46.53% | 224 21.90% 68.43% | 210 20.53% 88.95% | 107 10.46% 99.41% | 6 0.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 1023 +system.ruby.ST.hit_latency_hist::samples 1069 +system.ruby.ST.hit_latency_hist::mean 1130.732460 +system.ruby.ST.hit_latency_hist::gmean 610.100104 +system.ruby.ST.hit_latency_hist::stdev 718.461557 +system.ruby.ST.hit_latency_hist | 260 24.32% 24.32% | 237 22.17% 46.49% | 220 20.58% 67.07% | 223 20.86% 87.93% | 115 10.76% 98.69% | 14 1.31% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 1069 system.ruby.ST.miss_latency_hist::bucket_size 512 system.ruby.ST.miss_latency_hist::max_bucket 5119 -system.ruby.ST.miss_latency_hist::samples 222794 -system.ruby.ST.miss_latency_hist::mean 1244.513492 -system.ruby.ST.miss_latency_hist::gmean 1012.667390 -system.ruby.ST.miss_latency_hist::stdev 668.307321 -system.ruby.ST.miss_latency_hist | 38789 17.41% 17.41% | 52359 23.50% 40.91% | 50696 22.75% 63.67% | 50496 22.66% 86.33% | 27148 12.19% 98.52% | 3283 1.47% 99.99% | 23 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 222794 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100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 165 +system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 198 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist::total 198 system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 512 system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 5119 -system.ruby.L1Cache.miss_mach_latency_hist::samples 2147 -system.ruby.L1Cache.miss_mach_latency_hist::mean 1248.519329 -system.ruby.L1Cache.miss_mach_latency_hist::gmean 969.471834 -system.ruby.L1Cache.miss_mach_latency_hist::stdev 675.761537 -system.ruby.L1Cache.miss_mach_latency_hist | 380 17.70% 17.70% | 491 22.87% 40.57% | 486 22.64% 63.20% | 483 22.50% 85.70% | 276 12.86% 98.56% | 31 1.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_mach_latency_hist::total 2147 +system.ruby.L1Cache.miss_mach_latency_hist::samples 2150 +system.ruby.L1Cache.miss_mach_latency_hist::mean 1253.348372 +system.ruby.L1Cache.miss_mach_latency_hist::gmean 981.859616 +system.ruby.L1Cache.miss_mach_latency_hist::stdev 675.772818 +system.ruby.L1Cache.miss_mach_latency_hist | 390 18.14% 18.14% | 450 20.93% 39.07% | 525 24.42% 63.49% | 485 22.56% 86.05% | 255 11.86% 97.91% | 45 2.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist::total 2150 system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 512 system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 5119 -system.ruby.L2Cache.hit_mach_latency_hist::samples 2698 -system.ruby.L2Cache.hit_mach_latency_hist::mean 1201.718310 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 920.120641 -system.ruby.L2Cache.hit_mach_latency_hist::stdev 671.015337 -system.ruby.L2Cache.hit_mach_latency_hist | 507 18.79% 18.79% | 629 23.31% 42.11% | 656 24.31% 66.42% | 578 21.42% 87.84% | 301 11.16% 99.00% | 27 1.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 2698 +system.ruby.L2Cache.hit_mach_latency_hist::samples 2763 +system.ruby.L2Cache.hit_mach_latency_hist::mean 1184.900471 +system.ruby.L2Cache.hit_mach_latency_hist::gmean 917.900956 +system.ruby.L2Cache.hit_mach_latency_hist::stdev 665.600614 +system.ruby.L2Cache.hit_mach_latency_hist | 541 19.58% 19.58% | 664 24.03% 43.61% | 645 23.34% 66.96% | 594 21.50% 88.45% | 287 10.39% 98.84% | 32 1.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist::total 2763 system.ruby.Directory.miss_mach_latency_hist::bucket_size 512 system.ruby.Directory.miss_mach_latency_hist::max_bucket 5119 -system.ruby.Directory.miss_mach_latency_hist::samples 621497 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0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 621477 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 3 @@ -1155,470 +1162,450 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion | system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 3 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 100 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 132 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 100 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 100 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 132 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 132 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 1365 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1247.561172 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 950.370533 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 686.038439 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 251 18.39% 18.39% | 304 22.27% 40.66% | 300 21.98% 62.64% | 311 22.78% 85.42% | 178 13.04% 98.46% | 21 1.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 1365 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 1339 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1280.535474 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1006.733527 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 680.945391 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 229 17.10% 17.10% | 276 20.61% 37.71% | 333 24.87% 62.58% | 304 22.70% 85.29% | 164 12.25% 97.54% | 33 2.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 1339 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 512 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 1740 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 1212.249425 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 939.070110 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 668.659412 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 316 18.16% 18.16% | 409 23.51% 41.67% | 432 24.83% 66.49% | 368 21.15% 87.64% | 194 11.15% 98.79% | 21 1.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 1740 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 1760 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 1173.405114 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 910.831654 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 657.956416 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 347 19.72% 19.72% | 427 24.26% 43.98% | 425 24.15% 68.12% | 371 21.08% 89.20% | 172 9.77% 98.98% | 18 1.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 1760 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 399485 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1245.982678 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 1014.316040 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 668.025449 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 69139 17.31% 17.31% | 93617 23.43% 40.74% | 91334 22.86% 63.60% | 90911 22.76% 86.36% | 48380 12.11% 98.47% | 6068 1.52% 99.99% | 36 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 399485 +system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 399993 +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1245.478163 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 1014.921384 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 667.876777 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 68682 17.17% 17.17% | 95330 23.83% 41.00% | 90214 22.55% 63.56% | 91230 22.81% 86.37% | 48403 12.10% 98.47% | 6070 1.52% 99.98% | 64 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::total 399993 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 65 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 66 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 65 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 65 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 66 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 66 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 782 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1250.191816 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 1003.738135 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 657.869161 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 129 16.50% 16.50% | 187 23.91% 40.41% | 186 23.79% 64.19% | 172 21.99% 86.19% | 98 12.53% 98.72% | 10 1.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 782 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 811 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1208.461159 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 942.129361 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 665.132497 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 161 19.85% 19.85% | 174 21.45% 41.31% | 192 23.67% 64.98% | 181 22.32% 87.30% | 91 11.22% 98.52% | 12 1.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 811 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 512 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 958 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 1182.590814 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 886.675622 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 675.203218 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 191 19.94% 19.94% | 220 22.96% 42.90% | 224 23.38% 66.28% | 210 21.92% 88.20% | 107 11.17% 99.37% | 6 0.63% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 958 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 1003 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 1205.071785 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 930.438584 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 678.666440 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 194 19.34% 19.34% | 237 23.63% 42.97% | 220 21.93% 64.91% | 223 22.23% 87.14% | 115 11.47% 98.60% | 14 1.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 1003 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 222012 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1244.493491 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 1012.698982 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 668.345173 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 38660 17.41% 17.41% | 52172 23.50% 40.91% | 50510 22.75% 63.66% | 50324 22.67% 86.33% | 27050 12.18% 98.52% | 3273 1.47% 99.99% | 23 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 222012 -system.ruby.Directory_Controller.GETX 239586 0.00% 0.00% -system.ruby.Directory_Controller.GETS 430890 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 145901 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 144660 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 415 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 306269 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner 441 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 316913 0.00% 0.00% -system.ruby.Directory_Controller.Tokens 164 0.00% 0.00% -system.ruby.Directory_Controller.Ack_All_Tokens 736 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 621309 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 303926 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 220810 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 397302 0.00% 0.00% -system.ruby.Directory_Controller.O.Lockdown 2735 0.00% 0.00% -system.ruby.Directory_Controller.O.Data_All_Tokens 112 0.00% 0.00% -system.ruby.Directory_Controller.O.Tokens 10 0.00% 0.00% -system.ruby.Directory_Controller.O.Ack_All_Tokens 727 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 1839 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETS 3317 0.00% 0.00% -system.ruby.Directory_Controller.NO.Lockdown 43557 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_Owner 414 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 303512 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner 440 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 316566 0.00% 0.00% -system.ruby.Directory_Controller.NO.Tokens 150 0.00% 0.00% -system.ruby.Directory_Controller.L.GETX 509 0.00% 0.00% -system.ruby.Directory_Controller.L.GETS 922 0.00% 0.00% -system.ruby.Directory_Controller.L.Lockdown 1101 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 144645 0.00% 0.00% -system.ruby.Directory_Controller.L.Data_Owner 1 0.00% 0.00% -system.ruby.Directory_Controller.L.Data_All_Tokens 2619 0.00% 0.00% -system.ruby.Directory_Controller.L.Ack_Owner 1 0.00% 0.00% -system.ruby.Directory_Controller.L.Ack_Owner_All_Tokens 347 0.00% 0.00% -system.ruby.Directory_Controller.L.Tokens 2 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETX 66 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETS 130 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Lockdown 139 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Data_All_Tokens 25 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Tokens 2 0.00% 0.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 221484 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1248.102838 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 1016.708923 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 669.367212 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 38109 17.21% 17.21% | 52464 23.69% 40.89% | 49915 22.54% 63.43% | 50358 22.74% 86.17% | 27327 12.34% 98.51% | 3266 1.47% 99.98% | 43 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 221484 +system.ruby.Directory_Controller.GETX 240452 0.00% 0.00% +system.ruby.Directory_Controller.GETS 432599 0.00% 0.00% +system.ruby.Directory_Controller.Lockdown 146609 0.00% 0.00% +system.ruby.Directory_Controller.Unlockdown 145349 0.00% 0.00% +system.ruby.Directory_Controller.Data_Owner 469 0.00% 0.00% +system.ruby.Directory_Controller.Data_All_Tokens 307348 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner 430 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner_All_Tokens 316863 0.00% 0.00% +system.ruby.Directory_Controller.Tokens 180 0.00% 0.00% +system.ruby.Directory_Controller.Ack_All_Tokens 746 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 621329 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 303987 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 220258 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 397725 0.00% 0.00% +system.ruby.Directory_Controller.O.Lockdown 2797 0.00% 0.00% +system.ruby.Directory_Controller.O.Data_All_Tokens 150 0.00% 0.00% +system.ruby.Directory_Controller.O.Tokens 17 0.00% 0.00% +system.ruby.Directory_Controller.O.Ack_All_Tokens 732 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 1901 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETS 3320 0.00% 0.00% +system.ruby.Directory_Controller.NO.Lockdown 44050 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_Owner 467 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_All_Tokens 303520 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner 430 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 316439 0.00% 0.00% +system.ruby.Directory_Controller.NO.Tokens 157 0.00% 0.00% +system.ruby.Directory_Controller.L.GETX 558 0.00% 0.00% +system.ruby.Directory_Controller.L.GETS 1002 0.00% 0.00% +system.ruby.Directory_Controller.L.Lockdown 1116 0.00% 0.00% +system.ruby.Directory_Controller.L.Unlockdown 145316 0.00% 0.00% +system.ruby.Directory_Controller.L.Data_Owner 2 0.00% 0.00% +system.ruby.Directory_Controller.L.Data_All_Tokens 3652 0.00% 0.00% +system.ruby.Directory_Controller.L.Ack_Owner_All_Tokens 424 0.00% 0.00% +system.ruby.Directory_Controller.L.Tokens 3 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETX 61 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETS 128 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Lockdown 149 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Data_All_Tokens 26 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Tokens 3 0.00% 0.00% system.ruby.Directory_Controller.O_W.Ack_All_Tokens 1 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Data 14 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 303788 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.GETX 277 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.GETS 364 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Lockdown 4 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Unlockdown 15 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Data_All_Tokens 1 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Ack_All_Tokens 3 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Memory_Data 3207 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Memory_Ack 138 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.GETX 1718 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.GETS 2571 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Lockdown 133 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 98230 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.GETX 14367 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.GETS 26284 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 98232 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Ack_All_Tokens 5 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 519858 0.00% 0.00% -system.ruby.L1Cache_Controller.Load | 50505 12.54% 12.54% | 50407 12.52% 25.06% | 50126 12.45% 37.51% | 50449 12.53% 50.03% | 50448 12.53% 62.56% | 50299 12.49% 75.05% | 49995 12.41% 87.47% | 50478 12.53% 100.00% -system.ruby.L1Cache_Controller.Load::total 402707 -system.ruby.L1Cache_Controller.Store | 27943 12.48% 12.48% | 27979 12.50% 24.98% | 27981 12.50% 37.49% | 27901 12.47% 49.95% | 27908 12.47% 62.42% | 28192 12.60% 75.02% | 28011 12.51% 87.53% | 27911 12.47% 100.00% -system.ruby.L1Cache_Controller.Store::total 223826 -system.ruby.L1Cache_Controller.L1_Replacement | 1478878 12.50% 12.50% | 1481158 12.52% 25.02% | 1476463 12.48% 37.50% | 1479129 12.50% 50.00% | 1480475 12.51% 62.51% | 1481780 12.52% 75.03% | 1473814 12.46% 87.49% | 1480509 12.51% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 11832206 -system.ruby.L1Cache_Controller.Data_Shared | 178 12.12% 12.12% | 178 12.12% 24.23% | 197 13.41% 37.64% | 208 14.16% 51.80% | 198 13.48% 65.28% | 179 12.19% 77.47% | 174 11.84% 89.31% | 157 10.69% 100.00% -system.ruby.L1Cache_Controller.Data_Shared::total 1469 -system.ruby.L1Cache_Controller.Data_Owner | 96 15.38% 15.38% | 88 14.10% 29.49% | 86 13.78% 43.27% | 81 12.98% 56.25% | 73 11.70% 67.95% | 69 11.06% 79.01% | 63 10.10% 89.10% | 68 10.90% 100.00% -system.ruby.L1Cache_Controller.Data_Owner::total 624 -system.ruby.L1Cache_Controller.Data_All_Tokens | 94481 12.53% 12.53% | 94367 12.51% 25.04% | 93960 12.46% 37.50% | 94404 12.52% 50.02% | 94178 12.49% 62.50% | 94590 12.54% 75.04% | 93848 12.44% 87.49% | 94366 12.51% 100.00% -system.ruby.L1Cache_Controller.Data_All_Tokens::total 754194 -system.ruby.L1Cache_Controller.Ack | 0 0.00% 0.00% | 1 9.09% 9.09% | 4 36.36% 45.45% | 2 18.18% 63.64% | 1 9.09% 72.73% | 0 0.00% 72.73% | 2 18.18% 90.91% | 1 9.09% 100.00% -system.ruby.L1Cache_Controller.Ack::total 11 -system.ruby.L1Cache_Controller.Ack_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.Ack_All_Tokens::total 3 -system.ruby.L1Cache_Controller.Transient_Local_GETX | 195825 12.50% 12.50% | 195791 12.50% 25.00% | 195788 12.50% 37.50% | 195864 12.50% 50.01% | 195860 12.50% 62.51% | 195577 12.49% 75.00% | 195758 12.50% 87.50% | 195857 12.50% 100.00% -system.ruby.L1Cache_Controller.Transient_Local_GETX::total 1566320 -system.ruby.L1Cache_Controller.Transient_Local_GETS | 352115 12.49% 12.49% | 352210 12.50% 24.99% | 352489 12.51% 37.50% | 352172 12.50% 50.00% | 352175 12.50% 62.49% | 352316 12.50% 74.99% | 352625 12.51% 87.50% | 352147 12.50% 100.00% -system.ruby.L1Cache_Controller.Transient_Local_GETS::total 2818249 -system.ruby.L1Cache_Controller.Persistent_GETX | 45620 12.52% 12.52% | 45605 12.51% 25.03% | 45551 12.50% 37.52% | 45486 12.48% 50.00% | 45630 12.52% 62.52% | 45481 12.48% 75.00% | 45555 12.50% 87.50% | 45577 12.50% 100.00% -system.ruby.L1Cache_Controller.Persistent_GETX::total 364505 -system.ruby.L1Cache_Controller.Persistent_GETS | 81967 12.48% 12.48% | 81961 12.48% 24.96% | 82084 12.50% 37.46% | 82097 12.50% 49.96% | 82151 12.51% 62.47% | 82050 12.49% 74.96% | 82334 12.54% 87.50% | 82129 12.50% 100.00% -system.ruby.L1Cache_Controller.Persistent_GETS::total 656773 -system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token::total 1 -system.ruby.L1Cache_Controller.Own_Lock_or_Unlock | 162974 12.51% 12.51% | 162996 12.51% 25.01% | 162926 12.50% 37.51% | 162978 12.51% 50.02% | 162779 12.49% 62.51% | 163030 12.51% 75.02% | 162672 12.48% 87.50% | 162855 12.50% 100.00% -system.ruby.L1Cache_Controller.Own_Lock_or_Unlock::total 1303210 -system.ruby.L1Cache_Controller.Request_Timeout | 113549 12.46% 12.46% | 114775 12.60% 25.06% | 113326 12.44% 37.50% | 113899 12.50% 50.01% | 114234 12.54% 62.55% | 114789 12.60% 75.15% | 112446 12.34% 87.49% | 113957 12.51% 100.00% -system.ruby.L1Cache_Controller.Request_Timeout::total 910975 -system.ruby.L1Cache_Controller.Use_TimeoutStarverX | 16 9.52% 9.52% | 13 7.74% 17.26% | 17 10.12% 27.38% | 20 11.90% 39.29% | 16 9.52% 48.81% | 19 11.31% 60.12% | 35 20.83% 80.95% | 32 19.05% 100.00% -system.ruby.L1Cache_Controller.Use_TimeoutStarverX::total 168 -system.ruby.L1Cache_Controller.Use_TimeoutStarverS | 23 7.52% 7.52% | 28 9.15% 16.67% | 37 12.09% 28.76% | 33 10.78% 39.54% | 37 12.09% 51.63% | 43 14.05% 65.69% | 41 13.40% 79.08% | 64 20.92% 100.00% -system.ruby.L1Cache_Controller.Use_TimeoutStarverS::total 306 -system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers | 78173 12.52% 12.52% | 78117 12.51% 25.04% | 77809 12.47% 37.50% | 78050 12.50% 50.01% | 78046 12.50% 62.51% | 78208 12.53% 75.04% | 77714 12.45% 87.49% | 78086 12.51% 100.00% -system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers::total 624203 -system.ruby.L1Cache_Controller.NP.Load | 50401 12.54% 12.54% | 50310 12.52% 25.05% | 50043 12.45% 37.50% | 50352 12.53% 50.03% | 50357 12.53% 62.56% | 50213 12.49% 75.05% | 49901 12.41% 87.46% | 50391 12.54% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 401968 -system.ruby.L1Cache_Controller.NP.Store | 27888 12.48% 12.48% | 27936 12.50% 24.99% | 27934 12.50% 37.49% | 27840 12.46% 49.95% | 27859 12.47% 62.42% | 28139 12.59% 75.01% | 27962 12.52% 87.53% | 27861 12.47% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 223419 -system.ruby.L1Cache_Controller.NP.Data_Shared | 26 14.77% 14.77% | 29 16.48% 31.25% | 22 12.50% 43.75% | 28 15.91% 59.66% | 15 8.52% 68.18% | 17 9.66% 77.84% | 20 11.36% 89.20% | 19 10.80% 100.00% -system.ruby.L1Cache_Controller.NP.Data_Shared::total 176 -system.ruby.L1Cache_Controller.NP.Data_Owner | 35 15.09% 15.09% | 30 12.93% 28.02% | 34 14.66% 42.67% | 31 13.36% 56.03% | 24 10.34% 66.38% | 25 10.78% 77.16% | 25 10.78% 87.93% | 28 12.07% 100.00% -system.ruby.L1Cache_Controller.NP.Data_Owner::total 232 -system.ruby.L1Cache_Controller.NP.Data_All_Tokens | 16181 12.54% 12.54% | 16113 12.48% 25.02% | 16021 12.41% 37.43% | 16247 12.59% 50.02% | 16023 12.41% 62.44% | 16284 12.62% 75.05% | 16035 12.42% 87.48% | 16162 12.52% 100.00% -system.ruby.L1Cache_Controller.NP.Data_All_Tokens::total 129066 -system.ruby.L1Cache_Controller.NP.Ack | 0 0.00% 0.00% | 1 14.29% 14.29% | 1 14.29% 28.57% | 2 28.57% 57.14% | 1 14.29% 71.43% | 0 0.00% 71.43% | 1 14.29% 85.71% | 1 14.29% 100.00% -system.ruby.L1Cache_Controller.NP.Ack::total 7 -system.ruby.L1Cache_Controller.NP.Transient_Local_GETX | 195216 12.50% 12.50% | 195146 12.50% 25.00% | 195155 12.50% 37.50% | 195221 12.50% 50.01% | 195223 12.50% 62.51% | 194979 12.49% 75.00% | 195119 12.50% 87.50% | 195196 12.50% 100.00% -system.ruby.L1Cache_Controller.NP.Transient_Local_GETX::total 1561255 -system.ruby.L1Cache_Controller.NP.Transient_Local_GETS | 350967 12.49% 12.49% | 351041 12.50% 24.99% | 351293 12.51% 37.50% | 351023 12.50% 49.99% | 351022 12.50% 62.49% | 351182 12.50% 74.99% | 351462 12.51% 87.51% | 350973 12.49% 100.00% -system.ruby.L1Cache_Controller.NP.Transient_Local_GETS::total 2808963 -system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock | 142016 12.51% 12.51% | 141908 12.50% 25.00% | 141885 12.50% 37.50% | 141935 12.50% 50.00% | 141954 12.50% 62.50% | 141859 12.49% 75.00% | 142016 12.51% 87.50% | 141902 12.50% 100.00% -system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock::total 1135475 -system.ruby.L1Cache_Controller.I.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 1 -system.ruby.L1Cache_Controller.I.L1_Replacement | 116 11.09% 11.09% | 113 10.80% 21.89% | 137 13.10% 34.99% | 130 12.43% 47.42% | 131 12.52% 59.94% | 123 11.76% 71.70% | 136 13.00% 84.70% | 160 15.30% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 1046 -system.ruby.L1Cache_Controller.I.Data_All_Tokens | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 2 66.67% 100.00% -system.ruby.L1Cache_Controller.I.Data_All_Tokens::total 3 -system.ruby.L1Cache_Controller.I.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.I.Transient_Local_GETX::total 2 -system.ruby.L1Cache_Controller.I.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% -system.ruby.L1Cache_Controller.I.Transient_Local_GETS::total 2 -system.ruby.L1Cache_Controller.I.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.I.Persistent_GETX::total 1 -system.ruby.L1Cache_Controller.I.Own_Lock_or_Unlock | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory_Controller.O_W.Memory_Data 33 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Ack 303838 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.GETX 543 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.GETS 896 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Lockdown 7 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Unlockdown 33 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Memory_Data 3337 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Memory_Ack 149 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.GETX 1538 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.GETS 2627 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Lockdown 129 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Memory_Data 98356 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.GETX 15593 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.GETS 26901 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Lockdown 98361 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Ack_All_Tokens 13 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Memory_Data 519603 0.00% 0.00% +system.ruby.L1Cache_Controller.Load | 50667 12.57% 12.57% | 50484 12.52% 25.08% | 50375 12.49% 37.58% | 50486 12.52% 50.10% | 50381 12.49% 62.59% | 50187 12.45% 75.04% | 50077 12.42% 87.46% | 50582 12.54% 100.00% +system.ruby.L1Cache_Controller.Load::total 403239 +system.ruby.L1Cache_Controller.Store | 27788 12.44% 12.44% | 27835 12.46% 24.90% | 28035 12.55% 37.45% | 28087 12.57% 50.03% | 27811 12.45% 62.48% | 28262 12.65% 75.13% | 27958 12.52% 87.64% | 27598 12.36% 100.00% +system.ruby.L1Cache_Controller.Store::total 223374 +system.ruby.L1Cache_Controller.L1_Replacement | 1482309 12.54% 12.54% | 1478152 12.50% 25.04% | 1477165 12.50% 37.54% | 1480092 12.52% 50.06% | 1475170 12.48% 62.54% | 1480320 12.52% 75.06% | 1470800 12.44% 87.50% | 1477330 12.50% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 11821338 +system.ruby.L1Cache_Controller.Data_Shared | 182 12.24% 12.24% | 184 12.37% 24.61% | 174 11.70% 36.31% | 192 12.91% 49.23% | 172 11.57% 60.79% | 175 11.77% 72.56% | 199 13.38% 85.94% | 209 14.06% 100.00% +system.ruby.L1Cache_Controller.Data_Shared::total 1487 +system.ruby.L1Cache_Controller.Data_Owner | 102 14.35% 14.35% | 88 12.38% 26.72% | 96 13.50% 40.23% | 87 12.24% 52.46% | 88 12.38% 64.84% | 87 12.24% 77.07% | 68 9.56% 86.64% | 95 13.36% 100.00% +system.ruby.L1Cache_Controller.Data_Owner::total 711 +system.ruby.L1Cache_Controller.Data_All_Tokens | 94528 12.51% 12.51% | 94324 12.49% 25.00% | 94557 12.52% 37.51% | 94990 12.57% 50.09% | 94377 12.49% 62.58% | 94479 12.51% 75.09% | 94128 12.46% 87.55% | 94089 12.45% 100.00% +system.ruby.L1Cache_Controller.Data_All_Tokens::total 755472 +system.ruby.L1Cache_Controller.Ack | 3 21.43% 21.43% | 1 7.14% 28.57% | 2 14.29% 42.86% | 2 14.29% 57.14% | 0 0.00% 57.14% | 2 14.29% 71.43% | 1 7.14% 78.57% | 3 21.43% 100.00% +system.ruby.L1Cache_Controller.Ack::total 14 +system.ruby.L1Cache_Controller.Transient_Local_GETX | 195530 12.51% 12.51% | 195478 12.51% 25.01% | 195278 12.49% 37.51% | 195229 12.49% 50.00% | 195505 12.51% 62.50% | 195060 12.48% 74.98% | 195357 12.50% 87.48% | 195719 12.52% 100.00% +system.ruby.L1Cache_Controller.Transient_Local_GETX::total 1563156 +system.ruby.L1Cache_Controller.Transient_Local_GETS | 352449 12.49% 12.49% | 352643 12.50% 24.99% | 352748 12.50% 37.49% | 352633 12.50% 49.99% | 352741 12.50% 62.49% | 352937 12.51% 74.99% | 353055 12.51% 87.51% | 352539 12.49% 100.00% +system.ruby.L1Cache_Controller.Transient_Local_GETS::total 2821745 +system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token | 1 25.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% +system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token::total 4 +system.ruby.L1Cache_Controller.Persistent_GETX | 45490 12.51% 12.51% | 45476 12.51% 25.02% | 45348 12.47% 37.50% | 45359 12.48% 49.97% | 45403 12.49% 62.46% | 45382 12.48% 74.94% | 45473 12.51% 87.45% | 45618 12.55% 100.00% +system.ruby.L1Cache_Controller.Persistent_GETX::total 363549 +system.ruby.L1Cache_Controller.Persistent_GETS | 82793 12.49% 12.49% | 82775 12.49% 24.98% | 82793 12.49% 37.48% | 82699 12.48% 49.96% | 82884 12.51% 62.46% | 82958 12.52% 74.98% | 82904 12.51% 87.49% | 82886 12.51% 100.00% +system.ruby.L1Cache_Controller.Persistent_GETS::total 662692 +system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token::total 2 +system.ruby.L1Cache_Controller.Own_Lock_or_Unlock | 163675 12.50% 12.50% | 163707 12.50% 25.00% | 163816 12.51% 37.51% | 163900 12.52% 50.03% | 163671 12.50% 62.53% | 163618 12.50% 75.02% | 163580 12.49% 87.52% | 163454 12.48% 100.00% +system.ruby.L1Cache_Controller.Own_Lock_or_Unlock::total 1309421 +system.ruby.L1Cache_Controller.Request_Timeout | 113982 12.40% 12.40% | 114218 12.43% 24.83% | 115677 12.58% 37.41% | 116297 12.65% 50.06% | 115021 12.51% 62.58% | 115438 12.56% 75.13% | 114863 12.50% 87.63% | 113699 12.37% 100.00% +system.ruby.L1Cache_Controller.Request_Timeout::total 919195 +system.ruby.L1Cache_Controller.Use_TimeoutStarverX | 10 4.93% 4.93% | 17 8.37% 13.30% | 26 12.81% 26.11% | 26 12.81% 38.92% | 26 12.81% 51.72% | 30 14.78% 66.50% | 34 16.75% 83.25% | 34 16.75% 100.00% +system.ruby.L1Cache_Controller.Use_TimeoutStarverX::total 203 +system.ruby.L1Cache_Controller.Use_TimeoutStarverS | 26 8.12% 8.12% | 19 5.94% 14.06% | 35 10.94% 25.00% | 33 10.31% 35.31% | 51 15.94% 51.25% | 51 15.94% 67.19% | 51 15.94% 83.12% | 54 16.88% 100.00% +system.ruby.L1Cache_Controller.Use_TimeoutStarverS::total 320 +system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers | 78180 12.53% 12.53% | 78041 12.50% 25.03% | 78121 12.52% 37.54% | 78269 12.54% 50.08% | 77894 12.48% 62.56% | 78131 12.52% 75.08% | 77705 12.45% 87.53% | 77837 12.47% 100.00% +system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers::total 624178 +system.ruby.L1Cache_Controller.NP.Load | 50581 12.57% 12.57% | 50392 12.52% 25.09% | 50283 12.49% 37.58% | 50410 12.53% 50.11% | 50271 12.49% 62.60% | 50089 12.45% 75.04% | 49958 12.41% 87.46% | 50481 12.54% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 402465 +system.ruby.L1Cache_Controller.NP.Store | 27727 12.44% 12.44% | 27793 12.47% 24.90% | 27984 12.55% 37.45% | 28032 12.57% 50.02% | 27756 12.45% 62.47% | 28215 12.65% 75.13% | 27910 12.52% 87.64% | 27550 12.36% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 222967 +system.ruby.L1Cache_Controller.NP.Data_Shared | 31 14.03% 14.03% | 28 12.67% 26.70% | 28 12.67% 39.37% | 23 10.41% 49.77% | 29 13.12% 62.90% | 25 11.31% 74.21% | 26 11.76% 85.97% | 31 14.03% 100.00% +system.ruby.L1Cache_Controller.NP.Data_Shared::total 221 +system.ruby.L1Cache_Controller.NP.Data_Owner | 37 13.41% 13.41% | 30 10.87% 24.28% | 36 13.04% 37.32% | 33 11.96% 49.28% | 35 12.68% 61.96% | 31 11.23% 73.19% | 30 10.87% 84.06% | 44 15.94% 100.00% +system.ruby.L1Cache_Controller.NP.Data_Owner::total 276 +system.ruby.L1Cache_Controller.NP.Data_All_Tokens | 16213 12.44% 12.44% | 16160 12.40% 24.84% | 16306 12.51% 37.36% | 16601 12.74% 50.09% | 16361 12.56% 62.65% | 16214 12.44% 75.09% | 16316 12.52% 87.61% | 16143 12.39% 100.00% +system.ruby.L1Cache_Controller.NP.Data_All_Tokens::total 130314 +system.ruby.L1Cache_Controller.NP.Ack | 2 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 2 25.00% 50.00% | 0 0.00% 50.00% | 1 12.50% 62.50% | 0 0.00% 62.50% | 3 37.50% 100.00% +system.ruby.L1Cache_Controller.NP.Ack::total 8 +system.ruby.L1Cache_Controller.NP.Transient_Local_GETX | 194864 12.51% 12.51% | 194884 12.51% 25.01% | 194599 12.49% 37.50% | 194606 12.49% 49.99% | 194888 12.51% 62.50% | 194419 12.48% 74.98% | 194754 12.50% 87.48% | 195093 12.52% 100.00% +system.ruby.L1Cache_Controller.NP.Transient_Local_GETX::total 1558107 +system.ruby.L1Cache_Controller.NP.Transient_Local_GETS | 351252 12.49% 12.49% | 351488 12.50% 24.99% | 351609 12.50% 37.49% | 351524 12.50% 49.99% | 351577 12.50% 62.49% | 351765 12.51% 75.00% | 351871 12.51% 87.51% | 351335 12.49% 100.00% +system.ruby.L1Cache_Controller.NP.Transient_Local_GETS::total 2812421 +system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock | 142654 12.51% 12.51% | 142579 12.50% 25.00% | 142548 12.50% 37.50% | 142694 12.51% 50.01% | 142513 12.49% 62.50% | 142552 12.50% 75.00% | 142576 12.50% 87.50% | 142609 12.50% 100.00% +system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock::total 1140725 +system.ruby.L1Cache_Controller.I.L1_Replacement | 115 11.11% 11.11% | 99 9.57% 20.68% | 132 12.75% 33.43% | 120 11.59% 45.02% | 149 14.40% 59.42% | 150 14.49% 73.91% | 130 12.56% 86.47% | 140 13.53% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 1035 +system.ruby.L1Cache_Controller.I.Data_All_Tokens | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.I.Data_All_Tokens::total 1 +system.ruby.L1Cache_Controller.I.Transient_Local_GETS | 0 0.00% 0.00% | 1 25.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% +system.ruby.L1Cache_Controller.I.Transient_Local_GETS::total 4 +system.ruby.L1Cache_Controller.I.Own_Lock_or_Unlock | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.I.Own_Lock_or_Unlock::total 3 -system.ruby.L1Cache_Controller.S.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 1 -system.ruby.L1Cache_Controller.S.L1_Replacement | 188 11.41% 11.41% | 187 11.35% 22.75% | 228 13.83% 36.59% | 226 13.71% 50.30% | 220 13.35% 63.65% | 204 12.38% 76.03% | 199 12.08% 88.11% | 196 11.89% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 1648 -system.ruby.L1Cache_Controller.S.Data_Shared | 2 10.00% 10.00% | 2 10.00% 20.00% | 4 20.00% 40.00% | 4 20.00% 60.00% | 3 15.00% 75.00% | 4 20.00% 95.00% | 1 5.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Data_Shared::total 20 -system.ruby.L1Cache_Controller.S.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 20.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 3 60.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Data_All_Tokens::total 5 -system.ruby.L1Cache_Controller.S.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Transient_Local_GETS::total 1 -system.ruby.L1Cache_Controller.S.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Persistent_GETX::total 3 -system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token::total 1 -system.ruby.L1Cache_Controller.O.L1_Replacement | 89 13.59% 13.59% | 81 12.37% 25.95% | 87 13.28% 39.24% | 79 12.06% 51.30% | 89 13.59% 64.89% | 76 11.60% 76.49% | 73 11.15% 87.63% | 81 12.37% 100.00% -system.ruby.L1Cache_Controller.O.L1_Replacement::total 655 -system.ruby.L1Cache_Controller.O.Data_All_Tokens | 1 16.67% 16.67% | 2 33.33% 50.00% | 1 16.67% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.O.Data_All_Tokens::total 6 -system.ruby.L1Cache_Controller.O.Ack_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.O.Ack_All_Tokens::total 1 -system.ruby.L1Cache_Controller.O.Transient_Local_GETS | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% -system.ruby.L1Cache_Controller.O.Transient_Local_GETS::total 3 -system.ruby.L1Cache_Controller.O.Persistent_GETS | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.O.Persistent_GETS::total 2 -system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock | 16 9.88% 9.88% | 30 18.52% 28.40% | 27 16.67% 45.06% | 22 13.58% 58.64% | 24 14.81% 73.46% | 19 11.73% 85.19% | 11 6.79% 91.98% | 13 8.02% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement | 199 11.94% 11.94% | 196 11.76% 23.70% | 190 11.40% 35.09% | 210 12.60% 47.69% | 197 11.82% 59.51% | 200 12.00% 71.51% | 237 14.22% 85.72% | 238 14.28% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 1667 +system.ruby.L1Cache_Controller.S.Data_Shared | 0 0.00% 0.00% | 1 8.33% 8.33% | 2 16.67% 25.00% | 1 8.33% 33.33% | 2 16.67% 50.00% | 3 25.00% 75.00% | 2 16.67% 91.67% | 1 8.33% 100.00% +system.ruby.L1Cache_Controller.S.Data_Shared::total 12 +system.ruby.L1Cache_Controller.S.Data_Owner | 1 25.00% 25.00% | 1 25.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Data_Owner::total 4 +system.ruby.L1Cache_Controller.S.Data_All_Tokens | 1 10.00% 10.00% | 3 30.00% 40.00% | 1 10.00% 50.00% | 2 20.00% 70.00% | 0 0.00% 70.00% | 1 10.00% 80.00% | 0 0.00% 80.00% | 2 20.00% 100.00% +system.ruby.L1Cache_Controller.S.Data_All_Tokens::total 10 +system.ruby.L1Cache_Controller.S.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Transient_Local_GETX::total 1 +system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token | 1 25.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% +system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token::total 4 +system.ruby.L1Cache_Controller.S.Persistent_GETX | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Persistent_GETX::total 1 +system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token::total 2 +system.ruby.L1Cache_Controller.O.L1_Replacement | 96 14.29% 14.29% | 87 12.95% 27.23% | 81 12.05% 39.29% | 78 11.61% 50.89% | 85 12.65% 63.54% | 77 11.46% 75.00% | 78 11.61% 86.61% | 90 13.39% 100.00% +system.ruby.L1Cache_Controller.O.L1_Replacement::total 672 +system.ruby.L1Cache_Controller.O.Data_Shared | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Data_Shared::total 1 +system.ruby.L1Cache_Controller.O.Data_All_Tokens | 3 37.50% 37.50% | 2 25.00% 62.50% | 0 0.00% 62.50% | 1 12.50% 75.00% | 0 0.00% 75.00% | 1 12.50% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% +system.ruby.L1Cache_Controller.O.Data_All_Tokens::total 8 +system.ruby.L1Cache_Controller.O.Ack | 1 25.00% 25.00% | 1 25.00% 50.00% | 2 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Ack::total 4 +system.ruby.L1Cache_Controller.O.Transient_Local_GETS | 0 0.00% 0.00% | 2 40.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 1 20.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Transient_Local_GETS::total 5 +system.ruby.L1Cache_Controller.O.Persistent_GETX | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Persistent_GETX::total 1 +system.ruby.L1Cache_Controller.O.Persistent_GETS | 1 14.29% 14.29% | 1 14.29% 28.57% | 2 28.57% 57.14% | 1 14.29% 71.43% | 1 14.29% 85.71% | 1 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Persistent_GETS::total 7 +system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock | 29 17.90% 17.90% | 21 12.96% 30.86% | 23 14.20% 45.06% | 16 9.88% 54.94% | 16 9.88% 64.81% | 31 19.14% 83.95% | 9 5.56% 89.51% | 17 10.49% 100.00% system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock::total 162 -system.ruby.L1Cache_Controller.M.Load | 2 10.00% 10.00% | 2 10.00% 20.00% | 1 5.00% 25.00% | 3 15.00% 40.00% | 2 10.00% 50.00% | 2 10.00% 60.00% | 4 20.00% 80.00% | 4 20.00% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 20 -system.ruby.L1Cache_Controller.M.Store | 1 7.69% 7.69% | 2 15.38% 23.08% | 2 15.38% 38.46% | 1 7.69% 46.15% | 2 15.38% 61.54% | 1 7.69% 69.23% | 2 15.38% 84.62% | 2 15.38% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 13 -system.ruby.L1Cache_Controller.M.L1_Replacement | 50162 12.55% 12.55% | 50082 12.53% 25.07% | 49741 12.44% 37.51% | 50062 12.52% 50.03% | 50061 12.52% 62.55% | 49960 12.50% 75.05% | 49650 12.42% 87.47% | 50117 12.53% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 399835 -system.ruby.L1Cache_Controller.M.Transient_Local_GETX | 17 9.50% 9.50% | 17 9.50% 18.99% | 30 16.76% 35.75% | 27 15.08% 50.84% | 26 14.53% 65.36% | 19 10.61% 75.98% | 19 10.61% 86.59% | 24 13.41% 100.00% -system.ruby.L1Cache_Controller.M.Transient_Local_GETX::total 179 -system.ruby.L1Cache_Controller.M.Transient_Local_GETS | 30 10.87% 10.87% | 25 9.06% 19.93% | 37 13.41% 33.33% | 32 11.59% 44.93% | 42 15.22% 60.14% | 33 11.96% 72.10% | 36 13.04% 85.14% | 41 14.86% 100.00% -system.ruby.L1Cache_Controller.M.Transient_Local_GETS::total 276 -system.ruby.L1Cache_Controller.M.Persistent_GETX | 15 13.51% 13.51% | 13 11.71% 25.23% | 8 7.21% 32.43% | 22 19.82% 52.25% | 18 16.22% 68.47% | 9 8.11% 76.58% | 12 10.81% 87.39% | 14 12.61% 100.00% +system.ruby.L1Cache_Controller.M.Load | 0 0.00% 0.00% | 2 6.45% 6.45% | 7 22.58% 29.03% | 1 3.23% 32.26% | 4 12.90% 45.16% | 4 12.90% 58.06% | 5 16.13% 74.19% | 8 25.81% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 31 +system.ruby.L1Cache_Controller.M.Store | 2 14.29% 14.29% | 1 7.14% 21.43% | 1 7.14% 28.57% | 3 21.43% 50.00% | 1 7.14% 57.14% | 4 28.57% 85.71% | 2 14.29% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 14 +system.ruby.L1Cache_Controller.M.L1_Replacement | 50307 12.57% 12.57% | 50130 12.52% 25.09% | 50031 12.50% 37.59% | 50119 12.52% 50.11% | 50010 12.49% 62.60% | 49833 12.45% 75.05% | 49674 12.41% 87.46% | 50184 12.54% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 400288 +system.ruby.L1Cache_Controller.M.Transient_Local_GETX | 25 14.29% 14.29% | 18 10.29% 24.57% | 22 12.57% 37.14% | 21 12.00% 49.14% | 26 14.86% 64.00% | 17 9.71% 73.71% | 24 13.71% 87.43% | 22 12.57% 100.00% +system.ruby.L1Cache_Controller.M.Transient_Local_GETX::total 175 +system.ruby.L1Cache_Controller.M.Transient_Local_GETS | 35 13.83% 13.83% | 33 13.04% 26.88% | 23 9.09% 35.97% | 26 10.28% 46.25% | 33 13.04% 59.29% | 23 9.09% 68.38% | 40 15.81% 84.19% | 40 15.81% 100.00% +system.ruby.L1Cache_Controller.M.Transient_Local_GETS::total 253 +system.ruby.L1Cache_Controller.M.Persistent_GETX | 14 12.61% 12.61% | 11 9.91% 22.52% | 13 11.71% 34.23% | 16 14.41% 48.65% | 22 19.82% 68.47% | 13 11.71% 80.18% | 15 13.51% 93.69% | 7 6.31% 100.00% system.ruby.L1Cache_Controller.M.Persistent_GETX::total 111 -system.ruby.L1Cache_Controller.M.Persistent_GETS | 26 12.50% 12.50% | 24 11.54% 24.04% | 36 17.31% 41.35% | 26 12.50% 53.85% | 23 11.06% 64.90% | 25 12.02% 76.92% | 23 11.06% 87.98% | 25 12.02% 100.00% -system.ruby.L1Cache_Controller.M.Persistent_GETS::total 208 -system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock | 1506 12.31% 12.31% | 1557 12.73% 25.04% | 1559 12.75% 37.79% | 1481 12.11% 49.89% | 1495 12.22% 62.12% | 1551 12.68% 74.80% | 1514 12.38% 87.17% | 1569 12.83% 100.00% -system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock::total 12232 -system.ruby.L1Cache_Controller.MM.Load | 2 14.29% 14.29% | 2 14.29% 28.57% | 2 14.29% 42.86% | 1 7.14% 50.00% | 1 7.14% 57.14% | 2 14.29% 71.43% | 1 7.14% 78.57% | 3 21.43% 100.00% -system.ruby.L1Cache_Controller.MM.Load::total 14 -system.ruby.L1Cache_Controller.MM.Store | 1 14.29% 14.29% | 1 14.29% 28.57% | 0 0.00% 28.57% | 1 14.29% 42.86% | 1 14.29% 57.14% | 2 28.57% 85.71% | 1 14.29% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.MM.Store::total 7 -system.ruby.L1Cache_Controller.MM.L1_Replacement | 27868 12.49% 12.49% | 27899 12.50% 24.99% | 27893 12.50% 37.49% | 27830 12.47% 49.96% | 27826 12.47% 62.43% | 28107 12.60% 75.03% | 27922 12.51% 87.54% | 27804 12.46% 100.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement::total 223149 -system.ruby.L1Cache_Controller.MM.Transient_Local_GETX | 11 10.89% 10.89% | 13 12.87% 23.76% | 16 15.84% 39.60% | 12 11.88% 51.49% | 10 9.90% 61.39% | 8 7.92% 69.31% | 17 16.83% 86.14% | 14 13.86% 100.00% -system.ruby.L1Cache_Controller.MM.Transient_Local_GETX::total 101 -system.ruby.L1Cache_Controller.MM.Transient_Local_GETS | 17 11.11% 11.11% | 17 11.11% 22.22% | 21 13.73% 35.95% | 20 13.07% 49.02% | 19 12.42% 61.44% | 24 15.69% 77.12% | 16 10.46% 87.58% | 19 12.42% 100.00% -system.ruby.L1Cache_Controller.MM.Transient_Local_GETS::total 153 -system.ruby.L1Cache_Controller.MM.Persistent_GETX | 8 11.59% 11.59% | 12 17.39% 28.99% | 9 13.04% 42.03% | 6 8.70% 50.72% | 9 13.04% 63.77% | 10 14.49% 78.26% | 5 7.25% 85.51% | 10 14.49% 100.00% -system.ruby.L1Cache_Controller.MM.Persistent_GETX::total 69 -system.ruby.L1Cache_Controller.MM.Persistent_GETS | 20 14.93% 14.93% | 17 12.69% 27.61% | 20 14.93% 42.54% | 14 10.45% 52.99% | 15 11.19% 64.18% | 15 11.19% 75.37% | 14 10.45% 85.82% | 19 14.18% 100.00% -system.ruby.L1Cache_Controller.MM.Persistent_GETS::total 134 -system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock | 792 11.85% 11.85% | 872 13.05% 24.91% | 857 12.83% 37.73% | 862 12.90% 50.64% | 853 12.77% 63.40% | 870 13.02% 76.43% | 767 11.48% 87.91% | 808 12.09% 100.00% -system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock::total 6681 -system.ruby.L1Cache_Controller.M_W.Load | 4 10.26% 10.26% | 4 10.26% 20.51% | 3 7.69% 28.21% | 8 20.51% 48.72% | 4 10.26% 58.97% | 4 10.26% 69.23% | 5 12.82% 82.05% | 7 17.95% 100.00% -system.ruby.L1Cache_Controller.M_W.Load::total 39 -system.ruby.L1Cache_Controller.M_W.Store | 4 14.81% 14.81% | 2 7.41% 22.22% | 5 18.52% 40.74% | 2 7.41% 48.15% | 4 14.81% 62.96% | 3 11.11% 74.07% | 2 7.41% 81.48% | 5 18.52% 100.00% -system.ruby.L1Cache_Controller.M_W.Store::total 27 -system.ruby.L1Cache_Controller.M_W.L1_Replacement | 366982 12.48% 12.48% | 367604 12.51% 24.99% | 367580 12.51% 37.50% | 366426 12.47% 49.96% | 370591 12.61% 62.57% | 367996 12.52% 75.09% | 364722 12.41% 87.50% | 367546 12.50% 100.00% -system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 2939447 -system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX | 56 12.07% 12.07% | 61 13.15% 25.22% | 67 14.44% 39.66% | 67 14.44% 54.09% | 64 13.79% 67.89% | 47 10.13% 78.02% | 58 12.50% 90.52% | 44 9.48% 100.00% -system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX::total 464 -system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS | 101 11.80% 11.80% | 110 12.85% 24.65% | 122 14.25% 38.90% | 106 12.38% 51.29% | 104 12.15% 63.43% | 99 11.57% 75.00% | 106 12.38% 87.38% | 108 12.62% 100.00% -system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS::total 856 -system.ruby.L1Cache_Controller.M_W.Persistent_GETX | 11 10.58% 10.58% | 12 11.54% 22.12% | 13 12.50% 34.62% | 12 11.54% 46.15% | 6 5.77% 51.92% | 12 11.54% 63.46% | 21 20.19% 83.65% | 17 16.35% 100.00% -system.ruby.L1Cache_Controller.M_W.Persistent_GETX::total 104 -system.ruby.L1Cache_Controller.M_W.Persistent_GETS | 12 7.10% 7.10% | 15 8.88% 15.98% | 22 13.02% 28.99% | 24 14.20% 43.20% | 17 10.06% 53.25% | 26 15.38% 68.64% | 22 13.02% 81.66% | 31 18.34% 100.00% -system.ruby.L1Cache_Controller.M_W.Persistent_GETS::total 169 -system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock | 1128 13.31% 13.31% | 1115 13.16% 26.47% | 1052 12.41% 38.88% | 1047 12.36% 51.24% | 1076 12.70% 63.94% | 1071 12.64% 76.58% | 989 11.67% 88.25% | 996 11.75% 100.00% -system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock::total 8474 -system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX | 11 9.82% 9.82% | 12 10.71% 20.54% | 15 13.39% 33.93% | 12 10.71% 44.64% | 8 7.14% 51.79% | 13 11.61% 63.39% | 23 20.54% 83.93% | 18 16.07% 100.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX::total 112 -system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS | 13 7.30% 7.30% | 16 8.99% 16.29% | 22 12.36% 28.65% | 25 14.04% 42.70% | 18 10.11% 52.81% | 27 15.17% 67.98% | 23 12.92% 80.90% | 34 19.10% 100.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS::total 178 -system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers | 50250 12.54% 12.54% | 50160 12.52% 25.06% | 49852 12.44% 37.51% | 50169 12.52% 50.03% | 50169 12.52% 62.55% | 50045 12.49% 75.05% | 49742 12.42% 87.46% | 50222 12.54% 100.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers::total 400609 -system.ruby.L1Cache_Controller.MM_W.Load | 5 19.23% 19.23% | 2 7.69% 26.92% | 2 7.69% 34.62% | 2 7.69% 42.31% | 9 34.62% 76.92% | 0 0.00% 76.92% | 2 7.69% 84.62% | 4 15.38% 100.00% -system.ruby.L1Cache_Controller.MM_W.Load::total 26 -system.ruby.L1Cache_Controller.MM_W.Store | 2 11.11% 11.11% | 5 27.78% 38.89% | 2 11.11% 50.00% | 1 5.56% 55.56% | 1 5.56% 61.11% | 2 11.11% 72.22% | 4 22.22% 94.44% | 1 5.56% 100.00% -system.ruby.L1Cache_Controller.MM_W.Store::total 18 -system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 204432 12.49% 12.49% | 204554 12.49% 24.98% | 205545 12.55% 37.54% | 203688 12.44% 49.98% | 202947 12.40% 62.37% | 204891 12.51% 74.89% | 206853 12.63% 87.52% | 204287 12.48% 100.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 1637197 -system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX | 44 15.55% 15.55% | 24 8.48% 24.03% | 36 12.72% 36.75% | 32 11.31% 48.06% | 41 14.49% 62.54% | 36 12.72% 75.27% | 31 10.95% 86.22% | 39 13.78% 100.00% -system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX::total 283 -system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS | 56 11.41% 11.41% | 65 13.24% 24.64% | 61 12.42% 37.07% | 58 11.81% 48.88% | 74 15.07% 63.95% | 57 11.61% 75.56% | 63 12.83% 88.39% | 57 11.61% 100.00% -system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS::total 491 -system.ruby.L1Cache_Controller.MM_W.Persistent_GETX | 5 9.80% 9.80% | 1 1.96% 11.76% | 1 1.96% 13.73% | 6 11.76% 25.49% | 8 15.69% 41.18% | 5 9.80% 50.98% | 12 23.53% 74.51% | 13 25.49% 100.00% -system.ruby.L1Cache_Controller.MM_W.Persistent_GETX::total 51 -system.ruby.L1Cache_Controller.MM_W.Persistent_GETS | 10 8.26% 8.26% | 9 7.44% 15.70% | 15 12.40% 28.10% | 8 6.61% 34.71% | 18 14.88% 49.59% | 16 13.22% 62.81% | 17 14.05% 76.86% | 28 23.14% 100.00% -system.ruby.L1Cache_Controller.MM_W.Persistent_GETS::total 121 -system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock | 594 12.47% 12.47% | 644 13.52% 25.98% | 590 12.38% 38.36% | 592 12.42% 50.79% | 621 13.03% 63.82% | 585 12.28% 76.10% | 571 11.98% 88.08% | 568 11.92% 100.00% -system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock::total 4765 -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX | 5 8.93% 8.93% | 1 1.79% 10.71% | 2 3.57% 14.29% | 8 14.29% 28.57% | 8 14.29% 42.86% | 6 10.71% 53.57% | 12 21.43% 75.00% | 14 25.00% 100.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX::total 56 -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS | 10 7.81% 7.81% | 12 9.38% 17.19% | 15 11.72% 28.91% | 8 6.25% 35.16% | 19 14.84% 50.00% | 16 12.50% 62.50% | 18 14.06% 76.56% | 30 23.44% 100.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS::total 128 -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers | 27923 12.49% 12.49% | 27957 12.50% 24.99% | 27957 12.50% 37.50% | 27881 12.47% 49.96% | 27877 12.47% 62.43% | 28163 12.60% 75.03% | 27972 12.51% 87.54% | 27864 12.46% 100.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers::total 223594 -system.ruby.L1Cache_Controller.IM.L1_Replacement | 294620 12.48% 12.48% | 293419 12.43% 24.90% | 292817 12.40% 37.31% | 296966 12.58% 49.88% | 294176 12.46% 62.34% | 299280 12.68% 75.02% | 294738 12.48% 87.50% | 295130 12.50% 100.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement::total 2361146 -system.ruby.L1Cache_Controller.IM.Data_Owner | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IM.Data_Owner::total 3 -system.ruby.L1Cache_Controller.IM.Data_All_Tokens | 27934 12.49% 12.49% | 27965 12.50% 24.98% | 27968 12.50% 37.48% | 27891 12.47% 49.95% | 27899 12.47% 62.42% | 28182 12.60% 75.02% | 27998 12.51% 87.53% | 27900 12.47% 100.00% -system.ruby.L1Cache_Controller.IM.Data_All_Tokens::total 223737 -system.ruby.L1Cache_Controller.IM.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IM.Ack::total 3 -system.ruby.L1Cache_Controller.IM.Transient_Local_GETX | 86 11.64% 11.64% | 111 15.02% 26.66% | 85 11.50% 38.16% | 97 13.13% 51.29% | 82 11.10% 62.38% | 82 11.10% 73.48% | 82 11.10% 84.57% | 114 15.43% 100.00% -system.ruby.L1Cache_Controller.IM.Transient_Local_GETX::total 739 -system.ruby.L1Cache_Controller.IM.Transient_Local_GETS | 162 11.96% 11.96% | 172 12.69% 24.65% | 170 12.55% 37.20% | 167 12.32% 49.52% | 166 12.25% 61.77% | 168 12.40% 74.17% | 174 12.84% 87.01% | 176 12.99% 100.00% -system.ruby.L1Cache_Controller.IM.Transient_Local_GETS::total 1355 -system.ruby.L1Cache_Controller.IM.Persistent_GETX | 21 11.23% 11.23% | 21 11.23% 22.46% | 21 11.23% 33.69% | 22 11.76% 45.45% | 22 11.76% 57.22% | 27 14.44% 71.66% | 35 18.72% 90.37% | 18 9.63% 100.00% -system.ruby.L1Cache_Controller.IM.Persistent_GETX::total 187 -system.ruby.L1Cache_Controller.IM.Persistent_GETS | 45 12.82% 12.82% | 39 11.11% 23.93% | 45 12.82% 36.75% | 38 10.83% 47.58% | 41 11.68% 59.26% | 49 13.96% 73.22% | 58 16.52% 89.74% | 36 10.26% 100.00% -system.ruby.L1Cache_Controller.IM.Persistent_GETS::total 351 -system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock | 5838 12.41% 12.41% | 5788 12.30% 24.71% | 5902 12.54% 37.25% | 5964 12.67% 49.92% | 5795 12.31% 62.24% | 5968 12.68% 74.92% | 5904 12.55% 87.47% | 5898 12.53% 100.00% -system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock::total 47057 -system.ruby.L1Cache_Controller.IM.Request_Timeout | 39638 12.22% 12.22% | 40916 12.62% 24.84% | 41161 12.69% 37.53% | 41081 12.67% 50.20% | 40231 12.41% 62.61% | 39967 12.32% 74.93% | 41068 12.66% 87.59% | 40229 12.41% 100.00% -system.ruby.L1Cache_Controller.IM.Request_Timeout::total 324291 -system.ruby.L1Cache_Controller.OM.L1_Replacement | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 19 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OM.L1_Replacement::total 19 -system.ruby.L1Cache_Controller.OM.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OM.Data_All_Tokens::total 1 -system.ruby.L1Cache_Controller.OM.Ack_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OM.Ack_All_Tokens::total 2 -system.ruby.L1Cache_Controller.OM.Own_Lock_or_Unlock | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OM.Own_Lock_or_Unlock::total 2 -system.ruby.L1Cache_Controller.OM.Request_Timeout | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OM.Request_Timeout::total 2 -system.ruby.L1Cache_Controller.IS.L1_Replacement | 532363 12.53% 12.53% | 535097 12.59% 25.12% | 530211 12.48% 37.60% | 531290 12.50% 50.10% | 532226 12.53% 62.63% | 528539 12.44% 75.07% | 526667 12.40% 87.46% | 532616 12.54% 100.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement::total 4249009 -system.ruby.L1Cache_Controller.IS.Data_Shared | 149 11.74% 11.74% | 147 11.58% 23.33% | 170 13.40% 36.72% | 175 13.79% 50.51% | 180 14.18% 64.70% | 158 12.45% 77.15% | 153 12.06% 89.20% | 137 10.80% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Shared::total 1269 -system.ruby.L1Cache_Controller.IS.Data_Owner | 61 15.72% 15.72% | 58 14.95% 30.67% | 52 13.40% 44.07% | 48 12.37% 56.44% | 49 12.63% 69.07% | 43 11.08% 80.15% | 37 9.54% 89.69% | 40 10.31% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Owner::total 388 -system.ruby.L1Cache_Controller.IS.Data_All_Tokens | 50277 12.54% 12.54% | 50188 12.52% 25.06% | 49892 12.44% 37.50% | 50206 12.52% 50.03% | 50195 12.52% 62.55% | 50086 12.49% 75.04% | 49788 12.42% 87.46% | 50275 12.54% 100.00% -system.ruby.L1Cache_Controller.IS.Data_All_Tokens::total 400907 -system.ruby.L1Cache_Controller.IS.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IS.Ack::total 1 -system.ruby.L1Cache_Controller.IS.Transient_Local_GETX | 147 11.03% 11.03% | 166 12.45% 23.48% | 156 11.70% 35.18% | 172 12.90% 48.09% | 174 13.05% 61.14% | 170 12.75% 73.89% | 170 12.75% 86.65% | 178 13.35% 100.00% -system.ruby.L1Cache_Controller.IS.Transient_Local_GETX::total 1333 -system.ruby.L1Cache_Controller.IS.Transient_Local_GETS | 321 13.08% 13.08% | 313 12.75% 25.84% | 318 12.96% 38.79% | 302 12.31% 51.10% | 289 11.78% 62.88% | 306 12.47% 75.35% | 308 12.55% 87.90% | 297 12.10% 100.00% -system.ruby.L1Cache_Controller.IS.Transient_Local_GETS::total 2454 -system.ruby.L1Cache_Controller.IS.Persistent_GETX | 37 9.71% 9.71% | 39 10.24% 19.95% | 53 13.91% 33.86% | 54 14.17% 48.03% | 47 12.34% 60.37% | 60 15.75% 76.12% | 46 12.07% 88.19% | 45 11.81% 100.00% -system.ruby.L1Cache_Controller.IS.Persistent_GETX::total 381 -system.ruby.L1Cache_Controller.IS.Persistent_GETS | 67 10.00% 10.00% | 81 12.09% 22.09% | 73 10.90% 32.99% | 88 13.13% 46.12% | 82 12.24% 58.36% | 91 13.58% 71.94% | 95 14.18% 86.12% | 93 13.88% 100.00% -system.ruby.L1Cache_Controller.IS.Persistent_GETS::total 670 -system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock | 10667 12.58% 12.58% | 10679 12.59% 25.17% | 10624 12.53% 37.69% | 10616 12.52% 50.21% | 10539 12.42% 62.63% | 10637 12.54% 75.17% | 10418 12.28% 87.45% | 10642 12.55% 100.00% -system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock::total 84822 -system.ruby.L1Cache_Controller.IS.Request_Timeout | 73359 12.60% 12.60% | 73340 12.59% 25.19% | 71758 12.32% 37.51% | 72207 12.40% 49.90% | 73615 12.64% 62.54% | 74201 12.74% 75.28% | 70644 12.13% 87.41% | 73315 12.59% 100.00% -system.ruby.L1Cache_Controller.IS.Request_Timeout::total 582439 -system.ruby.L1Cache_Controller.I_L.Load | 91 14.26% 14.26% | 87 13.64% 27.90% | 75 11.76% 39.66% | 83 13.01% 52.66% | 74 11.60% 64.26% | 78 12.23% 76.49% | 81 12.70% 89.18% | 69 10.82% 100.00% -system.ruby.L1Cache_Controller.I_L.Load::total 638 -system.ruby.L1Cache_Controller.I_L.Store | 47 13.74% 13.74% | 33 9.65% 23.39% | 38 11.11% 34.50% | 56 16.37% 50.88% | 41 11.99% 62.87% | 45 13.16% 76.02% | 40 11.70% 87.72% | 42 12.28% 100.00% -system.ruby.L1Cache_Controller.I_L.Store::total 342 -system.ruby.L1Cache_Controller.I_L.L1_Replacement | 338 9.55% 9.55% | 366 10.34% 19.89% | 384 10.85% 30.74% | 403 11.39% 42.13% | 438 12.38% 54.51% | 403 11.39% 65.89% | 534 15.09% 80.98% | 673 19.02% 100.00% -system.ruby.L1Cache_Controller.I_L.L1_Replacement::total 3539 -system.ruby.L1Cache_Controller.I_L.Data_All_Tokens | 87 19.95% 19.95% | 93 21.33% 41.28% | 74 16.97% 58.26% | 54 12.39% 70.64% | 53 12.16% 82.80% | 32 7.34% 90.14% | 23 5.28% 95.41% | 20 4.59% 100.00% -system.ruby.L1Cache_Controller.I_L.Data_All_Tokens::total 436 -system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX | 245 12.53% 12.53% | 253 12.94% 25.47% | 240 12.28% 37.75% | 235 12.02% 49.77% | 238 12.17% 61.94% | 236 12.07% 74.02% | 261 13.35% 87.37% | 247 12.63% 100.00% -system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX::total 1955 -system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS | 459 12.46% 12.46% | 464 12.60% 25.05% | 464 12.60% 37.65% | 461 12.51% 50.16% | 458 12.43% 62.60% | 446 12.11% 74.70% | 458 12.43% 87.13% | 474 12.87% 100.00% -system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS::total 3684 -system.ruby.L1Cache_Controller.I_L.Persistent_GETX | 45518 12.52% 12.52% | 45503 12.52% 25.04% | 45434 12.50% 37.54% | 45349 12.48% 50.02% | 45509 12.52% 62.54% | 45334 12.47% 75.01% | 45390 12.49% 87.50% | 45441 12.50% 100.00% -system.ruby.L1Cache_Controller.I_L.Persistent_GETX::total 363478 -system.ruby.L1Cache_Controller.I_L.Persistent_GETS | 81786 12.49% 12.49% | 81763 12.49% 24.98% | 81855 12.50% 37.48% | 81864 12.50% 49.98% | 81922 12.51% 62.49% | 81769 12.49% 74.97% | 82046 12.53% 87.50% | 81829 12.50% 100.00% -system.ruby.L1Cache_Controller.I_L.Persistent_GETS::total 654834 -system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock | 71 11.49% 11.49% | 67 10.84% 22.33% | 70 11.33% 33.66% | 71 11.49% 45.15% | 78 12.62% 57.77% | 72 11.65% 69.42% | 84 13.59% 83.01% | 105 16.99% 100.00% -system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock::total 618 -system.ruby.L1Cache_Controller.S_L.L1_Replacement | 109 12.56% 12.56% | 124 14.29% 26.84% | 128 14.75% 41.59% | 108 12.44% 54.03% | 121 13.94% 67.97% | 116 13.36% 81.34% | 62 7.14% 88.48% | 100 11.52% 100.00% -system.ruby.L1Cache_Controller.S_L.L1_Replacement::total 868 -system.ruby.L1Cache_Controller.S_L.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S_L.Transient_Local_GETX::total 1 -system.ruby.L1Cache_Controller.S_L.Persistent_GETX | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S_L.Persistent_GETX::total 1 -system.ruby.L1Cache_Controller.S_L.Persistent_GETS | 0 0.00% 0.00% | 4 5.33% 5.33% | 7 9.33% 14.67% | 11 14.67% 29.33% | 6 8.00% 37.33% | 16 21.33% 58.67% | 10 13.33% 72.00% | 21 28.00% 100.00% -system.ruby.L1Cache_Controller.S_L.Persistent_GETS::total 75 -system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock | 39 10.05% 10.05% | 40 10.31% 20.36% | 59 15.21% 35.57% | 51 13.14% 48.71% | 42 10.82% 59.54% | 52 13.40% 72.94% | 46 11.86% 84.79% | 59 15.21% 100.00% -system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock::total 388 -system.ruby.L1Cache_Controller.IM_L.L1_Replacement | 658 13.92% 13.92% | 546 11.55% 25.48% | 482 10.20% 35.67% | 488 10.33% 46.00% | 587 12.42% 58.42% | 762 16.12% 74.55% | 736 15.57% 90.12% | 467 9.88% 100.00% -system.ruby.L1Cache_Controller.IM_L.L1_Replacement::total 4726 -system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens | 0 0.00% 0.00% | 3 25.00% 25.00% | 1 8.33% 33.33% | 2 16.67% 50.00% | 1 8.33% 58.33% | 1 8.33% 66.67% | 1 8.33% 75.00% | 3 25.00% 100.00% -system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens::total 12 -system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% +system.ruby.L1Cache_Controller.M.Persistent_GETS | 36 16.36% 16.36% | 32 14.55% 30.91% | 20 9.09% 40.00% | 24 10.91% 50.91% | 27 12.27% 63.18% | 26 11.82% 75.00% | 31 14.09% 89.09% | 24 10.91% 100.00% +system.ruby.L1Cache_Controller.M.Persistent_GETS::total 220 +system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock | 1544 12.49% 12.49% | 1604 12.98% 25.48% | 1578 12.77% 38.25% | 1508 12.20% 50.45% | 1549 12.54% 62.98% | 1497 12.11% 75.10% | 1552 12.56% 87.66% | 1525 12.34% 100.00% +system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock::total 12357 +system.ruby.L1Cache_Controller.MM.Load | 1 6.25% 6.25% | 2 12.50% 18.75% | 2 12.50% 31.25% | 2 12.50% 43.75% | 3 18.75% 62.50% | 3 18.75% 81.25% | 2 12.50% 93.75% | 1 6.25% 100.00% +system.ruby.L1Cache_Controller.MM.Load::total 16 +system.ruby.L1Cache_Controller.MM.Store | 1 11.11% 11.11% | 0 0.00% 11.11% | 1 11.11% 22.22% | 2 22.22% 44.44% | 0 0.00% 44.44% | 4 44.44% 88.89% | 1 11.11% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.MM.Store::total 9 +system.ruby.L1Cache_Controller.MM.L1_Replacement | 27714 12.44% 12.44% | 27777 12.47% 24.92% | 27951 12.55% 37.46% | 28022 12.58% 50.05% | 27723 12.45% 62.49% | 28154 12.64% 75.14% | 27879 12.52% 87.65% | 27500 12.35% 100.00% +system.ruby.L1Cache_Controller.MM.L1_Replacement::total 222720 +system.ruby.L1Cache_Controller.MM.Transient_Local_GETX | 18 16.98% 16.98% | 12 11.32% 28.30% | 14 13.21% 41.51% | 14 13.21% 54.72% | 8 7.55% 62.26% | 17 16.04% 78.30% | 9 8.49% 86.79% | 14 13.21% 100.00% +system.ruby.L1Cache_Controller.MM.Transient_Local_GETX::total 106 +system.ruby.L1Cache_Controller.MM.Transient_Local_GETS | 14 8.09% 8.09% | 20 11.56% 19.65% | 27 15.61% 35.26% | 14 8.09% 43.35% | 24 13.87% 57.23% | 29 16.76% 73.99% | 19 10.98% 84.97% | 26 15.03% 100.00% +system.ruby.L1Cache_Controller.MM.Transient_Local_GETS::total 173 +system.ruby.L1Cache_Controller.MM.Persistent_GETX | 8 14.55% 14.55% | 5 9.09% 23.64% | 6 10.91% 34.55% | 6 10.91% 45.45% | 8 14.55% 60.00% | 5 9.09% 69.09% | 7 12.73% 81.82% | 10 18.18% 100.00% +system.ruby.L1Cache_Controller.MM.Persistent_GETX::total 55 +system.ruby.L1Cache_Controller.MM.Persistent_GETS | 14 14.89% 14.89% | 8 8.51% 23.40% | 15 15.96% 39.36% | 10 10.64% 50.00% | 13 13.83% 63.83% | 15 15.96% 79.79% | 7 7.45% 87.23% | 12 12.77% 100.00% +system.ruby.L1Cache_Controller.MM.Persistent_GETS::total 94 +system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock | 814 11.97% 11.97% | 872 12.82% 24.78% | 871 12.80% 37.59% | 802 11.79% 49.38% | 885 13.01% 62.38% | 911 13.39% 75.78% | 828 12.17% 87.95% | 820 12.05% 100.00% +system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock::total 6803 +system.ruby.L1Cache_Controller.M_W.Load | 5 9.09% 9.09% | 12 21.82% 30.91% | 4 7.27% 38.18% | 5 9.09% 47.27% | 8 14.55% 61.82% | 6 10.91% 72.73% | 11 20.00% 92.73% | 4 7.27% 100.00% +system.ruby.L1Cache_Controller.M_W.Load::total 55 +system.ruby.L1Cache_Controller.M_W.Store | 5 16.67% 16.67% | 3 10.00% 26.67% | 2 6.67% 33.33% | 2 6.67% 40.00% | 5 16.67% 56.67% | 4 13.33% 70.00% | 3 10.00% 80.00% | 6 20.00% 100.00% +system.ruby.L1Cache_Controller.M_W.Store::total 30 +system.ruby.L1Cache_Controller.M_W.L1_Replacement | 368001 12.55% 12.55% | 367387 12.53% 25.08% | 364960 12.45% 37.53% | 365705 12.47% 50.01% | 366083 12.49% 62.50% | 366138 12.49% 74.99% | 365181 12.46% 87.44% | 368148 12.56% 100.00% +system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 2931603 +system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX | 49 11.01% 11.01% | 37 8.31% 19.33% | 60 13.48% 32.81% | 64 14.38% 47.19% | 69 15.51% 62.70% | 53 11.91% 74.61% | 54 12.13% 86.74% | 59 13.26% 100.00% +system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX::total 445 +system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS | 119 13.46% 13.46% | 114 12.90% 26.36% | 91 10.29% 36.65% | 100 11.31% 47.96% | 111 12.56% 60.52% | 129 14.59% 75.11% | 105 11.88% 86.99% | 115 13.01% 100.00% +system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS::total 884 +system.ruby.L1Cache_Controller.M_W.Persistent_GETX | 7 6.09% 6.09% | 13 11.30% 17.39% | 15 13.04% 30.43% | 18 15.65% 46.09% | 16 13.91% 60.00% | 19 16.52% 76.52% | 10 8.70% 85.22% | 17 14.78% 100.00% +system.ruby.L1Cache_Controller.M_W.Persistent_GETX::total 115 +system.ruby.L1Cache_Controller.M_W.Persistent_GETS | 14 7.41% 7.41% | 11 5.82% 13.23% | 26 13.76% 26.98% | 20 10.58% 37.57% | 25 13.23% 50.79% | 26 13.76% 64.55% | 33 17.46% 82.01% | 34 17.99% 100.00% +system.ruby.L1Cache_Controller.M_W.Persistent_GETS::total 189 +system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock | 1068 12.52% 12.52% | 1087 12.75% 25.27% | 1113 13.05% 38.32% | 1079 12.65% 50.97% | 1065 12.49% 63.46% | 1029 12.07% 75.53% | 1063 12.46% 87.99% | 1024 12.01% 100.00% +system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock::total 8528 +system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX | 7 5.56% 5.56% | 13 10.32% 15.87% | 17 13.49% 29.37% | 19 15.08% 44.44% | 16 12.70% 57.14% | 20 15.87% 73.02% | 15 11.90% 84.92% | 19 15.08% 100.00% +system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX::total 126 +system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS | 14 6.76% 6.76% | 13 6.28% 13.04% | 26 12.56% 25.60% | 23 11.11% 36.71% | 29 14.01% 50.72% | 27 13.04% 63.77% | 36 17.39% 81.16% | 39 18.84% 100.00% +system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS::total 207 +system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers | 50414 12.57% 12.57% | 50220 12.52% 25.09% | 50109 12.49% 37.59% | 50206 12.52% 50.11% | 50119 12.50% 62.60% | 49914 12.45% 75.05% | 49786 12.41% 87.46% | 50275 12.54% 100.00% +system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers::total 401043 +system.ruby.L1Cache_Controller.MM_W.Load | 4 13.33% 13.33% | 5 16.67% 30.00% | 3 10.00% 40.00% | 4 13.33% 53.33% | 1 3.33% 56.67% | 4 13.33% 70.00% | 7 23.33% 93.33% | 2 6.67% 100.00% +system.ruby.L1Cache_Controller.MM_W.Load::total 30 +system.ruby.L1Cache_Controller.MM_W.Store | 2 15.38% 15.38% | 1 7.69% 23.08% | 1 7.69% 30.77% | 1 7.69% 38.46% | 2 15.38% 53.85% | 2 15.38% 69.23% | 1 7.69% 76.92% | 3 23.08% 100.00% +system.ruby.L1Cache_Controller.MM_W.Store::total 13 +system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 203874 12.47% 12.47% | 204301 12.50% 24.97% | 203682 12.46% 37.43% | 204611 12.52% 49.95% | 202828 12.41% 62.35% | 206627 12.64% 74.99% | 204717 12.52% 87.52% | 204080 12.48% 100.00% +system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 1634720 +system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX | 40 13.56% 13.56% | 39 13.22% 26.78% | 34 11.53% 38.31% | 40 13.56% 51.86% | 38 12.88% 64.75% | 49 16.61% 81.36% | 33 11.19% 92.54% | 22 7.46% 100.00% +system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX::total 295 +system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS | 63 13.04% 13.04% | 54 11.18% 24.22% | 66 13.66% 37.89% | 58 12.01% 49.90% | 56 11.59% 61.49% | 54 11.18% 72.67% | 59 12.22% 84.89% | 73 15.11% 100.00% +system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS::total 483 +system.ruby.L1Cache_Controller.MM_W.Persistent_GETX | 3 4.17% 4.17% | 4 5.56% 9.72% | 9 12.50% 22.22% | 7 9.72% 31.94% | 10 13.89% 45.83% | 9 12.50% 58.33% | 17 23.61% 81.94% | 13 18.06% 100.00% +system.ruby.L1Cache_Controller.MM_W.Persistent_GETX::total 72 +system.ruby.L1Cache_Controller.MM_W.Persistent_GETS | 9 8.26% 8.26% | 6 5.50% 13.76% | 9 8.26% 22.02% | 10 9.17% 31.19% | 22 20.18% 51.38% | 23 21.10% 72.48% | 15 13.76% 86.24% | 15 13.76% 100.00% +system.ruby.L1Cache_Controller.MM_W.Persistent_GETS::total 109 +system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock | 604 12.79% 12.79% | 622 13.18% 25.97% | 622 13.18% 39.14% | 599 12.69% 51.83% | 595 12.60% 64.44% | 603 12.77% 77.21% | 525 11.12% 88.33% | 551 11.67% 100.00% +system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock::total 4721 +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX | 3 3.90% 3.90% | 4 5.19% 9.09% | 9 11.69% 20.78% | 7 9.09% 29.87% | 10 12.99% 42.86% | 10 12.99% 55.84% | 19 24.68% 80.52% | 15 19.48% 100.00% +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX::total 77 +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS | 12 10.62% 10.62% | 6 5.31% 15.93% | 9 7.96% 23.89% | 10 8.85% 32.74% | 22 19.47% 52.21% | 24 21.24% 73.45% | 15 13.27% 86.73% | 15 13.27% 100.00% +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS::total 113 +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers | 27766 12.44% 12.44% | 27821 12.47% 24.91% | 28012 12.55% 37.47% | 28063 12.58% 50.04% | 27775 12.45% 62.49% | 28217 12.65% 75.14% | 27919 12.51% 87.65% | 27562 12.35% 100.00% +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers::total 223135 +system.ruby.L1Cache_Controller.IM.L1_Replacement | 293829 12.43% 12.43% | 294288 12.45% 24.89% | 297278 12.58% 37.47% | 297532 12.59% 50.06% | 292259 12.37% 62.42% | 298219 12.62% 75.04% | 295523 12.51% 87.55% | 294226 12.45% 100.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement::total 2363154 +system.ruby.L1Cache_Controller.IM.Data_All_Tokens | 27773 12.44% 12.44% | 27827 12.46% 24.90% | 28028 12.55% 37.45% | 28078 12.58% 50.03% | 27803 12.45% 62.48% | 28244 12.65% 75.13% | 27946 12.52% 87.65% | 27585 12.35% 100.00% +system.ruby.L1Cache_Controller.IM.Data_All_Tokens::total 223284 +system.ruby.L1Cache_Controller.IM.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.IM.Ack::total 2 +system.ruby.L1Cache_Controller.IM.Transient_Local_GETX | 89 12.34% 12.34% | 84 11.65% 23.99% | 108 14.98% 38.97% | 75 10.40% 49.38% | 73 10.12% 59.50% | 92 12.76% 72.26% | 104 14.42% 86.69% | 96 13.31% 100.00% +system.ruby.L1Cache_Controller.IM.Transient_Local_GETX::total 721 +system.ruby.L1Cache_Controller.IM.Transient_Local_GETS | 180 13.16% 13.16% | 148 10.82% 23.98% | 194 14.18% 38.16% | 147 10.75% 48.90% | 178 13.01% 61.92% | 183 13.38% 75.29% | 165 12.06% 87.35% | 173 12.65% 100.00% +system.ruby.L1Cache_Controller.IM.Transient_Local_GETS::total 1368 +system.ruby.L1Cache_Controller.IM.Persistent_GETX | 15 7.58% 7.58% | 23 11.62% 19.19% | 28 14.14% 33.33% | 23 11.62% 44.95% | 23 11.62% 56.57% | 26 13.13% 69.70% | 33 16.67% 86.36% | 27 13.64% 100.00% +system.ruby.L1Cache_Controller.IM.Persistent_GETX::total 198 +system.ruby.L1Cache_Controller.IM.Persistent_GETS | 42 12.10% 12.10% | 31 8.93% 21.04% | 40 11.53% 32.56% | 47 13.54% 46.11% | 42 12.10% 58.21% | 45 12.97% 71.18% | 55 15.85% 87.03% | 45 12.97% 100.00% +system.ruby.L1Cache_Controller.IM.Persistent_GETS::total 347 +system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock | 5813 12.38% 12.38% | 5806 12.36% 24.74% | 5927 12.62% 37.37% | 5944 12.66% 50.02% | 5905 12.58% 62.60% | 5925 12.62% 75.22% | 5900 12.56% 87.78% | 5737 12.22% 100.00% +system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock::total 46957 +system.ruby.L1Cache_Controller.IM.Request_Timeout | 40928 12.51% 12.51% | 40339 12.33% 24.84% | 40691 12.44% 37.28% | 41426 12.66% 49.94% | 40569 12.40% 62.34% | 42216 12.90% 75.24% | 40851 12.49% 87.73% | 40139 12.27% 100.00% +system.ruby.L1Cache_Controller.IM.Request_Timeout::total 327159 +system.ruby.L1Cache_Controller.IS.L1_Replacement | 535929 12.62% 12.62% | 531889 12.53% 25.15% | 530564 12.50% 37.64% | 531367 12.51% 50.16% | 533202 12.56% 62.72% | 528282 12.44% 75.16% | 524494 12.35% 87.51% | 530355 12.49% 100.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement::total 4246082 +system.ruby.L1Cache_Controller.IS.Data_Shared | 151 12.09% 12.09% | 154 12.33% 24.42% | 144 11.53% 35.95% | 165 13.21% 49.16% | 141 11.29% 60.45% | 147 11.77% 72.22% | 170 13.61% 85.83% | 177 14.17% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Shared::total 1249 +system.ruby.L1Cache_Controller.IS.Data_Owner | 64 14.85% 14.85% | 57 13.23% 28.07% | 59 13.69% 41.76% | 54 12.53% 54.29% | 52 12.06% 66.36% | 56 12.99% 79.35% | 38 8.82% 88.17% | 51 11.83% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Owner::total 431 +system.ruby.L1Cache_Controller.IS.Data_All_Tokens | 50440 12.57% 12.57% | 50246 12.52% 25.09% | 50151 12.49% 37.58% | 50247 12.52% 50.10% | 50165 12.50% 62.60% | 49962 12.45% 75.05% | 49832 12.42% 87.46% | 50330 12.54% 100.00% +system.ruby.L1Cache_Controller.IS.Data_All_Tokens::total 401373 +system.ruby.L1Cache_Controller.IS.Transient_Local_GETX | 201 14.57% 14.57% | 147 10.65% 25.22% | 201 14.57% 39.78% | 171 12.39% 52.17% | 172 12.46% 64.64% | 184 13.33% 77.97% | 144 10.43% 88.41% | 160 11.59% 100.00% +system.ruby.L1Cache_Controller.IS.Transient_Local_GETX::total 1380 +system.ruby.L1Cache_Controller.IS.Transient_Local_GETS | 334 13.51% 13.51% | 299 12.09% 25.60% | 274 11.08% 36.68% | 294 11.89% 48.56% | 317 12.82% 61.38% | 292 11.81% 73.19% | 336 13.59% 86.78% | 327 13.22% 100.00% +system.ruby.L1Cache_Controller.IS.Transient_Local_GETS::total 2473 +system.ruby.L1Cache_Controller.IS.Persistent_GETX | 46 11.86% 11.86% | 49 12.63% 24.48% | 53 13.66% 38.14% | 48 12.37% 50.52% | 51 13.14% 63.66% | 47 12.11% 75.77% | 41 10.57% 86.34% | 53 13.66% 100.00% +system.ruby.L1Cache_Controller.IS.Persistent_GETX::total 388 +system.ruby.L1Cache_Controller.IS.Persistent_GETS | 68 10.09% 10.09% | 78 11.57% 21.66% | 70 10.39% 32.05% | 99 14.69% 46.74% | 89 13.20% 59.94% | 91 13.50% 73.44% | 94 13.95% 87.39% | 85 12.61% 100.00% +system.ruby.L1Cache_Controller.IS.Persistent_GETS::total 674 +system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock | 10744 12.55% 12.55% | 10736 12.54% 25.09% | 10707 12.51% 37.60% | 10817 12.64% 50.23% | 10654 12.44% 62.68% | 10612 12.40% 75.07% | 10635 12.42% 87.49% | 10706 12.51% 100.00% +system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock::total 85611 +system.ruby.L1Cache_Controller.IS.Request_Timeout | 72575 12.35% 12.35% | 73377 12.49% 24.85% | 74350 12.66% 37.50% | 74310 12.65% 50.15% | 73874 12.58% 62.73% | 72578 12.36% 75.08% | 73347 12.49% 87.57% | 73021 12.43% 100.00% +system.ruby.L1Cache_Controller.IS.Request_Timeout::total 587432 +system.ruby.L1Cache_Controller.I_L.Load | 76 11.84% 11.84% | 71 11.06% 22.90% | 76 11.84% 34.74% | 64 9.97% 44.70% | 94 14.64% 59.35% | 81 12.62% 71.96% | 94 14.64% 86.60% | 86 13.40% 100.00% +system.ruby.L1Cache_Controller.I_L.Load::total 642 +system.ruby.L1Cache_Controller.I_L.Store | 51 14.96% 14.96% | 37 10.85% 25.81% | 46 13.49% 39.30% | 47 13.78% 53.08% | 47 13.78% 66.86% | 33 9.68% 76.54% | 41 12.02% 88.56% | 39 11.44% 100.00% +system.ruby.L1Cache_Controller.I_L.Store::total 341 +system.ruby.L1Cache_Controller.I_L.L1_Replacement | 393 10.96% 10.96% | 357 9.95% 20.91% | 349 9.73% 30.64% | 428 11.93% 42.57% | 589 16.42% 58.99% | 509 14.19% 73.18% | 506 14.11% 87.29% | 456 12.71% 100.00% +system.ruby.L1Cache_Controller.I_L.L1_Replacement::total 3587 +system.ruby.L1Cache_Controller.I_L.Data_All_Tokens | 94 21.71% 21.71% | 82 18.94% 40.65% | 67 15.47% 56.12% | 57 13.16% 69.28% | 43 9.93% 79.21% | 51 11.78% 90.99% | 22 5.08% 96.07% | 17 3.93% 100.00% +system.ruby.L1Cache_Controller.I_L.Data_All_Tokens::total 433 +system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX | 243 12.64% 12.64% | 257 13.36% 26.00% | 240 12.48% 38.48% | 235 12.22% 50.70% | 231 12.01% 62.71% | 229 11.91% 74.62% | 235 12.22% 86.84% | 253 13.16% 100.00% +system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX::total 1923 +system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS | 450 12.27% 12.27% | 482 13.14% 25.41% | 464 12.65% 38.06% | 463 12.62% 50.68% | 444 12.10% 62.79% | 459 12.51% 75.30% | 459 12.51% 87.81% | 447 12.19% 100.00% +system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS::total 3668 +system.ruby.L1Cache_Controller.I_L.Persistent_GETX | 45396 12.52% 12.52% | 45363 12.51% 25.04% | 45210 12.47% 37.51% | 45228 12.48% 49.99% | 45261 12.49% 62.48% | 45241 12.48% 74.96% | 45319 12.50% 87.46% | 45459 12.54% 100.00% +system.ruby.L1Cache_Controller.I_L.Persistent_GETX::total 362477 +system.ruby.L1Cache_Controller.I_L.Persistent_GETS | 82609 12.50% 12.50% | 82595 12.50% 25.00% | 82589 12.50% 37.50% | 82459 12.48% 49.98% | 82626 12.50% 62.48% | 82687 12.51% 75.00% | 82597 12.50% 87.50% | 82607 12.50% 100.00% +system.ruby.L1Cache_Controller.I_L.Persistent_GETS::total 660769 +system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock | 59 10.15% 10.15% | 49 8.43% 18.59% | 69 11.88% 30.46% | 70 12.05% 42.51% | 91 15.66% 58.18% | 87 14.97% 73.15% | 78 13.43% 86.57% | 78 13.43% 100.00% +system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock::total 581 +system.ruby.L1Cache_Controller.S_L.L1_Replacement | 142 14.42% 14.42% | 139 14.11% 28.53% | 85 8.63% 37.16% | 113 11.47% 48.63% | 125 12.69% 61.32% | 129 13.10% 74.42% | 149 15.13% 89.54% | 103 10.46% 100.00% +system.ruby.L1Cache_Controller.S_L.L1_Replacement::total 985 +system.ruby.L1Cache_Controller.S_L.Transient_Local_GETS | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S_L.Transient_Local_GETS::total 1 +system.ruby.L1Cache_Controller.S_L.Persistent_GETS | 0 0.00% 0.00% | 2 2.47% 2.47% | 7 8.64% 11.11% | 7 8.64% 19.75% | 13 16.05% 35.80% | 11 13.58% 49.38% | 17 20.99% 70.37% | 24 29.63% 100.00% +system.ruby.L1Cache_Controller.S_L.Persistent_GETS::total 81 +system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock | 51 11.70% 11.70% | 46 10.55% 22.25% | 49 11.24% 33.49% | 48 11.01% 44.50% | 57 13.07% 57.57% | 54 12.39% 69.95% | 68 15.60% 85.55% | 63 14.45% 100.00% +system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock::total 436 +system.ruby.L1Cache_Controller.IM_L.L1_Replacement | 565 10.94% 10.94% | 424 8.21% 19.15% | 773 14.97% 34.12% | 681 13.19% 47.31% | 662 12.82% 60.13% | 600 11.62% 71.75% | 945 18.30% 90.05% | 514 9.95% 100.00% +system.ruby.L1Cache_Controller.IM_L.L1_Replacement::total 5164 +system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens | 3 21.43% 21.43% | 1 7.14% 28.57% | 1 7.14% 35.71% | 0 0.00% 35.71% | 0 0.00% 35.71% | 3 21.43% 57.14% | 4 28.57% 85.71% | 2 14.29% 100.00% +system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens::total 14 +system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETX | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETX::total 2 -system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETS | 1 12.50% 12.50% | 2 25.00% 37.50% | 1 12.50% 50.00% | 2 25.00% 75.00% | 0 0.00% 75.00% | 1 12.50% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETS::total 8 -system.ruby.L1Cache_Controller.IM_L.Persistent_GETX | 2 5.00% 5.00% | 1 2.50% 7.50% | 3 7.50% 15.00% | 5 12.50% 27.50% | 3 7.50% 35.00% | 6 15.00% 50.00% | 15 37.50% 87.50% | 5 12.50% 100.00% -system.ruby.L1Cache_Controller.IM_L.Persistent_GETX::total 40 -system.ruby.L1Cache_Controller.IM_L.Persistent_GETS | 0 0.00% 0.00% | 2 2.86% 2.86% | 2 2.86% 5.71% | 6 8.57% 14.29% | 8 11.43% 25.71% | 22 31.43% 57.14% | 15 21.43% 78.57% | 15 21.43% 100.00% +system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETS | 0 0.00% 0.00% | 1 16.67% 16.67% | 0 0.00% 16.67% | 5 83.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETS::total 6 +system.ruby.L1Cache_Controller.IM_L.Persistent_GETX | 0 0.00% 0.00% | 2 4.08% 4.08% | 6 12.24% 16.33% | 3 6.12% 22.45% | 6 12.24% 34.69% | 6 12.24% 46.94% | 14 28.57% 75.51% | 12 24.49% 100.00% +system.ruby.L1Cache_Controller.IM_L.Persistent_GETX::total 49 +system.ruby.L1Cache_Controller.IM_L.Persistent_GETS | 0 0.00% 0.00% | 1 1.43% 1.43% | 6 8.57% 10.00% | 7 10.00% 20.00% | 11 15.71% 35.71% | 10 14.29% 50.00% | 21 30.00% 80.00% | 14 20.00% 100.00% system.ruby.L1Cache_Controller.IM_L.Persistent_GETS::total 70 -system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock | 113 13.02% 13.02% | 90 10.37% 23.39% | 103 11.87% 35.25% | 114 13.13% 48.39% | 103 11.87% 60.25% | 120 13.82% 74.08% | 132 15.21% 89.29% | 93 10.71% 100.00% -system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock::total 868 -system.ruby.L1Cache_Controller.IM_L.Request_Timeout | 209 12.85% 12.85% | 193 11.86% 24.71% | 151 9.28% 33.99% | 178 10.94% 44.93% | 141 8.67% 53.60% | 277 17.03% 70.62% | 328 20.16% 90.78% | 150 9.22% 100.00% -system.ruby.L1Cache_Controller.IM_L.Request_Timeout::total 1627 -system.ruby.L1Cache_Controller.IS_L.L1_Replacement | 953 9.60% 9.60% | 1086 10.95% 20.55% | 1230 12.40% 32.95% | 1414 14.25% 47.20% | 1062 10.70% 57.90% | 1323 13.33% 71.24% | 1522 15.34% 86.58% | 1332 13.42% 100.00% -system.ruby.L1Cache_Controller.IS_L.L1_Replacement::total 9922 -system.ruby.L1Cache_Controller.IS_L.Data_Shared | 1 25.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% +system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock | 105 12.04% 12.04% | 90 10.32% 22.36% | 113 12.96% 35.32% | 117 13.42% 48.74% | 112 12.84% 61.58% | 101 11.58% 73.17% | 125 14.33% 87.50% | 109 12.50% 100.00% +system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock::total 872 +system.ruby.L1Cache_Controller.IM_L.Request_Timeout | 157 10.06% 10.06% | 120 7.69% 17.75% | 259 16.59% 34.34% | 210 13.45% 47.79% | 169 10.83% 58.62% | 143 9.16% 67.78% | 356 22.81% 90.58% | 147 9.42% 100.00% +system.ruby.L1Cache_Controller.IM_L.Request_Timeout::total 1561 +system.ruby.L1Cache_Controller.IS_L.L1_Replacement | 1145 11.85% 11.85% | 1078 11.16% 23.01% | 1089 11.27% 34.28% | 1106 11.45% 45.73% | 1258 13.02% 58.75% | 1402 14.51% 73.26% | 1287 13.32% 86.59% | 1296 13.41% 100.00% +system.ruby.L1Cache_Controller.IS_L.L1_Replacement::total 9661 +system.ruby.L1Cache_Controller.IS_L.Data_Shared | 0 0.00% 0.00% | 1 25.00% 25.00% | 0 0.00% 25.00% | 2 50.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.IS_L.Data_Shared::total 4 -system.ruby.L1Cache_Controller.IS_L.Data_Owner | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IS_L.Data_Owner::total 1 -system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens | 1 4.76% 4.76% | 2 9.52% 14.29% | 2 9.52% 23.81% | 2 9.52% 33.33% | 5 23.81% 57.14% | 2 9.52% 66.67% | 3 14.29% 80.95% | 4 19.05% 100.00% -system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens::total 21 -system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETX | 3 50.00% 50.00% | 0 0.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 0 0.00% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETX::total 6 -system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS::total 3 -system.ruby.L1Cache_Controller.IS_L.Persistent_GETX | 2 2.53% 2.53% | 3 3.80% 6.33% | 9 11.39% 17.72% | 10 12.66% 30.38% | 7 8.86% 39.24% | 15 18.99% 58.23% | 19 24.05% 82.28% | 14 17.72% 100.00% -system.ruby.L1Cache_Controller.IS_L.Persistent_GETX::total 79 -system.ruby.L1Cache_Controller.IS_L.Persistent_GETS | 0 0.00% 0.00% | 7 5.04% 5.04% | 8 5.76% 10.79% | 18 12.95% 23.74% | 19 13.67% 37.41% | 21 15.11% 52.52% | 34 24.46% 76.98% | 32 23.02% 100.00% -system.ruby.L1Cache_Controller.IS_L.Persistent_GETS::total 139 -system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock | 193 11.61% 11.61% | 205 12.33% 23.93% | 198 11.91% 35.84% | 222 13.35% 49.19% | 198 11.91% 61.09% | 226 13.59% 74.68% | 219 13.17% 87.85% | 202 12.15% 100.00% -system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock::total 1663 -system.ruby.L1Cache_Controller.IS_L.Request_Timeout | 343 13.11% 13.11% | 326 12.46% 25.57% | 256 9.79% 35.36% | 432 16.51% 51.87% | 247 9.44% 61.31% | 344 13.15% 74.46% | 405 15.48% 89.95% | 263 10.05% 100.00% -system.ruby.L1Cache_Controller.IS_L.Request_Timeout::total 2616 -system.ruby.L2Cache_Controller.L1_GETS 402582 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS_Last_Token 25 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 223760 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_INV 1052 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 510548 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Shared_Data 1063 0.00% 0.00% +system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens | 0 0.00% 0.00% | 3 8.57% 8.57% | 3 8.57% 17.14% | 4 11.43% 28.57% | 5 14.29% 42.86% | 3 8.57% 51.43% | 8 22.86% 74.29% | 9 25.71% 100.00% +system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens::total 35 +system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETX::total 1 +system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS | 2 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 2 33.33% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% +system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS::total 6 +system.ruby.L1Cache_Controller.IS_L.Persistent_GETX | 0 0.00% 0.00% | 5 6.10% 6.10% | 8 9.76% 15.85% | 10 12.20% 28.05% | 6 7.32% 35.37% | 16 19.51% 54.88% | 17 20.73% 75.61% | 20 24.39% 100.00% +system.ruby.L1Cache_Controller.IS_L.Persistent_GETX::total 82 +system.ruby.L1Cache_Controller.IS_L.Persistent_GETS | 0 0.00% 0.00% | 10 7.58% 7.58% | 9 6.82% 14.39% | 15 11.36% 25.76% | 15 11.36% 37.12% | 23 17.42% 54.55% | 34 25.76% 80.30% | 26 19.70% 100.00% +system.ruby.L1Cache_Controller.IS_L.Persistent_GETS::total 132 +system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock | 190 11.41% 11.41% | 194 11.65% 23.06% | 196 11.77% 34.83% | 205 12.31% 47.15% | 229 13.75% 60.90% | 216 12.97% 73.87% | 220 13.21% 87.09% | 215 12.91% 100.00% +system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock::total 1665 +system.ruby.L1Cache_Controller.IS_L.Request_Timeout | 322 10.58% 10.58% | 382 12.55% 23.14% | 377 12.39% 35.52% | 351 11.53% 47.06% | 409 13.44% 60.50% | 501 16.46% 76.96% | 309 10.15% 87.12% | 392 12.88% 100.00% +system.ruby.L1Cache_Controller.IS_L.Request_Timeout::total 3043 +system.ruby.L2Cache_Controller.L1_GETS 403097 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS_Last_Token 10 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 223308 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_INV 1037 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 510458 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_Shared_Data 1095 0.00% 0.00% system.ruby.L2Cache_Controller.Writeback_All_Tokens 623664 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Owned 560 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETX 52074 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETS 93822 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETS_Last_Token 5 0.00% 0.00% -system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 144660 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 401187 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 222975 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_INV 538 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 923 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 509290 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_Owned 343 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 130923 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L1_GETS 106 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L1_GETX 48 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L2_Replacement 13947 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 337 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_Owned 8 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Persistent_GETX 21 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Persistent_GETS 33 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETS_Last_Token 25 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 817 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Writeback_Shared_Data 9 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Writeback_All_Tokens 95 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Writeback_Owned 1 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Persistent_GETS 3 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Persistent_GETS_Last_Token 1 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L1_GETS 21 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L1_GETX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L2_Replacement 768 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Writeback_Shared_Data 2 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 585 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_Owned 588 0.00% 0.00% +system.ruby.L2Cache_Controller.Persistent_GETX 51938 0.00% 0.00% +system.ruby.L2Cache_Controller.Persistent_GETS 94665 0.00% 0.00% +system.ruby.L2Cache_Controller.Persistent_GETS_Last_Token 6 0.00% 0.00% +system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 145349 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 401663 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 222518 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_INV 556 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 896 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 509229 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_Owned 341 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 131369 0.00% 0.00% +system.ruby.L2Cache_Controller.I.L1_GETS 114 0.00% 0.00% +system.ruby.L2Cache_Controller.I.L1_GETX 61 0.00% 0.00% +system.ruby.L2Cache_Controller.I.L1_INV 2 0.00% 0.00% +system.ruby.L2Cache_Controller.I.L2_Replacement 14121 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Writeback_Shared_Data 1 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 358 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Writeback_Owned 4 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Persistent_GETX 23 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Persistent_GETS 39 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L1_GETS_Last_Token 10 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L2_Replacement 829 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Writeback_Shared_Data 12 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Writeback_All_Tokens 84 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Writeback_Owned 2 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Persistent_GETS 5 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Persistent_GETS_Last_Token 2 0.00% 0.00% +system.ruby.L2Cache_Controller.O.L1_GETS 22 0.00% 0.00% +system.ruby.L2Cache_Controller.O.L2_Replacement 773 0.00% 0.00% +system.ruby.L2Cache_Controller.O.Writeback_Shared_Data 10 0.00% 0.00% +system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 572 0.00% 0.00% system.ruby.L2Cache_Controller.O.Persistent_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Persistent_GETS 16 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1020 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 602 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 493835 0.00% 0.00% -system.ruby.L2Cache_Controller.M.Persistent_GETX 5355 0.00% 0.00% -system.ruby.L2Cache_Controller.M.Persistent_GETS 9488 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L1_GETS 248 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L1_GETX 133 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L1_INV 514 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L2_Replacement 1180 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Writeback_Shared_Data 128 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 113357 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Writeback_Owned 208 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Persistent_GETX 46697 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Persistent_GETS 84282 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock 13718 0.00% 0.00% +system.ruby.L2Cache_Controller.O.Persistent_GETS 29 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1028 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 591 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 493571 0.00% 0.00% +system.ruby.L2Cache_Controller.M.Persistent_GETX 5438 0.00% 0.00% +system.ruby.L2Cache_Controller.M.Persistent_GETS 9607 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.L1_GETS 270 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.L1_GETX 138 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.L1_INV 479 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.L2_Replacement 1163 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Writeback_Shared_Data 175 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 113421 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Writeback_Owned 241 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Persistent_GETX 46476 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Persistent_GETS 84985 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock 13945 0.00% 0.00% system.ruby.L2Cache_Controller.S_L.L2_Replacement 1 0.00% 0.00% system.ruby.L2Cache_Controller.S_L.Writeback_Shared_Data 1 0.00% 0.00% system.ruby.L2Cache_Controller.S_L.Persistent_GETS_Last_Token 4 0.00% 0.00% -system.ruby.L2Cache_Controller.S_L.Own_Lock_or_Unlock 19 0.00% 0.00% +system.ruby.L2Cache_Controller.S_L.Own_Lock_or_Unlock 35 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index dfc861f9f..a4e64dc29 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.004743 # Number of seconds simulated -sim_ticks 4742973 # Number of ticks simulated -final_tick 4742973 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.004723 # Number of seconds simulated +sim_ticks 4722948 # Number of ticks simulated +final_tick 4722948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 45769 # Simulator tick rate (ticks/s) -host_mem_usage 536396 # Number of bytes of host memory used -host_seconds 103.63 # Real time elapsed on the host +host_tick_rate 62228 # Simulator tick rate (ticks/s) +host_mem_usage 467464 # Number of bytes of host memory used +host_seconds 75.90 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39054528 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 39054528 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14246976 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 14246976 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 610227 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 610227 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 222609 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 222609 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 8234187291 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 8234187291 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 3003807106 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 3003807106 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 11237994397 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 11237994397 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 610250 # Number of read requests accepted -system.mem_ctrls.writeReqs 222609 # Number of write requests accepted -system.mem_ctrls.readBursts 610250 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 222609 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 38053888 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 1001280 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 14059648 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 39056000 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 14246976 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 15645 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 2873 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 38973248 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 38973248 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14131456 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 14131456 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 608957 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 608957 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 220804 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 220804 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 8251890133 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 8251890133 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 2992083758 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 2992083758 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 11243973891 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 11243973891 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 608977 # Number of read requests accepted +system.mem_ctrls.writeReqs 220804 # Number of write requests accepted +system.mem_ctrls.readBursts 608977 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 220804 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 37976000 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 997824 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 13939200 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 38974528 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 14131456 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 15591 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 2959 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 74498 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 74525 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 74310 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 74504 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 74325 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 73878 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 74319 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 74233 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 74105 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 73980 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 74679 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 74154 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 74161 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 73974 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 74309 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 74013 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts @@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 27489 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 27502 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 27341 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 27543 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 27465 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 27437 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 27510 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 27395 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 27203 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 26999 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 27374 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 27330 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 26957 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 27414 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 27321 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 27202 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts @@ -68,54 +68,54 @@ system.mem_ctrls.perBankWrBursts::13 0 # Pe system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 431 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 4742904 # Total gap between requests +system.mem_ctrls.numWrRetry 424 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 4722934 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 610250 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 608977 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 222609 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 183 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 454 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 882 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 1419 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 2192 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 3210 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 4517 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 5780 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 7330 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 8967 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 11520 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 15720 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 22155 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 32291 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 45169 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 59050 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 69462 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 71920 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 65572 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 51940 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 36463 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 23851 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 16056 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 11838 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 9161 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 7022 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 4894 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 3013 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 1622 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 707 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 216 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 29 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 220804 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 169 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 460 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 895 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 1451 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 2111 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 3075 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 4290 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 5411 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 7051 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 8881 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 11531 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 15691 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 22424 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 32193 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 44982 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 58729 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 70091 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 72682 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 65307 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 51432 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 36131 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 23722 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 15901 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 11796 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 9263 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 7114 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 4981 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 3028 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 1644 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 696 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 224 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 30 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -137,1360 +137,1357 @@ system.mem_ctrls.wrQLenPdf::17 1 # Wh system.mem_ctrls.wrQLenPdf::18 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::20 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 7 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 3 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 4 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 4 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 12 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 18 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 24 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 82 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 130 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 8 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 8 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 25 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 31 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 48 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 74 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 110 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 195 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 238 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 373 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 535 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 708 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 1623 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 3276 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 5749 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 8355 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 10650 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 12348 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 13616 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 14516 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 14996 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 15464 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 16227 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 17053 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 16631 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 15978 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 15996 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 17089 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 10329 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 3468 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 1030 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 747 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 456 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 360 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 319 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 268 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 737 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 219832 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 237.057244 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 187.548428 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 171.370651 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 38260 17.40% 17.40% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 93723 42.63% 60.04% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 45576 20.73% 80.77% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 21096 9.60% 90.37% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 11022 5.01% 95.38% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 5805 2.64% 98.02% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 2645 1.20% 99.22% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1067 0.49% 99.71% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 638 0.29% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 219832 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 13723 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 43.326896 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 31.312521 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 26.132238 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-15 3196 23.29% 23.29% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-31 1709 12.45% 35.74% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::32-47 2313 16.85% 52.60% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::48-63 2707 19.73% 72.32% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::64-79 2779 20.25% 92.57% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-95 955 6.96% 99.53% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::96-111 62 0.45% 99.99% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::112-127 1 0.01% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.wrQLenPdf::35 279 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 528 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 678 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 1538 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 3259 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 5632 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 8230 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 10381 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 12285 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 13587 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 14659 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 15020 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 15616 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 16200 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 16964 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 16340 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 15807 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 15724 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 16997 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 10061 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 3449 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 1011 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 658 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 446 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 318 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 289 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 239 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 718 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 219845 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 236.140481 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 186.921535 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 170.771501 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 38344 17.44% 17.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 94183 42.84% 60.28% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 45510 20.70% 80.98% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 20713 9.42% 90.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 11139 5.07% 95.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 5659 2.57% 98.05% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 2638 1.20% 99.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1011 0.46% 99.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 648 0.29% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 219845 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 13607 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 43.605791 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 31.669532 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 26.121939 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-15 3129 23.00% 23.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-31 1666 12.24% 35.24% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::32-47 2283 16.78% 52.02% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::48-63 2725 20.03% 72.04% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::64-79 2805 20.61% 92.66% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::80-95 914 6.72% 99.38% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::96-111 80 0.59% 99.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::112-127 3 0.02% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::128-143 1 0.01% 99.99% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::272-287 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 13723 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 13723 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.008307 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.006962 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.240707 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 13696 99.80% 99.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 7 0.05% 99.85% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 5 0.04% 99.89% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 3 0.02% 99.91% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 2 0.01% 99.93% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 3 0.02% 99.95% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 1 0.01% 99.96% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 2 0.01% 99.97% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 1 0.01% 99.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 1 0.01% 99.99% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 1 0.01% 99.99% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 13723 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 75132689 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 86429937 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 2972960 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 126.36 # Average queueing delay per DRAM burst +system.mem_ctrls.rdPerTurnAround::total 13607 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 13607 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.006467 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.005210 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.240875 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 13590 99.88% 99.88% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 4 0.03% 99.90% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 3 0.02% 99.93% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 1 0.01% 99.93% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 2 0.01% 99.95% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 1 0.01% 99.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 1 0.01% 99.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 2 0.01% 99.98% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 2 0.01% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::33 1 0.01% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 13607 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 74869628 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 86143753 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 2966875 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 126.17 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 145.36 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 8023.21 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 2964.31 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 8234.50 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 3003.81 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 145.17 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 8040.74 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 2951.38 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 8252.16 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 2992.08 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 85.84 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 62.68 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 23.16 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 19.69 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 50.36 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 380998 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 213441 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 64.08 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 97.14 # Row buffer hit rate for writes +system.mem_ctrls.busUtil 85.88 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 62.82 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 23.06 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 19.71 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 50.33 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 379695 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 211632 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 63.99 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 97.15 # Row buffer hit rate for writes system.mem_ctrls.avgGap 5.69 # Average gap between requests -system.mem_ctrls.pageHitRate 73.00 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 1661582160 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 923101200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 7418785920 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 2277165312 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 309713040 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 3231845964 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 10228800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 15832422396 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 3338.786567 # Core power per rank (mW) +system.mem_ctrls.pageHitRate 72.89 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1660380120 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 922433400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7398231360 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2256004224 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 308187360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 3215945016 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 10178400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 15771359880 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 3342.354273 # Core power per rank (mW) system.mem_ctrls_0.memoryStateTime::IDLE 10 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 158340 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 157560 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 4583633 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 4561082 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 309713040 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 102472776 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 2755263600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 3167449416 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 667.967704 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 4583594 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 158340 # Time in different power states +system.mem_ctrls_1.refreshEnergy 308187360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 101967984 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 2741691600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 3151846944 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.967687 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 4561016 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 157560 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 1 # Clock period in ticks -system.cpu0.num_reads 100001 # number of read accesses completed -system.cpu0.num_writes 55951 # number of write accesses completed -system.cpu1.num_reads 99313 # number of read accesses completed -system.cpu1.num_writes 55361 # number of write accesses completed -system.cpu2.num_reads 99921 # number of read accesses completed -system.cpu2.num_writes 56034 # number of write accesses completed -system.cpu3.num_reads 99775 # number of read accesses completed -system.cpu3.num_writes 55492 # number of write accesses completed -system.cpu4.num_reads 99187 # number of read accesses completed -system.cpu4.num_writes 55780 # number of write accesses completed -system.cpu5.num_reads 99798 # number of read accesses completed -system.cpu5.num_writes 55459 # number of write accesses completed -system.cpu6.num_reads 99746 # number of read accesses completed -system.cpu6.num_writes 56212 # number of write accesses completed -system.cpu7.num_reads 99802 # number of read accesses completed -system.cpu7.num_writes 56048 # number of write accesses completed +system.cpu0.num_reads 99221 # number of read accesses completed +system.cpu0.num_writes 55233 # number of write accesses completed +system.cpu1.num_reads 99634 # number of read accesses completed +system.cpu1.num_writes 55697 # number of write accesses completed +system.cpu2.num_reads 99089 # number of read accesses completed +system.cpu2.num_writes 55519 # number of write accesses completed +system.cpu3.num_reads 100000 # number of read accesses completed +system.cpu3.num_writes 55486 # number of write accesses completed +system.cpu4.num_reads 99397 # number of read accesses completed +system.cpu4.num_writes 55450 # number of write accesses completed +system.cpu5.num_reads 99838 # number of read accesses completed +system.cpu5.num_writes 55386 # number of write accesses completed +system.cpu6.num_reads 99890 # number of read accesses completed +system.cpu6.num_writes 55532 # number of write accesses completed +system.cpu7.num_reads 99124 # number of read accesses completed +system.cpu7.num_writes 55205 # number of write accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 631678 -system.ruby.outstanding_req_hist::mean 15.998455 -system.ruby.outstanding_req_hist::gmean 15.997200 -system.ruby.outstanding_req_hist::stdev 0.125408 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 32 0.01% 0.02% | 631542 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 631678 +system.ruby.outstanding_req_hist::samples 630039 +system.ruby.outstanding_req_hist::mean 15.998449 +system.ruby.outstanding_req_hist::gmean 15.997191 +system.ruby.outstanding_req_hist::stdev 0.125577 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 33 0.01% 0.02% | 629902 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 630039 system.ruby.latency_hist::bucket_size 512 system.ruby.latency_hist::max_bucket 5119 -system.ruby.latency_hist::samples 631550 -system.ruby.latency_hist::mean 961.095964 -system.ruby.latency_hist::gmean 654.936783 -system.ruby.latency_hist::stdev 680.308912 -system.ruby.latency_hist | 215848 34.18% 34.18% | 133828 21.19% 55.37% | 131680 20.85% 76.22% | 107500 17.02% 93.24% | 38687 6.13% 99.37% | 3901 0.62% 99.98% | 106 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 631550 -system.ruby.hit_latency_hist::bucket_size 256 -system.ruby.hit_latency_hist::max_bucket 2559 -system.ruby.hit_latency_hist::samples 621 -system.ruby.hit_latency_hist::mean 73.967794 -system.ruby.hit_latency_hist::gmean 13.390102 -system.ruby.hit_latency_hist::stdev 184.239647 -system.ruby.hit_latency_hist | 568 91.47% 91.47% | 32 5.15% 96.62% | 11 1.77% 98.39% | 6 0.97% 99.36% | 1 0.16% 99.52% | 1 0.16% 99.68% | 1 0.16% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 621 +system.ruby.latency_hist::samples 629911 +system.ruby.latency_hist::mean 959.551335 +system.ruby.latency_hist::gmean 653.122123 +system.ruby.latency_hist::stdev 680.118422 +system.ruby.latency_hist | 216304 34.34% 34.34% | 132336 21.01% 55.35% | 131857 20.93% 76.28% | 106965 16.98% 93.26% | 38659 6.14% 99.40% | 3724 0.59% 99.99% | 66 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 629911 +system.ruby.hit_latency_hist::bucket_size 128 +system.ruby.hit_latency_hist::max_bucket 1279 +system.ruby.hit_latency_hist::samples 662 +system.ruby.hit_latency_hist::mean 64.490937 +system.ruby.hit_latency_hist::gmean 13.604512 +system.ruby.hit_latency_hist::stdev 143.889590 +system.ruby.hit_latency_hist | 564 85.20% 85.20% | 45 6.80% 91.99% | 27 4.08% 96.07% | 10 1.51% 97.58% | 5 0.76% 98.34% | 4 0.60% 98.94% | 4 0.60% 99.55% | 2 0.30% 99.85% | 0 0.00% 99.85% | 1 0.15% 100.00% +system.ruby.hit_latency_hist::total 662 system.ruby.miss_latency_hist::bucket_size 512 system.ruby.miss_latency_hist::max_bucket 5119 -system.ruby.miss_latency_hist::samples 630929 -system.ruby.miss_latency_hist::mean 961.969131 -system.ruby.miss_latency_hist::gmean 657.449215 -system.ruby.miss_latency_hist::stdev 680.049279 -system.ruby.miss_latency_hist | 215248 34.12% 34.12% | 133811 21.21% 55.32% | 131678 20.87% 76.20% | 107498 17.04% 93.23% | 38687 6.13% 99.36% | 3901 0.62% 99.98% | 106 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 630929 -system.ruby.L1Cache.incomplete_times 1061 -system.ruby.Directory.incomplete_times 178013 +system.ruby.miss_latency_hist::samples 629249 +system.ruby.miss_latency_hist::mean 960.492981 +system.ruby.miss_latency_hist::gmean 655.787621 +system.ruby.miss_latency_hist::stdev 679.839862 +system.ruby.miss_latency_hist | 215658 34.27% 34.27% | 132321 21.03% 55.30% | 131856 20.95% 76.26% | 106965 17.00% 93.25% | 38659 6.14% 99.40% | 3724 0.59% 99.99% | 66 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 629249 +system.ruby.L1Cache.incomplete_times 962 +system.ruby.Directory.incomplete_times 176578 system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Dcache.demand_hits 19 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 79264 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 79283 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Dcache.demand_hits 10 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 78639 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78649 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl0.L2cache.demand_hits 46 # Number of cache demand hits -system.ruby.l1_cntrl0.L2cache.demand_misses 79218 # Number of cache demand misses -system.ruby.l1_cntrl0.L2cache.demand_accesses 79264 # Number of cache demand accesses +system.ruby.l1_cntrl0.L2cache.demand_hits 70 # Number of cache demand hits +system.ruby.l1_cntrl0.L2cache.demand_misses 78569 # Number of cache demand misses +system.ruby.l1_cntrl0.L2cache.demand_accesses 78639 # Number of cache demand accesses system.ruby.l1_cntrl0.fully_busy_cycles 19 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl1.L1Dcache.demand_hits 14 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 78562 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78576 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 13 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 78770 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78783 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl1.L2cache.demand_hits 57 # Number of cache demand hits -system.ruby.l1_cntrl1.L2cache.demand_misses 78505 # Number of cache demand misses -system.ruby.l1_cntrl1.L2cache.demand_accesses 78562 # Number of cache demand accesses -system.ruby.l1_cntrl1.fully_busy_cycles 23 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl2.L1Dcache.demand_hits 15 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 79034 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 79049 # Number of cache demand accesses +system.ruby.l1_cntrl1.L2cache.demand_hits 66 # Number of cache demand hits +system.ruby.l1_cntrl1.L2cache.demand_misses 78704 # Number of cache demand misses +system.ruby.l1_cntrl1.L2cache.demand_accesses 78770 # Number of cache demand accesses +system.ruby.l1_cntrl1.fully_busy_cycles 15 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl2.L1Dcache.demand_hits 19 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Dcache.demand_misses 78920 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78939 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl2.L2cache.demand_hits 65 # Number of cache demand hits -system.ruby.l1_cntrl2.L2cache.demand_misses 78969 # Number of cache demand misses -system.ruby.l1_cntrl2.L2cache.demand_accesses 79034 # Number of cache demand accesses -system.ruby.l1_cntrl2.fully_busy_cycles 21 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl3.L1Dcache.demand_hits 18 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 78954 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78972 # Number of cache demand accesses +system.ruby.l1_cntrl2.L2cache.demand_hits 68 # Number of cache demand hits +system.ruby.l1_cntrl2.L2cache.demand_misses 78852 # Number of cache demand misses +system.ruby.l1_cntrl2.L2cache.demand_accesses 78920 # Number of cache demand accesses +system.ruby.l1_cntrl2.fully_busy_cycles 16 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl3.L1Dcache.demand_hits 12 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 78627 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78639 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses system.ruby.l1_cntrl3.L2cache.demand_hits 62 # Number of cache demand hits -system.ruby.l1_cntrl3.L2cache.demand_misses 78892 # Number of cache demand misses -system.ruby.l1_cntrl3.L2cache.demand_accesses 78954 # Number of cache demand accesses -system.ruby.l1_cntrl3.fully_busy_cycles 17 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl4.L1Dcache.demand_hits 14 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Dcache.demand_misses 78583 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78597 # Number of cache demand accesses +system.ruby.l1_cntrl3.L2cache.demand_misses 78565 # Number of cache demand misses +system.ruby.l1_cntrl3.L2cache.demand_accesses 78627 # Number of cache demand accesses +system.ruby.l1_cntrl3.fully_busy_cycles 14 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl4.L1Dcache.demand_hits 19 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Dcache.demand_misses 78575 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78594 # Number of cache demand accesses system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl4.L2cache.demand_hits 67 # Number of cache demand hits -system.ruby.l1_cntrl4.L2cache.demand_misses 78516 # Number of cache demand misses -system.ruby.l1_cntrl4.L2cache.demand_accesses 78583 # Number of cache demand accesses -system.ruby.l1_cntrl4.fully_busy_cycles 18 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl5.L1Dcache.demand_hits 13 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Dcache.demand_misses 78978 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78991 # Number of cache demand accesses +system.ruby.l1_cntrl4.L2cache.demand_hits 52 # Number of cache demand hits +system.ruby.l1_cntrl4.L2cache.demand_misses 78523 # Number of cache demand misses +system.ruby.l1_cntrl4.L2cache.demand_accesses 78575 # Number of cache demand accesses +system.ruby.l1_cntrl4.fully_busy_cycles 17 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl5.L1Dcache.demand_hits 19 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Dcache.demand_misses 78844 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78863 # Number of cache demand accesses system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl5.L2cache.demand_hits 66 # Number of cache demand hits -system.ruby.l1_cntrl5.L2cache.demand_misses 78912 # Number of cache demand misses -system.ruby.l1_cntrl5.L2cache.demand_accesses 78978 # Number of cache demand accesses -system.ruby.l1_cntrl5.fully_busy_cycles 22 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl6.L1Dcache.demand_hits 27 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Dcache.demand_misses 79053 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Dcache.demand_accesses 79080 # Number of cache demand accesses +system.ruby.l1_cntrl5.L2cache.demand_hits 64 # Number of cache demand hits +system.ruby.l1_cntrl5.L2cache.demand_misses 78780 # Number of cache demand misses +system.ruby.l1_cntrl5.L2cache.demand_accesses 78844 # Number of cache demand accesses +system.ruby.l1_cntrl5.fully_busy_cycles 18 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl6.L1Dcache.demand_hits 20 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Dcache.demand_misses 78880 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78900 # Number of cache demand accesses system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl6.L2cache.demand_hits 64 # Number of cache demand hits -system.ruby.l1_cntrl6.L2cache.demand_misses 78989 # Number of cache demand misses -system.ruby.l1_cntrl6.L2cache.demand_accesses 79053 # Number of cache demand accesses -system.ruby.l1_cntrl6.fully_busy_cycles 19 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl7.L1Dcache.demand_hits 12 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Dcache.demand_misses 79018 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Dcache.demand_accesses 79030 # Number of cache demand accesses +system.ruby.l1_cntrl6.L2cache.demand_hits 70 # Number of cache demand hits +system.ruby.l1_cntrl6.L2cache.demand_misses 78810 # Number of cache demand misses +system.ruby.l1_cntrl6.L2cache.demand_accesses 78880 # Number of cache demand accesses +system.ruby.l1_cntrl6.fully_busy_cycles 21 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl7.L1Dcache.demand_hits 14 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Dcache.demand_misses 78558 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78572 # Number of cache demand accesses system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl7.L2cache.demand_hits 62 # Number of cache demand hits -system.ruby.l1_cntrl7.L2cache.demand_misses 78956 # Number of cache demand misses -system.ruby.l1_cntrl7.L2cache.demand_accesses 79018 # Number of cache demand accesses -system.ruby.l1_cntrl7.fully_busy_cycles 18 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl7.L2cache.demand_hits 84 # Number of cache demand hits +system.ruby.l1_cntrl7.L2cache.demand_misses 78474 # Number of cache demand misses +system.ruby.l1_cntrl7.L2cache.demand_accesses 78558 # Number of cache demand accesses +system.ruby.l1_cntrl7.fully_busy_cycles 9 # cycles for which number of transistions == max transitions system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 15.770383 -system.ruby.network.routers0.msg_count.Request_Control::2 79218 -system.ruby.network.routers0.msg_count.Request_Control::3 133 -system.ruby.network.routers0.msg_count.Response_Data::4 81751 -system.ruby.network.routers0.msg_count.Response_Control::4 1099403 -system.ruby.network.routers0.msg_count.Writeback_Data::5 27913 -system.ruby.network.routers0.msg_count.Writeback_Control::2 74694 -system.ruby.network.routers0.msg_count.Writeback_Control::3 74694 -system.ruby.network.routers0.msg_count.Writeback_Control::5 46622 -system.ruby.network.routers0.msg_count.Broadcast_Control::3 550830 -system.ruby.network.routers0.msg_count.Unblock_Control::5 79373 -system.ruby.network.routers0.msg_bytes.Request_Control::2 633744 -system.ruby.network.routers0.msg_bytes.Request_Control::3 1064 -system.ruby.network.routers0.msg_bytes.Response_Data::4 5886072 -system.ruby.network.routers0.msg_bytes.Response_Control::4 8795224 -system.ruby.network.routers0.msg_bytes.Writeback_Data::5 2009736 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-system.ruby.network.routers1.msg_count.Unblock_Control::5 78722 -system.ruby.network.routers1.msg_bytes.Request_Control::2 628040 -system.ruby.network.routers1.msg_bytes.Request_Control::3 944 -system.ruby.network.routers1.msg_bytes.Response_Data::4 5838480 -system.ruby.network.routers1.msg_bytes.Response_Control::4 8761992 -system.ruby.network.routers1.msg_bytes.Writeback_Data::5 1997712 -system.ruby.network.routers1.msg_bytes.Writeback_Control::2 592960 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 592960 -system.ruby.network.routers1.msg_bytes.Writeback_Control::5 369232 -system.ruby.network.routers1.msg_bytes.Broadcast_Control::3 4412192 -system.ruby.network.routers1.msg_bytes.Unblock_Control::5 629776 -system.ruby.network.routers2.percent_links_utilized 15.752899 -system.ruby.network.routers2.msg_count.Request_Control::2 78969 -system.ruby.network.routers2.msg_count.Request_Control::3 145 -system.ruby.network.routers2.msg_count.Response_Data::4 81572 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-system.ruby.network.routers5.msg_bytes.Request_Control::2 631296 -system.ruby.network.routers5.msg_bytes.Request_Control::3 1088 -system.ruby.network.routers5.msg_bytes.Response_Data::4 5867352 -system.ruby.network.routers5.msg_bytes.Response_Control::4 8781840 +system.ruby.network.routers5.msg_count.Writeback_Control::2 74357 +system.ruby.network.routers5.msg_count.Writeback_Control::3 74354 +system.ruby.network.routers5.msg_count.Writeback_Control::5 46458 +system.ruby.network.routers5.msg_count.Broadcast_Control::3 549648 +system.ruby.network.routers5.msg_count.Unblock_Control::5 78962 +system.ruby.network.routers5.msg_bytes.Request_Control::2 630240 +system.ruby.network.routers5.msg_bytes.Request_Control::3 896 +system.ruby.network.routers5.msg_bytes.Response_Data::4 5850072 +system.ruby.network.routers5.msg_bytes.Response_Control::4 8763144 system.ruby.network.routers5.msg_bytes.Writeback_Data::5 1995048 -system.ruby.network.routers5.msg_bytes.Writeback_Control::2 595344 -system.ruby.network.routers5.msg_bytes.Writeback_Control::3 595344 -system.ruby.network.routers5.msg_bytes.Writeback_Control::5 372208 -system.ruby.network.routers5.msg_bytes.Broadcast_Control::3 4408864 -system.ruby.network.routers5.msg_bytes.Unblock_Control::5 632728 -system.ruby.network.routers6.percent_links_utilized 15.747486 -system.ruby.network.routers6.msg_count.Request_Control::2 78989 -system.ruby.network.routers6.msg_count.Request_Control::3 129 -system.ruby.network.routers6.msg_count.Response_Data::4 81543 -system.ruby.network.routers6.msg_count.Response_Control::4 1098074 -system.ruby.network.routers6.msg_count.Writeback_Data::5 27894 -system.ruby.network.routers6.msg_count.Writeback_Control::2 74445 -system.ruby.network.routers6.msg_count.Writeback_Control::3 74445 -system.ruby.network.routers6.msg_count.Writeback_Control::5 46359 -system.ruby.network.routers6.msg_count.Broadcast_Control::3 551045 -system.ruby.network.routers6.msg_count.Unblock_Control::5 79177 -system.ruby.network.routers6.msg_bytes.Request_Control::2 631912 -system.ruby.network.routers6.msg_bytes.Request_Control::3 1032 -system.ruby.network.routers6.msg_bytes.Response_Data::4 5871096 -system.ruby.network.routers6.msg_bytes.Response_Control::4 8784592 -system.ruby.network.routers6.msg_bytes.Writeback_Data::5 2008368 -system.ruby.network.routers6.msg_bytes.Writeback_Control::2 595560 -system.ruby.network.routers6.msg_bytes.Writeback_Control::3 595560 -system.ruby.network.routers6.msg_bytes.Writeback_Control::5 370872 -system.ruby.network.routers6.msg_bytes.Broadcast_Control::3 4408360 -system.ruby.network.routers6.msg_bytes.Unblock_Control::5 633416 -system.ruby.network.routers7.percent_links_utilized 15.747918 -system.ruby.network.routers7.msg_count.Request_Control::2 78956 -system.ruby.network.routers7.msg_count.Request_Control::3 133 -system.ruby.network.routers7.msg_count.Response_Data::4 81554 -system.ruby.network.routers7.msg_count.Response_Control::4 1097823 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-system.ruby.network.routers8.throttle0.msg_count.Writeback_Control::2 595079 -system.ruby.network.routers8.throttle0.msg_count.Writeback_Control::5 370969 -system.ruby.network.routers8.throttle0.msg_count.Unblock_Control::5 632428 -system.ruby.network.routers8.throttle0.msg_bytes.Request_Control::2 5047656 -system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Data::5 16027848 -system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Control::2 4760632 -system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Control::5 2967752 -system.ruby.network.routers8.throttle0.msg_bytes.Unblock_Control::5 5059424 -system.ruby.network.routers8.throttle1.link_utilization 70.820949 -system.ruby.network.routers8.throttle1.msg_count.Request_Control::3 1060 -system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 610223 -system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 595079 -system.ruby.network.routers8.throttle1.msg_count.Broadcast_Control::3 629896 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-system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 74006 -system.ruby.network.routers9.throttle4.msg_count.Broadcast_Control::3 551508 -system.ruby.network.routers9.throttle4.msg_bytes.Request_Control::3 1144 -system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5652936 -system.ruby.network.routers9.throttle4.msg_bytes.Response_Control::4 4370264 -system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 592048 -system.ruby.network.routers9.throttle4.msg_bytes.Broadcast_Control::3 4412064 -system.ruby.network.routers9.throttle5.link_utilization 19.870480 -system.ruby.network.routers9.throttle5.msg_count.Request_Control::3 136 -system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78908 -system.ruby.network.routers9.throttle5.msg_count.Response_Control::4 549069 -system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 74418 -system.ruby.network.routers9.throttle5.msg_count.Broadcast_Control::3 551108 -system.ruby.network.routers9.throttle5.msg_bytes.Request_Control::3 1088 -system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5681376 -system.ruby.network.routers9.throttle5.msg_bytes.Response_Control::4 4392552 -system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 595344 -system.ruby.network.routers9.throttle5.msg_bytes.Broadcast_Control::3 4408864 -system.ruby.network.routers9.throttle6.link_utilization 19.881433 -system.ruby.network.routers9.throttle6.msg_count.Request_Control::3 129 -system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78985 -system.ruby.network.routers9.throttle6.msg_count.Response_Control::4 549458 -system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 74445 -system.ruby.network.routers9.throttle6.msg_count.Broadcast_Control::3 551045 -system.ruby.network.routers9.throttle6.msg_bytes.Request_Control::3 1032 -system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5686920 -system.ruby.network.routers9.throttle6.msg_bytes.Response_Control::4 4395664 -system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 595560 -system.ruby.network.routers9.throttle6.msg_bytes.Broadcast_Control::3 4408360 -system.ruby.network.routers9.throttle7.link_utilization 19.876099 -system.ruby.network.routers9.throttle7.msg_count.Request_Control::3 133 -system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 78952 -system.ruby.network.routers9.throttle7.msg_count.Response_Control::4 549209 -system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 74443 -system.ruby.network.routers9.throttle7.msg_count.Broadcast_Control::3 551083 -system.ruby.network.routers9.throttle7.msg_bytes.Request_Control::3 1064 -system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5684544 -system.ruby.network.routers9.throttle7.msg_bytes.Response_Control::4 4393672 -system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 595544 -system.ruby.network.routers9.throttle7.msg_bytes.Broadcast_Control::3 4408664 -system.ruby.network.routers9.throttle8.link_utilization 44.623003 -system.ruby.network.routers9.throttle8.msg_count.Request_Control::2 630957 -system.ruby.network.routers9.throttle8.msg_count.Writeback_Data::5 222609 -system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::2 595079 -system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::5 370969 -system.ruby.network.routers9.throttle8.msg_count.Unblock_Control::5 632428 -system.ruby.network.routers9.throttle8.msg_bytes.Request_Control::2 5047656 -system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Data::5 16027848 -system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::2 4760632 -system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::5 2967752 -system.ruby.network.routers9.throttle8.msg_bytes.Unblock_Control::5 5059424 +system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Control::2 594856 +system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Control::5 371664 +system.ruby.network.routers5.throttle1.msg_bytes.Unblock_Control::5 631696 +system.ruby.network.routers6.throttle0.link_utilization 19.921255 +system.ruby.network.routers6.throttle0.msg_count.Request_Control::3 118 +system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 78806 +system.ruby.network.routers6.throttle0.msg_count.Response_Control::4 548372 +system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 74372 +system.ruby.network.routers6.throttle0.msg_count.Broadcast_Control::3 549625 +system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::3 944 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5674032 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::4 4386976 +system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 594976 +system.ruby.network.routers6.throttle0.msg_bytes.Broadcast_Control::3 4397000 +system.ruby.network.routers6.throttle1.link_utilization 11.613499 +system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 78810 +system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 2567 +system.ruby.network.routers6.throttle1.msg_count.Response_Control::4 547174 +system.ruby.network.routers6.throttle1.msg_count.Writeback_Data::5 27545 +system.ruby.network.routers6.throttle1.msg_count.Writeback_Control::2 74373 +system.ruby.network.routers6.throttle1.msg_count.Writeback_Control::5 46647 +system.ruby.network.routers6.throttle1.msg_count.Unblock_Control::5 78987 +system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 630480 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4 184824 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::4 4377392 +system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Data::5 1983240 +system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Control::2 594984 +system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Control::5 373176 +system.ruby.network.routers6.throttle1.msg_bytes.Unblock_Control::5 631896 +system.ruby.network.routers7.throttle0.link_utilization 19.865453 +system.ruby.network.routers7.throttle0.msg_count.Request_Control::3 141 +system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 78470 +system.ruby.network.routers7.throttle0.msg_count.Response_Control::4 546131 +system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 74026 +system.ruby.network.routers7.throttle0.msg_count.Broadcast_Control::3 549942 +system.ruby.network.routers7.throttle0.msg_bytes.Request_Control::3 1128 +system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5649840 +system.ruby.network.routers7.throttle0.msg_bytes.Response_Control::4 4369048 +system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 592208 +system.ruby.network.routers7.throttle0.msg_bytes.Broadcast_Control::3 4399536 +system.ruby.network.routers7.throttle1.link_utilization 11.600964 +system.ruby.network.routers7.throttle1.msg_count.Request_Control::2 78474 +system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 2546 +system.ruby.network.routers7.throttle1.msg_count.Response_Control::4 547535 +system.ruby.network.routers7.throttle1.msg_count.Writeback_Data::5 27546 +system.ruby.network.routers7.throttle1.msg_count.Writeback_Control::2 74028 +system.ruby.network.routers7.throttle1.msg_count.Writeback_Control::5 46294 +system.ruby.network.routers7.throttle1.msg_count.Unblock_Control::5 78656 +system.ruby.network.routers7.throttle1.msg_bytes.Request_Control::2 627792 +system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 183312 +system.ruby.network.routers7.throttle1.msg_bytes.Response_Control::4 4380280 +system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Data::5 1983312 +system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Control::2 592224 +system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Control::5 370352 +system.ruby.network.routers7.throttle1.msg_bytes.Unblock_Control::5 629248 +system.ruby.network.routers8.throttle0.link_utilization 44.591164 +system.ruby.network.routers8.throttle0.msg_count.Request_Control::2 629277 +system.ruby.network.routers8.throttle0.msg_count.Writeback_Data::5 220804 +system.ruby.network.routers8.throttle0.msg_count.Writeback_Control::2 593547 +system.ruby.network.routers8.throttle0.msg_count.Writeback_Control::5 371278 +system.ruby.network.routers8.throttle0.msg_count.Unblock_Control::5 630697 +system.ruby.network.routers8.throttle0.msg_bytes.Request_Control::2 5034216 +system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Data::5 15897888 +system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Control::2 4748376 +system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Control::5 2970224 +system.ruby.network.routers8.throttle0.msg_bytes.Unblock_Control::5 5045576 +system.ruby.network.routers8.throttle1.link_utilization 70.965941 +system.ruby.network.routers8.throttle1.msg_count.Request_Control::3 962 +system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 608952 +system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 593536 +system.ruby.network.routers8.throttle1.msg_count.Broadcast_Control::3 628303 +system.ruby.network.routers8.throttle1.msg_bytes.Request_Control::3 7696 +system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 43844544 +system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3 4748288 +system.ruby.network.routers8.throttle1.msg_bytes.Broadcast_Control::3 5026424 +system.ruby.network.routers9.throttle0.link_utilization 19.878030 +system.ruby.network.routers9.throttle0.msg_count.Request_Control::3 120 +system.ruby.network.routers9.throttle0.msg_count.Response_Data::4 78565 +system.ruby.network.routers9.throttle0.msg_count.Response_Control::4 546616 +system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3 73979 +system.ruby.network.routers9.throttle0.msg_count.Broadcast_Control::3 549858 +system.ruby.network.routers9.throttle0.msg_bytes.Request_Control::3 960 +system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5656680 +system.ruby.network.routers9.throttle0.msg_bytes.Response_Control::4 4372928 +system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 591832 +system.ruby.network.routers9.throttle0.msg_bytes.Broadcast_Control::3 4398864 +system.ruby.network.routers9.throttle1.link_utilization 19.905269 +system.ruby.network.routers9.throttle1.msg_count.Request_Control::3 125 +system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 78701 +system.ruby.network.routers9.throttle1.msg_count.Response_Control::4 547781 +system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 74303 +system.ruby.network.routers9.throttle1.msg_count.Broadcast_Control::3 549713 +system.ruby.network.routers9.throttle1.msg_bytes.Request_Control::3 1000 +system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5666472 +system.ruby.network.routers9.throttle1.msg_bytes.Response_Control::4 4382248 +system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 594424 +system.ruby.network.routers9.throttle1.msg_bytes.Broadcast_Control::3 4397704 +system.ruby.network.routers9.throttle2.link_utilization 19.929068 +system.ruby.network.routers9.throttle2.msg_count.Request_Control::3 126 +system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 78848 +system.ruby.network.routers9.throttle2.msg_count.Response_Control::4 548762 +system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 74390 +system.ruby.network.routers9.throttle2.msg_count.Broadcast_Control::3 549569 +system.ruby.network.routers9.throttle2.msg_bytes.Request_Control::3 1008 +system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5677056 +system.ruby.network.routers9.throttle2.msg_bytes.Response_Control::4 4390096 +system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 595120 +system.ruby.network.routers9.throttle2.msg_bytes.Broadcast_Control::3 4396552 +system.ruby.network.routers9.throttle3.link_utilization 19.878326 +system.ruby.network.routers9.throttle3.msg_count.Request_Control::3 100 +system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 78563 +system.ruby.network.routers9.throttle3.msg_count.Response_Control::4 546645 +system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 74010 +system.ruby.network.routers9.throttle3.msg_count.Broadcast_Control::3 549867 +system.ruby.network.routers9.throttle3.msg_bytes.Request_Control::3 800 +system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5656536 +system.ruby.network.routers9.throttle3.msg_bytes.Response_Control::4 4373160 +system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 592080 +system.ruby.network.routers9.throttle3.msg_bytes.Broadcast_Control::3 4398936 +system.ruby.network.routers9.throttle4.link_utilization 19.872641 +system.ruby.network.routers9.throttle4.msg_count.Request_Control::3 120 +system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78519 +system.ruby.network.routers9.throttle4.msg_count.Response_Control::4 546358 +system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 74101 +system.ruby.network.routers9.throttle4.msg_count.Broadcast_Control::3 549899 +system.ruby.network.routers9.throttle4.msg_bytes.Request_Control::3 960 +system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5653368 +system.ruby.network.routers9.throttle4.msg_bytes.Response_Control::4 4370864 +system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 592808 +system.ruby.network.routers9.throttle4.msg_bytes.Broadcast_Control::3 4399192 +system.ruby.network.routers9.throttle5.link_utilization 19.915506 +system.ruby.network.routers9.throttle5.msg_count.Request_Control::3 112 +system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78775 +system.ruby.network.routers9.throttle5.msg_count.Response_Control::4 548109 +system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 74354 +system.ruby.network.routers9.throttle5.msg_count.Broadcast_Control::3 549648 +system.ruby.network.routers9.throttle5.msg_bytes.Request_Control::3 896 +system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5671800 +system.ruby.network.routers9.throttle5.msg_bytes.Response_Control::4 4384872 +system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 594832 +system.ruby.network.routers9.throttle5.msg_bytes.Broadcast_Control::3 4397184 +system.ruby.network.routers9.throttle6.link_utilization 19.921255 +system.ruby.network.routers9.throttle6.msg_count.Request_Control::3 118 +system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78806 +system.ruby.network.routers9.throttle6.msg_count.Response_Control::4 548372 +system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 74372 +system.ruby.network.routers9.throttle6.msg_count.Broadcast_Control::3 549625 +system.ruby.network.routers9.throttle6.msg_bytes.Request_Control::3 944 +system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5674032 +system.ruby.network.routers9.throttle6.msg_bytes.Response_Control::4 4386976 +system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 594976 +system.ruby.network.routers9.throttle6.msg_bytes.Broadcast_Control::3 4397000 +system.ruby.network.routers9.throttle7.link_utilization 19.865453 +system.ruby.network.routers9.throttle7.msg_count.Request_Control::3 141 +system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 78470 +system.ruby.network.routers9.throttle7.msg_count.Response_Control::4 546131 +system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 74026 +system.ruby.network.routers9.throttle7.msg_count.Broadcast_Control::3 549942 +system.ruby.network.routers9.throttle7.msg_bytes.Request_Control::3 1128 +system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5649840 +system.ruby.network.routers9.throttle7.msg_bytes.Response_Control::4 4369048 +system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 592208 +system.ruby.network.routers9.throttle7.msg_bytes.Broadcast_Control::3 4399536 +system.ruby.network.routers9.throttle8.link_utilization 44.591207 +system.ruby.network.routers9.throttle8.msg_count.Request_Control::2 629277 +system.ruby.network.routers9.throttle8.msg_count.Writeback_Data::5 220805 +system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::2 593547 +system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::5 371278 +system.ruby.network.routers9.throttle8.msg_count.Unblock_Control::5 630697 +system.ruby.network.routers9.throttle8.msg_bytes.Request_Control::2 5034216 +system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Data::5 15897960 +system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::2 4748376 +system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::5 2970224 +system.ruby.network.routers9.throttle8.msg_bytes.Unblock_Control::5 5045576 system.ruby.LD.latency_hist::bucket_size 512 system.ruby.LD.latency_hist::max_bucket 5119 -system.ruby.LD.latency_hist::samples 406091 -system.ruby.LD.latency_hist::mean 960.831604 -system.ruby.LD.latency_hist::gmean 654.504897 -system.ruby.LD.latency_hist::stdev 680.362903 -system.ruby.LD.latency_hist | 138898 34.20% 34.20% | 86005 21.18% 55.38% | 84713 20.86% 76.24% | 69041 17.00% 93.24% | 24841 6.12% 99.36% | 2520 0.62% 99.98% | 73 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 406091 -system.ruby.LD.hit_latency_hist::bucket_size 256 -system.ruby.LD.hit_latency_hist::max_bucket 2559 -system.ruby.LD.hit_latency_hist::samples 412 -system.ruby.LD.hit_latency_hist::mean 74.883495 -system.ruby.LD.hit_latency_hist::gmean 14.223923 -system.ruby.LD.hit_latency_hist::stdev 181.196056 -system.ruby.LD.hit_latency_hist | 374 90.78% 90.78% | 24 5.83% 96.60% | 7 1.70% 98.30% | 5 1.21% 99.51% | 1 0.24% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 412 +system.ruby.LD.latency_hist::samples 406290 +system.ruby.LD.latency_hist::mean 960.374656 +system.ruby.LD.latency_hist::gmean 653.723269 +system.ruby.LD.latency_hist::stdev 680.173118 +system.ruby.LD.latency_hist | 139274 34.28% 34.28% | 85290 20.99% 55.27% | 85200 20.97% 76.24% | 69101 17.01% 93.25% | 24962 6.14% 99.39% | 2420 0.60% 99.99% | 43 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 406290 +system.ruby.LD.hit_latency_hist::bucket_size 128 +system.ruby.LD.hit_latency_hist::max_bucket 1279 +system.ruby.LD.hit_latency_hist::samples 444 +system.ruby.LD.hit_latency_hist::mean 62.301802 +system.ruby.LD.hit_latency_hist::gmean 13.718667 +system.ruby.LD.hit_latency_hist::stdev 132.474944 +system.ruby.LD.hit_latency_hist | 374 84.23% 84.23% | 34 7.66% 91.89% | 20 4.50% 96.40% | 8 1.80% 98.20% | 5 1.13% 99.32% | 1 0.23% 99.55% | 1 0.23% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.23% 100.00% +system.ruby.LD.hit_latency_hist::total 444 system.ruby.LD.miss_latency_hist::bucket_size 512 system.ruby.LD.miss_latency_hist::max_bucket 5119 -system.ruby.LD.miss_latency_hist::samples 405679 -system.ruby.LD.miss_latency_hist::mean 961.731357 -system.ruby.LD.miss_latency_hist::gmean 657.054969 -system.ruby.LD.miss_latency_hist::stdev 680.097478 -system.ruby.LD.miss_latency_hist | 138500 34.14% 34.14% | 85993 21.20% 55.34% | 84712 20.88% 76.22% | 69040 17.02% 93.24% | 24841 6.12% 99.36% | 2520 0.62% 99.98% | 73 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 405679 +system.ruby.LD.miss_latency_hist::samples 405846 +system.ruby.LD.miss_latency_hist::mean 961.357158 +system.ruby.LD.miss_latency_hist::gmean 656.492523 +system.ruby.LD.miss_latency_hist::stdev 679.881694 +system.ruby.LD.miss_latency_hist | 138838 34.21% 34.21% | 85283 21.01% 55.22% | 85199 20.99% 76.22% | 69101 17.03% 93.24% | 24962 6.15% 99.39% | 2420 0.60% 99.99% | 43 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 405846 system.ruby.ST.latency_hist::bucket_size 512 system.ruby.ST.latency_hist::max_bucket 5119 -system.ruby.ST.latency_hist::samples 225459 -system.ruby.ST.latency_hist::mean 961.572122 -system.ruby.ST.latency_hist::gmean 655.715404 -system.ruby.ST.latency_hist::stdev 680.212903 -system.ruby.ST.latency_hist | 76950 34.13% 34.13% | 47823 21.21% 55.34% | 46967 20.83% 76.17% | 38459 17.06% 93.23% | 13846 6.14% 99.37% | 1381 0.61% 99.99% | 33 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 225459 -system.ruby.ST.hit_latency_hist::bucket_size 256 -system.ruby.ST.hit_latency_hist::max_bucket 2559 -system.ruby.ST.hit_latency_hist::samples 209 -system.ruby.ST.hit_latency_hist::mean 72.162679 -system.ruby.ST.hit_latency_hist::gmean 11.886830 -system.ruby.ST.hit_latency_hist::stdev 190.526226 -system.ruby.ST.hit_latency_hist | 194 92.82% 92.82% | 8 3.83% 96.65% | 4 1.91% 98.56% | 1 0.48% 99.04% | 0 0.00% 99.04% | 1 0.48% 99.52% | 1 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 209 +system.ruby.ST.latency_hist::samples 223621 +system.ruby.ST.latency_hist::mean 958.055469 +system.ruby.ST.latency_hist::gmean 652.031334 +system.ruby.ST.latency_hist::stdev 680.018005 +system.ruby.ST.latency_hist | 77030 34.45% 34.45% | 47046 21.04% 55.48% | 46657 20.86% 76.35% | 37864 16.93% 93.28% | 13697 6.13% 99.41% | 1304 0.58% 99.99% | 23 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 223621 +system.ruby.ST.hit_latency_hist::bucket_size 128 +system.ruby.ST.hit_latency_hist::max_bucket 1279 +system.ruby.ST.hit_latency_hist::samples 218 +system.ruby.ST.hit_latency_hist::mean 68.949541 +system.ruby.ST.hit_latency_hist::gmean 13.374942 +system.ruby.ST.hit_latency_hist::stdev 164.954210 +system.ruby.ST.hit_latency_hist | 190 87.16% 87.16% | 11 5.05% 92.20% | 7 3.21% 95.41% | 2 0.92% 96.33% | 0 0.00% 96.33% | 3 1.38% 97.71% | 3 1.38% 99.08% | 2 0.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 218 system.ruby.ST.miss_latency_hist::bucket_size 512 system.ruby.ST.miss_latency_hist::max_bucket 5119 -system.ruby.ST.miss_latency_hist::samples 225250 -system.ruby.ST.miss_latency_hist::mean 962.397367 -system.ruby.ST.miss_latency_hist::gmean 658.159856 -system.ruby.ST.miss_latency_hist::stdev 679.963763 -system.ruby.ST.miss_latency_hist | 76748 34.07% 34.07% | 47818 21.23% 55.30% | 46966 20.85% 76.15% | 38458 17.07% 93.23% | 13846 6.15% 99.37% | 1381 0.61% 99.99% | 33 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 225250 +system.ruby.ST.miss_latency_hist::samples 223403 +system.ruby.ST.miss_latency_hist::mean 958.923072 +system.ruby.ST.miss_latency_hist::gmean 654.508995 +system.ruby.ST.miss_latency_hist::stdev 679.762571 +system.ruby.ST.miss_latency_hist | 76820 34.39% 34.39% | 47038 21.06% 55.44% | 46657 20.88% 76.33% | 37864 16.95% 93.27% | 13697 6.13% 99.41% | 1304 0.58% 99.99% | 23 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 223403 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist::samples 132 +system.ruby.L1Cache.hit_mach_latency_hist::samples 126 system.ruby.L1Cache.hit_mach_latency_hist::mean 1 system.ruby.L1Cache.hit_mach_latency_hist::gmean 1 -system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 132 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 132 +system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 126 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist::total 126 system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 512 system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 5119 -system.ruby.L1Cache.miss_mach_latency_hist::samples 23423 -system.ruby.L1Cache.miss_mach_latency_hist::mean 919.039918 -system.ruby.L1Cache.miss_mach_latency_hist::gmean 601.957770 -system.ruby.L1Cache.miss_mach_latency_hist::stdev 673.674189 -system.ruby.L1Cache.miss_mach_latency_hist | 8555 36.52% 36.52% | 4925 21.03% 57.55% | 4756 20.30% 77.86% | 3886 16.59% 94.45% | 1199 5.12% 99.56% | 99 0.42% 99.99% | 3 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_mach_latency_hist::total 23423 +system.ruby.L1Cache.miss_mach_latency_hist::samples 22929 +system.ruby.L1Cache.miss_mach_latency_hist::mean 917.294474 +system.ruby.L1Cache.miss_mach_latency_hist::gmean 599.636042 +system.ruby.L1Cache.miss_mach_latency_hist::stdev 676.350403 +system.ruby.L1Cache.miss_mach_latency_hist | 8471 36.94% 36.94% | 4760 20.76% 57.70% | 4639 20.23% 77.94% | 3735 16.29% 94.23% | 1218 5.31% 99.54% | 105 0.46% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist::total 22929 system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::bucket_size 512 system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::max_bucket 5119 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::samples 22362 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::mean 771.074770 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::gmean 164.369066 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::stdev 668.586052 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request | 9418 42.12% 42.12% | 4751 21.25% 63.36% | 4511 20.17% 83.53% | 3052 13.65% 97.18% | 594 2.66% 99.84% | 34 0.15% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::total 22362 +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::samples 21967 +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::mean 769.291483 +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::gmean 161.408765 +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::stdev 672.554554 +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request | 9332 42.48% 42.48% | 4595 20.92% 63.40% | 4421 20.13% 83.53% | 2933 13.35% 96.88% | 655 2.98% 99.86% | 31 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::total 21967 system.ruby.L1Cache.miss_latency_hist.initial_to_forward::bucket_size 128 system.ruby.L1Cache.miss_latency_hist.initial_to_forward::max_bucket 1279 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::samples 22362 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::mean 49.937707 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::gmean 20.723466 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::stdev 76.918062 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward | 19391 86.71% 86.71% | 2310 10.33% 97.04% | 535 2.39% 99.44% | 70 0.31% 99.75% | 46 0.21% 99.96% | 10 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::total 22362 +system.ruby.L1Cache.miss_latency_hist.initial_to_forward::samples 21967 +system.ruby.L1Cache.miss_latency_hist.initial_to_forward::mean 49.655074 +system.ruby.L1Cache.miss_latency_hist.initial_to_forward::gmean 20.745857 +system.ruby.L1Cache.miss_latency_hist.initial_to_forward::stdev 75.819936 +system.ruby.L1Cache.miss_latency_hist.initial_to_forward | 19070 86.81% 86.81% | 2265 10.31% 97.12% | 517 2.35% 99.48% | 68 0.31% 99.79% | 39 0.18% 99.96% | 8 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_latency_hist.initial_to_forward::total 21967 system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::bucket_size 32 system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::max_bucket 319 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::samples 22362 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::mean 86.767686 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::gmean 71.899838 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::stdev 49.926191 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response | 3731 16.68% 16.68% | 4873 21.79% 38.48% | 5269 23.56% 62.04% | 3438 15.37% 77.41% | 2710 12.12% 89.53% | 1689 7.55% 97.08% | 604 2.70% 99.79% | 47 0.21% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::total 22362 +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::samples 21967 +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::mean 86.871580 +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::gmean 72.228308 +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::stdev 49.302472 +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response | 3616 16.46% 16.46% | 4690 21.35% 37.81% | 5205 23.69% 61.51% | 3592 16.35% 77.86% | 2696 12.27% 90.13% | 1595 7.26% 97.39% | 528 2.40% 99.80% | 42 0.19% 99.99% | 3 0.01% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::total 21967 system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::bucket_size 32 system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::max_bucket 319 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::samples 22362 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::mean 9.805921 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::stdev 22.489320 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion | 20295 90.76% 90.76% | 897 4.01% 94.77% | 716 3.20% 97.97% | 340 1.52% 99.49% | 109 0.49% 99.98% | 5 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::total 22362 -system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 256 -system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 2559 -system.ruby.L2Cache.hit_mach_latency_hist::samples 489 -system.ruby.L2Cache.hit_mach_latency_hist::mean 93.664622 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 26.974066 -system.ruby.L2Cache.hit_mach_latency_hist::stdev 203.216507 -system.ruby.L2Cache.hit_mach_latency_hist | 436 89.16% 89.16% | 32 6.54% 95.71% | 11 2.25% 97.96% | 6 1.23% 99.18% | 1 0.20% 99.39% | 1 0.20% 99.59% | 1 0.20% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 489 +system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::samples 21967 +system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::mean 9.646606 +system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::stdev 22.383574 +system.ruby.L1Cache.miss_latency_hist.first_response_to_completion | 20003 91.06% 91.06% | 858 3.91% 94.97% | 665 3.03% 97.99% | 325 1.48% 99.47% | 99 0.45% 99.92% | 15 0.07% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::total 21967 +system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 128 +system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 1279 +system.ruby.L2Cache.hit_mach_latency_hist::samples 536 +system.ruby.L2Cache.hit_mach_latency_hist::mean 79.416045 +system.ruby.L2Cache.hit_mach_latency_hist::gmean 25.129455 +system.ruby.L2Cache.hit_mach_latency_hist::stdev 156.229930 +system.ruby.L2Cache.hit_mach_latency_hist | 438 81.72% 81.72% | 45 8.40% 90.11% | 27 5.04% 95.15% | 10 1.87% 97.01% | 5 0.93% 97.95% | 4 0.75% 98.69% | 4 0.75% 99.44% | 2 0.37% 99.81% | 0 0.00% 99.81% | 1 0.19% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist::total 536 system.ruby.Directory.miss_mach_latency_hist::bucket_size 512 system.ruby.Directory.miss_mach_latency_hist::max_bucket 5119 -system.ruby.Directory.miss_mach_latency_hist::samples 607506 -system.ruby.Directory.miss_mach_latency_hist::mean 963.624310 -system.ruby.Directory.miss_mach_latency_hist::gmean 659.688266 -system.ruby.Directory.miss_mach_latency_hist::stdev 680.240190 -system.ruby.Directory.miss_mach_latency_hist | 206693 34.02% 34.02% | 128886 21.22% 55.24% | 126922 20.89% 76.13% | 103612 17.06% 93.19% | 37488 6.17% 99.36% | 3802 0.63% 99.98% | 103 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 607506 +system.ruby.Directory.miss_mach_latency_hist::samples 606320 +system.ruby.Directory.miss_mach_latency_hist::mean 962.126605 +system.ruby.Directory.miss_mach_latency_hist::gmean 658.011306 +system.ruby.Directory.miss_mach_latency_hist::stdev 679.918169 +system.ruby.Directory.miss_mach_latency_hist | 207187 34.17% 34.17% | 127561 21.04% 55.21% | 127217 20.98% 76.19% | 103230 17.03% 93.22% | 37441 6.18% 99.39% | 3619 0.60% 99.99% | 65 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 606320 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 512 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 5119 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 429493 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::mean 784.523138 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::gmean 183.145093 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev 667.016025 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 178473 41.55% 41.55% | 91905 21.40% 62.95% | 87742 20.43% 83.38% | 58030 13.51% 96.89% | 12645 2.94% 99.84% | 684 0.16% 100.00% | 14 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 429493 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 429742 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::mean 784.153017 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::gmean 182.710086 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev 666.397335 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 178531 41.54% 41.54% | 92185 21.45% 63.00% | 88049 20.49% 83.48% | 57641 13.41% 96.90% | 12707 2.96% 99.85% | 623 0.14% 100.00% | 6 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 429742 system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 64 system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 639 -system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 429493 -system.ruby.Directory.miss_latency_hist.initial_to_forward::mean 18.538495 -system.ruby.Directory.miss_latency_hist.initial_to_forward::gmean 12.530183 -system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev 21.383945 -system.ruby.Directory.miss_latency_hist.initial_to_forward | 397741 92.61% 92.61% | 31350 7.30% 99.91% | 330 0.08% 99.98% | 46 0.01% 99.99% | 22 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.initial_to_forward::total 429493 +system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 429742 +system.ruby.Directory.miss_latency_hist.initial_to_forward::mean 18.305988 +system.ruby.Directory.miss_latency_hist.initial_to_forward::gmean 12.466522 +system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev 20.935609 +system.ruby.Directory.miss_latency_hist.initial_to_forward | 399534 92.97% 92.97% | 29865 6.95% 99.92% | 276 0.06% 99.98% | 52 0.01% 100.00% | 9 0.00% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.initial_to_forward::total 429742 system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 32 system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 319 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 429493 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::mean 61.817315 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::gmean 53.294699 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev 34.032918 -system.ruby.Directory.miss_latency_hist.forward_to_first_response | 103446 24.09% 24.09% | 148411 34.55% 58.64% | 105271 24.51% 83.15% | 49455 11.51% 94.67% | 18888 4.40% 99.06% | 3847 0.90% 99.96% | 175 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 429493 +system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 429742 +system.ruby.Directory.miss_latency_hist.forward_to_first_response::mean 62.043489 +system.ruby.Directory.miss_latency_hist.forward_to_first_response::gmean 53.541478 +system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev 33.955511 +system.ruby.Directory.miss_latency_hist.forward_to_first_response | 102053 23.75% 23.75% | 148225 34.49% 58.24% | 106521 24.79% 83.03% | 50471 11.74% 94.77% | 18432 4.29% 99.06% | 3871 0.90% 99.96% | 168 0.04% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 429742 system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 128 system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 1279 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 429493 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 141.909822 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev 103.360709 -system.ruby.Directory.miss_latency_hist.first_response_to_completion | 225810 52.58% 52.58% | 153300 35.69% 88.27% | 36208 8.43% 96.70% | 8998 2.10% 98.79% | 5012 1.17% 99.96% | 165 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 429493 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 429742 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 141.234122 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev 102.647241 +system.ruby.Directory.miss_latency_hist.first_response_to_completion | 226604 52.73% 52.73% | 153344 35.68% 88.41% | 35970 8.37% 96.78% | 9098 2.12% 98.90% | 4598 1.07% 99.97% | 128 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 429742 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 80 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 83 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 80 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 80 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 83 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 83 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 13232 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 921.922310 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 599.574827 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 674.352683 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 4814 36.38% 36.38% | 2739 20.70% 57.08% | 2703 20.43% 77.51% | 2261 17.09% 94.60% | 666 5.03% 99.63% | 47 0.36% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 13232 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 256 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 2559 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 332 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 92.686747 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 26.968413 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 197.813008 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 294 88.55% 88.55% | 24 7.23% 95.78% | 7 2.11% 97.89% | 5 1.51% 99.40% | 1 0.30% 99.70% | 0 0.00% 99.70% | 0 0.00% 99.70% | 1 0.30% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 332 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 13098 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 918.714613 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 600.249224 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 672.644684 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 4798 36.63% 36.63% | 2729 20.84% 57.47% | 2722 20.78% 78.25% | 2123 16.21% 94.46% | 664 5.07% 99.53% | 61 0.47% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 13098 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 128 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 1279 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 361 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 76.396122 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 25.049504 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 143.283503 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 291 80.61% 80.61% | 34 9.42% 90.03% | 20 5.54% 95.57% | 8 2.22% 97.78% | 5 1.39% 99.17% | 1 0.28% 99.45% | 1 0.28% 99.72% | 0 0.00% 99.72% | 0 0.00% 99.72% | 1 0.28% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 361 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 392447 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 963.073584 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 659.086204 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 680.250582 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 133686 34.06% 34.06% | 83254 21.21% 55.28% | 82009 20.90% 76.18% | 66779 17.02% 93.19% | 24175 6.16% 99.35% | 2473 0.63% 99.98% | 71 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 392447 +system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 392748 +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 962.779271 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 658.456401 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 680.076496 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 134040 34.13% 34.13% | 82554 21.02% 55.15% | 82477 21.00% 76.15% | 66978 17.05% 93.20% | 24298 6.19% 99.39% | 2359 0.60% 99.99% | 42 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::total 392748 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 52 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 43 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 52 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 52 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-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 10191 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 256 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 2559 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 157 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 95.732484 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 26.986024 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 214.832922 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 142 90.45% 90.45% | 8 5.10% 95.54% | 4 2.55% 98.09% | 1 0.64% 98.73% | 0 0.00% 98.73% | 1 0.64% 99.36% | 1 0.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 157 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 9831 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 915.402401 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 598.820063 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 681.285952 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 3673 37.36% 37.36% | 2031 20.66% 58.02% | 1917 19.50% 77.52% | 1612 16.40% 93.92% | 554 5.64% 99.55% | 44 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 9831 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 128 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 1279 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 175 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 85.645714 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 25.295189 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 180.313043 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 147 84.00% 84.00% | 11 6.29% 90.29% | 7 4.00% 94.29% | 2 1.14% 95.43% | 0 0.00% 95.43% | 3 1.71% 97.14% | 3 1.71% 98.86% | 2 1.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 175 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 215059 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 964.629292 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 660.788346 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 680.221658 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 73007 33.95% 33.95% | 45632 21.22% 55.17% | 44913 20.88% 76.05% | 36833 17.13% 93.18% | 13313 6.19% 99.37% | 1329 0.62% 99.99% | 32 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 215059 -system.ruby.Directory_Controller.GETX 229283 0.00% 0.00% -system.ruby.Directory_Controller.GETS 411874 0.00% 0.00% -system.ruby.Directory_Controller.PUT 609367 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 1501 0.00% 0.00% -system.ruby.Directory_Controller.UnblockS 26308 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 604619 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Clean 8140 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Dirty 1407 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 362829 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 221202 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 610223 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 222609 0.00% 0.00% -system.ruby.Directory_Controller.All_Unblocks 1060 0.00% 0.00% -system.ruby.Directory_Controller.NX.GETX 73 0.00% 0.00% -system.ruby.Directory_Controller.NX.GETS 100 0.00% 0.00% -system.ruby.Directory_Controller.NX.PUT 11010 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 7402 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETS 12071 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 584069 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 9467 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 16592 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 208316 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 375875 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.GETX 541 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.GETS 1060 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.PUT 14039 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockS 8603 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 603072 0.00% 0.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 213572 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 960.926385 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 657.193585 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 679.626872 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 73147 34.25% 34.25% | 45007 21.07% 55.32% | 44740 20.95% 76.27% | 36252 16.97% 93.25% | 13143 6.15% 99.40% | 1260 0.59% 99.99% | 23 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 213572 +system.ruby.Directory_Controller.GETX 227359 0.00% 0.00% +system.ruby.Directory_Controller.GETS 412013 0.00% 0.00% +system.ruby.Directory_Controller.PUT 607708 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 1451 0.00% 0.00% +system.ruby.Directory_Controller.UnblockS 26373 0.00% 0.00% +system.ruby.Directory_Controller.UnblockM 602873 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Clean 8050 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Dirty 1352 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Clean 363228 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 219452 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 608953 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 220804 0.00% 0.00% +system.ruby.Directory_Controller.All_Unblocks 962 0.00% 0.00% +system.ruby.Directory_Controller.NX.GETX 83 0.00% 0.00% +system.ruby.Directory_Controller.NX.GETS 74 0.00% 0.00% +system.ruby.Directory_Controller.NX.PUT 10821 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 7117 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETS 12062 0.00% 0.00% +system.ruby.Directory_Controller.NO.PUT 582725 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 9321 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 16807 0.00% 0.00% +system.ruby.Directory_Controller.E.GETX 206891 0.00% 0.00% +system.ruby.Directory_Controller.E.GETS 375959 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.GETX 569 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.GETS 962 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.PUT 13941 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockS 8535 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockM 601412 0.00% 0.00% system.ruby.Directory_Controller.NO_B_X.GETX 1 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_X.PUT 14 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_X.UnblockS 19 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_X.UnblockM 522 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S.GETX 1 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S.PUT 32 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S.UnblockS 35 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S.UnblockM 1025 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.GETX 1 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.GETS 5 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.PUT 128 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.UnblockS 1061 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.All_Unblocks 1060 0.00% 0.00% -system.ruby.Directory_Controller.O_B.GETX 16 0.00% 0.00% -system.ruby.Directory_Controller.O_B.GETS 19 0.00% 0.00% -system.ruby.Directory_Controller.O_B.UnblockS 16590 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.GETX 1978 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.GETS 3587 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 593633 0.00% 0.00% -system.ruby.Directory_Controller.O_B_W.GETX 51 0.00% 0.00% -system.ruby.Directory_Controller.O_B_W.GETS 109 0.00% 0.00% -system.ruby.Directory_Controller.O_B_W.Memory_Data 16590 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETX 1391 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETS 2390 0.00% 0.00% -system.ruby.Directory_Controller.WB.PUT 75 0.00% 0.00% -system.ruby.Directory_Controller.WB.Unblock 1501 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Clean 8140 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Dirty 1407 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 362829 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 221202 0.00% 0.00% -system.ruby.Directory_Controller.WB_O_W.Memory_Ack 1407 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.GETX 45 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.GETS 65 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 221202 0.00% 0.00% -system.ruby.L1Cache_Controller.Load | 51076 12.57% 12.57% | 50551 12.44% 25.00% | 50770 12.49% 37.50% | 50953 12.54% 50.03% | 50510 12.43% 62.46% | 50964 12.54% 75.00% | 50868 12.52% 87.51% | 50752 12.49% 100.00% -system.ruby.L1Cache_Controller.Load::total 406444 -system.ruby.L1Cache_Controller.Store | 28262 12.52% 12.52% | 28089 12.45% 24.97% | 28349 12.56% 37.53% | 28095 12.45% 49.98% | 28149 12.47% 62.46% | 28108 12.46% 74.91% | 28283 12.53% 87.45% | 28332 12.55% 100.00% -system.ruby.L1Cache_Controller.Store::total 225667 -system.ruby.L1Cache_Controller.L2_Replacement | 78021 12.56% 12.56% | 77301 12.45% 25.01% | 77724 12.51% 37.52% | 77676 12.51% 50.02% | 77281 12.44% 62.47% | 77681 12.51% 74.97% | 77756 12.52% 87.49% | 77698 12.51% 100.00% -system.ruby.L1Cache_Controller.L2_Replacement::total 621138 -system.ruby.L1Cache_Controller.L1_to_L2 | 1269533 12.54% 12.54% | 1259231 12.44% 24.97% | 1267134 12.51% 37.49% | 1266713 12.51% 49.99% | 1261837 12.46% 62.46% | 1266942 12.51% 74.97% | 1268741 12.53% 87.50% | 1266215 12.50% 100.00% -system.ruby.L1Cache_Controller.L1_to_L2::total 10126346 -system.ruby.L1Cache_Controller.Trigger_L2_to_L1D | 47 9.46% 9.46% | 59 11.87% 21.33% | 65 13.08% 34.41% | 63 12.68% 47.08% | 68 13.68% 60.76% | 68 13.68% 74.45% | 65 13.08% 87.53% | 62 12.47% 100.00% -system.ruby.L1Cache_Controller.Trigger_L2_to_L1D::total 497 -system.ruby.L1Cache_Controller.Complete_L2_to_L1 | 47 9.46% 9.46% | 59 11.87% 21.33% | 65 13.08% 34.41% | 63 12.68% 47.08% | 68 13.68% 60.76% | 68 13.68% 74.45% | 65 13.08% 87.53% | 62 12.47% 100.00% -system.ruby.L1Cache_Controller.Complete_L2_to_L1::total 497 -system.ruby.L1Cache_Controller.Other_GETX | 197042 12.50% 12.50% | 197220 12.51% 25.00% | 196965 12.49% 37.50% | 197230 12.51% 50.00% | 197158 12.50% 62.51% | 197197 12.51% 75.01% | 197025 12.50% 87.51% | 196969 12.49% 100.00% -system.ruby.L1Cache_Controller.Other_GETX::total 1576806 -system.ruby.L1Cache_Controller.Other_GETS | 353788 12.49% 12.49% | 354304 12.51% 25.00% | 354075 12.50% 37.50% | 353904 12.49% 49.99% | 354350 12.51% 62.50% | 353911 12.49% 75.00% | 354020 12.50% 87.50% | 354114 12.50% 100.00% -system.ruby.L1Cache_Controller.Other_GETS::total 2832466 -system.ruby.L1Cache_Controller.Merged_GETS | 133 12.55% 12.55% | 118 11.13% 23.68% | 145 13.68% 37.36% | 123 11.60% 48.96% | 143 13.49% 62.45% | 136 12.83% 75.28% | 129 12.17% 87.45% | 133 12.55% 100.00% -system.ruby.L1Cache_Controller.Merged_GETS::total 1060 -system.ruby.L1Cache_Controller.Ack | 550921 12.55% 12.55% | 546153 12.44% 24.99% | 549458 12.52% 37.51% | 548874 12.51% 50.02% | 546236 12.44% 62.46% | 549014 12.51% 74.97% | 549409 12.52% 87.49% | 549153 12.51% 100.00% -system.ruby.L1Cache_Controller.Ack::total 4389218 -system.ruby.L1Cache_Controller.Shared_Ack | 54 13.17% 13.17% | 43 10.49% 23.66% | 49 11.95% 35.61% | 57 13.90% 49.51% | 47 11.46% 60.98% | 55 13.41% 74.39% | 49 11.95% 86.34% | 56 13.66% 100.00% -system.ruby.L1Cache_Controller.Shared_Ack::total 410 -system.ruby.L1Cache_Controller.Data | 3540 12.82% 12.82% | 3306 11.98% 24.80% | 3491 12.65% 37.45% | 3485 12.63% 50.07% | 3428 12.42% 62.49% | 3409 12.35% 74.84% | 3496 12.67% 87.51% | 3448 12.49% 100.00% -system.ruby.L1Cache_Controller.Data::total 27603 -system.ruby.L1Cache_Controller.Shared_Data | 1247 12.83% 12.83% | 1191 12.26% 25.09% | 1201 12.36% 37.45% | 1173 12.07% 49.52% | 1215 12.50% 62.02% | 1212 12.47% 74.49% | 1240 12.76% 87.25% | 1239 12.75% 100.00% -system.ruby.L1Cache_Controller.Shared_Data::total 9718 -system.ruby.L1Cache_Controller.Exclusive_Data | 74429 12.54% 12.54% | 74004 12.47% 25.01% | 74273 12.51% 37.52% | 74229 12.50% 50.02% | 73870 12.44% 62.47% | 74287 12.51% 74.98% | 74249 12.51% 87.49% | 74265 12.51% 100.00% -system.ruby.L1Cache_Controller.Exclusive_Data::total 593606 -system.ruby.L1Cache_Controller.Writeback_Ack | 74694 12.55% 12.55% | 74120 12.46% 25.01% | 74477 12.52% 37.52% | 74476 12.52% 50.04% | 74006 12.44% 62.47% | 74418 12.51% 74.98% | 74445 12.51% 87.49% | 74443 12.51% 100.00% -system.ruby.L1Cache_Controller.Writeback_Ack::total 595079 -system.ruby.L1Cache_Controller.All_acks | 1291 12.80% 12.80% | 1232 12.21% 25.01% | 1245 12.34% 37.36% | 1225 12.14% 49.50% | 1258 12.47% 61.97% | 1263 12.52% 74.49% | 1286 12.75% 87.24% | 1287 12.76% 100.00% -system.ruby.L1Cache_Controller.All_acks::total 10087 -system.ruby.L1Cache_Controller.All_acks_no_sharers | 77925 12.55% 12.55% | 77270 12.45% 25.00% | 77720 12.52% 37.52% | 77663 12.51% 50.03% | 77255 12.44% 62.47% | 77645 12.51% 74.98% | 77699 12.52% 87.49% | 77665 12.51% 100.00% -system.ruby.L1Cache_Controller.All_acks_no_sharers::total 620842 -system.ruby.L1Cache_Controller.I.Load | 51002 12.57% 12.57% | 50467 12.44% 25.01% | 50676 12.49% 37.50% | 50864 12.54% 50.04% | 50416 12.43% 62.47% | 50851 12.53% 75.00% | 50756 12.51% 87.51% | 50667 12.49% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 405699 -system.ruby.L1Cache_Controller.I.Store | 28215 12.53% 12.53% | 28036 12.45% 24.97% | 28293 12.56% 37.53% | 28026 12.44% 49.98% | 28099 12.47% 62.45% | 28059 12.46% 74.91% | 28232 12.53% 87.44% | 28289 12.56% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 225249 -system.ruby.L1Cache_Controller.I.Other_GETX | 195949 12.50% 12.50% | 196072 12.51% 25.01% | 195765 12.49% 37.49% | 196134 12.51% 50.00% | 195992 12.50% 62.51% | 196038 12.50% 75.01% | 195871 12.49% 87.51% | 195868 12.49% 100.00% -system.ruby.L1Cache_Controller.I.Other_GETX::total 1567689 -system.ruby.L1Cache_Controller.I.Other_GETS | 351874 12.49% 12.49% | 352426 12.51% 25.00% | 352187 12.50% 37.50% | 351932 12.49% 49.99% | 352421 12.51% 62.50% | 352026 12.50% 75.00% | 352179 12.50% 87.50% | 352158 12.50% 100.00% -system.ruby.L1Cache_Controller.I.Other_GETS::total 2817203 -system.ruby.L1Cache_Controller.S.Load | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory_Controller.NO_B_X.PUT 20 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_X.UnblockS 31 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_X.UnblockM 538 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S.PUT 29 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S.UnblockS 39 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S.UnblockM 923 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.GETX 4 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.GETS 1 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.PUT 112 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.UnblockS 962 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.All_Unblocks 962 0.00% 0.00% +system.ruby.Directory_Controller.O_B.GETX 10 0.00% 0.00% +system.ruby.Directory_Controller.O_B.GETS 32 0.00% 0.00% +system.ruby.Directory_Controller.O_B.UnblockS 16806 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.GETX 1902 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.GETS 3515 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.Memory_Data 592146 0.00% 0.00% +system.ruby.Directory_Controller.O_B_W.GETX 49 0.00% 0.00% +system.ruby.Directory_Controller.O_B_W.GETS 101 0.00% 0.00% +system.ruby.Directory_Controller.O_B_W.Memory_Data 16807 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETX 1378 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETS 2421 0.00% 0.00% +system.ruby.Directory_Controller.WB.PUT 60 0.00% 0.00% +system.ruby.Directory_Controller.WB.Unblock 1451 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Clean 8050 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Dirty 1352 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 363228 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 219452 0.00% 0.00% +system.ruby.Directory_Controller.WB_O_W.Memory_Ack 1352 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.GETX 34 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.GETS 79 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.Memory_Ack 219452 0.00% 0.00% +system.ruby.L1Cache_Controller.Load | 50971 12.54% 12.54% | 50665 12.46% 25.00% | 50845 12.50% 37.50% | 50743 12.48% 49.98% | 50754 12.48% 62.46% | 50895 12.52% 74.98% | 51016 12.55% 87.52% | 50730 12.48% 100.00% +system.ruby.L1Cache_Controller.Load::total 406619 +system.ruby.L1Cache_Controller.Store | 27735 12.39% 12.39% | 28186 12.59% 24.99% | 28157 12.58% 37.57% | 27944 12.49% 50.05% | 27882 12.46% 62.51% | 28029 12.52% 75.03% | 27949 12.49% 87.52% | 27925 12.48% 100.00% +system.ruby.L1Cache_Controller.Store::total 223807 +system.ruby.L1Cache_Controller.L2_Replacement | 77360 12.48% 12.48% | 77497 12.51% 24.99% | 77632 12.53% 37.52% | 77372 12.49% 50.01% | 77315 12.48% 62.48% | 77607 12.52% 75.01% | 77589 12.52% 87.53% | 77281 12.47% 100.00% +system.ruby.L1Cache_Controller.L2_Replacement::total 619653 +system.ruby.L1Cache_Controller.L1_to_L2 | 1262689 12.50% 12.50% | 1264010 12.51% 25.01% | 1265832 12.53% 37.54% | 1258023 12.45% 50.00% | 1260220 12.48% 62.47% | 1264438 12.52% 74.99% | 1265548 12.53% 87.52% | 1260958 12.48% 100.00% +system.ruby.L1Cache_Controller.L1_to_L2::total 10101718 +system.ruby.L1Cache_Controller.Trigger_L2_to_L1D | 73 13.20% 13.20% | 67 12.12% 25.32% | 70 12.66% 37.97% | 65 11.75% 49.73% | 55 9.95% 59.67% | 67 12.12% 71.79% | 71 12.84% 84.63% | 85 15.37% 100.00% +system.ruby.L1Cache_Controller.Trigger_L2_to_L1D::total 553 +system.ruby.L1Cache_Controller.Complete_L2_to_L1 | 73 13.20% 13.20% | 67 12.12% 25.32% | 70 12.66% 37.97% | 65 11.75% 49.73% | 55 9.95% 59.67% | 67 12.12% 71.79% | 71 12.84% 84.63% | 85 15.37% 100.00% +system.ruby.L1Cache_Controller.Complete_L2_to_L1::total 553 +system.ruby.L1Cache_Controller.Other_GETX | 195724 12.52% 12.52% | 195274 12.49% 25.00% | 195314 12.49% 37.49% | 195506 12.50% 49.99% | 195571 12.51% 62.50% | 195421 12.50% 74.99% | 195515 12.50% 87.50% | 195545 12.50% 100.00% +system.ruby.L1Cache_Controller.Other_GETX::total 1563870 +system.ruby.L1Cache_Controller.Other_GETS | 354134 12.49% 12.49% | 354439 12.51% 25.00% | 354255 12.50% 37.50% | 354361 12.50% 50.00% | 354328 12.50% 62.50% | 354227 12.50% 75.00% | 354110 12.49% 87.50% | 354397 12.50% 100.00% +system.ruby.L1Cache_Controller.Other_GETS::total 2834251 +system.ruby.L1Cache_Controller.Merged_GETS | 120 12.47% 12.47% | 125 12.99% 25.47% | 126 13.10% 38.57% | 100 10.40% 48.96% | 120 12.47% 61.43% | 112 11.64% 73.08% | 118 12.27% 85.34% | 141 14.66% 100.00% +system.ruby.L1Cache_Controller.Merged_GETS::total 962 +system.ruby.L1Cache_Controller.Ack | 546565 12.48% 12.48% | 547738 12.51% 24.99% | 548718 12.53% 37.53% | 546605 12.48% 50.01% | 546312 12.48% 62.49% | 548045 12.52% 75.00% | 548316 12.52% 87.53% | 546087 12.47% 100.00% +system.ruby.L1Cache_Controller.Ack::total 4378386 +system.ruby.L1Cache_Controller.Shared_Ack | 51 13.14% 13.14% | 43 11.08% 24.23% | 44 11.34% 35.57% | 40 10.31% 45.88% | 46 11.86% 57.73% | 64 16.49% 74.23% | 56 14.43% 88.66% | 44 11.34% 100.00% +system.ruby.L1Cache_Controller.Shared_Ack::total 388 +system.ruby.L1Cache_Controller.Data | 3541 12.82% 12.82% | 3379 12.23% 25.05% | 3493 12.65% 37.70% | 3551 12.86% 50.55% | 3408 12.34% 62.89% | 3461 12.53% 75.42% | 3404 12.32% 87.75% | 3385 12.25% 100.00% +system.ruby.L1Cache_Controller.Data::total 27622 +system.ruby.L1Cache_Controller.Shared_Data | 1202 12.56% 12.56% | 1159 12.11% 24.68% | 1180 12.33% 37.01% | 1226 12.81% 49.83% | 1192 12.46% 62.29% | 1221 12.76% 75.05% | 1195 12.49% 87.54% | 1192 12.46% 100.00% +system.ruby.L1Cache_Controller.Shared_Data::total 9567 +system.ruby.L1Cache_Controller.Exclusive_Data | 73822 12.47% 12.47% | 74163 12.53% 25.00% | 74175 12.53% 37.52% | 73785 12.46% 49.99% | 73919 12.49% 62.47% | 74093 12.51% 74.99% | 74207 12.53% 87.52% | 73893 12.48% 100.00% +system.ruby.L1Cache_Controller.Exclusive_Data::total 592057 +system.ruby.L1Cache_Controller.Writeback_Ack | 73979 12.46% 12.46% | 74303 12.52% 24.98% | 74390 12.53% 37.52% | 74010 12.47% 49.99% | 74101 12.48% 62.47% | 74354 12.53% 75.00% | 74372 12.53% 87.53% | 74026 12.47% 100.00% +system.ruby.L1Cache_Controller.Writeback_Ack::total 593535 +system.ruby.L1Cache_Controller.All_acks | 1249 12.60% 12.60% | 1194 12.04% 24.64% | 1213 12.23% 36.87% | 1266 12.77% 49.64% | 1237 12.47% 62.11% | 1277 12.88% 74.99% | 1248 12.59% 87.58% | 1232 12.42% 100.00% +system.ruby.L1Cache_Controller.All_acks::total 9916 +system.ruby.L1Cache_Controller.All_acks_no_sharers | 77316 12.48% 12.48% | 77507 12.51% 25.00% | 77635 12.54% 37.53% | 77297 12.48% 50.01% | 77282 12.48% 62.49% | 77499 12.51% 75.01% | 77559 12.52% 87.53% | 77238 12.47% 100.00% +system.ruby.L1Cache_Controller.All_acks_no_sharers::total 619333 +system.ruby.L1Cache_Controller.I.Load | 50883 12.54% 12.54% | 50568 12.46% 25.00% | 50755 12.51% 37.50% | 50661 12.48% 49.98% | 50684 12.49% 62.47% | 50791 12.51% 74.99% | 50914 12.54% 87.53% | 50609 12.47% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 405865 +system.ruby.L1Cache_Controller.I.Store | 27682 12.39% 12.39% | 28135 12.59% 24.99% | 28094 12.58% 37.56% | 27901 12.49% 50.05% | 27835 12.46% 62.51% | 27986 12.53% 75.04% | 27895 12.49% 87.53% | 27863 12.47% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 223391 +system.ruby.L1Cache_Controller.I.Other_GETX | 194570 12.51% 12.51% | 194171 12.49% 25.00% | 194237 12.49% 37.49% | 194432 12.50% 49.99% | 194464 12.51% 62.50% | 194330 12.50% 75.00% | 194397 12.50% 87.50% | 194438 12.50% 100.00% +system.ruby.L1Cache_Controller.I.Other_GETX::total 1555039 +system.ruby.L1Cache_Controller.I.Other_GETS | 352245 12.49% 12.49% | 352525 12.50% 25.00% | 352324 12.50% 37.50% | 352485 12.50% 50.00% | 352423 12.50% 62.50% | 352389 12.50% 75.00% | 352205 12.49% 87.49% | 352535 12.51% 100.00% +system.ruby.L1Cache_Controller.I.Other_GETS::total 2819131 +system.ruby.L1Cache_Controller.S.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.S.Load::total 3 -system.ruby.L1Cache_Controller.S.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Store::total 1 -system.ruby.L1Cache_Controller.S.L2_Replacement | 3327 12.77% 12.77% | 3181 12.21% 24.97% | 3247 12.46% 37.43% | 3200 12.28% 49.71% | 3275 12.57% 62.28% | 3263 12.52% 74.80% | 3311 12.71% 87.51% | 3255 12.49% 100.00% -system.ruby.L1Cache_Controller.S.L2_Replacement::total 26059 -system.ruby.L1Cache_Controller.S.L1_to_L2 | 3358 12.77% 12.77% | 3212 12.21% 24.98% | 3286 12.50% 37.48% | 3229 12.28% 49.76% | 3298 12.54% 62.30% | 3299 12.55% 74.85% | 3334 12.68% 87.53% | 3280 12.47% 100.00% -system.ruby.L1Cache_Controller.S.L1_to_L2::total 26296 -system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D | 5 25.00% 25.00% | 5 25.00% 50.00% | 2 10.00% 60.00% | 1 5.00% 65.00% | 1 5.00% 70.00% | 3 15.00% 85.00% | 3 15.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D::total 20 -system.ruby.L1Cache_Controller.S.Other_GETX | 26 10.83% 10.83% | 30 12.50% 23.33% | 41 17.08% 40.42% | 30 12.50% 52.92% | 26 10.83% 63.75% | 35 14.58% 78.33% | 23 9.58% 87.92% | 29 12.08% 100.00% -system.ruby.L1Cache_Controller.S.Other_GETX::total 240 -system.ruby.L1Cache_Controller.S.Other_GETS | 46 11.22% 11.22% | 43 10.49% 21.71% | 45 10.98% 32.68% | 57 13.90% 46.59% | 58 14.15% 60.73% | 53 12.93% 73.66% | 45 10.98% 84.63% | 63 15.37% 100.00% -system.ruby.L1Cache_Controller.S.Other_GETS::total 410 -system.ruby.L1Cache_Controller.O.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.L1Cache_Controller.O.Load::total 1 -system.ruby.L1Cache_Controller.O.L2_Replacement | 836 12.15% 12.15% | 853 12.40% 24.55% | 870 12.65% 37.20% | 865 12.57% 49.77% | 871 12.66% 62.44% | 879 12.78% 75.21% | 844 12.27% 87.48% | 861 12.52% 100.00% -system.ruby.L1Cache_Controller.O.L2_Replacement::total 6879 -system.ruby.L1Cache_Controller.O.L1_to_L2 | 57 9.55% 9.55% | 71 11.89% 21.44% | 77 12.90% 34.34% | 80 13.40% 47.74% | 76 12.73% 60.47% | 80 13.40% 73.87% | 83 13.90% 87.77% | 73 12.23% 100.00% -system.ruby.L1Cache_Controller.O.L1_to_L2::total 597 -system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D | 1 16.67% 16.67% | 1 16.67% 33.33% | 0 0.00% 33.33% | 2 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% -system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D::total 6 -system.ruby.L1Cache_Controller.O.Other_GETX | 11 23.91% 23.91% | 1 2.17% 26.09% | 7 15.22% 41.30% | 4 8.70% 50.00% | 7 15.22% 65.22% | 6 13.04% 78.26% | 6 13.04% 91.30% | 4 8.70% 100.00% -system.ruby.L1Cache_Controller.O.Other_GETX::total 46 -system.ruby.L1Cache_Controller.O.Other_GETS | 11 18.03% 18.03% | 5 8.20% 26.23% | 4 6.56% 32.79% | 7 11.48% 44.26% | 11 18.03% 62.30% | 8 13.11% 75.41% | 8 13.11% 88.52% | 7 11.48% 100.00% -system.ruby.L1Cache_Controller.O.Other_GETS::total 61 -system.ruby.L1Cache_Controller.O.Merged_GETS | 3 16.67% 16.67% | 1 5.56% 22.22% | 3 16.67% 38.89% | 2 11.11% 50.00% | 2 11.11% 61.11% | 3 16.67% 77.78% | 3 16.67% 94.44% | 1 5.56% 100.00% -system.ruby.L1Cache_Controller.O.Merged_GETS::total 18 -system.ruby.L1Cache_Controller.M.Load | 6 28.57% 28.57% | 2 9.52% 38.10% | 3 14.29% 52.38% | 6 28.57% 80.95% | 1 4.76% 85.71% | 1 4.76% 90.48% | 1 4.76% 95.24% | 1 4.76% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 21 -system.ruby.L1Cache_Controller.M.Store | 4 23.53% 23.53% | 0 0.00% 23.53% | 4 23.53% 47.06% | 3 17.65% 64.71% | 1 5.88% 70.59% | 0 0.00% 70.59% | 4 23.53% 94.12% | 1 5.88% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 17 -system.ruby.L1Cache_Controller.M.L2_Replacement | 46372 12.57% 12.57% | 45955 12.46% 25.03% | 46049 12.48% 37.51% | 46319 12.56% 50.07% | 45786 12.41% 62.48% | 46227 12.53% 75.02% | 46095 12.50% 87.51% | 46061 12.49% 100.00% -system.ruby.L1Cache_Controller.M.L2_Replacement::total 368864 -system.ruby.L1Cache_Controller.M.L1_to_L2 | 47565 12.56% 12.56% | 47164 12.45% 25.01% | 47305 12.49% 37.50% | 47546 12.55% 50.06% | 47035 12.42% 62.48% | 47471 12.53% 75.01% | 47324 12.50% 87.51% | 47308 12.49% 100.00% -system.ruby.L1Cache_Controller.M.L1_to_L2::total 378718 -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D | 20 6.78% 6.78% | 35 11.86% 18.64% | 45 15.25% 33.90% | 40 13.56% 47.46% | 43 14.58% 62.03% | 37 12.54% 74.58% | 32 10.85% 85.42% | 43 14.58% 100.00% -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D::total 295 -system.ruby.L1Cache_Controller.M.Other_GETX | 454 12.03% 12.03% | 474 12.56% 24.60% | 480 12.72% 37.32% | 458 12.14% 49.46% | 463 12.27% 61.73% | 480 12.72% 74.45% | 487 12.91% 87.36% | 477 12.64% 100.00% -system.ruby.L1Cache_Controller.M.Other_GETX::total 3773 -system.ruby.L1Cache_Controller.M.Other_GETS | 741 12.28% 12.28% | 752 12.47% 24.75% | 752 12.47% 37.22% | 771 12.78% 50.00% | 758 12.57% 62.57% | 768 12.73% 75.30% | 736 12.20% 87.50% | 754 12.50% 100.00% -system.ruby.L1Cache_Controller.M.Other_GETS::total 6032 -system.ruby.L1Cache_Controller.M.Merged_GETS | 62 11.42% 11.42% | 50 9.21% 20.63% | 77 14.18% 34.81% | 61 11.23% 46.04% | 78 14.36% 60.41% | 63 11.60% 72.01% | 84 15.47% 87.48% | 68 12.52% 100.00% -system.ruby.L1Cache_Controller.M.Merged_GETS::total 543 -system.ruby.L1Cache_Controller.MM.Load | 3 20.00% 20.00% | 3 20.00% 40.00% | 1 6.67% 46.67% | 3 20.00% 66.67% | 1 6.67% 73.33% | 0 0.00% 73.33% | 1 6.67% 80.00% | 3 20.00% 100.00% -system.ruby.L1Cache_Controller.MM.Load::total 15 -system.ruby.L1Cache_Controller.MM.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 7.14% 7.14% | 1 7.14% 14.29% | 2 14.29% 28.57% | 6 42.86% 71.43% | 3 21.43% 92.86% | 1 7.14% 100.00% -system.ruby.L1Cache_Controller.MM.Store::total 14 -system.ruby.L1Cache_Controller.MM.L2_Replacement | 27486 12.53% 12.53% | 27312 12.45% 24.98% | 27558 12.56% 37.55% | 27292 12.44% 49.99% | 27349 12.47% 62.46% | 27312 12.45% 74.91% | 27506 12.54% 87.45% | 27521 12.55% 100.00% -system.ruby.L1Cache_Controller.MM.L2_Replacement::total 219336 -system.ruby.L1Cache_Controller.MM.L1_to_L2 | 28183 12.52% 12.52% | 28013 12.44% 24.96% | 28286 12.56% 37.53% | 28018 12.45% 49.97% | 28080 12.47% 62.45% | 28050 12.46% 74.91% | 28217 12.53% 87.44% | 28272 12.56% 100.00% -system.ruby.L1Cache_Controller.MM.L1_to_L2::total 225119 -system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D | 21 11.93% 11.93% | 18 10.23% 22.16% | 18 10.23% 32.39% | 20 11.36% 43.75% | 24 13.64% 57.39% | 28 15.91% 73.30% | 29 16.48% 89.77% | 18 10.23% 100.00% -system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D::total 176 -system.ruby.L1Cache_Controller.MM.Other_GETX | 259 12.03% 12.03% | 265 12.31% 24.34% | 278 12.91% 37.25% | 268 12.45% 49.70% | 293 13.61% 63.31% | 278 12.91% 76.22% | 260 12.08% 88.30% | 252 11.70% 100.00% -system.ruby.L1Cache_Controller.MM.Other_GETX::total 2153 -system.ruby.L1Cache_Controller.MM.Other_GETS | 436 12.41% 12.41% | 421 11.98% 24.39% | 429 12.21% 36.60% | 443 12.61% 49.20% | 435 12.38% 61.58% | 420 11.95% 73.53% | 445 12.66% 86.20% | 485 13.80% 100.00% -system.ruby.L1Cache_Controller.MM.Other_GETS::total 3514 -system.ruby.L1Cache_Controller.MM.Merged_GETS | 44 12.50% 12.50% | 53 15.06% 27.56% | 48 13.64% 41.19% | 38 10.80% 51.99% | 42 11.93% 63.92% | 54 15.34% 79.26% | 30 8.52% 87.78% | 43 12.22% 100.00% -system.ruby.L1Cache_Controller.MM.Merged_GETS::total 352 -system.ruby.L1Cache_Controller.SR.Load | 4 28.57% 28.57% | 4 28.57% 57.14% | 2 14.29% 71.43% | 1 7.14% 78.57% | 0 0.00% 78.57% | 1 7.14% 85.71% | 2 14.29% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SR.Load::total 14 -system.ruby.L1Cache_Controller.SR.Store | 1 16.67% 16.67% | 1 16.67% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 2 33.33% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SR.Store::total 6 -system.ruby.L1Cache_Controller.SR.L1_to_L2 | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SR.L1_to_L2::total 2 -system.ruby.L1Cache_Controller.OR.Load | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% -system.ruby.L1Cache_Controller.OR.Load::total 4 -system.ruby.L1Cache_Controller.OR.Store | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OR.Store::total 2 -system.ruby.L1Cache_Controller.OR.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OR.L1_to_L2::total 7 -system.ruby.L1Cache_Controller.MR.Load | 14 6.97% 6.97% | 22 10.95% 17.91% | 30 14.93% 32.84% | 24 11.94% 44.78% | 26 12.94% 57.71% | 31 15.42% 73.13% | 24 11.94% 85.07% | 30 14.93% 100.00% -system.ruby.L1Cache_Controller.MR.Load::total 201 -system.ruby.L1Cache_Controller.MR.Store | 6 6.38% 6.38% | 13 13.83% 20.21% | 15 15.96% 36.17% | 16 17.02% 53.19% | 17 18.09% 71.28% | 6 6.38% 77.66% | 8 8.51% 86.17% | 13 13.83% 100.00% -system.ruby.L1Cache_Controller.MR.Store::total 94 -system.ruby.L1Cache_Controller.MR.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 77.78% 77.78% | 0 0.00% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.MR.L1_to_L2::total 9 -system.ruby.L1Cache_Controller.MMR.Load | 13 11.50% 11.50% | 10 8.85% 20.35% | 12 10.62% 30.97% | 10 8.85% 39.82% | 16 14.16% 53.98% | 21 18.58% 72.57% | 18 15.93% 88.50% | 13 11.50% 100.00% -system.ruby.L1Cache_Controller.MMR.Load::total 113 -system.ruby.L1Cache_Controller.MMR.Store | 8 12.70% 12.70% | 8 12.70% 25.40% | 6 9.52% 34.92% | 10 15.87% 50.79% | 8 12.70% 63.49% | 7 11.11% 74.60% | 11 17.46% 92.06% | 5 7.94% 100.00% -system.ruby.L1Cache_Controller.MMR.Store::total 63 -system.ruby.L1Cache_Controller.MMR.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 16.67% 16.67% | 1 16.67% 33.33% | 1 16.67% 50.00% | 3 50.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Store | 1 25.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% +system.ruby.L1Cache_Controller.S.Store::total 4 +system.ruby.L1Cache_Controller.S.L2_Replacement | 3379 12.94% 12.94% | 3194 12.23% 25.18% | 3240 12.41% 37.59% | 3362 12.88% 50.47% | 3212 12.30% 62.77% | 3250 12.45% 75.22% | 3216 12.32% 87.54% | 3253 12.46% 100.00% +system.ruby.L1Cache_Controller.S.L2_Replacement::total 26106 +system.ruby.L1Cache_Controller.S.L1_to_L2 | 3414 12.95% 12.95% | 3228 12.24% 25.19% | 3282 12.45% 37.64% | 3389 12.85% 50.49% | 3250 12.33% 62.82% | 3282 12.45% 75.27% | 3240 12.29% 87.56% | 3280 12.44% 100.00% +system.ruby.L1Cache_Controller.S.L1_to_L2::total 26365 +system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D | 8 25.00% 25.00% | 3 9.38% 34.38% | 3 9.38% 43.75% | 3 9.38% 53.12% | 5 15.62% 68.75% | 5 15.62% 84.38% | 1 3.12% 87.50% | 4 12.50% 100.00% +system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D::total 32 +system.ruby.L1Cache_Controller.S.Other_GETX | 29 11.79% 11.79% | 34 13.82% 25.61% | 38 15.45% 41.06% | 26 10.57% 51.63% | 34 13.82% 65.45% | 31 12.60% 78.05% | 28 11.38% 89.43% | 26 10.57% 100.00% +system.ruby.L1Cache_Controller.S.Other_GETX::total 246 +system.ruby.L1Cache_Controller.S.Other_GETS | 61 15.72% 15.72% | 40 10.31% 26.03% | 51 13.14% 39.18% | 45 11.60% 50.77% | 54 13.92% 64.69% | 49 12.63% 77.32% | 38 9.79% 87.11% | 50 12.89% 100.00% +system.ruby.L1Cache_Controller.S.Other_GETS::total 388 +system.ruby.L1Cache_Controller.O.L2_Replacement | 837 12.41% 12.41% | 884 13.10% 25.51% | 862 12.78% 38.29% | 816 12.10% 50.39% | 866 12.84% 63.22% | 809 11.99% 75.21% | 832 12.33% 87.55% | 840 12.45% 100.00% +system.ruby.L1Cache_Controller.O.L2_Replacement::total 6746 +system.ruby.L1Cache_Controller.O.L1_to_L2 | 69 12.97% 12.97% | 78 14.66% 27.63% | 53 9.96% 37.59% | 54 10.15% 47.74% | 78 14.66% 62.41% | 61 11.47% 73.87% | 61 11.47% 85.34% | 78 14.66% 100.00% +system.ruby.L1Cache_Controller.O.L1_to_L2::total 532 +system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D | 2 20.00% 20.00% | 1 10.00% 30.00% | 1 10.00% 40.00% | 2 20.00% 60.00% | 1 10.00% 70.00% | 1 10.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% +system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D::total 10 +system.ruby.L1Cache_Controller.O.Other_GETX | 7 15.91% 15.91% | 5 11.36% 27.27% | 7 15.91% 43.18% | 5 11.36% 54.55% | 4 9.09% 63.64% | 7 15.91% 79.55% | 3 6.82% 86.36% | 6 13.64% 100.00% +system.ruby.L1Cache_Controller.O.Other_GETX::total 44 +system.ruby.L1Cache_Controller.O.Other_GETS | 2 5.00% 5.00% | 6 15.00% 20.00% | 5 12.50% 32.50% | 6 15.00% 47.50% | 5 12.50% 60.00% | 3 7.50% 67.50% | 7 17.50% 85.00% | 6 15.00% 100.00% +system.ruby.L1Cache_Controller.O.Other_GETS::total 40 +system.ruby.L1Cache_Controller.O.Merged_GETS | 3 17.65% 17.65% | 0 0.00% 17.65% | 4 23.53% 41.18% | 3 17.65% 58.82% | 2 11.76% 70.59% | 3 17.65% 88.24% | 1 5.88% 94.12% | 1 5.88% 100.00% +system.ruby.L1Cache_Controller.O.Merged_GETS::total 17 +system.ruby.L1Cache_Controller.M.Load | 0 0.00% 0.00% | 3 13.04% 13.04% | 2 8.70% 21.74% | 1 4.35% 26.09% | 8 34.78% 60.87% | 2 8.70% 69.57% | 4 17.39% 86.96% | 3 13.04% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 23 +system.ruby.L1Cache_Controller.M.Store | 2 15.38% 15.38% | 1 7.69% 23.08% | 1 7.69% 30.77% | 0 0.00% 30.77% | 2 15.38% 46.15% | 3 23.08% 69.23% | 2 15.38% 84.62% | 2 15.38% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 13 +system.ruby.L1Cache_Controller.M.L2_Replacement | 46198 12.51% 12.51% | 46006 12.46% 24.97% | 46208 12.51% 37.49% | 46008 12.46% 49.95% | 46151 12.50% 62.44% | 46263 12.53% 74.97% | 46379 12.56% 87.53% | 46030 12.47% 100.00% +system.ruby.L1Cache_Controller.M.L2_Replacement::total 369243 +system.ruby.L1Cache_Controller.M.L1_to_L2 | 47396 12.51% 12.51% | 47252 12.47% 24.98% | 47404 12.51% 37.49% | 47224 12.46% 49.95% | 47339 12.49% 62.44% | 47445 12.52% 74.96% | 47605 12.56% 87.53% | 47263 12.47% 100.00% +system.ruby.L1Cache_Controller.M.L1_to_L2::total 378928 +system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D | 35 10.61% 10.61% | 38 11.52% 22.12% | 40 12.12% 34.24% | 44 13.33% 47.58% | 31 9.39% 56.97% | 38 11.52% 68.48% | 48 14.55% 83.03% | 56 16.97% 100.00% +system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D::total 330 +system.ruby.L1Cache_Controller.M.Other_GETX | 454 12.65% 12.65% | 458 12.76% 25.40% | 407 11.34% 36.74% | 451 12.56% 49.30% | 431 12.01% 61.31% | 444 12.37% 73.68% | 464 12.92% 86.60% | 481 13.40% 100.00% +system.ruby.L1Cache_Controller.M.Other_GETX::total 3590 +system.ruby.L1Cache_Controller.M.Other_GETS | 746 12.47% 12.47% | 778 13.00% 25.47% | 761 12.72% 38.19% | 742 12.40% 50.59% | 769 12.85% 63.45% | 723 12.08% 75.53% | 736 12.30% 87.83% | 728 12.17% 100.00% +system.ruby.L1Cache_Controller.M.Other_GETS::total 5983 +system.ruby.L1Cache_Controller.M.Merged_GETS | 54 10.87% 10.87% | 71 14.29% 25.15% | 74 14.89% 40.04% | 51 10.26% 50.30% | 56 11.27% 61.57% | 59 11.87% 73.44% | 64 12.88% 86.32% | 68 13.68% 100.00% +system.ruby.L1Cache_Controller.M.Merged_GETS::total 497 +system.ruby.L1Cache_Controller.MM.Load | 1 4.76% 4.76% | 2 9.52% 14.29% | 5 23.81% 38.10% | 2 9.52% 47.62% | 4 19.05% 66.67% | 1 4.76% 71.43% | 3 14.29% 85.71% | 3 14.29% 100.00% +system.ruby.L1Cache_Controller.MM.Load::total 21 +system.ruby.L1Cache_Controller.MM.Store | 2 22.22% 22.22% | 1 11.11% 33.33% | 2 22.22% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% +system.ruby.L1Cache_Controller.MM.Store::total 9 +system.ruby.L1Cache_Controller.MM.L2_Replacement | 26946 12.39% 12.39% | 27413 12.60% 24.99% | 27322 12.56% 37.54% | 27186 12.50% 50.04% | 27086 12.45% 62.49% | 27285 12.54% 75.03% | 27162 12.48% 87.52% | 27158 12.48% 100.00% +system.ruby.L1Cache_Controller.MM.L2_Replacement::total 217558 +system.ruby.L1Cache_Controller.MM.L1_to_L2 | 27649 12.39% 12.39% | 28125 12.60% 24.98% | 28083 12.58% 37.56% | 27887 12.49% 50.06% | 27807 12.46% 62.51% | 27967 12.53% 75.04% | 27876 12.49% 87.53% | 27839 12.47% 100.00% +system.ruby.L1Cache_Controller.MM.L1_to_L2::total 223233 +system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D | 28 15.47% 15.47% | 25 13.81% 29.28% | 26 14.36% 43.65% | 16 8.84% 52.49% | 18 9.94% 62.43% | 23 12.71% 75.14% | 21 11.60% 86.74% | 24 13.26% 100.00% +system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D::total 181 +system.ruby.L1Cache_Controller.MM.Other_GETX | 281 13.30% 13.30% | 260 12.31% 25.62% | 282 13.35% 38.97% | 254 12.03% 50.99% | 275 13.02% 64.02% | 260 12.31% 76.33% | 264 12.50% 88.83% | 236 11.17% 100.00% +system.ruby.L1Cache_Controller.MM.Other_GETX::total 2112 +system.ruby.L1Cache_Controller.MM.Other_GETS | 424 12.01% 12.01% | 438 12.40% 24.41% | 473 13.40% 37.81% | 444 12.57% 50.38% | 450 12.74% 63.13% | 418 11.84% 74.96% | 452 12.80% 87.77% | 432 12.23% 100.00% +system.ruby.L1Cache_Controller.MM.Other_GETS::total 3531 +system.ruby.L1Cache_Controller.MM.Merged_GETS | 45 14.33% 14.33% | 40 12.74% 27.07% | 34 10.83% 37.90% | 29 9.24% 47.13% | 45 14.33% 61.46% | 35 11.15% 72.61% | 36 11.46% 84.08% | 50 15.92% 100.00% +system.ruby.L1Cache_Controller.MM.Merged_GETS::total 314 +system.ruby.L1Cache_Controller.SR.Load | 5 27.78% 27.78% | 2 11.11% 38.89% | 1 5.56% 44.44% | 1 5.56% 50.00% | 2 11.11% 61.11% | 3 16.67% 77.78% | 1 5.56% 83.33% | 3 16.67% 100.00% +system.ruby.L1Cache_Controller.SR.Load::total 18 +system.ruby.L1Cache_Controller.SR.Store | 3 21.43% 21.43% | 1 7.14% 28.57% | 2 14.29% 42.86% | 2 14.29% 57.14% | 3 21.43% 78.57% | 2 14.29% 92.86% | 0 0.00% 92.86% | 1 7.14% 100.00% +system.ruby.L1Cache_Controller.SR.Store::total 14 +system.ruby.L1Cache_Controller.SR.L1_to_L2 | 1 14.29% 14.29% | 0 0.00% 14.29% | 3 42.86% 57.14% | 0 0.00% 57.14% | 1 14.29% 71.43% | 2 28.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SR.L1_to_L2::total 7 +system.ruby.L1Cache_Controller.OR.Load | 2 28.57% 28.57% | 1 14.29% 42.86% | 1 14.29% 57.14% | 1 14.29% 71.43% | 1 14.29% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 1 14.29% 100.00% +system.ruby.L1Cache_Controller.OR.Load::total 7 +system.ruby.L1Cache_Controller.OR.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OR.Store::total 3 +system.ruby.L1Cache_Controller.OR.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OR.L1_to_L2::total 2 +system.ruby.L1Cache_Controller.MR.Load | 25 11.16% 11.16% | 20 8.93% 20.09% | 25 11.16% 31.25% | 32 14.29% 45.54% | 16 7.14% 52.68% | 31 13.84% 66.52% | 32 14.29% 80.80% | 43 19.20% 100.00% +system.ruby.L1Cache_Controller.MR.Load::total 224 +system.ruby.L1Cache_Controller.MR.Store | 10 9.43% 9.43% | 18 16.98% 26.42% | 15 14.15% 40.57% | 12 11.32% 51.89% | 15 14.15% 66.04% | 7 6.60% 72.64% | 16 15.09% 87.74% | 13 12.26% 100.00% +system.ruby.L1Cache_Controller.MR.Store::total 106 +system.ruby.L1Cache_Controller.MR.L1_to_L2 | 11 50.00% 50.00% | 0 0.00% 50.00% | 2 9.09% 59.09% | 3 13.64% 72.73% | 0 0.00% 72.73% | 1 4.55% 77.27% | 5 22.73% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.MR.L1_to_L2::total 22 +system.ruby.L1Cache_Controller.MMR.Load | 16 14.29% 14.29% | 20 17.86% 32.14% | 17 15.18% 47.32% | 8 7.14% 54.46% | 13 11.61% 66.07% | 12 10.71% 76.79% | 14 12.50% 89.29% | 12 10.71% 100.00% +system.ruby.L1Cache_Controller.MMR.Load::total 112 +system.ruby.L1Cache_Controller.MMR.Store | 12 17.39% 17.39% | 5 7.25% 24.64% | 9 13.04% 37.68% | 8 11.59% 49.28% | 5 7.25% 56.52% | 11 15.94% 72.46% | 7 10.14% 82.61% | 12 17.39% 100.00% +system.ruby.L1Cache_Controller.MMR.Store::total 69 +system.ruby.L1Cache_Controller.MMR.L1_to_L2 | 0 0.00% 0.00% | 1 16.67% 16.67% | 0 0.00% 16.67% | 2 33.33% 50.00% | 0 0.00% 50.00% | 3 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.MMR.L1_to_L2::total 6 -system.ruby.L1Cache_Controller.IM.L1_to_L2 | 306597 12.47% 12.47% | 305312 12.41% 24.88% | 308056 12.53% 37.41% | 306682 12.47% 49.88% | 307381 12.50% 62.38% | 306468 12.46% 74.84% | 310891 12.64% 87.48% | 307863 12.52% 100.00% -system.ruby.L1Cache_Controller.IM.L1_to_L2::total 2459250 -system.ruby.L1Cache_Controller.IM.Other_GETX | 70 14.11% 14.11% | 55 11.09% 25.20% | 60 12.10% 37.30% | 49 9.88% 47.18% | 61 12.30% 59.48% | 72 14.52% 73.99% | 68 13.71% 87.70% | 61 12.30% 100.00% -system.ruby.L1Cache_Controller.IM.Other_GETX::total 496 -system.ruby.L1Cache_Controller.IM.Other_GETS | 121 13.10% 13.10% | 113 12.23% 25.32% | 117 12.66% 37.99% | 123 13.31% 51.30% | 116 12.55% 63.85% | 116 12.55% 76.41% | 111 12.01% 88.42% | 107 11.58% 100.00% -system.ruby.L1Cache_Controller.IM.Other_GETS::total 924 -system.ruby.L1Cache_Controller.IM.Ack | 136150 12.48% 12.48% | 135760 12.44% 24.92% | 137830 12.63% 37.55% | 135721 12.44% 49.99% | 136011 12.47% 62.46% | 135595 12.43% 74.88% | 136815 12.54% 87.42% | 137251 12.58% 100.00% -system.ruby.L1Cache_Controller.IM.Ack::total 1091133 -system.ruby.L1Cache_Controller.IM.Data | 1432 13.01% 13.01% | 1284 11.67% 24.68% | 1403 12.75% 37.43% | 1426 12.96% 50.38% | 1339 12.17% 62.55% | 1319 11.98% 74.53% | 1400 12.72% 87.25% | 1403 12.75% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 11006 -system.ruby.L1Cache_Controller.IM.Exclusive_Data | 26783 12.50% 12.50% | 26750 12.49% 24.99% | 26889 12.55% 37.54% | 26598 12.42% 49.95% | 26759 12.49% 62.44% | 26739 12.48% 74.93% | 26831 12.52% 87.45% | 26886 12.55% 100.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 214235 -system.ruby.L1Cache_Controller.SM.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SM.L1_to_L2::total 3 -system.ruby.L1Cache_Controller.SM.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 25.00% 25.00% | 7 25.00% 50.00% | 14 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 28 -system.ruby.L1Cache_Controller.SM.Data | 1 14.29% 14.29% | 1 14.29% 28.57% | 0 0.00% 28.57% | 1 14.29% 42.86% | 1 14.29% 57.14% | 2 28.57% 85.71% | 1 14.29% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SM.Data::total 7 -system.ruby.L1Cache_Controller.OM.L1_to_L2 | 0 0.00% 0.00% | 28 93.33% 93.33% | 0 0.00% 93.33% | 2 6.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OM.L1_to_L2::total 30 -system.ruby.L1Cache_Controller.OM.Ack | 0 0.00% 0.00% | 7 50.00% 50.00% | 0 0.00% 50.00% | 7 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OM.Ack::total 14 -system.ruby.L1Cache_Controller.OM.All_acks_no_sharers | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OM.All_acks_no_sharers::total 2 -system.ruby.L1Cache_Controller.ISM.L1_to_L2 | 1394 10.91% 10.91% | 1598 12.51% 23.42% | 1658 12.98% 36.39% | 1887 14.77% 51.16% | 1613 12.62% 63.79% | 1566 12.26% 76.04% | 1536 12.02% 88.06% | 1525 11.94% 100.00% -system.ruby.L1Cache_Controller.ISM.L1_to_L2::total 12777 -system.ruby.L1Cache_Controller.ISM.Ack | 3113 13.39% 13.39% | 2633 11.32% 24.71% | 3023 13.00% 37.71% | 3008 12.94% 50.65% | 2836 12.20% 62.84% | 2838 12.20% 75.05% | 2952 12.69% 87.74% | 2851 12.26% 100.00% -system.ruby.L1Cache_Controller.ISM.Ack::total 23254 -system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers | 1433 13.01% 13.01% | 1285 11.67% 24.68% | 1403 12.74% 37.42% | 1427 12.96% 50.38% | 1340 12.17% 62.54% | 1321 11.99% 74.54% | 1401 12.72% 87.26% | 1403 12.74% 100.00% -system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers::total 11013 -system.ruby.L1Cache_Controller.M_W.Load | 2 8.00% 8.00% | 1 4.00% 12.00% | 2 8.00% 20.00% | 3 12.00% 32.00% | 2 8.00% 40.00% | 2 8.00% 48.00% | 11 44.00% 92.00% | 2 8.00% 100.00% -system.ruby.L1Cache_Controller.M_W.Load::total 25 -system.ruby.L1Cache_Controller.M_W.Store | 1 7.69% 7.69% | 4 30.77% 38.46% | 3 23.08% 61.54% | 0 0.00% 61.54% | 4 30.77% 92.31% | 0 0.00% 92.31% | 0 0.00% 92.31% | 1 7.69% 100.00% +system.ruby.L1Cache_Controller.IM.L1_to_L2 | 302923 12.45% 12.45% | 307239 12.63% 25.09% | 307083 12.63% 37.71% | 302980 12.46% 50.17% | 301277 12.39% 62.56% | 306307 12.59% 75.15% | 302955 12.46% 87.61% | 301458 12.39% 100.00% +system.ruby.L1Cache_Controller.IM.L1_to_L2::total 2432222 +system.ruby.L1Cache_Controller.IM.Other_GETX | 70 14.40% 14.40% | 57 11.73% 26.13% | 62 12.76% 38.89% | 59 12.14% 51.03% | 62 12.76% 63.79% | 50 10.29% 74.07% | 67 13.79% 87.86% | 59 12.14% 100.00% +system.ruby.L1Cache_Controller.IM.Other_GETX::total 486 +system.ruby.L1Cache_Controller.IM.Other_GETS | 132 14.54% 14.54% | 115 12.67% 27.20% | 112 12.33% 39.54% | 109 12.00% 51.54% | 117 12.89% 64.43% | 110 12.11% 76.54% | 115 12.67% 89.21% | 98 10.79% 100.00% +system.ruby.L1Cache_Controller.IM.Other_GETS::total 908 +system.ruby.L1Cache_Controller.IM.Ack | 134226 12.37% 12.37% | 136054 12.54% 24.91% | 136885 12.62% 37.53% | 135510 12.49% 50.02% | 135173 12.46% 62.47% | 136621 12.59% 75.06% | 135127 12.45% 87.52% | 135424 12.48% 100.00% +system.ruby.L1Cache_Controller.IM.Ack::total 1085020 +system.ruby.L1Cache_Controller.IM.Data | 1327 12.29% 12.29% | 1308 12.11% 24.40% | 1387 12.84% 37.25% | 1384 12.82% 50.06% | 1346 12.47% 62.53% | 1397 12.94% 75.47% | 1355 12.55% 88.02% | 1294 11.98% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 10798 +system.ruby.L1Cache_Controller.IM.Exclusive_Data | 26355 12.40% 12.40% | 26825 12.62% 25.02% | 26706 12.56% 37.58% | 26516 12.47% 50.05% | 26488 12.46% 62.51% | 26588 12.51% 75.02% | 26538 12.48% 87.50% | 26568 12.50% 100.00% +system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 212584 +system.ruby.L1Cache_Controller.SM.L1_to_L2 | 40 32.79% 32.79% | 8 6.56% 39.34% | 11 9.02% 48.36% | 10 8.20% 56.56% | 10 8.20% 64.75% | 12 9.84% 74.59% | 0 0.00% 74.59% | 31 25.41% 100.00% +system.ruby.L1Cache_Controller.SM.L1_to_L2::total 122 +system.ruby.L1Cache_Controller.SM.Ack | 9 11.84% 11.84% | 7 9.21% 21.05% | 11 14.47% 35.53% | 14 18.42% 53.95% | 21 27.63% 81.58% | 14 18.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 76 +system.ruby.L1Cache_Controller.SM.Data | 4 22.22% 22.22% | 1 5.56% 27.78% | 3 16.67% 44.44% | 2 11.11% 55.56% | 4 22.22% 77.78% | 2 11.11% 88.89% | 0 0.00% 88.89% | 2 11.11% 100.00% +system.ruby.L1Cache_Controller.SM.Data::total 18 +system.ruby.L1Cache_Controller.OM.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OM.L1_to_L2::total 10 +system.ruby.L1Cache_Controller.OM.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 33.33% 33.33% | 0 0.00% 33.33% | 7 33.33% 66.67% | 7 33.33% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OM.Ack::total 21 +system.ruby.L1Cache_Controller.OM.All_acks_no_sharers | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OM.All_acks_no_sharers::total 3 +system.ruby.L1Cache_Controller.ISM.L1_to_L2 | 1405 11.94% 11.94% | 1364 11.59% 23.53% | 1489 12.65% 36.18% | 1604 13.63% 49.80% | 1332 11.32% 61.12% | 1603 13.62% 74.74% | 1519 12.91% 87.65% | 1454 12.35% 100.00% +system.ruby.L1Cache_Controller.ISM.L1_to_L2::total 11770 +system.ruby.L1Cache_Controller.ISM.Ack | 2799 12.37% 12.37% | 2747 12.14% 24.51% | 2955 13.06% 37.57% | 2944 13.01% 50.58% | 2774 12.26% 62.84% | 2765 12.22% 75.05% | 2793 12.34% 87.40% | 2852 12.60% 100.00% +system.ruby.L1Cache_Controller.ISM.Ack::total 22629 +system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers | 1331 12.31% 12.31% | 1309 12.10% 24.41% | 1390 12.85% 37.26% | 1386 12.81% 50.07% | 1350 12.48% 62.56% | 1399 12.93% 75.49% | 1355 12.53% 88.02% | 1296 11.98% 100.00% +system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers::total 10816 +system.ruby.L1Cache_Controller.M_W.Load | 2 8.70% 8.70% | 2 8.70% 17.39% | 1 4.35% 21.74% | 2 8.70% 30.43% | 1 4.35% 34.78% | 8 34.78% 69.57% | 3 13.04% 82.61% | 4 17.39% 100.00% +system.ruby.L1Cache_Controller.M_W.Load::total 23 +system.ruby.L1Cache_Controller.M_W.Store | 1 7.69% 7.69% | 2 15.38% 23.08% | 2 15.38% 38.46% | 1 7.69% 46.15% | 1 7.69% 53.85% | 2 15.38% 69.23% | 4 30.77% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.M_W.Store::total 13 -system.ruby.L1Cache_Controller.M_W.L1_to_L2 | 200171 12.54% 12.54% | 201389 12.61% 25.15% | 199062 12.47% 37.62% | 199984 12.53% 50.14% | 200073 12.53% 62.67% | 199333 12.48% 75.16% | 198630 12.44% 87.60% | 198028 12.40% 100.00% -system.ruby.L1Cache_Controller.M_W.L1_to_L2::total 1596670 -system.ruby.L1Cache_Controller.M_W.Ack | 100064 12.51% 12.51% | 99138 12.39% 24.90% | 100497 12.56% 37.46% | 100328 12.54% 50.00% | 99100 12.39% 62.39% | 100240 12.53% 74.92% | 100840 12.60% 87.52% | 99833 12.48% 100.00% -system.ruby.L1Cache_Controller.M_W.Ack::total 800040 -system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers | 47645 12.56% 12.56% | 47250 12.46% 25.01% | 47381 12.49% 37.50% | 47631 12.56% 50.06% | 47107 12.42% 62.48% | 47548 12.53% 75.01% | 47418 12.50% 87.51% | 47378 12.49% 100.00% -system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers::total 379358 -system.ruby.L1Cache_Controller.MM_W.Load | 1 7.69% 7.69% | 1 7.69% 15.38% | 0 0.00% 15.38% | 1 7.69% 23.08% | 2 15.38% 38.46% | 2 15.38% 53.85% | 6 46.15% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.MM_W.Load::total 13 -system.ruby.L1Cache_Controller.MM_W.Store | 1 12.50% 12.50% | 2 25.00% 37.50% | 1 12.50% 50.00% | 1 12.50% 62.50% | 1 12.50% 75.00% | 0 0.00% 75.00% | 1 12.50% 87.50% | 1 12.50% 100.00% +system.ruby.L1Cache_Controller.M_W.L1_to_L2 | 201445 12.59% 12.59% | 199880 12.49% 25.07% | 199351 12.45% 37.53% | 199459 12.46% 49.99% | 199708 12.48% 62.47% | 199635 12.47% 74.94% | 200784 12.54% 87.48% | 200348 12.52% 100.00% +system.ruby.L1Cache_Controller.M_W.L1_to_L2::total 1600610 +system.ruby.L1Cache_Controller.M_W.Ack | 99436 12.49% 12.49% | 98487 12.37% 24.86% | 99684 12.52% 37.39% | 98522 12.38% 49.76% | 100457 12.62% 62.38% | 99804 12.54% 74.92% | 99953 12.56% 87.48% | 99670 12.52% 100.00% +system.ruby.L1Cache_Controller.M_W.Ack::total 796013 +system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers | 47466 12.51% 12.51% | 47336 12.47% 24.98% | 47467 12.51% 37.49% | 47268 12.46% 49.95% | 47430 12.50% 62.45% | 47503 12.52% 74.97% | 47665 12.56% 87.53% | 47325 12.47% 100.00% +system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers::total 379460 +system.ruby.L1Cache_Controller.MM_W.Load | 2 16.67% 16.67% | 2 16.67% 33.33% | 1 8.33% 41.67% | 2 16.67% 58.33% | 2 16.67% 75.00% | 0 0.00% 75.00% | 3 25.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.MM_W.Load::total 12 +system.ruby.L1Cache_Controller.MM_W.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 25.00% 25.00% | 3 37.50% 62.50% | 0 0.00% 62.50% | 1 12.50% 75.00% | 1 12.50% 87.50% | 1 12.50% 100.00% system.ruby.L1Cache_Controller.MM_W.Store::total 8 -system.ruby.L1Cache_Controller.MM_W.L1_to_L2 | 111219 12.38% 12.38% | 110686 12.32% 24.70% | 111741 12.44% 37.14% | 111545 12.42% 49.56% | 112926 12.57% 62.14% | 113082 12.59% 74.72% | 113474 12.63% 87.36% | 113559 12.64% 100.00% -system.ruby.L1Cache_Controller.MM_W.L1_to_L2::total 898232 -system.ruby.L1Cache_Controller.MM_W.Ack | 57311 12.60% 12.60% | 57008 12.53% 25.13% | 56263 12.37% 37.49% | 56533 12.42% 49.92% | 56954 12.52% 62.43% | 57042 12.54% 74.97% | 56905 12.51% 87.48% | 56979 12.52% 100.00% -system.ruby.L1Cache_Controller.MM_W.Ack::total 454995 -system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers | 26784 12.50% 12.50% | 26754 12.49% 24.99% | 26892 12.55% 37.54% | 26598 12.41% 49.96% | 26763 12.49% 62.45% | 26739 12.48% 74.93% | 26831 12.52% 87.45% | 26887 12.55% 100.00% -system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers::total 214248 -system.ruby.L1Cache_Controller.IS.L1_to_L2 | 559135 12.61% 12.61% | 550430 12.41% 25.02% | 555834 12.53% 37.56% | 556201 12.54% 50.10% | 549545 12.39% 62.49% | 555811 12.53% 75.02% | 552887 12.47% 87.49% | 554704 12.51% 100.00% -system.ruby.L1Cache_Controller.IS.L1_to_L2::total 4434547 -system.ruby.L1Cache_Controller.IS.Other_GETX | 114 12.58% 12.58% | 103 11.37% 23.95% | 128 14.13% 38.08% | 113 12.47% 50.55% | 122 13.47% 64.02% | 104 11.48% 75.50% | 118 13.02% 88.52% | 104 11.48% 100.00% -system.ruby.L1Cache_Controller.IS.Other_GETX::total 906 -system.ruby.L1Cache_Controller.IS.Other_GETS | 228 12.97% 12.97% | 211 12.00% 24.97% | 235 13.37% 38.34% | 223 12.68% 51.02% | 220 12.51% 63.54% | 216 12.29% 75.82% | 201 11.43% 87.26% | 224 12.74% 100.00% -system.ruby.L1Cache_Controller.IS.Other_GETS::total 1758 -system.ruby.L1Cache_Controller.IS.Ack | 246749 12.58% 12.58% | 244495 12.47% 25.05% | 244426 12.47% 37.52% | 246249 12.56% 50.08% | 243880 12.44% 62.52% | 245608 12.53% 75.05% | 244326 12.46% 87.51% | 244931 12.49% 100.00% -system.ruby.L1Cache_Controller.IS.Ack::total 1960664 -system.ruby.L1Cache_Controller.IS.Shared_Ack | 41 14.19% 14.19% | 26 9.00% 23.18% | 37 12.80% 35.99% | 42 14.53% 50.52% | 37 12.80% 63.32% | 39 13.49% 76.82% | 31 10.73% 87.54% | 36 12.46% 100.00% -system.ruby.L1Cache_Controller.IS.Shared_Ack::total 289 -system.ruby.L1Cache_Controller.IS.Data | 2107 12.70% 12.70% | 2021 12.18% 24.88% | 2088 12.59% 37.47% | 2058 12.41% 49.87% | 2088 12.59% 62.46% | 2088 12.59% 75.05% | 2095 12.63% 87.67% | 2045 12.33% 100.00% -system.ruby.L1Cache_Controller.IS.Data::total 16590 -system.ruby.L1Cache_Controller.IS.Shared_Data | 1247 12.83% 12.83% | 1191 12.26% 25.09% | 1201 12.36% 37.45% | 1173 12.07% 49.52% | 1215 12.50% 62.02% | 1212 12.47% 74.49% | 1240 12.76% 87.25% | 1239 12.75% 100.00% -system.ruby.L1Cache_Controller.IS.Shared_Data::total 9718 -system.ruby.L1Cache_Controller.IS.Exclusive_Data | 47646 12.56% 12.56% | 47254 12.46% 25.02% | 47384 12.49% 37.51% | 47631 12.56% 50.06% | 47111 12.42% 62.48% | 47548 12.53% 75.01% | 47418 12.50% 87.51% | 47379 12.49% 100.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 379371 -system.ruby.L1Cache_Controller.SS.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% -system.ruby.L1Cache_Controller.SS.Load::total 2 -system.ruby.L1Cache_Controller.SS.Store | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.MM_W.L1_to_L2 | 110034 12.43% 12.43% | 112800 12.74% 25.18% | 110873 12.53% 37.70% | 109927 12.42% 50.12% | 110569 12.49% 62.61% | 109742 12.40% 75.01% | 110682 12.50% 87.52% | 110478 12.48% 100.00% +system.ruby.L1Cache_Controller.MM_W.L1_to_L2::total 885105 +system.ruby.L1Cache_Controller.MM_W.Ack | 55850 12.44% 12.44% | 57296 12.76% 25.20% | 55937 12.46% 37.66% | 55962 12.46% 50.12% | 55976 12.47% 62.59% | 55627 12.39% 74.98% | 56487 12.58% 87.56% | 55876 12.44% 100.00% +system.ruby.L1Cache_Controller.MM_W.Ack::total 449011 +system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers | 26356 12.40% 12.40% | 26827 12.62% 25.02% | 26708 12.56% 37.58% | 26517 12.47% 50.05% | 26489 12.46% 62.51% | 26590 12.51% 75.02% | 26542 12.48% 87.50% | 26568 12.50% 100.00% +system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers::total 212597 +system.ruby.L1Cache_Controller.IS.L1_to_L2 | 556503 12.51% 12.51% | 552231 12.42% 24.93% | 556440 12.51% 37.44% | 553059 12.44% 49.88% | 556823 12.52% 62.40% | 556311 12.51% 74.91% | 558973 12.57% 87.48% | 556691 12.52% 100.00% +system.ruby.L1Cache_Controller.IS.L1_to_L2::total 4447031 +system.ruby.L1Cache_Controller.IS.Other_GETX | 125 13.90% 13.90% | 103 11.46% 25.36% | 99 11.01% 36.37% | 116 12.90% 49.28% | 118 13.13% 62.40% | 113 12.57% 74.97% | 112 12.46% 87.43% | 113 12.57% 100.00% +system.ruby.L1Cache_Controller.IS.Other_GETX::total 899 +system.ruby.L1Cache_Controller.IS.Other_GETS | 233 13.80% 13.80% | 185 10.96% 24.76% | 207 12.26% 37.03% | 218 12.91% 49.94% | 201 11.91% 61.85% | 212 12.56% 74.41% | 214 12.68% 87.09% | 218 12.91% 100.00% +system.ruby.L1Cache_Controller.IS.Other_GETS::total 1688 +system.ruby.L1Cache_Controller.IS.Ack | 246873 12.55% 12.55% | 245877 12.50% 25.05% | 246145 12.51% 37.56% | 246067 12.51% 50.07% | 244793 12.44% 62.51% | 245889 12.50% 75.01% | 246666 12.54% 87.55% | 244851 12.45% 100.00% +system.ruby.L1Cache_Controller.IS.Ack::total 1967161 +system.ruby.L1Cache_Controller.IS.Shared_Ack | 43 15.09% 15.09% | 30 10.53% 25.61% | 29 10.18% 35.79% | 29 10.18% 45.96% | 31 10.88% 56.84% | 44 15.44% 72.28% | 42 14.74% 87.02% | 37 12.98% 100.00% +system.ruby.L1Cache_Controller.IS.Shared_Ack::total 285 +system.ruby.L1Cache_Controller.IS.Data | 2210 13.15% 13.15% | 2070 12.32% 25.47% | 2103 12.51% 37.98% | 2165 12.88% 50.86% | 2058 12.25% 63.11% | 2062 12.27% 75.38% | 2049 12.19% 87.57% | 2089 12.43% 100.00% +system.ruby.L1Cache_Controller.IS.Data::total 16806 +system.ruby.L1Cache_Controller.IS.Shared_Data | 1202 12.56% 12.56% | 1159 12.11% 24.68% | 1180 12.33% 37.01% | 1226 12.81% 49.83% | 1192 12.46% 62.29% | 1221 12.76% 75.05% | 1195 12.49% 87.54% | 1192 12.46% 100.00% +system.ruby.L1Cache_Controller.IS.Shared_Data::total 9567 +system.ruby.L1Cache_Controller.IS.Exclusive_Data | 47467 12.51% 12.51% | 47338 12.47% 24.98% | 47469 12.51% 37.49% | 47269 12.46% 49.95% | 47431 12.50% 62.45% | 47505 12.52% 74.97% | 47669 12.56% 87.53% | 47325 12.47% 100.00% +system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 379473 +system.ruby.L1Cache_Controller.SS.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SS.Load::total 1 +system.ruby.L1Cache_Controller.SS.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 2 66.67% 100.00% system.ruby.L1Cache_Controller.SS.Store::total 3 -system.ruby.L1Cache_Controller.SS.L1_to_L2 | 11840 12.60% 12.60% | 11314 12.04% 24.65% | 11805 12.57% 37.21% | 11485 12.23% 49.44% | 11796 12.56% 62.00% | 11769 12.53% 74.53% | 12345 13.14% 87.67% | 11586 12.33% 100.00% -system.ruby.L1Cache_Controller.SS.L1_to_L2::total 93940 -system.ruby.L1Cache_Controller.SS.Ack | 7534 12.75% 12.75% | 7112 12.04% 24.79% | 7419 12.56% 37.34% | 7021 11.88% 49.22% | 7448 12.60% 61.83% | 7677 12.99% 74.82% | 7571 12.81% 87.63% | 7308 12.37% 100.00% -system.ruby.L1Cache_Controller.SS.Ack::total 59090 -system.ruby.L1Cache_Controller.SS.Shared_Ack | 13 10.74% 10.74% | 17 14.05% 24.79% | 12 9.92% 34.71% | 15 12.40% 47.11% | 10 8.26% 55.37% | 16 13.22% 68.60% | 18 14.88% 83.47% | 20 16.53% 100.00% -system.ruby.L1Cache_Controller.SS.Shared_Ack::total 121 -system.ruby.L1Cache_Controller.SS.All_acks | 1291 12.80% 12.80% | 1232 12.21% 25.01% | 1245 12.34% 37.36% | 1225 12.14% 49.50% | 1258 12.47% 61.97% | 1263 12.52% 74.49% | 1286 12.75% 87.24% | 1287 12.76% 100.00% -system.ruby.L1Cache_Controller.SS.All_acks::total 10087 -system.ruby.L1Cache_Controller.SS.All_acks_no_sharers | 2063 12.72% 12.72% | 1980 12.21% 24.92% | 2044 12.60% 37.53% | 2006 12.37% 49.89% | 2045 12.61% 62.50% | 2037 12.56% 75.06% | 2049 12.63% 87.69% | 1997 12.31% 100.00% -system.ruby.L1Cache_Controller.SS.All_acks_no_sharers::total 16221 -system.ruby.L1Cache_Controller.OI.Load | 1 14.29% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 1 14.29% 28.57% | 3 42.86% 71.43% | 2 28.57% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OI.Load::total 7 -system.ruby.L1Cache_Controller.OI.Store | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OI.Store::total 2 -system.ruby.L1Cache_Controller.OI.Other_GETX | 1 8.33% 8.33% | 3 25.00% 33.33% | 0 0.00% 33.33% | 4 33.33% 66.67% | 0 0.00% 66.67% | 1 8.33% 75.00% | 2 16.67% 91.67% | 1 8.33% 100.00% -system.ruby.L1Cache_Controller.OI.Other_GETX::total 12 -system.ruby.L1Cache_Controller.OI.Other_GETS | 1 7.14% 7.14% | 1 7.14% 14.29% | 0 0.00% 14.29% | 3 21.43% 35.71% | 2 14.29% 50.00% | 2 14.29% 64.29% | 2 14.29% 78.57% | 3 21.43% 100.00% -system.ruby.L1Cache_Controller.OI.Other_GETS::total 14 -system.ruby.L1Cache_Controller.OI.Merged_GETS | 3 17.65% 17.65% | 1 5.88% 23.53% | 3 17.65% 41.18% | 5 29.41% 70.59% | 2 11.76% 82.35% | 1 5.88% 88.24% | 0 0.00% 88.24% | 2 11.76% 100.00% -system.ruby.L1Cache_Controller.OI.Merged_GETS::total 17 -system.ruby.L1Cache_Controller.OI.Writeback_Ack | 1186 12.42% 12.42% | 1195 12.52% 24.94% | 1190 12.46% 37.40% | 1223 12.81% 50.21% | 1219 12.77% 62.98% | 1195 12.52% 75.50% | 1147 12.01% 87.51% | 1192 12.49% 100.00% -system.ruby.L1Cache_Controller.OI.Writeback_Ack::total 9547 -system.ruby.L1Cache_Controller.MI.Load | 13 9.03% 9.03% | 17 11.81% 20.83% | 19 13.19% 34.03% | 16 11.11% 45.14% | 24 16.67% 61.81% | 22 15.28% 77.08% | 22 15.28% 92.36% | 11 7.64% 100.00% -system.ruby.L1Cache_Controller.MI.Load::total 144 -system.ruby.L1Cache_Controller.MI.Store | 16 16.49% 16.49% | 10 10.31% 26.80% | 10 10.31% 37.11% | 18 18.56% 55.67% | 6 6.19% 61.86% | 15 15.46% 77.32% | 12 12.37% 89.69% | 10 10.31% 100.00% -system.ruby.L1Cache_Controller.MI.Store::total 97 -system.ruby.L1Cache_Controller.MI.Other_GETX | 158 10.61% 10.61% | 217 14.57% 25.18% | 206 13.83% 39.02% | 169 11.35% 50.37% | 194 13.03% 63.40% | 182 12.22% 75.62% | 190 12.76% 88.38% | 173 11.62% 100.00% -system.ruby.L1Cache_Controller.MI.Other_GETX::total 1489 -system.ruby.L1Cache_Controller.MI.Other_GETS | 330 12.94% 12.94% | 332 13.02% 25.96% | 306 12.00% 37.96% | 345 13.53% 51.49% | 329 12.90% 64.39% | 302 11.84% 76.24% | 293 11.49% 87.73% | 313 12.27% 100.00% -system.ruby.L1Cache_Controller.MI.Other_GETS::total 2550 -system.ruby.L1Cache_Controller.MI.Merged_GETS | 21 16.15% 16.15% | 13 10.00% 26.15% | 14 10.77% 36.92% | 17 13.08% 50.00% | 19 14.62% 64.62% | 15 11.54% 76.15% | 12 9.23% 85.38% | 19 14.62% 100.00% -system.ruby.L1Cache_Controller.MI.Merged_GETS::total 130 -system.ruby.L1Cache_Controller.MI.Writeback_Ack | 73349 12.56% 12.56% | 72705 12.45% 25.01% | 73081 12.51% 37.52% | 73080 12.51% 50.03% | 72593 12.43% 62.46% | 73040 12.51% 74.97% | 73106 12.52% 87.49% | 73077 12.51% 100.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 584031 -system.ruby.L1Cache_Controller.II.Other_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.II.Other_GETX::total 2 -system.ruby.L1Cache_Controller.II.Writeback_Ack | 159 10.59% 10.59% | 220 14.66% 25.25% | 206 13.72% 38.97% | 173 11.53% 50.50% | 194 12.92% 63.42% | 183 12.19% 75.62% | 192 12.79% 88.41% | 174 11.59% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Ack::total 1501 -system.ruby.L1Cache_Controller.ST.Load | 2 20.00% 20.00% | 3 30.00% 50.00% | 3 30.00% 80.00% | 1 10.00% 90.00% | 0 0.00% 90.00% | 0 0.00% 90.00% | 1 10.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.ST.Load::total 10 -system.ruby.L1Cache_Controller.ST.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 50.00% 50.00% | 2 33.33% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.ST.Store::total 6 -system.ruby.L1Cache_Controller.ST.L1_to_L2 | 3 33.33% 33.33% | 6 66.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.ST.L1_to_L2::total 9 -system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1 | 5 25.00% 25.00% | 5 25.00% 50.00% | 2 10.00% 60.00% | 1 5.00% 65.00% | 1 5.00% 70.00% | 3 15.00% 85.00% | 3 15.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1::total 20 -system.ruby.L1Cache_Controller.OT.Load | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OT.Load::total 3 -system.ruby.L1Cache_Controller.OT.Store | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SS.L1_to_L2 | 11768 12.31% 12.31% | 11790 12.33% 24.64% | 11742 12.28% 36.92% | 12395 12.96% 49.88% | 12008 12.56% 62.44% | 12055 12.61% 75.05% | 11824 12.37% 87.41% | 12035 12.59% 100.00% +system.ruby.L1Cache_Controller.SS.L1_to_L2::total 95617 +system.ruby.L1Cache_Controller.SS.Ack | 7372 12.61% 12.61% | 7270 12.44% 25.05% | 7101 12.15% 37.20% | 7579 12.97% 50.16% | 7118 12.18% 62.34% | 7318 12.52% 74.86% | 7283 12.46% 87.32% | 7414 12.68% 100.00% +system.ruby.L1Cache_Controller.SS.Ack::total 58455 +system.ruby.L1Cache_Controller.SS.Shared_Ack | 8 7.77% 7.77% | 13 12.62% 20.39% | 15 14.56% 34.95% | 11 10.68% 45.63% | 15 14.56% 60.19% | 20 19.42% 79.61% | 14 13.59% 93.20% | 7 6.80% 100.00% +system.ruby.L1Cache_Controller.SS.Shared_Ack::total 103 +system.ruby.L1Cache_Controller.SS.All_acks | 1249 12.60% 12.60% | 1194 12.04% 24.64% | 1213 12.23% 36.87% | 1266 12.77% 49.64% | 1237 12.47% 62.11% | 1277 12.88% 74.99% | 1248 12.59% 87.58% | 1232 12.42% 100.00% +system.ruby.L1Cache_Controller.SS.All_acks::total 9916 +system.ruby.L1Cache_Controller.SS.All_acks_no_sharers | 2163 13.14% 13.14% | 2035 12.37% 25.51% | 2070 12.58% 38.09% | 2125 12.91% 51.00% | 2013 12.23% 63.23% | 2006 12.19% 75.42% | 1996 12.13% 87.55% | 2049 12.45% 100.00% +system.ruby.L1Cache_Controller.SS.All_acks_no_sharers::total 16457 +system.ruby.L1Cache_Controller.OI.Load | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OI.Load::total 2 +system.ruby.L1Cache_Controller.OI.Store | 0 0.00% 0.00% | 2 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% +system.ruby.L1Cache_Controller.OI.Store::total 4 +system.ruby.L1Cache_Controller.OI.Other_GETX | 2 10.53% 10.53% | 1 5.26% 15.79% | 1 5.26% 21.05% | 5 26.32% 47.37% | 3 15.79% 63.16% | 3 15.79% 78.95% | 1 5.26% 84.21% | 3 15.79% 100.00% +system.ruby.L1Cache_Controller.OI.Other_GETX::total 19 +system.ruby.L1Cache_Controller.OI.Other_GETS | 1 5.56% 5.56% | 2 11.11% 16.67% | 2 11.11% 27.78% | 3 16.67% 44.44% | 3 16.67% 61.11% | 1 5.56% 66.67% | 4 22.22% 88.89% | 2 11.11% 100.00% +system.ruby.L1Cache_Controller.OI.Other_GETS::total 18 +system.ruby.L1Cache_Controller.OI.Merged_GETS | 4 18.18% 18.18% | 2 9.09% 27.27% | 2 9.09% 36.36% | 2 9.09% 45.45% | 2 9.09% 54.55% | 1 4.55% 59.09% | 6 27.27% 86.36% | 3 13.64% 100.00% +system.ruby.L1Cache_Controller.OI.Merged_GETS::total 22 +system.ruby.L1Cache_Controller.OI.Writeback_Ack | 1139 12.11% 12.11% | 1245 13.24% 25.36% | 1193 12.69% 38.05% | 1135 12.07% 50.12% | 1183 12.58% 62.70% | 1142 12.15% 74.85% | 1181 12.56% 87.41% | 1184 12.59% 100.00% +system.ruby.L1Cache_Controller.OI.Writeback_Ack::total 9402 +system.ruby.L1Cache_Controller.MI.Load | 13 10.16% 10.16% | 19 14.84% 25.00% | 13 10.16% 35.16% | 15 11.72% 46.88% | 13 10.16% 57.03% | 21 16.41% 73.44% | 20 15.62% 89.06% | 14 10.94% 100.00% +system.ruby.L1Cache_Controller.MI.Load::total 128 +system.ruby.L1Cache_Controller.MI.Store | 11 14.10% 14.10% | 11 14.10% 28.21% | 9 11.54% 39.74% | 6 7.69% 47.44% | 8 10.26% 57.69% | 8 10.26% 67.95% | 8 10.26% 78.21% | 17 21.79% 100.00% +system.ruby.L1Cache_Controller.MI.Store::total 78 +system.ruby.L1Cache_Controller.MI.Other_GETX | 186 12.99% 12.99% | 184 12.85% 25.84% | 179 12.50% 38.34% | 158 11.03% 49.37% | 180 12.57% 61.94% | 183 12.78% 74.72% | 179 12.50% 87.22% | 183 12.78% 100.00% +system.ruby.L1Cache_Controller.MI.Other_GETX::total 1432 +system.ruby.L1Cache_Controller.MI.Other_GETS | 290 11.31% 11.31% | 350 13.65% 24.96% | 320 12.48% 37.44% | 309 12.05% 49.49% | 306 11.93% 61.43% | 322 12.56% 73.99% | 339 13.22% 87.21% | 328 12.79% 100.00% +system.ruby.L1Cache_Controller.MI.Other_GETS::total 2564 +system.ruby.L1Cache_Controller.MI.Merged_GETS | 14 12.50% 12.50% | 12 10.71% 23.21% | 12 10.71% 33.93% | 15 13.39% 47.32% | 15 13.39% 60.71% | 14 12.50% 73.21% | 11 9.82% 83.04% | 19 16.96% 100.00% +system.ruby.L1Cache_Controller.MI.Merged_GETS::total 112 +system.ruby.L1Cache_Controller.MI.Writeback_Ack | 72652 12.47% 12.47% | 72873 12.51% 24.98% | 73017 12.53% 37.51% | 72712 12.48% 49.99% | 72735 12.48% 62.47% | 73026 12.53% 75.00% | 73011 12.53% 87.53% | 72656 12.47% 100.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 582682 +system.ruby.L1Cache_Controller.II.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.II.Store::total 1 +system.ruby.L1Cache_Controller.II.Other_GETX | 0 0.00% 0.00% | 1 33.33% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.II.Other_GETX::total 3 +system.ruby.L1Cache_Controller.II.Writeback_Ack | 188 12.96% 12.96% | 185 12.75% 25.71% | 180 12.41% 38.11% | 163 11.23% 49.35% | 183 12.61% 61.96% | 186 12.82% 74.78% | 180 12.41% 87.18% | 186 12.82% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Ack::total 1451 +system.ruby.L1Cache_Controller.ST.Load | 2 22.22% 22.22% | 2 22.22% 44.44% | 0 0.00% 44.44% | 0 0.00% 44.44% | 1 11.11% 55.56% | 2 22.22% 77.78% | 0 0.00% 77.78% | 2 22.22% 100.00% +system.ruby.L1Cache_Controller.ST.Load::total 9 +system.ruby.L1Cache_Controller.ST.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 40.00% 40.00% | 1 20.00% 60.00% | 2 40.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.ST.Store::total 5 +system.ruby.L1Cache_Controller.ST.L1_to_L2 | 1 8.33% 8.33% | 0 0.00% 8.33% | 7 58.33% 66.67% | 1 8.33% 75.00% | 1 8.33% 83.33% | 2 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.ST.L1_to_L2::total 12 +system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1 | 8 25.00% 25.00% | 3 9.38% 34.38% | 3 9.38% 43.75% | 3 9.38% 53.12% | 5 15.62% 68.75% | 5 15.62% 84.38% | 1 3.12% 87.50% | 4 12.50% 100.00% +system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1::total 32 +system.ruby.L1Cache_Controller.OT.Load | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OT.Load::total 2 +system.ruby.L1Cache_Controller.OT.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.OT.Store::total 2 -system.ruby.L1Cache_Controller.OT.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9 81.82% 81.82% | 0 0.00% 81.82% | 0 0.00% 81.82% | 2 18.18% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OT.L1_to_L2::total 11 -system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1 | 1 16.67% 16.67% | 1 16.67% 33.33% | 0 0.00% 33.33% | 2 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% -system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1::total 6 -system.ruby.L1Cache_Controller.MT.Load | 7 6.60% 6.60% | 13 12.26% 18.87% | 17 16.04% 34.91% | 18 16.98% 51.89% | 11 10.38% 62.26% | 13 12.26% 74.53% | 9 8.49% 83.02% | 18 16.98% 100.00% -system.ruby.L1Cache_Controller.MT.Load::total 106 -system.ruby.L1Cache_Controller.MT.Store | 5 9.26% 9.26% | 9 16.67% 25.93% | 11 20.37% 46.30% | 9 16.67% 62.96% | 3 5.56% 68.52% | 6 11.11% 79.63% | 3 5.56% 85.19% | 8 14.81% 100.00% -system.ruby.L1Cache_Controller.MT.Store::total 54 -system.ruby.L1Cache_Controller.MT.L1_to_L2 | 11 13.58% 13.58% | 2 2.47% 16.05% | 16 19.75% 35.80% | 21 25.93% 61.73% | 10 12.35% 74.07% | 3 3.70% 77.78% | 3 3.70% 81.48% | 15 18.52% 100.00% -system.ruby.L1Cache_Controller.MT.L1_to_L2::total 81 -system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 | 20 6.78% 6.78% | 35 11.86% 18.64% | 45 15.25% 33.90% | 40 13.56% 47.46% | 43 14.58% 62.03% | 37 12.54% 74.58% | 32 10.85% 85.42% | 43 14.58% 100.00% -system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1::total 295 -system.ruby.L1Cache_Controller.MMT.Load | 5 7.94% 7.94% | 7 11.11% 19.05% | 5 7.94% 26.98% | 4 6.35% 33.33% | 10 15.87% 49.21% | 15 23.81% 73.02% | 13 20.63% 93.65% | 4 6.35% 100.00% -system.ruby.L1Cache_Controller.MMT.Load::total 63 -system.ruby.L1Cache_Controller.MMT.Store | 4 11.11% 11.11% | 3 8.33% 19.44% | 4 11.11% 30.56% | 7 19.44% 50.00% | 4 11.11% 61.11% | 5 13.89% 75.00% | 6 16.67% 91.67% | 3 8.33% 100.00% -system.ruby.L1Cache_Controller.MMT.Store::total 36 -system.ruby.L1Cache_Controller.MMT.L1_to_L2 | 0 0.00% 0.00% | 4 9.52% 9.52% | 8 19.05% 28.57% | 6 14.29% 42.86% | 3 7.14% 50.00% | 7 16.67% 66.67% | 12 28.57% 95.24% | 2 4.76% 100.00% +system.ruby.L1Cache_Controller.OT.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OT.L1_to_L2::total 6 +system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1 | 2 20.00% 20.00% | 1 10.00% 30.00% | 1 10.00% 40.00% | 2 20.00% 60.00% | 1 10.00% 70.00% | 1 10.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% +system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1::total 10 +system.ruby.L1Cache_Controller.MT.Load | 12 10.00% 10.00% | 10 8.33% 18.33% | 16 13.33% 31.67% | 16 13.33% 45.00% | 5 4.17% 49.17% | 17 14.17% 63.33% | 17 14.17% 77.50% | 27 22.50% 100.00% +system.ruby.L1Cache_Controller.MT.Load::total 120 +system.ruby.L1Cache_Controller.MT.Store | 2 3.92% 3.92% | 7 13.73% 17.65% | 13 25.49% 43.14% | 4 7.84% 50.98% | 6 11.76% 62.75% | 3 5.88% 68.63% | 10 19.61% 88.24% | 6 11.76% 100.00% +system.ruby.L1Cache_Controller.MT.Store::total 51 +system.ruby.L1Cache_Controller.MT.L1_to_L2 | 18 23.68% 23.68% | 11 14.47% 38.16% | 7 9.21% 47.37% | 9 11.84% 59.21% | 13 17.11% 76.32% | 6 7.89% 84.21% | 10 13.16% 97.37% | 2 2.63% 100.00% +system.ruby.L1Cache_Controller.MT.L1_to_L2::total 76 +system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 | 35 10.61% 10.61% | 38 11.52% 22.12% | 40 12.12% 34.24% | 44 13.33% 47.58% | 31 9.39% 56.97% | 38 11.52% 68.48% | 48 14.55% 83.03% | 56 16.97% 100.00% +system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1::total 330 +system.ruby.L1Cache_Controller.MMT.Load | 7 14.29% 14.29% | 12 24.49% 38.78% | 4 8.16% 46.94% | 2 4.08% 51.02% | 4 8.16% 59.18% | 6 12.24% 71.43% | 5 10.20% 81.63% | 9 18.37% 100.00% +system.ruby.L1Cache_Controller.MMT.Load::total 49 +system.ruby.L1Cache_Controller.MMT.Store | 9 27.27% 27.27% | 3 9.09% 36.36% | 5 15.15% 51.52% | 2 6.06% 57.58% | 2 6.06% 63.64% | 4 12.12% 75.76% | 3 9.09% 84.85% | 5 15.15% 100.00% +system.ruby.L1Cache_Controller.MMT.Store::total 33 +system.ruby.L1Cache_Controller.MMT.L1_to_L2 | 12 28.57% 28.57% | 3 7.14% 35.71% | 2 4.76% 40.48% | 2 4.76% 45.24% | 4 9.52% 54.76% | 4 9.52% 64.29% | 14 33.33% 97.62% | 1 2.38% 100.00% system.ruby.L1Cache_Controller.MMT.L1_to_L2::total 42 -system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 | 21 11.93% 11.93% | 18 10.23% 22.16% | 18 10.23% 32.39% | 20 11.36% 43.75% | 24 13.64% 57.39% | 28 15.91% 73.30% | 29 16.48% 89.77% | 18 10.23% 100.00% -system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1::total 176 +system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 | 28 15.47% 15.47% | 25 13.81% 29.28% | 26 14.36% 43.65% | 16 8.84% 52.49% | 18 9.94% 62.43% | 23 12.71% 75.14% | 21 11.60% 86.74% | 24 13.26% 100.00% +system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1::total 181 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index ab4492b68..9a512176f 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.007628 # Number of seconds simulated -sim_ticks 7628407 # Number of ticks simulated -final_tick 7628407 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.007679 # Number of seconds simulated +sim_ticks 7678882 # Number of ticks simulated +final_tick 7678882 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 107171 # Simulator tick rate (ticks/s) -host_mem_usage 570400 # Number of bytes of host memory used -host_seconds 71.18 # Real time elapsed on the host +host_tick_rate 155896 # Simulator tick rate (ticks/s) +host_mem_usage 461848 # Number of bytes of host memory used +host_seconds 49.26 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39424192 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 39424192 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39422720 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 39422720 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 616003 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 616003 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 615980 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 615980 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 5168076638 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 5168076638 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 5167883675 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 5167883675 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 10335960313 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 10335960313 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 616011 # Number of read requests accepted -system.mem_ctrls.writeReqs 615980 # Number of write requests accepted -system.mem_ctrls.readBursts 616011 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 615980 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 38546240 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 878016 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 38914560 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 39424704 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 39422720 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 13719 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 7894 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39687936 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 39687936 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39686592 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 39686592 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 620124 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 620124 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 620103 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 620103 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 5168452387 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 5168452387 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 5168277361 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 5168277361 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 10336729748 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 10336729748 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 620135 # Number of read requests accepted +system.mem_ctrls.writeReqs 620103 # Number of write requests accepted +system.mem_ctrls.readBursts 620135 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 620103 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 38814144 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 874432 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 39178240 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 39688640 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 39686592 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 13663 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 7899 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 75559 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 75206 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 75541 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 75279 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 75094 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 75219 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 75226 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 75161 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 76107 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 76000 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 75939 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 75805 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 75453 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 75733 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 75604 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 75830 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts @@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 76283 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 75934 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 76261 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 75996 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 75771 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 75956 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 75972 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 75867 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 76774 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 76710 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 76671 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 76539 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 76175 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 76456 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 76301 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 76534 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts @@ -68,53 +68,53 @@ system.mem_ctrls.perBankWrBursts::13 0 # Pe system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 1424 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 7628395 # Total gap between requests +system.mem_ctrls.numWrRetry 1460 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 7678686 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 616011 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 620135 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 615980 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 25 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 195 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 967 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 3353 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 8048 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 15327 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 25449 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 36939 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 46571 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 53086 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 54456 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 51043 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 44247 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 37338 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 31432 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 28037 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 25414 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 23932 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 22731 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 21483 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 19669 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 16976 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 13632 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 9974 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 6272 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 3457 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 1526 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 549 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 137 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 27 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 620103 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 19 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 184 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 983 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 3255 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 7746 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 15554 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 26175 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 37685 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 47133 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 52357 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 54286 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 51593 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 44542 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 37610 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 32124 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 28105 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 25786 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 24080 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 22962 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 21687 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 19844 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 17181 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 13705 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 9888 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 6282 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 3447 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 1554 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 523 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 143 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 35 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 4 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see @@ -148,510 +148,510 @@ system.mem_ctrls.wrQLenPdf::28 1 # Wh system.mem_ctrls.wrQLenPdf::29 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 22 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 147 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 361 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 847 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 1615 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 3027 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 4976 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 8134 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 12086 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 14765 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 17339 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 20329 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 21789 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 23131 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 24481 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 25165 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 26727 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 28046 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 29963 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 32445 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 34376 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 36999 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 40909 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 66129 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 58716 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 24444 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 18469 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 13646 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 8729 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 5033 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 2433 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 2776 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 244245 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 317.135204 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 241.142921 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 226.912785 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 34193 14.00% 14.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 75298 30.83% 44.83% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 46291 18.95% 63.78% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 34717 14.21% 78.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 24177 9.90% 87.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 14520 5.94% 93.84% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 7856 3.22% 97.06% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3857 1.58% 98.63% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 3336 1.37% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 244245 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 38003 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 15.848354 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 8.285712 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 11.890603 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-3 13518 35.57% 35.57% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::4-7 1239 3.26% 38.83% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::8-11 331 0.87% 39.70% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-15 174 0.46% 40.16% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-19 3040 8.00% 48.16% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-23 5947 15.65% 63.81% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::24-27 5763 15.16% 78.97% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::28-31 6322 16.64% 95.61% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::32-35 1615 4.25% 99.86% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-39 53 0.14% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.wrQLenPdf::32 18 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 122 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 330 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 810 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 1760 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 3235 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 5017 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 8822 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 11772 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 14646 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 17978 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 20446 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 22363 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 23166 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 24550 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 25656 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 26802 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 28849 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 30890 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 32798 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 34545 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 37340 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 41995 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 65965 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 58297 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 24690 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 18242 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 13049 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 8033 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 4660 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 2636 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 2690 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 246538 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 316.347760 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 240.406220 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 226.949392 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 34759 14.10% 14.10% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 76086 30.86% 44.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 46939 19.04% 64.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 34923 14.17% 78.17% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 24196 9.81% 87.98% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 14479 5.87% 93.85% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 7763 3.15% 97.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 3969 1.61% 98.61% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 3424 1.39% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 246538 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 38260 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.850732 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 8.293167 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 11.882732 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-3 13623 35.61% 35.61% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::4-7 1256 3.28% 38.89% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::8-11 278 0.73% 39.62% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-15 163 0.43% 40.04% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-19 3078 8.04% 48.09% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-23 6049 15.81% 63.90% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::24-27 5774 15.09% 78.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::28-31 6360 16.62% 95.61% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::32-35 1623 4.24% 99.85% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-39 55 0.14% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::80-83 1 0.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 38003 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 38002 # Writes before turning the bus around for reads +system.mem_ctrls.rdPerTurnAround::total 38260 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 38260 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 38002 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 38002 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 113901888 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 125345303 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3011425 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 189.11 # Average queueing delay per DRAM burst +system.mem_ctrls.wrPerTurnAround::16 38260 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 38260 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 114599292 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 126122241 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3032355 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 188.96 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 208.11 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 5052.99 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 5101.27 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 5168.14 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 5167.88 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 207.96 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 5054.66 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 5102.08 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 5168.54 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 5168.28 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 79.33 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 39.48 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 39.85 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 79.35 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 39.49 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 39.86 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 18.26 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 53.79 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 367457 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 598615 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 61.01 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 98.44 # Row buffer hit rate for writes +system.mem_ctrls.avgWrQLen 53.74 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 369343 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 602743 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 60.90 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 98.45 # Row buffer hit rate for writes system.mem_ctrls.avgGap 6.19 # Average gap between requests -system.mem_ctrls.pageHitRate 79.82 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 1845176760 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 1025098200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 7510863360 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 6299379072 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 497880240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 5195257704 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 16444800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 22390100136 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 2937.248651 # Core power per rank (mW) +system.mem_ctrls.pageHitRate 79.77 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1863396360 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 1035220200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7566948480 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 6345547776 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 501440160 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 5232384540 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 16562400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 22561499916 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 2938.732659 # Core power per rank (mW) system.mem_ctrls_0.memoryStateTime::IDLE 10 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 254540 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 256360 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 7368278 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 7420933 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 497880240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 164730456 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 4429143600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 5091754296 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 667.969037 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 7368214 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 254540 # Time in different power states +system.mem_ctrls_1.refreshEnergy 501440160 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 165908304 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 4460811600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 5128160064 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.969052 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 7420896 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 256360 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 1 # Clock period in ticks -system.cpu0.num_reads 98683 # number of read accesses completed -system.cpu0.num_writes 55108 # number of write accesses completed -system.cpu1.num_reads 98569 # number of read accesses completed -system.cpu1.num_writes 55169 # number of write accesses completed -system.cpu2.num_reads 98938 # number of read accesses completed -system.cpu2.num_writes 54854 # number of write accesses completed -system.cpu3.num_reads 98908 # number of read accesses completed -system.cpu3.num_writes 55032 # number of write accesses completed -system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 54873 # number of write accesses completed -system.cpu5.num_reads 98822 # number of read accesses completed -system.cpu5.num_writes 55092 # number of write accesses completed -system.cpu6.num_reads 99067 # number of read accesses completed -system.cpu6.num_writes 55225 # number of write accesses completed -system.cpu7.num_reads 98521 # number of read accesses completed -system.cpu7.num_writes 54958 # number of write accesses completed +system.cpu0.num_reads 99754 # number of read accesses completed +system.cpu0.num_writes 55550 # number of write accesses completed +system.cpu1.num_reads 99722 # number of read accesses completed +system.cpu1.num_writes 55422 # number of write accesses completed +system.cpu2.num_reads 99859 # number of read accesses completed +system.cpu2.num_writes 56114 # number of write accesses completed +system.cpu3.num_reads 99399 # number of read accesses completed +system.cpu3.num_writes 55238 # number of write accesses completed +system.cpu4.num_reads 99564 # number of read accesses completed +system.cpu4.num_writes 55685 # number of write accesses completed +system.cpu5.num_reads 100000 # number of read accesses completed +system.cpu5.num_writes 55705 # number of write accesses completed +system.cpu6.num_reads 99381 # number of read accesses completed +system.cpu6.num_writes 55293 # number of write accesses completed +system.cpu7.num_reads 99930 # number of read accesses completed +system.cpu7.num_writes 55169 # number of write accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 32 # delay histogram for all message system.ruby.delayHist::max_bucket 319 # delay histogram for all message -system.ruby.delayHist::samples 1252435 # delay histogram for all message -system.ruby.delayHist::mean 2.287851 # delay histogram for all message -system.ruby.delayHist::stdev 7.720503 # delay histogram for all message -system.ruby.delayHist | 1234738 98.59% 98.59% | 11472 0.92% 99.50% | 5561 0.44% 99.95% | 542 0.04% 99.99% | 92 0.01% 100.00% | 30 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 1252435 # delay histogram for all message +system.ruby.delayHist::samples 1260795 # delay histogram for all message +system.ruby.delayHist::mean 2.261395 # delay histogram for all message +system.ruby.delayHist::stdev 7.584807 # delay histogram for all message +system.ruby.delayHist | 1243450 98.62% 98.62% | 11474 0.91% 99.53% | 5225 0.41% 99.95% | 542 0.04% 99.99% | 89 0.01% 100.00% | 15 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 1260795 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 624450 -system.ruby.outstanding_req_hist::mean 15.998439 -system.ruby.outstanding_req_hist::gmean 15.997169 -system.ruby.outstanding_req_hist::stdev 0.126125 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 31 0.00% 0.02% | 624315 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 624450 +system.ruby.outstanding_req_hist::samples 628584 +system.ruby.outstanding_req_hist::mean 15.998449 +system.ruby.outstanding_req_hist::gmean 15.997188 +system.ruby.outstanding_req_hist::stdev 0.125710 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 31 0.00% 0.02% | 628449 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 628584 system.ruby.latency_hist::bucket_size 512 system.ruby.latency_hist::max_bucket 5119 -system.ruby.latency_hist::samples 624322 -system.ruby.latency_hist::mean 1563.820583 -system.ruby.latency_hist::gmean 1541.725032 -system.ruby.latency_hist::stdev 262.741586 -system.ruby.latency_hist | 77 0.01% 0.01% | 6093 0.98% 0.99% | 296516 47.49% 48.48% | 294997 47.25% 95.73% | 26431 4.23% 99.97% | 208 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 624322 +system.ruby.latency_hist::samples 628456 +system.ruby.latency_hist::mean 1563.811233 +system.ruby.latency_hist::gmean 1541.792365 +system.ruby.latency_hist::stdev 262.265559 +system.ruby.latency_hist | 77 0.01% 0.01% | 6104 0.97% 0.98% | 298062 47.43% 48.41% | 297436 47.33% 95.74% | 26586 4.23% 99.97% | 191 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 628456 system.ruby.miss_latency_hist::bucket_size 512 system.ruby.miss_latency_hist::max_bucket 5119 -system.ruby.miss_latency_hist::samples 624322 -system.ruby.miss_latency_hist::mean 1563.820583 -system.ruby.miss_latency_hist::gmean 1541.725032 -system.ruby.miss_latency_hist::stdev 262.741586 -system.ruby.miss_latency_hist | 77 0.01% 0.01% | 6093 0.98% 0.99% | 296516 47.49% 48.48% | 294997 47.25% 95.73% | 26431 4.23% 99.97% | 208 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 624322 -system.ruby.L1Cache.incomplete_times 8324 -system.ruby.Directory.incomplete_times 615995 +system.ruby.miss_latency_hist::samples 628456 +system.ruby.miss_latency_hist::mean 1563.811233 +system.ruby.miss_latency_hist::gmean 1541.792365 +system.ruby.miss_latency_hist::stdev 262.265559 +system.ruby.miss_latency_hist | 77 0.01% 0.01% | 6104 0.97% 0.98% | 298062 47.43% 48.41% | 297436 47.33% 95.74% | 26586 4.23% 99.97% | 191 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 628456 +system.ruby.L1Cache.incomplete_times 8337 +system.ruby.Directory.incomplete_times 620116 system.ruby.l1_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 78210 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 78210 # Number of cache demand accesses +system.ruby.l1_cntrl0.cacheMemory.demand_misses 78526 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 78526 # Number of cache demand accesses system.ruby.l1_cntrl1.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl1.cacheMemory.demand_misses 77748 # Number of cache demand misses -system.ruby.l1_cntrl1.cacheMemory.demand_accesses 77748 # Number of cache demand accesses +system.ruby.l1_cntrl1.cacheMemory.demand_misses 78474 # Number of cache demand misses +system.ruby.l1_cntrl1.cacheMemory.demand_accesses 78474 # Number of cache demand accesses system.ruby.l1_cntrl2.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl2.cacheMemory.demand_misses 78082 # Number of cache demand misses -system.ruby.l1_cntrl2.cacheMemory.demand_accesses 78082 # Number of cache demand accesses +system.ruby.l1_cntrl2.cacheMemory.demand_misses 78844 # Number of cache demand misses +system.ruby.l1_cntrl2.cacheMemory.demand_accesses 78844 # Number of cache demand accesses system.ruby.l1_cntrl3.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl3.cacheMemory.demand_misses 77959 # Number of cache demand misses -system.ruby.l1_cntrl3.cacheMemory.demand_accesses 77959 # Number of cache demand accesses +system.ruby.l1_cntrl3.cacheMemory.demand_misses 78573 # Number of cache demand misses +system.ruby.l1_cntrl3.cacheMemory.demand_accesses 78573 # Number of cache demand accesses system.ruby.l1_cntrl4.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl4.cacheMemory.demand_misses 78377 # Number of cache demand misses -system.ruby.l1_cntrl4.cacheMemory.demand_accesses 78377 # Number of cache demand accesses +system.ruby.l1_cntrl4.cacheMemory.demand_misses 78575 # Number of cache demand misses +system.ruby.l1_cntrl4.cacheMemory.demand_accesses 78575 # Number of cache demand accesses system.ruby.l1_cntrl5.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl5.cacheMemory.demand_misses 77942 # Number of cache demand misses -system.ruby.l1_cntrl5.cacheMemory.demand_accesses 77942 # Number of cache demand accesses +system.ruby.l1_cntrl5.cacheMemory.demand_misses 78529 # Number of cache demand misses +system.ruby.l1_cntrl5.cacheMemory.demand_accesses 78529 # Number of cache demand accesses system.ruby.l1_cntrl6.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl6.cacheMemory.demand_misses 78075 # Number of cache demand misses -system.ruby.l1_cntrl6.cacheMemory.demand_accesses 78075 # Number of cache demand accesses +system.ruby.l1_cntrl6.cacheMemory.demand_misses 78440 # Number of cache demand misses +system.ruby.l1_cntrl6.cacheMemory.demand_accesses 78440 # Number of cache demand accesses system.ruby.l1_cntrl7.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl7.cacheMemory.demand_misses 77947 # Number of cache demand misses -system.ruby.l1_cntrl7.cacheMemory.demand_accesses 77947 # Number of cache demand accesses +system.ruby.l1_cntrl7.cacheMemory.demand_misses 78515 # Number of cache demand misses +system.ruby.l1_cntrl7.cacheMemory.demand_accesses 78515 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 5.142266 -system.ruby.network.routers0.msg_count.Control::2 78210 -system.ruby.network.routers0.msg_count.Data::2 77671 -system.ruby.network.routers0.msg_count.Response_Data::4 79238 -system.ruby.network.routers0.msg_count.Writeback_Control::3 78701 -system.ruby.network.routers0.msg_bytes.Control::2 625680 -system.ruby.network.routers0.msg_bytes.Data::2 5592312 -system.ruby.network.routers0.msg_bytes.Response_Data::4 5705136 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 629608 -system.ruby.network.routers1.percent_links_utilized 5.111745 -system.ruby.network.routers1.msg_count.Control::2 77747 -system.ruby.network.routers1.msg_count.Data::2 77174 -system.ruby.network.routers1.msg_count.Response_Data::4 78804 -system.ruby.network.routers1.msg_count.Writeback_Control::3 78231 -system.ruby.network.routers1.msg_bytes.Control::2 621976 -system.ruby.network.routers1.msg_bytes.Data::2 5556528 -system.ruby.network.routers1.msg_bytes.Response_Data::4 5673888 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 625848 -system.ruby.network.routers2.percent_links_utilized 5.132661 -system.ruby.network.routers2.msg_count.Control::2 78082 -system.ruby.network.routers2.msg_count.Data::2 77541 -system.ruby.network.routers2.msg_count.Response_Data::4 79075 -system.ruby.network.routers2.msg_count.Writeback_Control::3 78535 -system.ruby.network.routers2.msg_bytes.Control::2 624656 -system.ruby.network.routers2.msg_bytes.Data::2 5582952 -system.ruby.network.routers2.msg_bytes.Response_Data::4 5693400 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 628280 -system.ruby.network.routers3.percent_links_utilized 5.125838 -system.ruby.network.routers3.msg_count.Control::2 77957 -system.ruby.network.routers3.msg_count.Data::2 77400 -system.ruby.network.routers3.msg_count.Response_Data::4 79008 -system.ruby.network.routers3.msg_count.Writeback_Control::3 78451 -system.ruby.network.routers3.msg_bytes.Control::2 623656 -system.ruby.network.routers3.msg_bytes.Data::2 5572800 -system.ruby.network.routers3.msg_bytes.Response_Data::4 5688576 -system.ruby.network.routers3.msg_bytes.Writeback_Control::3 627608 -system.ruby.network.routers4.percent_links_utilized 5.152842 -system.ruby.network.routers4.msg_count.Control::2 78377 -system.ruby.network.routers4.msg_count.Data::2 77823 -system.ruby.network.routers4.msg_count.Response_Data::4 79409 -system.ruby.network.routers4.msg_count.Writeback_Control::3 78857 -system.ruby.network.routers4.msg_bytes.Control::2 627016 -system.ruby.network.routers4.msg_bytes.Data::2 5603256 -system.ruby.network.routers4.msg_bytes.Response_Data::4 5717448 -system.ruby.network.routers4.msg_bytes.Writeback_Control::3 630856 -system.ruby.network.routers5.percent_links_utilized 5.123353 -system.ruby.network.routers5.msg_count.Control::2 77942 -system.ruby.network.routers5.msg_count.Data::2 77382 -system.ruby.network.routers5.msg_count.Response_Data::4 78950 -system.ruby.network.routers5.msg_count.Writeback_Control::3 78391 -system.ruby.network.routers5.msg_bytes.Control::2 623536 -system.ruby.network.routers5.msg_bytes.Data::2 5571504 -system.ruby.network.routers5.msg_bytes.Response_Data::4 5684400 -system.ruby.network.routers5.msg_bytes.Writeback_Control::3 627128 -system.ruby.network.routers6.percent_links_utilized 5.133182 -system.ruby.network.routers6.msg_count.Control::2 78075 -system.ruby.network.routers6.msg_count.Data::2 77472 -system.ruby.network.routers6.msg_count.Response_Data::4 79160 -system.ruby.network.routers6.msg_count.Writeback_Control::3 78557 -system.ruby.network.routers6.msg_bytes.Control::2 624600 -system.ruby.network.routers6.msg_bytes.Data::2 5577984 -system.ruby.network.routers6.msg_bytes.Response_Data::4 5699520 -system.ruby.network.routers6.msg_bytes.Writeback_Control::3 628456 -system.ruby.network.routers7.percent_links_utilized 5.123455 -system.ruby.network.routers7.msg_count.Control::2 77947 -system.ruby.network.routers7.msg_count.Data::2 77333 -system.ruby.network.routers7.msg_count.Response_Data::4 79002 -system.ruby.network.routers7.msg_count.Writeback_Control::3 78390 -system.ruby.network.routers7.msg_bytes.Control::2 623576 -system.ruby.network.routers7.msg_bytes.Data::2 5567976 -system.ruby.network.routers7.msg_bytes.Response_Data::4 5688144 -system.ruby.network.routers7.msg_bytes.Writeback_Control::3 627120 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+system.ruby.network.routers1.throttle1.msg_count.Data::2 77933 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1013 +system.ruby.network.routers1.throttle1.msg_bytes.Control::2 627792 +system.ruby.network.routers1.throttle1.msg_bytes.Data::2 5611176 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 72936 +system.ruby.network.routers2.throttle0.link_utilization 5.136920 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 78843 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 79329 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5676696 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 634632 +system.ruby.network.routers2.throttle1.link_utilization 5.162242 +system.ruby.network.routers2.throttle1.msg_count.Control::2 78844 +system.ruby.network.routers2.throttle1.msg_count.Data::2 78287 +system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1042 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 630752 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5636664 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 75024 +system.ruby.network.routers3.throttle0.link_utilization 5.119365 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 78570 +system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 79090 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5657040 +system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 632720 +system.ruby.network.routers3.throttle1.link_utilization 5.146472 +system.ruby.network.routers3.throttle1.msg_count.Control::2 78573 +system.ruby.network.routers3.throttle1.msg_count.Data::2 78015 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 1075 +system.ruby.network.routers3.throttle1.msg_bytes.Control::2 628584 +system.ruby.network.routers3.throttle1.msg_bytes.Data::2 5617080 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 77400 +system.ruby.network.routers4.throttle0.link_utilization 5.119248 +system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 78574 +system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 79036 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5657328 +system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 632288 +system.ruby.network.routers4.throttle1.link_utilization 5.143320 +system.ruby.network.routers4.throttle1.msg_count.Control::2 78575 +system.ruby.network.routers4.throttle1.msg_count.Data::2 78023 +system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 1013 +system.ruby.network.routers4.throttle1.msg_bytes.Control::2 628600 +system.ruby.network.routers4.throttle1.msg_bytes.Data::2 5617656 +system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 72936 +system.ruby.network.routers5.throttle0.link_utilization 5.116279 +system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 78525 +system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 79024 +system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5653800 +system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 632192 +system.ruby.network.routers5.throttle1.link_utilization 5.142292 +system.ruby.network.routers5.throttle1.msg_count.Control::2 78525 +system.ruby.network.routers5.throttle1.msg_count.Data::2 77953 +system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 1071 +system.ruby.network.routers5.throttle1.msg_bytes.Control::2 628200 +system.ruby.network.routers5.throttle1.msg_bytes.Data::2 5612616 +system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 77112 +system.ruby.network.routers6.throttle0.link_utilization 5.110633 +system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 78438 +system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 78937 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5647536 +system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 631496 +system.ruby.network.routers6.throttle1.link_utilization 5.136640 +system.ruby.network.routers6.throttle1.msg_count.Control::2 78440 +system.ruby.network.routers6.throttle1.msg_count.Data::2 77859 +system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 1078 +system.ruby.network.routers6.throttle1.msg_bytes.Control::2 627520 +system.ruby.network.routers6.throttle1.msg_bytes.Data::2 5605848 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4 77616 +system.ruby.network.routers7.throttle0.link_utilization 5.115302 +system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 78512 +system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 78988 +system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5652864 +system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 631904 +system.ruby.network.routers7.throttle1.link_utilization 5.140117 +system.ruby.network.routers7.throttle1.msg_count.Control::2 78515 +system.ruby.network.routers7.throttle1.msg_count.Data::2 77951 +system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 1037 +system.ruby.network.routers7.throttle1.msg_bytes.Control::2 628120 +system.ruby.network.routers7.throttle1.msg_bytes.Data::2 5612472 +system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 74664 +system.ruby.network.routers8.throttle0.link_utilization 40.660151 +system.ruby.network.routers8.throttle0.msg_count.Control::2 628472 +system.ruby.network.routers8.throttle0.msg_count.Data::2 624002 +system.ruby.network.routers8.throttle0.msg_bytes.Control::2 5027776 +system.ruby.network.routers8.throttle0.msg_bytes.Data::2 44928144 +system.ruby.network.routers8.throttle1.link_utilization 40.457804 +system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 620120 +system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 632339 +system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 44648640 +system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3 5058712 +system.ruby.network.routers9.throttle0.link_utilization 5.115953 +system.ruby.network.routers9.throttle0.msg_count.Response_Data::4 78523 +system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3 78989 +system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5653656 +system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 631912 +system.ruby.network.routers9.throttle1.link_utilization 5.112626 +system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 78471 +system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 78946 +system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5649912 +system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 631568 +system.ruby.network.routers9.throttle2.link_utilization 5.136920 +system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 78843 +system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 79329 +system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5676696 +system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 634632 +system.ruby.network.routers9.throttle3.link_utilization 5.119365 +system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 78570 +system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 79090 +system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5657040 +system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 632720 +system.ruby.network.routers9.throttle4.link_utilization 5.119248 +system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78574 +system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 79036 +system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5657328 +system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 632288 +system.ruby.network.routers9.throttle5.link_utilization 5.116298 +system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78525 +system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 79024 +system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5653800 +system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 632192 +system.ruby.network.routers9.throttle6.link_utilization 5.110633 +system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78438 +system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 78937 +system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5647536 +system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 631496 +system.ruby.network.routers9.throttle7.link_utilization 5.115302 +system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 78512 +system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 78988 +system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5652864 +system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 631904 +system.ruby.network.routers9.throttle8.link_utilization 40.660151 +system.ruby.network.routers9.throttle8.msg_count.Control::2 628472 +system.ruby.network.routers9.throttle8.msg_count.Data::2 624002 +system.ruby.network.routers9.throttle8.msg_bytes.Control::2 5027776 +system.ruby.network.routers9.throttle8.msg_bytes.Data::2 44928144 system.ruby.delayVCHist.vnet_1::bucket_size 4 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 39 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 624322 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.273740 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 1.333932 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 598643 95.89% 95.89% | 18636 2.98% 98.87% | 6023 0.96% 99.84% | 827 0.13% 99.97% | 164 0.03% 100.00% | 26 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 624322 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 628456 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.270507 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 1.327302 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 602976 95.95% 95.95% | 18460 2.94% 98.88% | 5975 0.95% 99.83% | 853 0.14% 99.97% | 168 0.03% 100.00% | 23 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 628456 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 32 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 319 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 628113 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 4.289806 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 10.442415 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 610416 97.18% 97.18% | 11472 1.83% 99.01% | 5561 0.89% 99.89% | 542 0.09% 99.98% | 92 0.01% 100.00% | 30 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 628113 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 632339 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 4.240058 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 10.251834 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 614994 97.26% 97.26% | 11474 1.81% 99.07% | 5225 0.83% 99.90% | 542 0.09% 99.98% | 89 0.01% 100.00% | 15 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 632339 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 512 system.ruby.LD.latency_hist::max_bucket 5119 -system.ruby.LD.latency_hist::samples 401809 -system.ruby.LD.latency_hist::mean 1563.925664 -system.ruby.LD.latency_hist::gmean 1541.792276 -system.ruby.LD.latency_hist::stdev 262.933960 -system.ruby.LD.latency_hist | 49 0.01% 0.01% | 3928 0.98% 0.99% | 190800 47.49% 48.48% | 189845 47.25% 95.72% | 17056 4.24% 99.97% | 131 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 401809 +system.ruby.LD.latency_hist::samples 404420 +system.ruby.LD.latency_hist::mean 1563.542728 +system.ruby.LD.latency_hist::gmean 1541.515221 +system.ruby.LD.latency_hist::stdev 262.248075 +system.ruby.LD.latency_hist | 49 0.01% 0.01% | 3881 0.96% 0.97% | 192068 47.49% 48.46% | 191307 47.30% 95.77% | 16988 4.20% 99.97% | 127 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 404420 system.ruby.LD.miss_latency_hist::bucket_size 512 system.ruby.LD.miss_latency_hist::max_bucket 5119 -system.ruby.LD.miss_latency_hist::samples 401809 -system.ruby.LD.miss_latency_hist::mean 1563.925664 -system.ruby.LD.miss_latency_hist::gmean 1541.792276 -system.ruby.LD.miss_latency_hist::stdev 262.933960 -system.ruby.LD.miss_latency_hist | 49 0.01% 0.01% | 3928 0.98% 0.99% | 190800 47.49% 48.48% | 189845 47.25% 95.72% | 17056 4.24% 99.97% | 131 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 401809 +system.ruby.LD.miss_latency_hist::samples 404420 +system.ruby.LD.miss_latency_hist::mean 1563.542728 +system.ruby.LD.miss_latency_hist::gmean 1541.515221 +system.ruby.LD.miss_latency_hist::stdev 262.248075 +system.ruby.LD.miss_latency_hist | 49 0.01% 0.01% | 3881 0.96% 0.97% | 192068 47.49% 48.46% | 191307 47.30% 95.77% | 16988 4.20% 99.97% | 127 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 404420 system.ruby.ST.latency_hist::bucket_size 512 system.ruby.ST.latency_hist::max_bucket 5119 -system.ruby.ST.latency_hist::samples 222513 -system.ruby.ST.latency_hist::mean 1563.630831 -system.ruby.ST.latency_hist::gmean 1541.603612 -system.ruby.ST.latency_hist::stdev 262.394328 -system.ruby.ST.latency_hist | 28 0.01% 0.01% | 2165 0.97% 0.99% | 105716 47.51% 48.50% | 105152 47.26% 95.75% | 9375 4.21% 99.97% | 77 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 222513 +system.ruby.ST.latency_hist::samples 224036 +system.ruby.ST.latency_hist::mean 1564.295926 +system.ruby.ST.latency_hist::gmean 1542.292779 +system.ruby.ST.latency_hist::stdev 262.297007 +system.ruby.ST.latency_hist | 28 0.01% 0.01% | 2223 0.99% 1.00% | 105994 47.31% 48.32% | 106129 47.37% 95.69% | 9598 4.28% 99.97% | 64 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 224036 system.ruby.ST.miss_latency_hist::bucket_size 512 system.ruby.ST.miss_latency_hist::max_bucket 5119 -system.ruby.ST.miss_latency_hist::samples 222513 -system.ruby.ST.miss_latency_hist::mean 1563.630831 -system.ruby.ST.miss_latency_hist::gmean 1541.603612 -system.ruby.ST.miss_latency_hist::stdev 262.394328 -system.ruby.ST.miss_latency_hist | 28 0.01% 0.01% | 2165 0.97% 0.99% | 105716 47.51% 48.50% | 105152 47.26% 95.75% | 9375 4.21% 99.97% | 77 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 222513 -system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 256 -system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 2559 -system.ruby.L1Cache.miss_mach_latency_hist::samples 8324 -system.ruby.L1Cache.miss_mach_latency_hist::mean 1452.515377 -system.ruby.L1Cache.miss_mach_latency_hist::gmean 1428.361700 -system.ruby.L1Cache.miss_mach_latency_hist::stdev 265.488417 -system.ruby.L1Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 1 0.01% 0.01% | 7 0.08% 0.10% | 306 3.68% 3.77% | 1921 23.08% 26.85% | 3141 37.73% 64.58% | 2036 24.46% 89.04% | 739 8.88% 97.92% | 154 1.85% 99.77% | 19 0.23% 100.00% -system.ruby.L1Cache.miss_mach_latency_hist::total 8324 +system.ruby.ST.miss_latency_hist::samples 224036 +system.ruby.ST.miss_latency_hist::mean 1564.295926 +system.ruby.ST.miss_latency_hist::gmean 1542.292779 +system.ruby.ST.miss_latency_hist::stdev 262.297007 +system.ruby.ST.miss_latency_hist | 28 0.01% 0.01% | 2223 0.99% 1.00% | 105994 47.31% 48.32% | 106129 47.37% 95.69% | 9598 4.28% 99.97% | 64 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 224036 +system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 512 +system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 5119 +system.ruby.L1Cache.miss_mach_latency_hist::samples 8337 +system.ruby.L1Cache.miss_mach_latency_hist::mean 1457.519731 +system.ruby.L1Cache.miss_mach_latency_hist::gmean 1434.160972 +system.ruby.L1Cache.miss_mach_latency_hist::stdev 261.316891 +system.ruby.L1Cache.miss_mach_latency_hist | 1 0.01% 0.01% | 260 3.12% 3.13% | 5041 60.47% 63.60% | 2865 34.36% 97.96% | 168 2.02% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist::total 8337 system.ruby.Directory.miss_mach_latency_hist::bucket_size 512 system.ruby.Directory.miss_mach_latency_hist::max_bucket 5119 -system.ruby.Directory.miss_mach_latency_hist::samples 615998 -system.ruby.Directory.miss_mach_latency_hist::mean 1565.324654 -system.ruby.Directory.miss_mach_latency_hist::gmean 1543.316978 -system.ruby.Directory.miss_mach_latency_hist::stdev 262.381355 -system.ruby.Directory.miss_mach_latency_hist | 76 0.01% 0.01% | 5780 0.94% 0.95% | 291454 47.31% 48.26% | 292222 47.44% 95.70% | 26258 4.26% 99.97% | 208 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 615998 +system.ruby.Directory.miss_mach_latency_hist::samples 620119 +system.ruby.Directory.miss_mach_latency_hist::mean 1565.240236 +system.ruby.Directory.miss_mach_latency_hist::gmean 1543.293101 +system.ruby.Directory.miss_mach_latency_hist::stdev 261.984881 +system.ruby.Directory.miss_mach_latency_hist | 76 0.01% 0.01% | 5844 0.94% 0.95% | 293021 47.25% 48.21% | 294571 47.50% 95.71% | 26418 4.26% 99.97% | 189 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 620119 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 3 @@ -677,82 +677,82 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion | system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 3 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 256 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 2559 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 5317 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1454.698890 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1430.943936 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 262.990374 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 1 0.02% 0.02% | 7 0.13% 0.15% | 178 3.35% 3.50% | 1222 22.98% 26.48% | 2001 37.63% 64.12% | 1329 25.00% 89.11% | 476 8.95% 98.06% | 94 1.77% 99.83% | 9 0.17% 100.00% -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 5317 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 5455 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1456.778185 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1433.055554 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 263.122030 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 1 0.02% 0.02% | 6 0.11% 0.13% | 171 3.13% 3.26% | 1270 23.28% 26.54% | 2035 37.31% 63.85% | 1383 25.35% 89.20% | 473 8.67% 97.87% | 103 1.89% 99.76% | 13 0.24% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 5455 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 396492 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1565.390406 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 1543.335680 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 262.625035 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 48 0.01% 0.01% | 3743 0.94% 0.96% | 187577 47.31% 48.27% | 188040 47.43% 95.69% | 16953 4.28% 99.97% | 131 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 396492 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 256 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 2559 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 3007 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1448.654473 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 1423.807170 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 269.849701 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 128 4.26% 4.26% | 699 23.25% 27.50% | 1140 37.91% 65.41% | 707 23.51% 88.93% | 263 8.75% 97.67% | 60 2.00% 99.67% | 10 0.33% 100.00% -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 3007 +system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 398965 +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1565.002506 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 1543.053698 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 261.935038 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 48 0.01% 0.01% | 3704 0.93% 0.94% | 188763 47.31% 48.25% | 189451 47.49% 95.74% | 16872 4.23% 99.97% | 127 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::total 398965 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 512 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 2882 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1458.923317 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 1436.255624 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 257.905109 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 83 2.88% 2.88% | 1736 60.24% 63.12% | 1009 35.01% 98.13% | 52 1.80% 99.93% | 2 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 2882 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 219506 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1565.205885 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 1543.283197 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 261.941179 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 28 0.01% 0.01% | 2037 0.93% 0.94% | 103877 47.32% 48.26% | 104182 47.46% 95.73% | 9305 4.24% 99.96% | 77 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 219506 -system.ruby.Directory_Controller.GETX 688579 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 615980 0.00% 0.00% -system.ruby.Directory_Controller.PUTX_NotOwner 3813 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 615999 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 615978 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 616011 0.00% 0.00% -system.ruby.Directory_Controller.M.GETX 8324 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 615980 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX_NotOwner 3813 0.00% 0.00% -system.ruby.Directory_Controller.IM.GETX 63966 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 615999 0.00% 0.00% -system.ruby.Directory_Controller.MI.GETX 278 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 615978 0.00% 0.00% -system.ruby.L1Cache_Controller.Load | 50212 12.50% 12.50% | 49807 12.40% 24.89% | 50313 12.52% 37.41% | 50234 12.50% 49.91% | 50688 12.61% 62.53% | 50127 12.47% 75.00% | 50243 12.50% 87.51% | 50196 12.49% 100.00% -system.ruby.L1Cache_Controller.Load::total 401820 -system.ruby.L1Cache_Controller.Store | 27998 12.58% 12.58% | 27941 12.56% 25.14% | 27769 12.48% 37.62% | 27725 12.46% 50.08% | 27689 12.44% 62.52% | 27815 12.50% 75.02% | 27832 12.51% 87.53% | 27751 12.47% 100.00% -system.ruby.L1Cache_Controller.Store::total 222520 -system.ruby.L1Cache_Controller.Data | 78208 12.53% 12.53% | 77745 12.45% 24.98% | 78081 12.51% 37.49% | 77956 12.49% 49.97% | 78375 12.55% 62.53% | 77941 12.48% 75.01% | 78073 12.51% 87.52% | 77943 12.48% 100.00% -system.ruby.L1Cache_Controller.Data::total 624322 -system.ruby.L1Cache_Controller.Fwd_GETX | 1030 12.37% 12.37% | 1059 12.72% 25.10% | 994 11.94% 37.04% | 1052 12.64% 49.68% | 1034 12.42% 62.10% | 1009 12.12% 74.22% | 1087 13.06% 87.28% | 1059 12.72% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 8324 -system.ruby.L1Cache_Controller.Replacement | 78206 12.53% 12.53% | 77744 12.45% 24.98% | 78078 12.51% 37.49% | 77955 12.49% 49.97% | 78373 12.55% 62.53% | 77938 12.48% 75.01% | 78071 12.51% 87.52% | 77943 12.48% 100.00% -system.ruby.L1Cache_Controller.Replacement::total 624308 -system.ruby.L1Cache_Controller.Writeback_Ack | 77176 12.53% 12.53% | 76683 12.45% 24.98% | 77084 12.51% 37.49% | 76901 12.48% 49.98% | 77339 12.56% 62.53% | 76929 12.49% 75.02% | 76982 12.50% 87.52% | 76882 12.48% 100.00% -system.ruby.L1Cache_Controller.Writeback_Ack::total 615976 -system.ruby.L1Cache_Controller.Writeback_Nack | 495 12.98% 12.98% | 489 12.82% 25.81% | 457 11.99% 37.79% | 498 13.06% 50.85% | 484 12.69% 63.55% | 453 11.88% 75.43% | 488 12.80% 88.22% | 449 11.78% 100.00% -system.ruby.L1Cache_Controller.Writeback_Nack::total 3813 -system.ruby.L1Cache_Controller.I.Load | 50212 12.50% 12.50% | 49807 12.40% 24.89% | 50313 12.52% 37.41% | 50234 12.50% 49.91% | 50688 12.61% 62.53% | 50127 12.47% 75.00% | 50243 12.50% 87.51% | 50196 12.49% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 401820 -system.ruby.L1Cache_Controller.I.Store | 27998 12.58% 12.58% | 27941 12.56% 25.14% | 27769 12.48% 37.62% | 27725 12.46% 50.08% | 27689 12.44% 62.52% | 27815 12.50% 75.02% | 27832 12.51% 87.53% | 27751 12.47% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 222520 -system.ruby.L1Cache_Controller.I.Replacement | 535 11.86% 11.86% | 570 12.64% 24.50% | 537 11.90% 36.40% | 554 12.28% 48.68% | 550 12.19% 60.87% | 556 12.33% 73.20% | 599 13.28% 86.48% | 610 13.52% 100.00% -system.ruby.L1Cache_Controller.I.Replacement::total 4511 -system.ruby.L1Cache_Controller.II.Writeback_Nack | 495 12.98% 12.98% | 489 12.82% 25.81% | 457 11.99% 37.79% | 498 13.06% 50.85% | 484 12.69% 63.55% | 453 11.88% 75.43% | 488 12.80% 88.22% | 449 11.78% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Nack::total 3813 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 535 11.86% 11.86% | 570 12.64% 24.50% | 537 11.90% 36.40% | 554 12.28% 48.68% | 550 12.19% 60.87% | 556 12.33% 73.20% | 599 13.28% 86.48% | 610 13.52% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 4511 -system.ruby.L1Cache_Controller.M.Replacement | 77671 12.53% 12.53% | 77174 12.45% 24.98% | 77541 12.51% 37.49% | 77401 12.49% 49.98% | 77823 12.56% 62.54% | 77382 12.49% 75.02% | 77472 12.50% 87.52% | 77333 12.48% 100.00% -system.ruby.L1Cache_Controller.M.Replacement::total 619797 -system.ruby.L1Cache_Controller.MI.Fwd_GETX | 495 12.98% 12.98% | 489 12.82% 25.81% | 457 11.99% 37.79% | 498 13.06% 50.85% | 484 12.69% 63.55% | 453 11.88% 75.43% | 488 12.80% 88.22% | 449 11.78% 100.00% -system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 3813 -system.ruby.L1Cache_Controller.MI.Writeback_Ack | 77176 12.53% 12.53% | 76683 12.45% 24.98% | 77084 12.51% 37.49% | 76901 12.48% 49.98% | 77339 12.56% 62.53% | 76929 12.49% 75.02% | 76982 12.50% 87.52% | 76882 12.48% 100.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 615976 -system.ruby.L1Cache_Controller.IS.Data | 50212 12.50% 12.50% | 49804 12.39% 24.89% | 50312 12.52% 37.41% | 50234 12.50% 49.91% | 50686 12.61% 62.53% | 50127 12.48% 75.00% | 50242 12.50% 87.51% | 50192 12.49% 100.00% -system.ruby.L1Cache_Controller.IS.Data::total 401809 -system.ruby.L1Cache_Controller.IM.Data | 27996 12.58% 12.58% | 27941 12.56% 25.14% | 27769 12.48% 37.62% | 27722 12.46% 50.08% | 27689 12.44% 62.52% | 27814 12.50% 75.02% | 27831 12.51% 87.53% | 27751 12.47% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 222513 +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 221154 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1565.669104 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 1543.725080 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 262.074821 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 28 0.01% 0.01% | 2140 0.97% 0.98% | 104258 47.14% 48.12% | 105120 47.53% 95.66% | 9546 4.32% 99.97% | 62 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 221154 +system.ruby.Directory_Controller.GETX 695129 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 620103 0.00% 0.00% +system.ruby.Directory_Controller.PUTX_NotOwner 3899 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 620120 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 620103 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 620135 0.00% 0.00% +system.ruby.Directory_Controller.M.GETX 8337 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 620103 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX_NotOwner 3899 0.00% 0.00% +system.ruby.Directory_Controller.IM.GETX 66370 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 620120 0.00% 0.00% +system.ruby.Directory_Controller.MI.GETX 287 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 620103 0.00% 0.00% +system.ruby.L1Cache_Controller.Load | 50377 12.46% 12.46% | 50576 12.51% 24.96% | 50610 12.51% 37.48% | 50632 12.52% 49.99% | 50644 12.52% 62.52% | 50559 12.50% 75.02% | 50404 12.46% 87.48% | 50629 12.52% 100.00% +system.ruby.L1Cache_Controller.Load::total 404431 +system.ruby.L1Cache_Controller.Store | 28149 12.56% 12.56% | 27898 12.45% 25.02% | 28234 12.60% 37.62% | 27941 12.47% 50.09% | 27931 12.47% 62.56% | 27970 12.48% 75.04% | 28036 12.51% 87.55% | 27886 12.45% 100.00% +system.ruby.L1Cache_Controller.Store::total 224045 +system.ruby.L1Cache_Controller.Data | 78523 12.49% 12.49% | 78471 12.49% 24.98% | 78843 12.55% 37.53% | 78570 12.50% 50.03% | 78574 12.50% 62.53% | 78525 12.49% 75.03% | 78438 12.48% 87.51% | 78512 12.49% 100.00% +system.ruby.L1Cache_Controller.Data::total 628456 +system.ruby.L1Cache_Controller.Fwd_GETX | 1008 12.09% 12.09% | 1013 12.15% 24.24% | 1042 12.50% 36.74% | 1075 12.89% 49.63% | 1013 12.15% 61.78% | 1071 12.85% 74.63% | 1078 12.93% 87.56% | 1037 12.44% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 8337 +system.ruby.L1Cache_Controller.Replacement | 78522 12.49% 12.49% | 78470 12.49% 24.98% | 78840 12.55% 37.53% | 78569 12.50% 50.03% | 78571 12.50% 62.53% | 78525 12.50% 75.03% | 78436 12.48% 87.51% | 78511 12.49% 100.00% +system.ruby.L1Cache_Controller.Replacement::total 628444 +system.ruby.L1Cache_Controller.Writeback_Ack | 77514 12.50% 12.50% | 77457 12.49% 24.99% | 77798 12.55% 37.54% | 77494 12.50% 50.03% | 77558 12.51% 62.54% | 77450 12.49% 75.03% | 77358 12.48% 87.51% | 77474 12.49% 100.00% +system.ruby.L1Cache_Controller.Writeback_Ack::total 620103 +system.ruby.L1Cache_Controller.Writeback_Nack | 467 11.98% 11.98% | 476 12.21% 24.19% | 489 12.54% 36.73% | 521 13.36% 50.09% | 465 11.93% 62.02% | 503 12.90% 74.92% | 501 12.85% 87.77% | 477 12.23% 100.00% +system.ruby.L1Cache_Controller.Writeback_Nack::total 3899 +system.ruby.L1Cache_Controller.I.Load | 50377 12.46% 12.46% | 50576 12.51% 24.96% | 50610 12.51% 37.48% | 50632 12.52% 49.99% | 50644 12.52% 62.52% | 50559 12.50% 75.02% | 50404 12.46% 87.48% | 50629 12.52% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 404431 +system.ruby.L1Cache_Controller.I.Store | 28149 12.56% 12.56% | 27898 12.45% 25.02% | 28234 12.60% 37.62% | 27941 12.47% 50.09% | 27931 12.47% 62.56% | 27970 12.48% 75.04% | 28036 12.51% 87.55% | 27886 12.45% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 224045 +system.ruby.L1Cache_Controller.I.Replacement | 541 12.19% 12.19% | 537 12.10% 24.29% | 553 12.46% 36.75% | 554 12.48% 49.23% | 548 12.35% 61.58% | 568 12.80% 74.38% | 577 13.00% 87.38% | 560 12.62% 100.00% +system.ruby.L1Cache_Controller.I.Replacement::total 4438 +system.ruby.L1Cache_Controller.II.Writeback_Nack | 467 11.98% 11.98% | 476 12.21% 24.19% | 489 12.54% 36.73% | 521 13.36% 50.09% | 465 11.93% 62.02% | 503 12.90% 74.92% | 501 12.85% 87.77% | 477 12.23% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Nack::total 3899 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 541 12.19% 12.19% | 537 12.10% 24.29% | 553 12.46% 36.75% | 554 12.48% 49.23% | 548 12.35% 61.58% | 568 12.80% 74.38% | 577 13.00% 87.38% | 560 12.62% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 4438 +system.ruby.L1Cache_Controller.M.Replacement | 77981 12.50% 12.50% | 77933 12.49% 24.99% | 78287 12.55% 37.53% | 78015 12.50% 50.03% | 78023 12.50% 62.54% | 77957 12.49% 75.03% | 77859 12.48% 87.51% | 77951 12.49% 100.00% +system.ruby.L1Cache_Controller.M.Replacement::total 624006 +system.ruby.L1Cache_Controller.MI.Fwd_GETX | 467 11.98% 11.98% | 476 12.21% 24.19% | 489 12.54% 36.73% | 521 13.36% 50.09% | 465 11.93% 62.02% | 503 12.90% 74.92% | 501 12.85% 87.77% | 477 12.23% 100.00% +system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 3899 +system.ruby.L1Cache_Controller.MI.Writeback_Ack | 77514 12.50% 12.50% | 77457 12.49% 24.99% | 77798 12.55% 37.54% | 77494 12.50% 50.03% | 77558 12.51% 62.54% | 77450 12.49% 75.03% | 77358 12.48% 87.51% | 77474 12.49% 100.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 620103 +system.ruby.L1Cache_Controller.IS.Data | 50375 12.46% 12.46% | 50575 12.51% 24.96% | 50609 12.51% 37.48% | 50632 12.52% 50.00% | 50643 12.52% 62.52% | 50556 12.50% 75.02% | 50402 12.46% 87.48% | 50628 12.52% 100.00% +system.ruby.L1Cache_Controller.IS.Data::total 404420 +system.ruby.L1Cache_Controller.IM.Data | 28148 12.56% 12.56% | 27896 12.45% 25.02% | 28234 12.60% 37.62% | 27938 12.47% 50.09% | 27931 12.47% 62.56% | 27969 12.48% 75.04% | 28036 12.51% 87.55% | 27884 12.45% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 224036 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index 61ea5a710..00706da1e 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -1,1819 +1,1819 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000518 # Number of seconds simulated -sim_ticks 518362500 # Number of ticks simulated -final_tick 518362500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000541 # Number of seconds simulated +sim_ticks 540820000 # Number of ticks simulated +final_tick 540820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 97254136 # Simulator tick rate (ticks/s) -host_mem_usage 280792 # Number of bytes of host memory used -host_seconds 5.33 # Real time elapsed on the host +host_tick_rate 106172397 # Simulator tick rate (ticks/s) +host_mem_usage 280772 # Number of bytes of host memory used +host_seconds 5.09 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 83556 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 80496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 82210 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 83458 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 79724 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 80437 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 82031 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 84431 # Number of bytes read from this memory -system.physmem.bytes_read::total 656343 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 416960 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5350 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5428 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5478 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5268 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5521 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5505 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5477 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5442 # Number of bytes written to this memory -system.physmem.bytes_written::total 460429 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10980 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10944 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11020 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10882 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10676 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11074 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11030 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10910 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87516 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6515 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5350 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5428 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5478 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5268 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5521 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5505 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5477 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5442 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49984 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 161192216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 155289011 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 158595577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 161003159 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 153799706 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 155175191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 158250259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 162880224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1266185343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 804379175 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 10320963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 10471436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 10567894 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 10162772 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 10650848 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 10619981 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 10565965 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 10498445 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 888237479 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 804379175 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 171513179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 165760448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 169163472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 171165931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 164450553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 165795172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 168816224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 173378668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2154422822 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 88157 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 82701 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 84142 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 82645 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 83993 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 79749 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 78765 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 84222 # Number of bytes read from this memory +system.physmem.bytes_read::total 664374 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 426368 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5567 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5462 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5416 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5447 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5329 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5472 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5531 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5421 # Number of bytes written to this memory +system.physmem.bytes_written::total 470013 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11108 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10881 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10951 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11102 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10890 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10914 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11079 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87861 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6662 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5567 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5462 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5416 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5447 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5329 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5472 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5531 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5421 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50307 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 163006176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 152917792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 155582264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 152814245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 155306756 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 147459413 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 145639954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 155730187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1228456788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 788373211 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10293628 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 10099479 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 10014423 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 10071743 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 9853556 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10117969 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 10227063 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10023668 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 869074738 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 788373211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 173299804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 163017270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 165596687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 162885988 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 165160312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 157577382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 155867017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 165753855 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2097531526 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99891 # number of read accesses completed -system.cpu0.num_writes 54838 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22327 # number of replacements -system.cpu0.l1c.tags.tagsinuse 391.597191 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13273 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22716 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.584302 # Average number of references to valid blocks. +system.cpu0.num_reads 99596 # number of read accesses completed +system.cpu0.num_writes 55268 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22066 # number of replacements +system.cpu0.l1c.tags.tagsinuse 391.486377 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13717 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22459 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.610757 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 391.597191 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.764838 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.764838 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 337776 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 337776 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8714 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8714 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1148 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1148 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9862 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9862 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9862 # number of overall hits -system.cpu0.l1c.overall_hits::total 9862 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36629 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36629 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23739 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23739 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60368 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60368 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60368 # number of overall misses -system.cpu0.l1c.overall_misses::total 60368 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 614304512 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 614304512 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 680799251 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 680799251 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1295103763 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1295103763 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1295103763 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1295103763 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45343 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45343 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24887 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24887 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70230 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70230 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70230 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70230 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807820 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.807820 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953871 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.953871 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.859576 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.859576 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.859576 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.859576 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16770.987797 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 16770.987797 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 28678.514301 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 28678.514301 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 21453.481364 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 21453.481364 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 21453.481364 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 21453.481364 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 764972 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 391.486377 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.764622 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.764622 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 338295 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 338295 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8878 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8878 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1162 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1162 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 10040 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 10040 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 10040 # number of overall hits +system.cpu0.l1c.overall_hits::total 10040 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36478 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36478 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23899 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23899 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60377 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60377 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60377 # number of overall misses +system.cpu0.l1c.overall_misses::total 60377 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 603408975 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 603408975 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 722750184 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 722750184 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1326159159 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1326159159 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1326159159 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1326159159 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45356 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45356 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25061 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25061 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70417 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70417 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70417 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70417 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.804260 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.804260 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953633 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.953633 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.857421 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.857421 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.857421 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.857421 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16541.723093 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 16541.723093 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 30241.858823 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 30241.858823 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 21964.641486 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 21964.641486 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 21964.641486 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 21964.641486 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 828428 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 61598 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 62795 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.418780 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 13.192579 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9814 # number of writebacks -system.cpu0.l1c.writebacks::total 9814 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36629 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36629 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23739 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23739 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60368 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60368 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60368 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60368 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9828 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9828 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5350 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5350 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15178 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15178 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 577676512 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 577676512 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 657061251 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 657061251 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1234737763 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1234737763 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1234737763 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1234737763 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 645410094 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 645410094 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 821386793 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 821386793 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1466796887 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1466796887 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807820 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807820 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953871 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953871 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859576 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.859576 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859576 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.859576 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15771.015097 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15771.015097 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 27678.556426 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 27678.556426 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20453.514494 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20453.514494 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20453.514494 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20453.514494 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 65670.542735 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65670.542735 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 153530.241682 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153530.241682 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 96639.668402 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 96639.668402 # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9669 # number of writebacks +system.cpu0.l1c.writebacks::total 9669 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36478 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36478 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23899 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23899 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60377 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60377 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60377 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60377 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9885 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9885 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5567 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5567 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15452 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15452 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 566933975 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 566933975 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 698852184 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 698852184 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1265786159 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1265786159 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1265786159 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1265786159 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 722511018 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 722511018 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 853790554 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 853790554 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1576301572 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1576301572 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.804260 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.804260 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953633 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953633 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.857421 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.857421 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.857421 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.857421 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15541.805335 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15541.805335 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 29241.900665 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 29241.900665 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20964.707736 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20964.707736 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20964.707736 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20964.707736 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 73091.655842 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73091.655842 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 153366.365008 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153366.365008 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 102012.786177 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 102012.786177 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99259 # number of read accesses completed -system.cpu1.num_writes 55194 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22288 # number of replacements -system.cpu1.l1c.tags.tagsinuse 392.187813 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13481 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22683 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.594322 # Average number of references to valid blocks. +system.cpu1.num_reads 98929 # number of read accesses completed +system.cpu1.num_writes 55238 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22532 # number of replacements +system.cpu1.l1c.tags.tagsinuse 392.132482 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13440 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22931 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.586106 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 392.187813 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.765992 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.765992 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 337082 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 337082 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8742 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8742 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1127 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1127 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9869 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9869 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9869 # number of overall hits -system.cpu1.l1c.overall_hits::total 9869 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36456 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36456 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23797 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23797 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60253 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60253 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60253 # number of overall misses -system.cpu1.l1c.overall_misses::total 60253 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 609449513 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 609449513 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 681132433 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 681132433 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1290581946 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1290581946 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1290581946 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1290581946 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45198 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45198 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24924 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24924 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70122 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70122 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70122 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70122 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806584 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.806584 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954783 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954783 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.859260 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.859260 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.859260 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.859260 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16717.399413 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 16717.399413 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 28622.617683 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 28622.617683 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 21419.380711 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 21419.380711 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 21419.380711 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 21419.380711 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 761379 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 392.132482 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.765884 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.765884 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 338385 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 338385 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8754 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8754 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1152 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1152 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9906 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9906 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9906 # number of overall hits +system.cpu1.l1c.overall_hits::total 9906 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36277 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36277 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 24198 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 24198 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60475 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60475 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60475 # number of overall misses +system.cpu1.l1c.overall_misses::total 60475 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 602891984 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 602891984 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 733995398 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 733995398 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1336887382 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1336887382 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1336887382 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1336887382 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45031 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45031 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25350 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25350 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70381 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70381 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70381 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70381 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805601 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.805601 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954556 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954556 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.859252 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.859252 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.859252 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.859252 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16619.124624 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 16619.124624 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 30332.895198 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 30332.895198 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 22106.446995 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 22106.446995 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 22106.446995 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 22106.446995 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 828861 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 61322 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 62856 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.416082 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 13.186665 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9824 # number of writebacks -system.cpu1.l1c.writebacks::total 9824 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36456 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36456 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23797 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23797 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60253 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60253 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60253 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60253 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9840 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9840 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5428 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5428 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15268 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15268 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 572994513 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 572994513 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 657337433 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 657337433 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1230331946 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1230331946 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1230331946 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1230331946 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 646152701 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 646152701 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 842788738 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 842788738 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1488941439 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1488941439 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.806584 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806584 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954783 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954783 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859260 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.859260 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859260 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.859260 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15717.426843 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15717.426843 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 27622.701727 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 27622.701727 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20419.430501 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20419.430501 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20419.430501 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20419.430501 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 65665.924898 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65665.924898 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 155266.900884 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155266.900884 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 97520.398153 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 97520.398153 # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9918 # number of writebacks +system.cpu1.l1c.writebacks::total 9918 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36277 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36277 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 24198 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 24198 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60475 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60475 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60475 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60475 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9741 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9741 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5463 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5463 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15204 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15204 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 566614984 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 566614984 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 709800398 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 709800398 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1276415382 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1276415382 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1276415382 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1276415382 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 713705140 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 713705140 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 858653101 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 858653101 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1572358241 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1572358241 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805601 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805601 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954556 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954556 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859252 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.859252 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859252 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.859252 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15619.124624 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15619.124624 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 29333.019175 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 29333.019175 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 21106.496602 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 21106.496602 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 21106.496602 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 21106.496602 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 73268.159327 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73268.159327 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 157176.112209 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157176.112209 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 103417.406012 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 103417.406012 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99508 # number of read accesses completed -system.cpu2.num_writes 54525 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22121 # number of replacements -system.cpu2.l1c.tags.tagsinuse 392.684502 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13597 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22507 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.604123 # Average number of references to valid blocks. +system.cpu2.num_reads 99726 # number of read accesses completed +system.cpu2.num_writes 55227 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22340 # number of replacements +system.cpu2.l1c.tags.tagsinuse 393.100704 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13463 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22750 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.591780 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 392.684502 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.766962 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.766962 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 338301 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 338301 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8815 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8815 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1121 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1121 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9936 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9936 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9936 # number of overall hits -system.cpu2.l1c.overall_hits::total 9936 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36608 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36608 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23851 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23851 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60459 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60459 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60459 # number of overall misses -system.cpu2.l1c.overall_misses::total 60459 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 611593894 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 611593894 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 682333894 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 682333894 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1293927788 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1293927788 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1293927788 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1293927788 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45423 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45423 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24972 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24972 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70395 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70395 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70395 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70395 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805935 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.805935 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955110 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.955110 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.858854 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.858854 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.858854 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.858854 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16706.563975 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 16706.563975 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 28608.188084 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 28608.188084 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 21401.739824 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 21401.739824 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 21401.739824 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 21401.739824 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 766345 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 393.100704 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.767775 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.767775 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 400 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 338035 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 338035 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8657 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8657 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1109 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1109 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9766 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9766 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9766 # number of overall hits +system.cpu2.l1c.overall_hits::total 9766 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36622 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36622 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23922 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23922 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60544 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60544 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60544 # number of overall misses +system.cpu2.l1c.overall_misses::total 60544 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 606579368 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 606579368 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 739451035 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 739451035 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1346030403 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1346030403 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1346030403 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1346030403 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45279 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45279 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25031 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25031 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70310 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70310 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70310 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70310 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808808 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.808808 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955695 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955695 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.861101 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.861101 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.861101 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.861101 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16563.250724 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 16563.250724 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 30910.920283 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 30910.920283 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 22232.267491 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 22232.267491 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 22232.267491 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 22232.267491 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 834628 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 61950 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 63193 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.370379 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 13.207602 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9721 # number of writebacks -system.cpu2.l1c.writebacks::total 9721 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36608 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36608 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23851 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23851 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60459 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60459 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60459 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60459 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9890 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9890 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5479 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5479 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15369 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15369 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 574987894 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 574987894 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 658483894 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 658483894 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1233471788 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1233471788 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1233471788 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1233471788 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 648669577 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 648669577 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 848315711 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 848315711 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1496985288 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1496985288 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805935 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805935 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955110 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955110 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858854 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.858854 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858854 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.858854 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15706.618608 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15706.618608 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 27608.230011 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 27608.230011 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20401.789444 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20401.789444 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20401.789444 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20401.789444 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 65588.430435 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65588.430435 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154830.390765 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154830.390765 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 97402.907671 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 97402.907671 # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9768 # number of writebacks +system.cpu2.l1c.writebacks::total 9768 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36622 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36622 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23922 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23922 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60544 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60544 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60544 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60544 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9774 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9774 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5417 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5417 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15191 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15191 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 569957368 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 569957368 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 715531035 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 715531035 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1285488403 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1285488403 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1285488403 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1285488403 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 714145091 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 714145091 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 834952155 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 834952155 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1549097246 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1549097246 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808808 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808808 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955695 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955695 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.861101 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.861101 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.861101 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.861101 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15563.250724 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15563.250724 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 29911.003888 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 29911.003888 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 21232.300525 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 21232.300525 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 21232.300525 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 21232.300525 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 73065.796092 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73065.796092 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154135.527968 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154135.527968 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 101974.672240 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 101974.672240 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 100000 # number of read accesses completed -system.cpu3.num_writes 55096 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22478 # number of replacements -system.cpu3.l1c.tags.tagsinuse 393.167313 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13728 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22864 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.600420 # Average number of references to valid blocks. +system.cpu3.num_reads 99494 # number of read accesses completed +system.cpu3.num_writes 54686 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22431 # number of replacements +system.cpu3.l1c.tags.tagsinuse 392.658378 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13393 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22832 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.586589 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 393.167313 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.767905 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.767905 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 380 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 339546 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 339546 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8879 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8879 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1139 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1139 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 10018 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 10018 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 10018 # number of overall hits -system.cpu3.l1c.overall_hits::total 10018 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36721 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36721 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23927 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23927 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60648 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60648 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60648 # number of overall misses -system.cpu3.l1c.overall_misses::total 60648 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 620124867 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 620124867 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 683533364 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 683533364 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1303658231 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1303658231 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1303658231 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1303658231 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45600 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45600 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25066 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25066 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70666 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70666 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70666 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70666 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805285 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.805285 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954560 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.954560 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.858235 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.858235 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.858235 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.858235 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16887.472209 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 16887.472209 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 28567.449492 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 28567.449492 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 21495.485935 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 21495.485935 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 21495.485935 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 21495.485935 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 763846 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 392.658378 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.766911 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.766911 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 337999 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 337999 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8615 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8615 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1106 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1106 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9721 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9721 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9721 # number of overall hits +system.cpu3.l1c.overall_hits::total 9721 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36594 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36594 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23974 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23974 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60568 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60568 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60568 # number of overall misses +system.cpu3.l1c.overall_misses::total 60568 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 607642440 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 607642440 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 730577546 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 730577546 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1338219986 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1338219986 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1338219986 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1338219986 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45209 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45209 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25080 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25080 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70289 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70289 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70289 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70289 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.809441 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.809441 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955901 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.955901 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.861700 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.861700 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.861700 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.861700 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16604.974586 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 16604.974586 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 30473.744306 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 30473.744306 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 22094.505118 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 22094.505118 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 22094.505118 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 22094.505118 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 833585 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 61681 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 63208 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.383813 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 13.187967 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 10011 # number of writebacks -system.cpu3.l1c.writebacks::total 10011 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36721 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36721 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23927 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23927 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60648 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60648 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60648 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60648 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9730 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9730 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5269 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5269 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 14999 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 14999 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 583406867 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 583406867 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 659607364 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 659607364 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1243014231 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1243014231 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1243014231 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1243014231 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 639132205 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 639132205 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 818596366 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 818596366 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1457728571 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1457728571 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805285 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805285 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954560 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954560 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858235 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.858235 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858235 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.858235 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15887.553906 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15887.553906 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 27567.491286 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 27567.491286 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20495.551890 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20495.551890 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20495.551890 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20495.551890 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 65686.763104 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65686.763104 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 155360.858987 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155360.858987 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 97188.383959 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 97188.383959 # average overall mshr uncacheable latency +system.cpu3.l1c.writebacks::writebacks 9871 # number of writebacks +system.cpu3.l1c.writebacks::total 9871 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36594 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36594 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23974 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23974 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60568 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60568 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60568 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60568 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9814 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9814 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5449 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5449 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15263 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15263 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 571049440 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 571049440 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 706605546 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 706605546 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1277654986 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1277654986 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1277654986 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1277654986 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 718813002 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 718813002 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 842609106 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 842609106 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1561422108 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1561422108 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.809441 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.809441 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955901 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955901 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861700 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.861700 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861700 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.861700 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15605.001913 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15605.001913 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 29473.827730 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 29473.827730 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 21094.554649 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 21094.554649 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 21094.554649 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 21094.554649 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 73243.631751 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73243.631751 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 154635.548908 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154635.548908 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 102301.127432 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 102301.127432 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 98810 # number of read accesses completed -system.cpu4.num_writes 55636 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22565 # number of replacements -system.cpu4.l1c.tags.tagsinuse 393.118080 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13493 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22961 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.587649 # Average number of references to valid blocks. +system.cpu4.num_reads 99490 # number of read accesses completed +system.cpu4.num_writes 54928 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22277 # number of replacements +system.cpu4.l1c.tags.tagsinuse 391.439470 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13388 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22671 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.590534 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 393.118080 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.767809 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.767809 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 338158 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 338158 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8694 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8694 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1170 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1170 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9864 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9864 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9864 # number of overall hits -system.cpu4.l1c.overall_hits::total 9864 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36355 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36355 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 24124 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 24124 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60479 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60479 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60479 # number of overall misses -system.cpu4.l1c.overall_misses::total 60479 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 612629802 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 612629802 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 686589261 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 686589261 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1299219063 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1299219063 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1299219063 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1299219063 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45049 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45049 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25294 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25294 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70343 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70343 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70343 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70343 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807010 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.807010 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953744 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.953744 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.859773 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.859773 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.859773 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.859773 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16851.321744 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 16851.321744 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 28460.838211 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 28460.838211 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 21482.151871 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 21482.151871 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 21482.151871 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 21482.151871 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 755009 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 391.439470 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.764530 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.764530 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 337649 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 337649 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8692 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8692 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1145 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1145 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9837 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9837 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9837 # number of overall hits +system.cpu4.l1c.overall_hits::total 9837 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36462 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36462 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23928 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23928 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60390 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60390 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60390 # number of overall misses +system.cpu4.l1c.overall_misses::total 60390 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 604688688 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 604688688 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 724847511 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 724847511 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1329536199 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1329536199 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1329536199 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1329536199 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45154 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45154 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25073 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25073 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70227 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70227 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70227 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70227 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807503 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.807503 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954333 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.954333 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.859926 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.859926 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.859926 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.859926 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16584.078986 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 16584.078986 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 30292.858200 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 30292.858200 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 22015.833731 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 22015.833731 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 22015.833731 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 22015.833731 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 834109 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 61034 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 63123 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.370302 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 13.214027 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 10039 # number of writebacks -system.cpu4.l1c.writebacks::total 10039 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36355 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36355 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24124 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 24124 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60479 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60479 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60479 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60479 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9580 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9580 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5521 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5521 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15101 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15101 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 576274802 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 576274802 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 662467261 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 662467261 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1238742063 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1238742063 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1238742063 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1238742063 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 630980804 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 630980804 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 867176198 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 867176198 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1498157002 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1498157002 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807010 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807010 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953744 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953744 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859773 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.859773 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859773 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.859773 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15851.321744 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15851.321744 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 27460.921116 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 27460.921116 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20482.184940 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20482.184940 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20482.184940 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20482.184940 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65864.384551 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65864.384551 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157068.682847 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157068.682847 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 99209.125356 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 99209.125356 # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 9949 # number of writebacks +system.cpu4.l1c.writebacks::total 9949 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36462 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36462 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23928 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23928 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60390 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60390 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60390 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60390 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9946 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9946 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5329 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5329 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15275 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15275 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 568228688 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 568228688 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 700919511 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 700919511 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1269148199 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1269148199 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1269148199 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1269148199 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 727166434 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 727166434 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 837934166 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 837934166 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1565100600 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1565100600 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807503 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807503 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954333 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954333 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859926 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.859926 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859926 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.859926 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15584.133838 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15584.133838 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 29292.858200 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 29292.858200 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 21015.866849 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 21015.866849 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 21015.866849 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 21015.866849 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 73111.445204 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73111.445204 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157240.413961 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157240.413961 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 102461.577741 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 102461.577741 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 98552 # number of read accesses completed -system.cpu5.num_writes 54926 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22151 # number of replacements -system.cpu5.l1c.tags.tagsinuse 392.121942 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13428 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22535 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.595873 # Average number of references to valid blocks. +system.cpu5.num_reads 99495 # number of read accesses completed +system.cpu5.num_writes 55318 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22409 # number of replacements +system.cpu5.l1c.tags.tagsinuse 392.682039 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13393 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22790 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.587670 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 392.121942 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.765863 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.765863 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 336693 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 336693 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8529 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8529 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1201 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1201 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9730 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9730 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9730 # number of overall hits -system.cpu5.l1c.overall_hits::total 9730 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36363 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36363 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23944 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23944 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60307 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60307 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60307 # number of overall misses -system.cpu5.l1c.overall_misses::total 60307 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 609487073 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 609487073 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 677626855 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 677626855 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1287113928 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1287113928 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1287113928 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1287113928 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44892 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44892 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25145 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25145 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70037 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70037 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70037 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70037 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.810011 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.810011 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952237 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.952237 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.861073 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.861073 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.861073 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.861073 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16761.187828 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 16761.187828 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 28300.486761 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 28300.486761 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 21342.695342 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 21342.695342 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 21342.695342 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 21342.695342 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 765746 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 392.682039 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.766957 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.766957 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 381 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.744141 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 337688 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 337688 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8637 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8637 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1146 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1146 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9783 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9783 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9783 # number of overall hits +system.cpu5.l1c.overall_hits::total 9783 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36329 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36329 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 24118 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 24118 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60447 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60447 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60447 # number of overall misses +system.cpu5.l1c.overall_misses::total 60447 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 601479868 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 601479868 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 729882091 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 729882091 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1331361959 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1331361959 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1331361959 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1331361959 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44966 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44966 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25264 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25264 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70230 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70230 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70230 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70230 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807922 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.807922 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954639 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.954639 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.860701 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.860701 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.860701 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.860701 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16556.466404 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 16556.466404 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 30262.960901 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 30262.960901 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 22025.277665 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 22025.277665 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 22025.277665 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 22025.277665 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 826632 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 61759 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 62727 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.398938 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 13.178249 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9825 # number of writebacks -system.cpu5.l1c.writebacks::total 9825 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36363 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36363 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23944 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23944 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60307 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60307 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60307 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60307 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9974 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9974 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5505 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5505 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15479 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15479 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 573124073 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 573124073 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 653684855 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 653684855 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1226808928 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1226808928 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1226808928 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1226808928 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 653819057 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 653819057 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 856353181 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 856353181 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1510172238 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1510172238 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.810011 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.810011 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952237 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952237 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.861073 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.861073 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.861073 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.861073 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15761.187828 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15761.187828 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 27300.570289 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 27300.570289 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20342.728506 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20342.728506 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20342.728506 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20342.728506 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 65552.341789 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65552.341789 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 155559.160945 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155559.160945 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 97562.648621 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 97562.648621 # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 9995 # number of writebacks +system.cpu5.l1c.writebacks::total 9995 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36329 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36329 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24118 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 24118 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60447 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60447 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60447 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60447 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9798 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9798 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5473 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5473 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15271 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15271 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 565152868 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 565152868 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 705764091 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 705764091 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1270916959 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1270916959 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1270916959 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1270916959 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 717311081 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 717311081 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 861132955 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 861132955 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1578444036 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1578444036 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807922 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807922 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954639 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954639 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860701 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.860701 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860701 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.860701 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15556.521457 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15556.521457 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 29262.960901 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 29262.960901 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 21025.310752 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 21025.310752 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 21025.310752 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 21025.310752 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 73209.949071 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73209.949071 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 157342.034533 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157342.034533 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 103362.192129 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 103362.192129 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 98949 # number of read accesses completed -system.cpu6.num_writes 55414 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22111 # number of replacements -system.cpu6.l1c.tags.tagsinuse 389.931977 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13393 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22506 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.595086 # Average number of references to valid blocks. +system.cpu6.num_reads 100000 # number of read accesses completed +system.cpu6.num_writes 55059 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22318 # number of replacements +system.cpu6.l1c.tags.tagsinuse 390.741535 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13451 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22720 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.592033 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 389.931977 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.761586 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.761586 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 337246 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 337246 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8611 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8611 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1144 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1144 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9755 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9755 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9755 # number of overall hits -system.cpu6.l1c.overall_hits::total 9755 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36346 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36346 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 24035 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 24035 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60381 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60381 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60381 # number of overall misses -system.cpu6.l1c.overall_misses::total 60381 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 607533641 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 607533641 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 684112648 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 684112648 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1291646289 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1291646289 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1291646289 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1291646289 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 44957 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 44957 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25179 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25179 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70136 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70136 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70136 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70136 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808461 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.808461 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954565 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.954565 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.860913 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.860913 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.860913 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.860913 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16715.282039 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 16715.282039 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28463.184855 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 28463.184855 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 21391.601481 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 21391.601481 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 21391.601481 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 21391.601481 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 766078 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 390.741535 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.763167 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.763167 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 338536 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 338536 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8731 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8731 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1150 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1150 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9881 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9881 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9881 # number of overall hits +system.cpu6.l1c.overall_hits::total 9881 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36733 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36733 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23795 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23795 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60528 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60528 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60528 # number of overall misses +system.cpu6.l1c.overall_misses::total 60528 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 609896687 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 609896687 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 716784676 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 716784676 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1326681363 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1326681363 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1326681363 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1326681363 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45464 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45464 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24945 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24945 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70409 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70409 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70409 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70409 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807958 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.807958 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953899 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.953899 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.859663 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.859663 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.859663 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.859663 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16603.508752 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 16603.508752 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 30123.331624 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 30123.331624 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 21918.473483 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 21918.473483 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 21918.473483 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 21918.473483 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 822803 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 61691 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 62827 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.417986 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 13.096328 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9648 # number of writebacks -system.cpu6.l1c.writebacks::total 9648 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36346 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36346 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24035 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 24035 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60381 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60381 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60381 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60381 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9904 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9904 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5478 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5478 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15382 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15382 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 571188641 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 571188641 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 660079648 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 660079648 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1231268289 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1231268289 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1231268289 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1231268289 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 650717068 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 650717068 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 843701696 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 843701696 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1494418764 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1494418764 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808461 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808461 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954565 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954565 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.860913 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.860913 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.860913 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.860913 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15715.309553 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15715.309553 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 27463.268067 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 27463.268067 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20391.651165 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20391.651165 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20391.651165 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20391.651165 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 65702.450323 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65702.450323 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 154016.373859 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154016.373859 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 97153.735795 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 97153.735795 # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9777 # number of writebacks +system.cpu6.l1c.writebacks::total 9777 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36733 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36733 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23795 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23795 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60528 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60528 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60528 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60528 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9837 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9837 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5532 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5532 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15369 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15369 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 573164687 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 573164687 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 692991676 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 692991676 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1266156363 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1266156363 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1266156363 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1266156363 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 718909036 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 718909036 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 867837123 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 867837123 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1586746159 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1586746159 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807958 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807958 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953899 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953899 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859663 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.859663 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859663 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.859663 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15603.535976 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15603.535976 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 29123.415676 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 29123.415676 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20918.523047 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20918.523047 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20918.523047 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20918.523047 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 73082.142523 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73082.142523 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 156875.835683 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156875.835683 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 103243.292277 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 103243.292277 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99388 # number of read accesses completed -system.cpu7.num_writes 55153 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22255 # number of replacements -system.cpu7.l1c.tags.tagsinuse 390.416736 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13442 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22659 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.593230 # Average number of references to valid blocks. +system.cpu7.num_reads 99734 # number of read accesses completed +system.cpu7.num_writes 54921 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22329 # number of replacements +system.cpu7.l1c.tags.tagsinuse 392.290074 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13499 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22713 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.594329 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 390.416736 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.762533 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.762533 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 338136 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 338136 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8702 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8702 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1125 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1125 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9827 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9827 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9827 # number of overall hits -system.cpu7.l1c.overall_hits::total 9827 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36623 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36623 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23879 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23879 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60502 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60502 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60502 # number of overall misses -system.cpu7.l1c.overall_misses::total 60502 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 619428018 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 619428018 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 681256931 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 681256931 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1300684949 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1300684949 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1300684949 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1300684949 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45325 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45325 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25004 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25004 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70329 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70329 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70329 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70329 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.808009 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.808009 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955007 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.955007 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.860271 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.860271 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.860271 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.860271 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16913.634000 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 16913.634000 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 28529.541899 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 28529.541899 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 21498.214092 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 21498.214092 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 21498.214092 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 21498.214092 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 764751 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 392.290074 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.766192 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.766192 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 338596 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 338596 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8795 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8795 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1165 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1165 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9960 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9960 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9960 # number of overall hits +system.cpu7.l1c.overall_hits::total 9960 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36684 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36684 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23790 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23790 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60474 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60474 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60474 # number of overall misses +system.cpu7.l1c.overall_misses::total 60474 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 611011013 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 611011013 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 715403706 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 715403706 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1326414719 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1326414719 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1326414719 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1326414719 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45479 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45479 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24955 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24955 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70434 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70434 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70434 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70434 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806614 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.806614 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953316 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953316 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.858591 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.858591 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.858591 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.858591 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16656.062943 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 16656.062943 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 30071.614376 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 30071.614376 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 21933.636257 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 21933.636257 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 21933.636257 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 21933.636257 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 829723 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 61551 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 63058 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.424672 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 13.158093 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9698 # number of writebacks -system.cpu7.l1c.writebacks::total 9698 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36623 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36623 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23879 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23879 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60502 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60502 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60502 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60502 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9744 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9744 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5445 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5445 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15189 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15189 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 582807018 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 582807018 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 657378931 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 657378931 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1240185949 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1240185949 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1240185949 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1240185949 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 639625650 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 639625650 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 835380703 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 835380703 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1475006353 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1475006353 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.808009 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.808009 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955007 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955007 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860271 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.860271 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860271 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.860271 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15913.688611 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15913.688611 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 27529.583777 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 27529.583777 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20498.263677 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20498.263677 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20498.263677 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20498.263677 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 65643.026478 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65643.026478 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 153421.616713 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153421.616713 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 97110.168741 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 97110.168741 # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9746 # number of writebacks +system.cpu7.l1c.writebacks::total 9746 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36684 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36684 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23790 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23790 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60474 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60474 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60474 # number of overall MSHR misses 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691615706 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1265942719 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1265942719 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1265942719 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1265942719 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 726668427 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 726668427 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 847371643 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 847371643 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1574040070 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1574040070 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806614 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806614 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953316 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953316 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858591 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.858591 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858591 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.858591 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15656.062943 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15656.062943 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 29071.698445 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 29071.698445 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20933.669329 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20933.669329 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20933.669329 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20933.669329 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 73267.637326 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73267.637326 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 156312.791551 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156312.791551 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 102616.863550 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 102616.863550 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 14059 # number of replacements -system.l2c.tags.tagsinuse 786.833616 # Cycle average of tags in use -system.l2c.tags.total_refs 163279 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14835 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.006336 # Average number of references to valid blocks. +system.l2c.tags.replacements 14328 # number of replacements +system.l2c.tags.tagsinuse 791.177993 # Cycle average of tags in use +system.l2c.tags.total_refs 163940 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 15120 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.842593 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 728.191655 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 7.576246 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 6.765492 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.413353 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.547486 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 7.173407 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 7.531253 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 7.038544 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 7.596181 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.711125 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.007399 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006607 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.007240 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.007371 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.007005 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.007355 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006874 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.007418 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768392 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 776 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 637 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2098126 # Number of tag accesses -system.l2c.tags.data_accesses 2098126 # Number of data accesses -system.l2c.Writeback_hits::writebacks 77297 # number of Writeback hits -system.l2c.Writeback_hits::total 77297 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 246 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 268 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 270 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 283 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 289 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 282 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 269 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 297 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2204 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1720 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1708 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1780 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1750 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1833 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1787 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1793 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1756 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14127 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0 10721 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1 10733 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2 10896 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3 11023 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu4 10756 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu5 10769 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu6 10556 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu7 10900 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 86354 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0 12441 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12441 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12676 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12773 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12589 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12556 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12349 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12656 # number of demand (read+write) hits -system.l2c.demand_hits::total 100481 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12441 # number of overall hits -system.l2c.overall_hits::cpu1 12441 # number of overall hits -system.l2c.overall_hits::cpu2 12676 # number of overall hits -system.l2c.overall_hits::cpu3 12773 # number of overall hits -system.l2c.overall_hits::cpu4 12589 # number of overall hits -system.l2c.overall_hits::cpu5 12556 # number of overall hits -system.l2c.overall_hits::cpu6 12349 # number of overall hits -system.l2c.overall_hits::cpu7 12656 # number of overall hits -system.l2c.overall_hits::total 100481 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0 1978 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 2026 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2150 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2091 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 2034 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2071 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 2011 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 2018 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 16379 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4713 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4655 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4607 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4594 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4660 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4574 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4699 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4645 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 37147 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0 745 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1 703 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2 745 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3 740 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu4 719 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu5 741 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu6 735 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu7 779 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 5907 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0 5458 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5358 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5352 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5334 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5379 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5315 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5434 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5424 # number of demand (read+write) misses -system.l2c.demand_misses::total 43054 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5458 # number of overall misses -system.l2c.overall_misses::cpu1 5358 # number of overall misses -system.l2c.overall_misses::cpu2 5352 # number of overall misses -system.l2c.overall_misses::cpu3 5334 # number of overall misses -system.l2c.overall_misses::cpu4 5379 # number of overall misses -system.l2c.overall_misses::cpu5 5315 # number of overall misses -system.l2c.overall_misses::cpu6 5434 # number of overall misses -system.l2c.overall_misses::cpu7 5424 # number of overall misses -system.l2c.overall_misses::total 43054 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0 60264491 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 62631489 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 64255988 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 63421482 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 62636494 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 62720987 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 60083486 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 62493486 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 498507903 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 264922404 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 260661407 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 257895914 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 258059392 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 261142926 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 256126416 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 263147923 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 259849424 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2081805806 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0 46156062 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1 44483916 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2 46780409 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3 45792918 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu4 45003906 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu5 46499399 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu6 45597417 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu7 48662406 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 368976433 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0 311078466 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 305145323 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 304676323 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 303852310 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 306146832 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 302625815 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 308745340 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 308511830 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2450782239 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 311078466 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 305145323 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 304676323 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 303852310 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 306146832 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 302625815 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 308745340 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 308511830 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2450782239 # number of overall miss cycles -system.l2c.Writeback_accesses::writebacks 77297 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 77297 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2224 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2294 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2420 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2374 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2323 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2353 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2280 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2315 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18583 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6433 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6363 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6387 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6344 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6493 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6361 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6492 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6401 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 51274 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0 11466 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1 11436 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2 11641 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3 11763 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu4 11475 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu5 11510 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu6 11291 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu7 11679 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 92261 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17899 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17799 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 18028 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 18107 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17968 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17871 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17783 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 18080 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 143535 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17899 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17799 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 18028 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 18107 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17968 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17871 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17783 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 18080 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 143535 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.889388 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.883173 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.888430 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.880792 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.875592 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.880153 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.882018 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.871706 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.881397 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.732629 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.731573 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.721309 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.724149 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.717696 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.719069 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.723814 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.725668 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.724480 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0 0.064975 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1 0.061473 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2 0.063998 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3 0.062909 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu4 0.062658 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu5 0.064379 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu6 0.065096 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu7 0.066701 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.064025 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0 0.304933 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.301028 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.296872 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.294582 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.299366 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.297409 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.305573 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.300000 # miss rate for demand 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# number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 732.189847 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 7.660754 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 7.418431 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.928491 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 7.181835 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 7.391664 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 6.508374 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.134486 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.764111 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.715029 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.007481 # Average percentage of cache occupancy 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accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu7 11708 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 93124 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17881 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18035 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18283 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 18199 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17910 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17975 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 18124 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18022 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 144429 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17881 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 18035 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18283 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 18199 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17910 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17975 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 18124 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18022 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 144429 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.881137 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.886801 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.883264 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.887354 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.870291 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.885969 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.874623 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.873023 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.880327 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.724252 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.727371 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.727534 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.724732 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.711565 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.721986 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.720492 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.721729 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.722483 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0 0.066863 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1 0.065950 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2 0.065941 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3 0.060299 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu4 0.068029 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu5 0.060196 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu6 0.060862 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.064827 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.064097 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.300319 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.304186 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.305530 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.295456 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.300112 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.294465 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.288733 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.294973 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.297973 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.300319 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.304186 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.305530 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.295456 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.300112 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.294465 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.288733 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.294973 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.297973 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0 35601.406158 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 34925.076885 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 35378.244908 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 35456.214008 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 35693.546483 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 32969.044019 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 35093.094089 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 36289.873679 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 35166.777622 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 63839.279626 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 63760.182222 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 63724.387793 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 63759.930591 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 63808.390992 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 63736.696125 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 63693.574595 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 63773.836515 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 63761.952006 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 68765.771725 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 68892.788436 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 69363.318596 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69021.739069 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 68245.722721 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 68995.566524 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 69281.724377 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 68727.146245 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 68905.889596 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 64546.602793 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 64472.160591 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 64500.674544 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 64453.741678 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 64451.494512 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 64431.188929 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 64464.574814 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 64481.052859 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 64475.405010 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 64546.602793 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 64472.160591 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 64500.674544 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 64453.741678 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 64451.494512 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 64431.188929 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 64464.574814 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 64481.052859 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 64475.405010 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 37689 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 3488 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 7229 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 5.550745 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 5.213584 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6515 # number of writebacks -system.l2c.writebacks::total 6515 # number of writebacks +system.l2c.writebacks::writebacks 6662 # number of writebacks +system.l2c.writebacks::total 6662 # number of writebacks system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu1 5 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 5 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 4 # number of ReadExReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 8 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 7 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu1 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 7 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 7 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 3 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 6 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu7 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 34 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0 7 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3 8 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu4 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu5 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu6 5 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu7 9 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 69 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 103 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 103 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 1301 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 1301 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1977 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2026 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2150 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2090 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 2034 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2069 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2011 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 2017 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_hits::total 45 # number of ReadExReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0 9 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1 9 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2 12 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu3 7 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu4 14 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu5 5 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu6 8 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu7 8 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 72 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 16 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 19 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 17 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 117 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 16 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 19 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 17 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 117 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 1261 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 1261 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 2045 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 2024 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2111 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2055 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 2032 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 2090 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 2030 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1987 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 16374 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4709 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4650 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4604 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4591 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4655 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4570 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4695 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4639 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 37113 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0 738 # number of ReadSharedReq MSHR misses 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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 514181757 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 515732776 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 517979251 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 524791253 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 517494740 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 519233265 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 524055269 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 4155041425 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 302263386 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 299275381 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 295496378 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 297456387 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 290732905 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 298997210 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 303692889 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 296080198 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2383994734 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 823836500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 813457138 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 811229154 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 815435638 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 815524158 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 816491950 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 822926154 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 820135467 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6539036159 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.888939 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.883173 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.888430 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.880371 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.875592 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.879303 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.882018 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.871274 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.881128 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.732007 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.730787 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.720839 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.723676 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.716926 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.718440 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.723198 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.724731 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.723817 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.064364 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.060598 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.063139 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.062229 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.061786 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.063510 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.064653 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.065930 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063277 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.304319 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.300185 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.296150 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.293975 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.298531 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.296626 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.305067 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.299170 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.299237 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.304319 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.300185 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.296150 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.293975 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.298531 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.296626 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.305067 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.299170 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.299237 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 45450.420840 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 45460.256170 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 45384.873953 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 45421.041148 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 45371.430678 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 45448.514258 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 45378.159125 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 45405.790778 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 45414.855258 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 46229.221491 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 46032.345591 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 46000.198523 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 46190.566761 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 46073.560902 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 46021.316411 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 46020.856869 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 45971.206079 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 46067.626088 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 52281.249322 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 53772.607504 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 53044.776871 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 52136.500000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 52982.239774 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 53144.868673 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 52161.531507 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 52767.411688 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 52778.681055 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 47049.195153 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 47036.276249 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 46969.999063 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 47008.230321 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 46986.732662 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 47003.643652 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 46847.159631 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 46938.682196 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 46979.808316 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 47049.195153 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 47036.276249 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 46969.999063 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 47008.230321 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 46986.732662 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 47003.643652 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 46847.159631 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 46938.682196 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 46979.808316 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44927.218559 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 45002.272561 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 45006.490495 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 45019.805550 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 45047.220146 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44972.916082 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 45028.391963 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44938.341544 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44992.694522 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 46260.365421 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 46369.461496 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 46373.118474 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 46391.945900 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 46368.309183 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 46372.920254 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 46332.743655 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 46551.714627 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 46377.702156 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 45397.131308 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 45488.328465 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 45493.631832 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 45501.765502 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 45530.216807 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 45470.817947 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 45492.856836 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 45516.504083 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 45486.343181 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.880706 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.884615 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.883264 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.886923 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.869863 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.885969 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.874623 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.873023 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.879897 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.723150 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.726601 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.726476 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.723645 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.711101 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.721358 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.719534 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.720779 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.721606 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.066083 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.065170 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.064912 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.059704 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.066806 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.059766 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.060187 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.064144 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063324 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.299424 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.303410 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.304491 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.294687 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.299162 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.293964 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.287961 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.294196 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.297163 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.299424 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.303410 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.304491 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.294687 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.299162 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.293964 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.287961 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.294196 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.297163 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 53341.056724 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 53434.268775 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 53352.335386 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 53304.519221 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 53306.082677 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 53314.491388 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 53354.660591 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 53296.911928 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 53338.045682 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 53883.459930 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 53797.322458 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 53787.708108 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 53824.577558 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 53807.612671 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 53775.355556 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 53766.751387 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 53809.574379 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 53806.527929 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59102.244094 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 59354.937500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59851.245707 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59219.962963 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58804.469281 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 59213.835735 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59609.813725 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 58991.884154 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59266.536035 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 54626.215540 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 54561.088268 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 54612.227232 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 54530.816707 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 54521.049645 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 54489.644966 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 54566.127994 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 54543.620898 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 54556.724062 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 54626.215540 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 54561.088268 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 54612.227232 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 54530.816707 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 54521.049645 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 54489.644966 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 54566.127994 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 54543.620898 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 54556.724062 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 52764.098533 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 52785.315368 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 52765.784326 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 52785.004688 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 52769.356762 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 52816.364564 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 52783.700823 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 52838.805102 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 52788.573706 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 54295.560625 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 54792.270414 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 54559.892541 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 54609.213696 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 54556.747044 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 54641.302997 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 54897.485358 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 54617.265818 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 54621.150483 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 53315.849081 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 53506.356509 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 53405.474259 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 53436.149279 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 53392.965693 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 53470.330714 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 53544.547726 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 53467.336006 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 53442.272686 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.snoop_filter.tot_requests 127987 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 121935 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 127545 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 121489 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.trans_dist::ReadReq 78487 # Transaction distribution -system.membus.trans_dist::ReadResp 84311 # Transaction distribution -system.membus.trans_dist::WriteReq 43469 # Transaction distribution -system.membus.trans_dist::WriteResp 43465 # Transaction distribution -system.membus.trans_dist::Writeback 6515 # Transaction distribution -system.membus.trans_dist::CleanEvict 1324 # Transaction distribution -system.membus.trans_dist::UpgradeReq 61199 # Transaction distribution -system.membus.trans_dist::UpgradeResp 50308 # Transaction distribution -system.membus.trans_dist::ReadExReq 49356 # Transaction distribution -system.membus.trans_dist::ReadExResp 3201 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 5828 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 427463 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 427463 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1116768 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1116768 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 57043 # Total snoops (count) -system.membus.snoop_fanout::samples 255514 # Request fanout histogram +system.membus.trans_dist::ReadReq 78710 # Transaction distribution +system.membus.trans_dist::ReadResp 84594 # Transaction distribution +system.membus.trans_dist::WriteReq 43645 # Transaction distribution +system.membus.trans_dist::WriteResp 43644 # Transaction distribution +system.membus.trans_dist::WritebackDirty 6662 # Transaction distribution +system.membus.trans_dist::CleanEvict 1288 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60944 # Transaction distribution +system.membus.trans_dist::UpgradeResp 50160 # Transaction distribution +system.membus.trans_dist::ReadExReq 49324 # Transaction distribution +system.membus.trans_dist::ReadExResp 3261 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5890 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 428122 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 428122 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1134381 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1134381 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 56843 # Total snoops (count) +system.membus.snoop_fanout::samples 246442 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 255514 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 246442 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 255514 # Request fanout histogram -system.membus.reqLayer0.occupancy 292277246 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 56.4 # Layer utilization (%) -system.membus.respLayer0.occupancy 310111858 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 59.8 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 663155 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 282754 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 334620 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 12643 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 6068 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 6575 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 78490 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 370569 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43469 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43464 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 83812 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 20730 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29471 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29469 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 161822 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 161815 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 292094 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122083 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122289 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122819 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122567 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122495 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122827 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122357 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122446 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 979883 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1778056 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1772835 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1781127 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1803862 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1797691 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1778038 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1761236 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1781905 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14254750 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 335326 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 800967 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.187618 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.006332 # Request fanout histogram +system.membus.snoop_fanout::total 246442 # Request fanout histogram +system.membus.reqLayer0.occupancy 292771939 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 54.1 # Layer utilization (%) +system.membus.respLayer0.occupancy 296967000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 54.9 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 667370 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 284034 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 336982 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 12889 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 5997 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 6892 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 78711 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 370868 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 5 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43646 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43643 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 84238 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 20479 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29389 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29387 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 162232 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 162225 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 292173 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122572 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122578 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122851 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122953 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122545 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122770 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122967 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122678 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 981914 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1769628 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1794530 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1801428 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1802844 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1789097 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1796324 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1791880 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1784489 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14330220 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 335082 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 628739 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.148986 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.990092 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 216572 27.04% 27.04% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 322054 40.21% 67.25% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 178446 22.28% 89.53% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 65924 8.23% 97.76% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 15526 1.94% 99.69% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 2251 0.28% 99.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 192 0.02% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 2 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 176143 28.02% 28.02% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 257926 41.02% 69.04% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 134453 21.38% 90.42% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 47224 7.51% 97.93% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 11211 1.78% 99.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 1632 0.26% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 146 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 4 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 800967 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 495267856 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 95.5 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 101287347 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 19.5 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 101004376 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 19.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 101361922 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 101351771 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 101153250 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 19.5 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 101246693 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 19.5 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 101297808 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 19.5 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 101337760 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 19.5 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 628739 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 500695190 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 92.6 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 101141048 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 18.7 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 101214213 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 18.7 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 101195728 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 18.7 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 101296930 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 18.7 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 101179412 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 18.7 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 101203668 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 18.7 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 101388789 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 18.7 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 101354632 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 18.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index 76540bca6..366a5b776 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -1,1811 +1,1811 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000518 # Number of seconds simulated -sim_ticks 517786000 # Number of ticks simulated -final_tick 517786000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000534 # Number of seconds simulated +sim_ticks 534039500 # Number of ticks simulated +final_tick 534039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 99723528 # Simulator tick rate (ticks/s) -host_mem_usage 280036 # Number of bytes of host memory used -host_seconds 5.19 # Real time elapsed on the host +host_tick_rate 107991246 # Simulator tick rate (ticks/s) +host_mem_usage 280540 # Number of bytes of host memory used +host_seconds 4.95 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 82733 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 82298 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 83808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 81707 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 79210 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 80419 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 83957 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 82578 # Number of bytes read from this memory -system.physmem.bytes_read::total 656710 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 415488 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5449 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5329 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5533 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5454 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5382 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5483 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5508 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5404 # Number of bytes written to this memory -system.physmem.bytes_written::total 459030 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10913 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10856 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10917 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10895 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10981 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10993 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11003 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10884 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87442 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6492 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5449 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5329 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5533 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5454 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5382 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5483 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5508 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5404 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50034 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 159782227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 158942111 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 161858374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 157800713 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 152978257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 155313199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 162146138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 159482875 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1268303894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 802431893 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 10523653 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 10291897 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 10685882 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 10533309 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 10394256 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 10589317 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 10637599 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 10436744 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 886524549 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 802431893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 170305879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 169234008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 172544256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 168334022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 163372513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 165902516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 172783737 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 169919619 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2154828443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 80135 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 83816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 79566 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 82290 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 82935 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 84320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 79631 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 84304 # Number of bytes read from this memory +system.physmem.bytes_read::total 656997 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 418368 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5512 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5388 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5320 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5503 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5449 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5363 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5499 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5488 # Number of bytes written to this memory +system.physmem.bytes_written::total 461890 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10988 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10833 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10911 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10989 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10835 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10972 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87288 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6537 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5512 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5388 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5320 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5503 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5449 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5363 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5499 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5488 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50059 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 150054444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 156947192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 148988979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 154089726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 155297501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 157890943 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 149110693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 157860982 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1230240460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 783402726 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10321334 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 10089141 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 9961810 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 10304481 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 10203365 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10042328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 10296991 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10276393 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 864898570 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 783402726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 160375777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 167036333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 158950789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 164394207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 165500867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 167933271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 159407684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 168137376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2095139030 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99592 # number of read accesses completed -system.cpu0.num_writes 55369 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22465 # number of replacements -system.cpu0.l1c.tags.tagsinuse 392.038302 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13410 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22854 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.586768 # Average number of references to valid blocks. +system.cpu0.num_reads 98970 # number of read accesses completed +system.cpu0.num_writes 54697 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22262 # number of replacements +system.cpu0.l1c.tags.tagsinuse 392.444163 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13142 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22657 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.580041 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 392.038302 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.765700 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.765700 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 338870 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 338870 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8751 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8751 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1148 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1148 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9899 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9899 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9899 # number of overall hits -system.cpu0.l1c.overall_hits::total 9899 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36676 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36676 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23894 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23894 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60570 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60570 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60570 # number of overall misses -system.cpu0.l1c.overall_misses::total 60570 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 605837577 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 605837577 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 675142476 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 675142476 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1280980053 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1280980053 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1280980053 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1280980053 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45427 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45427 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25042 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25042 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70469 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70469 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70469 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70469 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807361 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.807361 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954157 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.954157 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.859527 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.859527 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.859527 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.859527 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16518.638265 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 16518.638265 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 28255.732653 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 28255.732653 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 21148.754383 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 21148.754383 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 21148.754383 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 21148.754383 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 743435 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 392.444163 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.766493 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.766493 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 335259 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 335259 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8424 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8424 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1108 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1108 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9532 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9532 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9532 # number of overall hits +system.cpu0.l1c.overall_hits::total 9532 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36392 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36392 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23768 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23768 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60160 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60160 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60160 # number of overall misses +system.cpu0.l1c.overall_misses::total 60160 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 598420373 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 598420373 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 705577272 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 705577272 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1303997645 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1303997645 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1303997645 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1303997645 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44816 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44816 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24876 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24876 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 69692 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 69692 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 69692 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 69692 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.812031 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.812031 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955459 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.955459 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.863227 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.863227 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.863227 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.863227 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16443.734145 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 16443.734145 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 29686.017839 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 29686.017839 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 21675.492769 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 21675.492769 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 21675.492769 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 21675.492769 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 798798 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 61083 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 61887 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.170899 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.907363 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9922 # number of writebacks -system.cpu0.l1c.writebacks::total 9922 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36676 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36676 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23894 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23894 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60570 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60570 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60570 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60570 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9773 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9773 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5450 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5450 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15223 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15223 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 569161577 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 569161577 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 651248476 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 651248476 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1220410053 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1220410053 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1220410053 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1220410053 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 638102868 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 638102868 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 843396249 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 843396249 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1481499117 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1481499117 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807361 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807361 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954157 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954157 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859527 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.859527 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859527 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.859527 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15518.638265 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15518.638265 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 27255.732653 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 27255.732653 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20148.754383 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20148.754383 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20148.754383 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20148.754383 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 65292.424844 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65292.424844 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 154751.605321 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154751.605321 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 97319.786967 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 97319.786967 # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9766 # number of writebacks +system.cpu0.l1c.writebacks::total 9766 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36392 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36392 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23768 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23768 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60160 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60160 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60160 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60160 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9799 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9799 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5512 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5512 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15311 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15311 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 562029373 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 562029373 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 681810272 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 681810272 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1243839645 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1243839645 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1243839645 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1243839645 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 706647630 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 706647630 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 855364129 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 855364129 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1562011759 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1562011759 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.812031 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.812031 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955459 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955459 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.863227 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.863227 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.863227 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.863227 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15443.761623 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15443.761623 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 28686.059912 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 28686.059912 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20675.526014 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20675.526014 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20675.526014 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20675.526014 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 72114.259618 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 72114.259618 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 155182.171444 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155182.171444 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 102018.924891 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 102018.924891 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99505 # number of read accesses completed -system.cpu1.num_writes 55135 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22526 # number of replacements -system.cpu1.l1c.tags.tagsinuse 393.510444 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13408 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22912 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.585196 # Average number of references to valid blocks. +system.cpu1.num_reads 98379 # number of read accesses completed +system.cpu1.num_writes 54883 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22236 # number of replacements +system.cpu1.l1c.tags.tagsinuse 391.015365 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13378 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22622 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.591371 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 393.510444 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.768575 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.768575 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_blocks::cpu1 391.015365 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.763702 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.763702 # Average percentage of cache occupancy system.cpu1.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 375 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id system.cpu1.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 339206 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 339206 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8687 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8687 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1167 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1167 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9854 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9854 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9854 # number of overall hits -system.cpu1.l1c.overall_hits::total 9854 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36759 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36759 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23925 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23925 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60684 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60684 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60684 # number of overall misses -system.cpu1.l1c.overall_misses::total 60684 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 611192958 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 611192958 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 677073428 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 677073428 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1288266386 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1288266386 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1288266386 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1288266386 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45446 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45446 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 25092 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 25092 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70538 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70538 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70538 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70538 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.808850 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.808850 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953491 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.953491 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.860302 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.860302 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.860302 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.860302 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16627.028972 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 16627.028972 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 28299.829801 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 28299.829801 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 21229.094753 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 21229.094753 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 21229.094753 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 21229.094753 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 746931 # number of cycles access was blocked +system.cpu1.l1c.tags.tag_accesses 335372 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 335372 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8546 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8546 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1143 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1143 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9689 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9689 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9689 # number of overall hits +system.cpu1.l1c.overall_hits::total 9689 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36240 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36240 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23835 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23835 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60075 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60075 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60075 # number of overall misses +system.cpu1.l1c.overall_misses::total 60075 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 593535449 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 593535449 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 712426271 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 712426271 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1305961720 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1305961720 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1305961720 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1305961720 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44786 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44786 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24978 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24978 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 69764 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 69764 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 69764 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 69764 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.809181 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.809181 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954240 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954240 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.861117 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.861117 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.861117 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.861117 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16377.909741 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 16377.909741 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 29889.921166 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 29889.921166 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 21738.855098 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 21738.855098 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 21738.855098 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 21738.855098 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 803378 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 61259 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 62137 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.193000 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.929140 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9855 # number of writebacks -system.cpu1.l1c.writebacks::total 9855 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36759 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36759 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23925 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23925 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60684 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60684 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60684 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60684 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9724 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9724 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5329 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5329 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15053 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15053 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 574433958 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 574433958 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 653148428 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 653148428 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1227582386 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1227582386 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1227582386 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1227582386 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 636306689 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 636306689 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 841464320 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 841464320 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1477771009 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1477771009 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.808850 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.808850 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953491 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953491 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860302 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.860302 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860302 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.860302 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15627.028972 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15627.028972 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 27299.829801 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 27299.829801 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20229.094753 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20229.094753 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20229.094753 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20229.094753 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 65436.722439 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65436.722439 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 157902.856071 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157902.856071 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 98171.195708 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 98171.195708 # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9779 # number of writebacks +system.cpu1.l1c.writebacks::total 9779 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36240 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36240 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23835 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23835 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60075 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60075 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60075 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60075 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9833 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9833 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5388 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5388 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15221 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15221 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 557295449 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 557295449 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 688592271 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 688592271 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1245887720 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1245887720 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1245887720 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1245887720 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 707451122 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 707451122 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 858171680 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 858171680 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1565622802 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1565622802 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.809181 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.809181 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954240 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954240 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.861117 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.861117 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.861117 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.861117 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15377.909741 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15377.909741 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 28889.963121 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 28889.963121 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20738.871744 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20738.871744 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20738.871744 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20738.871744 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 71946.620767 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71946.620767 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 159274.625093 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159274.625093 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 102859.391761 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 102859.391761 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99747 # number of read accesses completed -system.cpu2.num_writes 54917 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22440 # number of replacements -system.cpu2.l1c.tags.tagsinuse 392.958774 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13419 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22848 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.587316 # Average number of references to valid blocks. +system.cpu2.num_reads 99126 # number of read accesses completed +system.cpu2.num_writes 55057 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22416 # number of replacements +system.cpu2.l1c.tags.tagsinuse 392.045662 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13448 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22823 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.589230 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 392.958774 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.767498 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.767498 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 337058 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 337058 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8566 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8566 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1197 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1197 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9763 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9763 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9763 # number of overall hits -system.cpu2.l1c.overall_hits::total 9763 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36656 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36656 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23689 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23689 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60345 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60345 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60345 # number of overall misses -system.cpu2.l1c.overall_misses::total 60345 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 609273651 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 609273651 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 671190571 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 671190571 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1280464222 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1280464222 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1280464222 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1280464222 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45222 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45222 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24886 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24886 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70108 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70108 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70108 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70108 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.810579 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.810579 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.951901 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.951901 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.860743 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.860743 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.860743 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.860743 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16621.389431 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 16621.389431 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 28333.427793 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 28333.427793 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 21219.060767 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 21219.060767 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 21219.060767 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 21219.060767 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 742867 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 392.045662 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.765714 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.765714 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 394 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 337969 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 337969 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8656 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8656 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1187 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1187 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9843 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9843 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9843 # number of overall hits +system.cpu2.l1c.overall_hits::total 9843 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36613 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36613 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23839 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23839 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60452 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60452 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60452 # number of overall misses +system.cpu2.l1c.overall_misses::total 60452 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 594021809 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 594021809 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 716005587 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 716005587 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1310027396 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1310027396 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1310027396 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1310027396 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45269 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45269 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25026 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25026 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70295 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70295 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70295 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70295 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808787 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.808787 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.952569 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.952569 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.859976 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.859976 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.859976 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.859976 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16224.341327 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 16224.341327 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 30035.051261 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 30035.051261 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 21670.538543 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 21670.538543 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 21670.538543 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 21670.538543 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 801429 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 60931 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 62324 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.191938 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.859075 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9836 # number of writebacks -system.cpu2.l1c.writebacks::total 9836 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36656 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36656 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23689 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23689 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60345 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60345 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60345 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60345 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9760 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9760 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5535 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5535 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15295 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15295 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 572617651 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 572617651 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 647503571 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 647503571 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1220121222 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1220121222 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1220121222 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1220121222 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 638440786 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 638440786 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 853548639 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 853548639 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1491989425 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1491989425 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.810579 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.810579 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.951901 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.951901 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860743 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.860743 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860743 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.860743 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15621.389431 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15621.389431 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 27333.512221 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 27333.512221 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20219.093910 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20219.093910 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20219.093910 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20219.093910 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 65414.014959 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65414.014959 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154209.329539 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154209.329539 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 97547.526970 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 97547.526970 # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9798 # number of writebacks +system.cpu2.l1c.writebacks::total 9798 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36613 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36613 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23839 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23839 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60452 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60452 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60452 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60452 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9743 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9743 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5322 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5322 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15065 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15065 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 557410809 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 557410809 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 692167587 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 692167587 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1249578396 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1249578396 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1249578396 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1249578396 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 702012144 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 702012144 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 835893746 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 835893746 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1537905890 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1537905890 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808787 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808787 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.952569 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.952569 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859976 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.859976 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859976 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.859976 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15224.395952 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15224.395952 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 29035.093209 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 29035.093209 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20670.588169 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20670.588169 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20670.588169 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20670.588169 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 72052.975880 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 72052.975880 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 157063.838031 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157063.838031 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 102084.692333 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 102084.692333 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 98987 # number of read accesses completed -system.cpu3.num_writes 55311 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22430 # number of replacements -system.cpu3.l1c.tags.tagsinuse 392.656254 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13364 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22840 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.585114 # Average number of references to valid blocks. +system.cpu3.num_reads 99267 # number of read accesses completed +system.cpu3.num_writes 54937 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22308 # number of replacements +system.cpu3.l1c.tags.tagsinuse 393.396608 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13642 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22699 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.600996 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 392.656254 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.766907 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.766907 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 337200 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 337200 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8601 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8601 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1133 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1133 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9734 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9734 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9734 # number of overall hits -system.cpu3.l1c.overall_hits::total 9734 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36299 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36299 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 24092 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 24092 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60391 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60391 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60391 # number of overall misses -system.cpu3.l1c.overall_misses::total 60391 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 601442350 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 601442350 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 682370713 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 682370713 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1283813063 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1283813063 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1283813063 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1283813063 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44900 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44900 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25225 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25225 # number of WriteReq accesses(hits+misses) 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overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16569.116229 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 16569.116229 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 28323.539474 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 28323.539474 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 21258.350797 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 21258.350797 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 21258.350797 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 21258.350797 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 746578 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 393.396608 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.768353 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.768353 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 377 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 336965 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 336965 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8834 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8834 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1126 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1126 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9960 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9960 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9960 # number of overall hits +system.cpu3.l1c.overall_hits::total 9960 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36404 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36404 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23769 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23769 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60173 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60173 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60173 # number of overall misses +system.cpu3.l1c.overall_misses::total 60173 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 595557078 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 595557078 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 707954928 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 707954928 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1303512006 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1303512006 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1303512006 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1303512006 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45238 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45238 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24895 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24895 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70133 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70133 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70133 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70133 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.804722 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.804722 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954770 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.954770 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.857984 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.857984 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.857984 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.857984 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16359.660422 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 16359.660422 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 29784.800707 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 29784.800707 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 21662.739202 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 21662.739202 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 21662.739202 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 21662.739202 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 796210 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 60969 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 61792 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.245207 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.885325 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9891 # number of writebacks -system.cpu3.l1c.writebacks::total 9891 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36299 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36299 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 24092 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 24092 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60391 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60391 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60391 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60391 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9771 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9771 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5455 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5455 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15226 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15226 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 565143350 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 565143350 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 658281713 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 658281713 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1223425063 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1223425063 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1223425063 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1223425063 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 638944774 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 638944774 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 852450723 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 852450723 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1491395497 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1491395497 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808441 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808441 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955084 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955084 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861191 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.861191 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861191 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.861191 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15569.116229 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15569.116229 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 27323.663996 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 27323.663996 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20258.400474 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20258.400474 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20258.400474 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20258.400474 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 65391.953127 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65391.953127 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 156269.610082 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156269.610082 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 97950.577762 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 97950.577762 # average overall mshr uncacheable latency +system.cpu3.l1c.writebacks::writebacks 9835 # number of writebacks +system.cpu3.l1c.writebacks::total 9835 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36404 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36404 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23769 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23769 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60173 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60173 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60173 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60173 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9778 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9778 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5503 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5503 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15281 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15281 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 559153078 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 559153078 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 684188928 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 684188928 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1243342006 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1243342006 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1243342006 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1243342006 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 702217176 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 702217176 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 867552200 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 867552200 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1569769376 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1569769376 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.804722 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.804722 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954770 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954770 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.857984 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.857984 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.857984 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.857984 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15359.660422 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15359.660422 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 28784.926922 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 28784.926922 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20662.789058 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20662.789058 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20662.789058 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20662.789058 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 71816.033545 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71816.033545 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 157650.772306 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157650.772306 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 102726.874943 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 102726.874943 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 54901 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22108 # number of replacements -system.cpu4.l1c.tags.tagsinuse 392.325245 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13548 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22499 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.602160 # Average number of references to valid blocks. +system.cpu4.num_reads 98613 # number of read accesses completed +system.cpu4.num_writes 54610 # number of write accesses completed +system.cpu4.l1c.tags.replacements 21998 # number of replacements +system.cpu4.l1c.tags.tagsinuse 392.447255 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13326 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22393 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.595097 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 392.325245 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.766260 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.766260 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 338175 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 338175 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8785 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8785 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1156 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1156 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9941 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9941 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9941 # number of overall hits -system.cpu4.l1c.overall_hits::total 9941 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36616 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36616 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23803 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23803 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60419 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60419 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60419 # number of overall misses -system.cpu4.l1c.overall_misses::total 60419 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 606172682 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 606172682 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 676089465 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 676089465 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1282262147 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1282262147 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1282262147 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1282262147 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45401 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45401 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24959 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24959 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70360 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70360 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70360 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70360 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.806502 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.806502 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953684 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.953684 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.858712 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.858712 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.858712 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.858712 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16554.858040 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 16554.858040 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 28403.540100 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 28403.540100 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 21222.829689 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 21222.829689 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 21222.829689 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 21222.829689 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 752786 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 392.447255 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.766499 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.766499 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 385 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 335144 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 335144 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8557 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8557 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1170 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1170 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9727 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9727 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9727 # number of overall hits +system.cpu4.l1c.overall_hits::total 9727 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36223 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36223 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23758 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23758 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 59981 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 59981 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 59981 # number of overall misses +system.cpu4.l1c.overall_misses::total 59981 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 587952444 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 587952444 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 716203349 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 716203349 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1304155793 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1304155793 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1304155793 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1304155793 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44780 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44780 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24928 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24928 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 69708 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 69708 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 69708 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 69708 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.808910 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.808910 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953065 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.953065 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.860461 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.860461 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.860461 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.860461 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16231.467410 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 16231.467410 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 30145.776118 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 30145.776118 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 21742.815108 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 21742.815108 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 21742.815108 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 21742.815108 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 805297 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 61311 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 61957 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.278156 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.997676 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9736 # number of writebacks -system.cpu4.l1c.writebacks::total 9736 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36616 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36616 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23803 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23803 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60419 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60419 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60419 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60419 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9898 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9898 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5382 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5382 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15280 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15280 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 569559682 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 569559682 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 652287465 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 652287465 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1221847147 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1221847147 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1221847147 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1221847147 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 646717625 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 646717625 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 846861232 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 846861232 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1493578857 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1493578857 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.806502 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.806502 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953684 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953684 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858712 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.858712 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858712 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.858712 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15554.939972 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15554.939972 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 27403.582111 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 27403.582111 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20222.895894 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20222.895894 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20222.895894 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20222.895894 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65338.212265 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65338.212265 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157350.656262 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157350.656262 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 97747.307395 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 97747.307395 # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 9749 # number of writebacks +system.cpu4.l1c.writebacks::total 9749 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36223 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36223 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23758 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23758 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 59981 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 59981 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 59981 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 59981 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9847 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9847 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5452 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5452 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15299 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15299 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 551729444 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 551729444 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 692447349 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 692447349 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1244176793 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1244176793 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1244176793 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1244176793 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 708336585 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 708336585 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 860694197 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 860694197 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1569030782 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1569030782 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.808910 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.808910 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953065 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953065 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.860461 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.860461 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.860461 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.860461 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15231.467410 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15231.467410 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 29145.860300 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 29145.860300 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20742.848452 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20742.848452 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20742.848452 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20742.848452 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 71934.252564 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71934.252564 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157867.607667 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157867.607667 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 102557.734623 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 102557.734623 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99420 # number of read accesses completed -system.cpu5.num_writes 55050 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22127 # number of replacements -system.cpu5.l1c.tags.tagsinuse 390.223258 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13616 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22515 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.604752 # Average number of references to valid blocks. +system.cpu5.num_reads 99530 # number of read accesses completed +system.cpu5.num_writes 55068 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22260 # number of replacements +system.cpu5.l1c.tags.tagsinuse 393.692529 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13670 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22641 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.603772 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 390.223258 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.762155 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.762155 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 338569 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 338569 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8830 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8830 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1218 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1218 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 10048 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 10048 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 10048 # number of overall hits -system.cpu5.l1c.overall_hits::total 10048 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36409 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36409 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23995 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23995 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60404 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60404 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60404 # number of overall misses -system.cpu5.l1c.overall_misses::total 60404 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 603629256 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 603629256 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 675904407 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 675904407 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1279533663 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1279533663 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1279533663 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1279533663 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45239 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45239 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25213 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25213 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70452 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70452 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70452 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70452 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.804814 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.804814 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.951692 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.951692 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.857378 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.857378 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.857378 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.857378 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16579.122085 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 16579.122085 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 28168.552073 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 28168.552073 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 21182.929326 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 21182.929326 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 21182.929326 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 21182.929326 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 750665 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 393.692529 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.768931 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.768931 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 381 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.744141 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 337364 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 337364 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8908 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8908 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1154 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1154 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 10062 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 10062 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 10062 # number of overall hits +system.cpu5.l1c.overall_hits::total 10062 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36264 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36264 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23895 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23895 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60159 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60159 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60159 # number of overall misses +system.cpu5.l1c.overall_misses::total 60159 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 595565994 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 595565994 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 715910266 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 715910266 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1311476260 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1311476260 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1311476260 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1311476260 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45172 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45172 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25049 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25049 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70221 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70221 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70221 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70221 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.802798 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.802798 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953930 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.953930 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.856710 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.856710 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.856710 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.856710 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16423.064030 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 16423.064030 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 29960.672358 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 29960.672358 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 21800.167224 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 21800.167224 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 21800.167224 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 21800.167224 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 800309 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 61291 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 61932 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.247557 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.922383 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9761 # number of writebacks -system.cpu5.l1c.writebacks::total 9761 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36409 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36409 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23995 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23995 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60404 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60404 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60404 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60404 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9891 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9891 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5483 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5483 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15374 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15374 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 567222256 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 567222256 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 651909407 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 651909407 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1219131663 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1219131663 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1219131663 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1219131663 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 648234678 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 648234678 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 860459231 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 860459231 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1508693909 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1508693909 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.804814 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.804814 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.951692 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.951692 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.857378 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.857378 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.857378 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.857378 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15579.177017 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15579.177017 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 27168.552073 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 27168.552073 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20182.962436 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20182.962436 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20182.962436 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20182.962436 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 65537.830149 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65537.830149 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 156932.196061 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156932.196061 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 98132.815728 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 98132.815728 # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 9774 # number of writebacks +system.cpu5.l1c.writebacks::total 9774 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36264 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36264 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23895 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23895 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60159 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60159 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60159 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60159 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9698 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9698 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5363 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5363 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15061 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15061 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 559302994 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 559302994 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 692016266 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 692016266 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1251319260 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1251319260 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1251319260 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1251319260 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 697234186 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 697234186 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 847695253 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 847695253 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1544929439 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1544929439 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.802798 # mshr miss rate for ReadReq accesses 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+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 28960.714208 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20800.200469 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20800.200469 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20800.200469 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20800.200469 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 71894.636626 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71894.636626 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 158063.630990 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 158063.630990 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 102578.144811 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 102578.144811 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99130 # number of read accesses completed -system.cpu6.num_writes 55082 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22211 # number of replacements -system.cpu6.l1c.tags.tagsinuse 391.729996 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13451 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22620 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.594651 # Average number of references to valid blocks. +system.cpu6.num_reads 100001 # number of read accesses completed +system.cpu6.num_writes 54955 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22371 # number of replacements +system.cpu6.l1c.tags.tagsinuse 392.789220 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13659 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22773 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.599789 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 391.729996 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.765098 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.765098 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 394 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 338357 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 338357 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8673 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8673 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1155 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1155 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9828 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9828 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9828 # number of overall hits -system.cpu6.l1c.overall_hits::total 9828 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36524 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36524 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 24020 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 24020 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60544 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60544 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60544 # number of overall misses -system.cpu6.l1c.overall_misses::total 60544 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 604615121 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 604615121 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 676363327 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 676363327 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1280978448 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1280978448 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1280978448 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1280978448 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45197 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45197 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25175 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25175 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70372 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70372 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70372 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70372 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808107 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.808107 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954121 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.954121 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.860342 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.860342 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.860342 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.860342 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16553.913071 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 16553.913071 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28158.340008 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 28158.340008 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 21157.809989 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 21157.809989 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 21157.809989 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 21157.809989 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 747919 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 392.789220 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.767166 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.767166 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 393 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 338676 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 338676 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8791 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8791 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1193 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1193 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9984 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9984 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9984 # number of overall hits +system.cpu6.l1c.overall_hits::total 9984 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36779 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36779 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23715 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23715 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60494 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60494 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60494 # number of overall misses +system.cpu6.l1c.overall_misses::total 60494 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 595549144 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 595549144 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 708070907 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 708070907 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1303620051 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1303620051 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1303620051 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1303620051 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45570 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45570 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24908 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24908 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70478 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70478 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70478 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70478 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807088 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.807088 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.952104 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.952104 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858339 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858339 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858339 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858339 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16192.641018 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 16192.641018 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 29857.512418 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 29857.512418 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 21549.576008 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 21549.576008 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 21549.576008 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 21549.576008 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 794028 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 61299 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 62044 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.201162 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.797821 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9790 # number of writebacks -system.cpu6.l1c.writebacks::total 9790 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36524 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36524 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24020 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 24020 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60544 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60544 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60544 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60544 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9846 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9846 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5510 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5510 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15356 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15356 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 568091121 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 568091121 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 652345327 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 652345327 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1220436448 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1220436448 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1220436448 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1220436448 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 644948195 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 644948195 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 860679200 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 860679200 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1505627395 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1505627395 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808107 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808107 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954121 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954121 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.860342 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.860342 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.860342 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.860342 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15553.913071 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15553.913071 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 27158.423272 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 27158.423272 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20157.843023 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20157.843023 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20157.843023 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20157.843023 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 65503.574548 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65503.574548 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 156203.121597 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156203.121597 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 98048.150234 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 98048.150234 # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9773 # number of writebacks +system.cpu6.l1c.writebacks::total 9773 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36779 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36779 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23715 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23715 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60494 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60494 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60494 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60494 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9743 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9743 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5502 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5502 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15245 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15245 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 558770144 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 558770144 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 684356907 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 684356907 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1243127051 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1243127051 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1243127051 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1243127051 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 702205139 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702205139 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 875087157 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 875087157 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1577292296 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1577292296 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807088 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807088 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.952104 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.952104 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858339 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858339 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858339 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858339 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15192.641018 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15192.641018 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 28857.554586 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 28857.554586 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20549.592538 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20549.592538 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20549.592538 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20549.592538 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 72072.784461 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 72072.784461 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 159048.919847 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159048.919847 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 103462.925287 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 103462.925287 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99282 # number of read accesses completed -system.cpu7.num_writes 55000 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22412 # number of replacements -system.cpu7.l1c.tags.tagsinuse 392.240178 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13369 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22828 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.585640 # Average number of references to valid blocks. +system.cpu7.num_reads 99732 # number of read accesses completed +system.cpu7.num_writes 55186 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22105 # number of replacements +system.cpu7.l1c.tags.tagsinuse 391.370136 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13595 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22490 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.604491 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 392.240178 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.766094 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.766094 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 407 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 337994 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 337994 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8608 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8608 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1119 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1119 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9727 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9727 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9727 # number of overall hits -system.cpu7.l1c.overall_hits::total 9727 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36557 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36557 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 24000 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 24000 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60557 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60557 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60557 # number of overall misses -system.cpu7.l1c.overall_misses::total 60557 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 604992547 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 604992547 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 682517760 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 682517760 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1287510307 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1287510307 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1287510307 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1287510307 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45165 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45165 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25119 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25119 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70284 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70284 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70284 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70284 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.809410 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.809410 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955452 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.955452 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.861604 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.861604 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.861604 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.861604 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16549.294171 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 16549.294171 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 28438.240000 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 28438.240000 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 21261.130951 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 21261.130951 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 21261.130951 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 21261.130951 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 748003 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 391.370136 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.764395 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.764395 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 385 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.751953 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 337196 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 337196 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8779 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8779 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1155 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1155 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9934 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9934 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9934 # number of overall hits +system.cpu7.l1c.overall_hits::total 9934 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36327 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36327 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23913 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23913 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60240 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60240 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60240 # number of overall misses +system.cpu7.l1c.overall_misses::total 60240 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 591115609 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 591115609 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 714870765 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 714870765 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1305986374 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1305986374 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1305986374 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1305986374 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45106 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45106 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25068 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25068 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70174 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70174 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70174 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70174 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805370 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.805370 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953925 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953925 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.858438 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.858438 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.858438 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.858438 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16272.073361 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 16272.073361 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 29894.649981 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 29894.649981 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 21679.720684 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 21679.720684 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 21679.720684 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 21679.720684 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 800916 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 61301 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 62109 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.202134 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.895329 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9927 # number of writebacks -system.cpu7.l1c.writebacks::total 9927 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36557 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36557 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24000 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 24000 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60557 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60557 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60557 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60557 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9747 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9747 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5404 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5404 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15151 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15151 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 568436547 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 568436547 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 658518760 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 658518760 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1226955307 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1226955307 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1226955307 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1226955307 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 638135236 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 638135236 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 851560751 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 851560751 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1489695987 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1489695987 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.809410 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.809410 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955452 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955452 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.861604 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.861604 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.861604 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.861604 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15549.321525 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15549.321525 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 27438.281667 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 27438.281667 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20261.163978 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20261.163978 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20261.163978 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20261.163978 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 65469.912383 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65469.912383 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 157579.709660 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157579.709660 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 98323.278133 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 98323.278133 # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9688 # number of writebacks +system.cpu7.l1c.writebacks::total 9688 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36327 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36327 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23913 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23913 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60240 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60240 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60240 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60240 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9808 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9808 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5490 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5490 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15298 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15298 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 554789609 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 554789609 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 690958765 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 690958765 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1245748374 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1245748374 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1245748374 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1245748374 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 704741576 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 704741576 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 868948151 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 868948151 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1573689727 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1573689727 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805370 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805370 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953925 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953925 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858438 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.858438 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858438 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.858438 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15272.100889 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15272.100889 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 28894.691799 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 28894.691799 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20679.753884 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20679.753884 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20679.753884 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20679.753884 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 71853.749592 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71853.749592 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 158278.351730 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 158278.351730 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 102868.984639 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 102868.984639 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 14184 # number of replacements -system.l2c.tags.tagsinuse 788.596931 # Cycle average of tags in use -system.l2c.tags.total_refs 165124 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14990 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.015610 # Average number of references to valid blocks. +system.l2c.tags.replacements 13995 # number of replacements +system.l2c.tags.tagsinuse 787.283340 # Cycle average of tags in use +system.l2c.tags.total_refs 163090 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14802 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.018106 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 730.575268 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 6.784178 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.707727 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.687216 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.484376 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.524449 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 7.360121 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 7.299960 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 7.173635 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.713452 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006625 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.007527 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.007507 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.007309 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006372 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.007188 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.007129 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.007006 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.770114 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 806 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 681 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.787109 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2105340 # Number of tag accesses -system.l2c.tags.data_accesses 2105340 # Number of data accesses -system.l2c.Writeback_hits::writebacks 77391 # number of Writeback hits -system.l2c.Writeback_hits::total 77391 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 263 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 239 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 258 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 273 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 248 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 266 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 263 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 283 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2093 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1731 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1747 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1743 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1722 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1763 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1786 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1787 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1783 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14062 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0 10988 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1 10938 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2 10927 # number of ReadSharedReq hits +system.l2c.tags.occ_blocks::writebacks 729.204744 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 7.276243 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 7.685702 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.303189 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 7.305571 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.947966 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 7.333904 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.314281 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 6.911739 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.712114 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.007106 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.007506 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.007132 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.007134 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006785 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.007162 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.007143 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.006750 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768831 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 807 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 673 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.788086 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 2092027 # Number of tag accesses +system.l2c.tags.data_accesses 2092027 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 76994 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 76994 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0 283 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 283 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 290 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 275 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 271 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 268 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 273 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 273 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2216 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1696 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1826 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1766 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1793 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1691 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1701 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1693 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1794 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 13960 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0 10787 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1 10737 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2 10799 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu3 10853 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu4 11009 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu5 10877 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu6 10827 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu7 10964 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 87383 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0 12719 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12685 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12670 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12575 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12772 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12663 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12614 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12747 # number of demand (read+write) hits -system.l2c.demand_hits::total 101445 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12719 # number of overall hits -system.l2c.overall_hits::cpu1 12685 # number of overall hits -system.l2c.overall_hits::cpu2 12670 # number of overall hits -system.l2c.overall_hits::cpu3 12575 # number of overall hits -system.l2c.overall_hits::cpu4 12772 # number of overall hits -system.l2c.overall_hits::cpu5 12663 # number of overall hits -system.l2c.overall_hits::cpu6 12614 # number of overall hits -system.l2c.overall_hits::cpu7 12747 # number of overall hits -system.l2c.overall_hits::total 101445 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0 1986 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 2040 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2071 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2052 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 2099 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2039 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 2050 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 2087 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 16424 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4684 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4646 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4587 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4709 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4574 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4603 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4641 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4708 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 37152 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0 746 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1 738 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2 778 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3 755 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu4 710 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu5 726 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu6 763 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu7 735 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 5951 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0 5430 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5384 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5365 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5464 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5284 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5329 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5404 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5443 # number of demand (read+write) misses -system.l2c.demand_misses::total 43103 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5430 # number of overall misses -system.l2c.overall_misses::cpu1 5384 # number of overall misses -system.l2c.overall_misses::cpu2 5365 # number of overall misses -system.l2c.overall_misses::cpu3 5464 # number of overall misses -system.l2c.overall_misses::cpu4 5284 # number of overall misses -system.l2c.overall_misses::cpu5 5329 # number of overall misses -system.l2c.overall_misses::cpu6 5404 # number of overall misses -system.l2c.overall_misses::cpu7 5443 # number of overall misses -system.l2c.overall_misses::total 43103 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0 59643812 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 60697485 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 64325987 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 61406491 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 65507992 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 63321487 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 63031988 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 64081491 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 502016733 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 260655915 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 258218912 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 254645420 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 260879417 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 253975429 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 255536909 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 257461916 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 261401431 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2062775349 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0 45984404 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1 45132427 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2 48152413 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3 46986917 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu4 43700923 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu5 45387411 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu6 47108917 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu7 45792412 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 368245824 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0 306640319 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 303351339 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 302797833 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 307866334 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 297676352 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 300924320 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 304570833 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 307193843 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2431021173 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 306640319 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 303351339 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 302797833 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 307866334 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 297676352 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 300924320 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 304570833 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 307193843 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2431021173 # number of overall miss cycles -system.l2c.Writeback_accesses::writebacks 77391 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 77391 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2249 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2279 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2329 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2325 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2347 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2305 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2313 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2370 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18517 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6415 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6393 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6330 # number of ReadExReq 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0.065833 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu7 0.062826 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.063760 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0 0.299190 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.297969 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.297477 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.302899 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.292645 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.296187 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.299922 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.299230 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.298192 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.299190 # miss rate for overall accesses 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cycles +system.l2c.overall_miss_latency::cpu1 338148266 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 340044284 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 336285098 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 340734294 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 339429288 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 335167781 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 341384275 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2703394563 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 76994 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 76994 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2287 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2378 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2328 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2336 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2349 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2368 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2347 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2342 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18735 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6220 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6394 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6430 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6373 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6375 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6310 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6280 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6461 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50843 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0 11521 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1 11527 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2 11528 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3 11595 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu4 11505 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu5 11516 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu6 11661 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu7 11556 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 92409 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17741 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17921 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17958 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17968 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17880 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17826 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17941 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18017 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 143252 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17741 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17921 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17958 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17968 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17880 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17826 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17941 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18017 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 143252 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.876257 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.880992 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.875430 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.882277 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.884632 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.886824 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.883681 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.883433 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.881719 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.727331 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.714420 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.725350 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.718657 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.734745 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.730428 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.730414 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.722334 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.725429 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0 0.063710 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1 0.068535 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2 0.063237 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3 0.063993 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu4 0.062234 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu5 0.066777 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu6 0.062173 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.064382 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.064377 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.296376 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.298979 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.300312 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.296193 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.302013 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.301694 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.296082 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.300327 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.298998 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.296376 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.298979 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.300312 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.296193 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.302013 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.301694 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.296082 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.300327 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.298998 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0 34087.565868 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 34057.982816 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 35130.263003 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 34039.291121 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 34562.309432 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 34068.563810 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 34543.625362 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 36143.692122 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 34578.524850 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 62346.677498 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 62366.215193 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 62292.319468 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 62368.274236 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 62437.420581 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 62472.091777 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 62298.752780 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 62298.127919 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 62359.997967 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 68317.313351 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 67416.955696 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 67918.938272 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 68245.824798 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 67426.558659 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 66964.131339 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 68142.623448 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 68063.053763 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 67804.800471 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 63180.159186 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 63110.911907 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 63052.898943 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 63187.729801 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 63098.943333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 63114.408330 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 63096.344315 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 63090.791905 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 63116.234661 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 63180.159186 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 63110.911907 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 63052.898943 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 63187.729801 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 63098.943333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 63114.408330 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 63096.344315 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 63090.791905 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 63116.234661 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 33757 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 3172 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 6432 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 5.581337 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 5.248290 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6492 # number of writebacks -system.l2c.writebacks::total 6492 # number of writebacks -system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 8 # number of ReadExReq MSHR hits +system.l2c.writebacks::writebacks 6537 # number of writebacks +system.l2c.writebacks::total 6537 # number of writebacks +system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 10 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu6 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 40 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0 8 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1 11 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2 15 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3 8 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu4 8 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu5 5 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu6 11 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu7 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 70 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 18 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 18 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 110 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 16 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 18 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 16 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 18 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 110 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 1197 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 1197 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1986 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2039 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2071 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2052 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 2099 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2037 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2050 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 2087 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 16421 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4678 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4641 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4584 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4701 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4570 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_hits::cpu7 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 39 # number of ReadExReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0 4 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1 13 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2 7 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu3 6 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu4 14 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu5 11 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu6 9 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu7 11 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 75 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 17 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 18 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 21 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 16 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+system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 42768413 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 341873266 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 279490777 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 284090767 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 285868286 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 282891598 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 286276796 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 285224290 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 281657282 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 286775277 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2272275073 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 279490777 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 284090767 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 285868286 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 282891598 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 286276796 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 285224290 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 281657282 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 286775277 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2272275073 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 503232104 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 504891308 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 500756647 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 501380612 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 505534787 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 497694775 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 500159589 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 503166776 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 4016816598 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 292229228 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 286836409 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 283709721 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 292753904 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 289394212 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 284248382 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 293152393 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 291492896 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2313817145 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 795461332 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 791727717 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 784466368 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 794134516 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 794928999 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 781943157 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 793311982 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 794659672 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6330633743 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.883059 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.894691 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.889223 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.882581 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.894333 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.883731 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.886295 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.880591 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.886807 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.729228 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.725950 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.724171 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.730991 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.721161 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.719831 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.720909 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.724850 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.724646 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.062894 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.062264 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.065186 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.064352 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.059903 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.062139 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.064884 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.062484 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063010 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.298419 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.297083 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.296479 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.302012 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.291981 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.295687 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.298923 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.298846 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.297431 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.298419 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.297083 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.296479 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.302012 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.291981 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.295687 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.298923 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.298846 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.297431 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 44922.610775 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 44954.132418 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 44938.666828 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 44950.770468 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 44833.006193 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 44949.669121 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 44860.720976 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 44964.533301 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44921.573351 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 45682.110945 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 45612.025856 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 45541.976440 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 45452.439268 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 45550.203282 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 45536.401174 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 45515.627104 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 45535.266950 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 45553.240165 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 51925.344173 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 51508.154058 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 52511.027523 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 52582.218206 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 51819.692308 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 52725.951456 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 52163.453457 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 52454.054720 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 52214.900357 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 46532.832164 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 46410.551416 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 46536.438003 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 46430.035609 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 46385.025228 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 46510.774436 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 46443.804864 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 46465.663171 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 46464.486730 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 46532.832164 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 46410.551416 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 46536.438003 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 46430.035609 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 46385.025228 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 46510.774436 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 46443.804864 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 46465.663171 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 46464.486730 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44420.329070 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44451.631081 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44461.256660 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44495.280217 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44517.718428 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44486.777070 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44473.425597 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44477.416538 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44473.085348 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45722.229950 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 46311.681366 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45905.193385 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45877.502108 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45846.631364 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 46046.768557 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 46061.443718 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 46016.177831 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45972.703971 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44886.368874 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 45110.162038 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44983.672268 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44990.487127 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44985.794961 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 45043.134123 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 45043.138605 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 45026.255957 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 45008.529040 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.875820 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.880992 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.875430 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.882277 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.884632 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.886402 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.883681 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.883433 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.881612 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.726527 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.713794 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.725039 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.718186 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.734118 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.728843 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.729299 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.721715 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.724662 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.063363 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.067407 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.062630 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.063476 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.061017 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.065821 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.061401 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.063430 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063565 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.295868 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.298030 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.299811 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.295692 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.301007 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.300516 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.295190 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.299495 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.298202 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.295868 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.298030 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.299811 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.295692 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.301007 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.300516 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.295190 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.299495 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.298202 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 51820.502247 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 51833.867780 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 51855.473994 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 51884.746725 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 51804.842637 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 51837.290138 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 51859.671649 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 51753.155631 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 51831.174608 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 52384.680018 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 52396.991893 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 52295.447876 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 52396.372296 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 52463.649145 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 52537.045445 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 52349.646070 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 52328.300236 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 52393.925931 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 58581.380822 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 57851.861004 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 58264.415512 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 58523.644022 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58044.042735 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 57528.255937 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 58513.831006 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 58347.084584 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 58201.100783 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 53246.480663 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 53190.557386 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 53095.892645 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 53245.171843 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 53191.526570 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 53243.287288 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 53183.021526 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 53145.900111 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 53192.449857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 53246.480663 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 53190.557386 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 53095.892645 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 53245.171843 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 53191.526570 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 53243.287288 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 53183.021526 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 53145.900111 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 53192.449857 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 51355.455046 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 51346.619343 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 51401.831965 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 51276.397218 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 51338.964862 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 51319.320994 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 51335.275480 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 51301.669657 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 51334.431525 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 53016.913643 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 53236.156088 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 53328.894925 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 53198.964928 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 53109.600294 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 53001.749394 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 53310.127841 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 53104.918200 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 53163.089516 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 51953.584482 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 52015.486302 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 52082.483601 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 51968.753092 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 51969.730583 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 51918.408937 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 52047.761580 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 51948.726678 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 51988.024595 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 78406 # Transaction distribution -system.membus.trans_dist::ReadResp 84270 # Transaction distribution -system.membus.trans_dist::WriteReq 43542 # Transaction distribution -system.membus.trans_dist::WriteResp 43539 # Transaction distribution -system.membus.trans_dist::Writeback 6492 # Transaction distribution -system.membus.trans_dist::CleanEvict 1226 # Transaction distribution -system.membus.trans_dist::UpgradeReq 61182 # Transaction distribution -system.membus.trans_dist::UpgradeResp 50391 # Transaction distribution -system.membus.trans_dist::ReadExReq 49587 # Transaction distribution -system.membus.trans_dist::ReadExResp 3167 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 5869 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 427671 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 427671 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1115735 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1115735 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 57207 # Total snoops (count) -system.membus.snoop_fanout::samples 255615 # Request fanout histogram +system.membus.trans_dist::ReadReq 78245 # Transaction distribution +system.membus.trans_dist::ReadResp 84100 # Transaction distribution +system.membus.trans_dist::WriteReq 43522 # Transaction distribution +system.membus.trans_dist::WriteResp 43520 # Transaction distribution +system.membus.trans_dist::WritebackDirty 6537 # Transaction distribution +system.membus.trans_dist::CleanEvict 1268 # Transaction distribution +system.membus.trans_dist::UpgradeReq 61107 # Transaction distribution +system.membus.trans_dist::UpgradeResp 50201 # Transaction distribution +system.membus.trans_dist::ReadExReq 48942 # Transaction distribution +system.membus.trans_dist::ReadExResp 3181 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5862 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 426485 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 426485 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1118817 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1118817 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 56662 # Total snoops (count) +system.membus.snoop_fanout::samples 253744 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 255615 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 253744 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 255615 # Request fanout histogram -system.membus.reqLayer0.occupancy 293172648 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 56.6 # Layer utilization (%) -system.membus.respLayer0.occupancy 310812284 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 60.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 663719 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 283046 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 335146 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 12757 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 5920 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 6837 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 78408 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 370885 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43543 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43537 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 83883 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 20723 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29304 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29302 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 162111 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 162107 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 292494 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122788 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122467 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122636 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122530 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122578 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122681 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122805 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122788 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 981273 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1801396 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1791690 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1789116 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1791289 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1784816 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1780428 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1784184 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1802670 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14325589 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 335027 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 801595 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.188537 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.005333 # Request fanout histogram +system.membus.snoop_fanout::total 253744 # Request fanout histogram +system.membus.reqLayer0.occupancy 292620525 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 54.8 # Layer utilization (%) +system.membus.respLayer0.occupancy 295409000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 55.3 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 663684 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 282033 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 335738 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 12570 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 5835 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 6735 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 78248 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 369469 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43523 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43520 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 83531 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 20342 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29636 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29633 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 160854 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 160848 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 291239 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 121995 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122071 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122139 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122334 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122013 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 121723 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122513 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122322 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 977110 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1766349 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1778610 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1781270 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1785072 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1775296 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1771667 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1779976 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1778751 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14216991 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 333737 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 624990 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.150519 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.991140 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 216155 26.97% 26.97% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 322197 40.19% 67.16% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 179904 22.44% 89.60% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 65286 8.14% 97.75% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 15605 1.95% 99.69% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 2259 0.28% 99.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 176 0.02% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 13 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 174852 27.98% 27.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 256379 41.02% 69.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 133497 21.36% 90.36% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 47307 7.57% 97.93% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 11157 1.79% 99.71% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 1650 0.26% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 145 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 3 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 801595 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 495500281 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 95.7 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 101557213 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 101587169 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 101172758 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 19.5 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 101251086 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 101367103 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 101469413 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 101588792 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 101399821 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 19.6 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 624990 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 497290718 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 93.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 100872915 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 18.9 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 100601006 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 18.8 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 101141480 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 18.9 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 100780789 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 18.9 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 100568051 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 18.8 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 100691951 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 18.9 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 101210192 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 19.0 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 100872512 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 18.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index e56af27bf..dfde51d65 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133625 # Number of seconds simulated -sim_ticks 133625300500 # Number of ticks simulated -final_tick 133625300500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.134742 # Number of seconds simulated +sim_ticks 134741611500 # Number of ticks simulated +final_tick 134741611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1279205 # Simulator instruction rate (inst/s) -host_op_rate 1279205 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1934942472 # Simulator tick rate (ticks/s) -host_mem_usage 304832 # Number of bytes of host memory used -host_seconds 69.06 # Real time elapsed on the host +host_inst_rate 1392855 # Simulator instruction rate (inst/s) +host_op_rate 1392855 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2124451972 # Simulator tick rate (ticks/s) +host_mem_usage 305428 # Number of bytes of host memory used +host_seconds 63.42 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 419712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10136000 # Number of bytes read from this memory -system.physmem.bytes_read::total 10555712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 419712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 419712 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7316416 # Number of bytes written to this memory -system.physmem.bytes_written::total 7316416 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6558 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158375 # Number of read requests responded to by this memory -system.physmem.num_reads::total 164933 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114319 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114319 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 3140962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75853899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 78994861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3140962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3140962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54753224 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54753224 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54753224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3140962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75853899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 133748085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 367360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10138112 # Number of bytes read from this memory +system.physmem.bytes_read::total 10505472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 367360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 367360 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7320448 # Number of bytes written to this memory +system.physmem.bytes_written::total 7320448 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5740 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158408 # Number of read requests responded to by this memory +system.physmem.num_reads::total 164148 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114382 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114382 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2726403 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 75241137 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 77967540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2726403 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2726403 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54329527 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54329527 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54329527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2726403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 75241137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 132297067 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -70,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 267250601 # number of cpu cycles simulated +system.cpu.numCycles 269483223 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88340673 # Number of instructions committed @@ -89,7 +89,7 @@ system.cpu.num_mem_refs 34987415 # nu system.cpu.num_load_insts 20366786 # Number of load instructions system.cpu.num_store_insts 14620629 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 267250601 # Number of busy cycles +system.cpu.num_busy_cycles 269483223 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 13754477 # Number of branches fetched @@ -129,18 +129,18 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 88438073 # Class of executed instruction system.cpu.dcache.tags.replacements 200248 # number of replacements -system.cpu.dcache.tags.tagsinuse 4078.862376 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4078.397630 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 936464500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4078.862376 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 983457500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4078.397630 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995703 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995703 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 482 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3562 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3595 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 204344 # n system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses system.cpu.dcache.overall_misses::total 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1944960000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1944960000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363504500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7363504500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9308464500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9308464500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9308464500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9308464500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2138978000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2138978000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8279807000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8279807000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10418785000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10418785000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10418785000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10418785000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32007.372544 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32007.372544 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51285.743638 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 51285.743638 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45552.913225 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45552.913225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45552.913225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45552.913225 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35200.243557 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35200.243557 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57667.657998 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57667.657998 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 50986.498258 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 50986.498258 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 50986.498258 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 50986.498258 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168314 # number of writebacks -system.cpu.dcache.writebacks::total 168314 # number of writebacks +system.cpu.dcache.writebacks::writebacks 168278 # number of writebacks +system.cpu.dcache.writebacks::total 168278 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204344 system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1884194000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1884194000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7219926500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7219926500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9104120500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9104120500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9104120500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9104120500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2078212000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2078212000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8136229000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8136229000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10214441000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10214441000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10214441000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10214441000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -226,27 +226,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31007.372544 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31007.372544 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50285.743638 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50285.743638 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44552.913225 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44552.913225 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44552.913225 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44552.913225 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34200.243557 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34200.243557 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56667.657998 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56667.657998 # average WriteReq mshr miss latency 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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1871.687345 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.913910 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.913910 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1870.507754 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.913334 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.913334 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 191 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1708 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998535 # Percentage of cache occupancy per task id @@ -264,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses system.cpu.icache.overall_misses::total 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1269528000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1269528000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1269528000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1269528000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1269528000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1269528000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1275518500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1275518500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1275518500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1275518500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1275518500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1275518500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses @@ -282,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16609.032393 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16609.032393 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16609.032393 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16609.032393 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16609.032393 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16609.032393 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16687.405149 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16687.405149 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16687.405149 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16687.405149 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16687.405149 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16687.405149 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -296,93 +296,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 74391 # number of writebacks +system.cpu.icache.writebacks::total 74391 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 76436 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 76436 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 76436 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1193092000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1193092000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1193092000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1193092000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1193092000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1193092000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1199082500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1199082500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1199082500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1199082500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1199082500 # number of overall MSHR miss cycles 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Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 131016 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30726.483059 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 246631 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 163072 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.512406 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 131998 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30708.485304 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 247404 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 164074 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.507881 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27128.298594 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1976.305001 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1621.879464 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.827890 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060312 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.049496 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.937698 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32056 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 655 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9977 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21188 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 27397.900187 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1667.759999 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1642.825119 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.836118 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.050896 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.050135 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.937149 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32076 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id 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-system.cpu.l2cache.Writeback_accesses::writebacks 168314 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168314 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4751004 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4751004 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 168278 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 168278 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 74391 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 74391 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12696 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12696 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 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ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 5740 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27526 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 27526 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 5740 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158408 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 164148 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 5740 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158408 # number of overall misses +system.cpu.l2cache.overall_misses::total 164148 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7787542500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7787542500 # number of ReadExReq miss cycles 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+system.cpu.l2cache.WritebackDirty_accesses::writebacks 168278 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 168278 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 74391 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 74391 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 143578 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143578 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 76436 # number of ReadCleanReq accesses(hits+misses) @@ -395,30 +401,30 @@ system.cpu.l2cache.demand_accesses::total 280780 # n system.cpu.l2cache.overall_accesses::cpu.inst 76436 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 204344 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911560 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911560 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.085797 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.085797 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.452473 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.452473 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085797 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775041 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.587410 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085797 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775041 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.587410 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.233038 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.233038 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52558.173224 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52558.173224 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52507.710493 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52507.710493 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52558.173224 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.531176 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52503.783354 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52558.173224 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.531176 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52503.783354 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911574 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911574 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.075096 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.075096 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.452984 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.452984 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.075096 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.775203 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.584614 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.075096 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.775203 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.584614 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.485170 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.485170 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59558.536585 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59558.536585 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59507.011553 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59507.011553 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59558.536585 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.619236 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59503.609547 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59558.536585 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.619236 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59503.609547 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -427,70 +433,71 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114319 # number of writebacks -system.cpu.l2cache.writebacks::total 114319 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1879 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1879 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130880 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130880 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6558 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6558 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27495 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27495 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 6558 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158375 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 164933 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 6558 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158375 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 164933 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5562430500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5562430500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 279096500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 279096500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1168749500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1168749500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 279096500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6731180000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7010276500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 279096500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6731180000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7010276500 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 114382 # number of writebacks +system.cpu.l2cache.writebacks::total 114382 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 105 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 105 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130882 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130882 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 5740 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 5740 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27526 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27526 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5740 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158408 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 164148 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5740 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158408 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 164148 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6478722500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6478722500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284466000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284466000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1362730000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1362730000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284466000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7841452500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8125918500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284466000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7841452500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8125918500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911560 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911560 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085797 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085797 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452473 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452473 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085797 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775041 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.587410 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085797 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775041 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.587410 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.233038 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.233038 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42558.173224 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42558.173224 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42507.710493 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42507.710493 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42558.173224 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.531176 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42503.783354 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42558.173224 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.531176 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42503.783354 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911574 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911574 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.075096 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452984 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452984 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775203 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.584614 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775203 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.584614 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.485170 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.485170 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49558.536585 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49558.536585 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49507.011553 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49507.011553 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49558.536585 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.619236 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.609547 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49558.536585 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.619236 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.609547 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 555419 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 274639 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3862 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3862 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3875 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3875 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 282633 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 123022 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 282660 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 74391 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 49586 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 76436 # Transaction distribution @@ -498,51 +505,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 60766 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 227263 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 608936 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 836199 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4891904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23850112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28742016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 131016 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 686435 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.005626 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.074797 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9652928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23847808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 33500736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 131998 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 412778 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009388 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.096434 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 682573 99.44% 99.44% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3862 0.56% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 408903 99.06% 99.06% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3875 0.94% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 686435 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 446023500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 412778 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 520378500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 34053 # Transaction distribution -system.membus.trans_dist::Writeback 114319 # Transaction distribution -system.membus.trans_dist::CleanEvict 14713 # Transaction distribution -system.membus.trans_dist::ReadExReq 130880 # Transaction distribution -system.membus.trans_dist::ReadExResp 130880 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34053 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 458898 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 458898 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17872128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17872128 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 33266 # Transaction distribution +system.membus.trans_dist::WritebackDirty 114382 # Transaction distribution +system.membus.trans_dist::CleanEvict 13845 # Transaction distribution +system.membus.trans_dist::ReadExReq 130882 # Transaction distribution +system.membus.trans_dist::ReadExResp 130882 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 33266 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 456523 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 456523 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17825920 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 294098 # Request fanout histogram +system.membus.snoop_fanout::samples 292375 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 294098 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 292375 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 294098 # Request fanout histogram -system.membus.reqLayer0.occupancy 751484676 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 292375 # Request fanout histogram +system.membus.reqLayer0.occupancy 750324500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 824727676 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 820740000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 11714b3d8..26a8d858a 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.127296 # Number of seconds simulated -sim_ticks 127296402500 # Number of ticks simulated -final_tick 127296402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.128077 # Number of seconds simulated +sim_ticks 128076812500 # Number of ticks simulated +final_tick 128076812500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 692014 # Simulator instruction rate (inst/s) -host_op_rate 883507 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1251758978 # Simulator tick rate (ticks/s) -host_mem_usage 324360 # Number of bytes of host memory used -host_seconds 101.69 # Real time elapsed on the host +host_inst_rate 787701 # Simulator instruction rate (inst/s) +host_op_rate 1005673 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1433579724 # Simulator tick rate (ticks/s) +host_mem_usage 323992 # Number of bytes of host memory used +host_seconds 89.34 # Real time elapsed on the host sim_insts 70373629 # Number of instructions simulated sim_ops 89847363 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 252800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7924480 # Number of bytes read from this memory -system.physmem.bytes_read::total 8177280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 252800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 252800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5511360 # Number of bytes written to this memory -system.physmem.bytes_written::total 5511360 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3950 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123820 # Number of read requests responded to by this memory -system.physmem.num_reads::total 127770 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 86115 # Number of write requests responded to by this memory -system.physmem.num_writes::total 86115 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1985916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 62252191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 64238108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1985916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1985916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43295489 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43295489 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43295489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1985916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 62252191 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 107533597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7925248 # Number of bytes read from this memory +system.physmem.bytes_read::total 8158400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 233152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 233152 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5513600 # Number of bytes written to this memory +system.physmem.bytes_written::total 5513600 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3643 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123832 # Number of read requests responded to by this memory +system.physmem.num_reads::total 127475 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 86150 # Number of write requests responded to by this memory +system.physmem.num_writes::total 86150 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1820408 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 61878867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 63699274 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1820408 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1820408 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43049166 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43049166 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43049166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1820408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 61878867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 106748441 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 254592805 # number of cpu cycles simulated +system.cpu.numCycles 256153625 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373629 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 43422001 # nu system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 254592804.998000 # Number of busy cycles +system.cpu.num_busy_cycles 256153624.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 13741486 # Number of branches fetched @@ -215,53 +215,53 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690084 # Class of executed instruction system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.388470 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42608158 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4075.927151 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42601677 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 266.304316 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1061128500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.388470 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 266.263810 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1109655500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927151 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995099 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995099 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 787 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3263 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22749833 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22749833 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 22743361 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22743361 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83618 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83618 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83609 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83609 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42492702 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42492702 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42576320 # number of overall hits -system.cpu.dcache.overall_hits::total 42576320 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 30234 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 30234 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 42486230 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42486230 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42569839 # number of overall hits +system.cpu.dcache.overall_hits::total 42569839 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 36706 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 36706 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 40126 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 40126 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 137266 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 137266 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 177392 # number of overall misses -system.cpu.dcache.overall_misses::total 177392 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 519264000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 519264000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689129500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5689129500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6208393500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6208393500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6208393500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6208393500 # number of overall miss cycles +system.cpu.dcache.SoftPFReq_misses::cpu.data 40135 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 40135 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 143738 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 143738 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 183873 # number of overall misses +system.cpu.dcache.overall_misses::total 183873 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 577584000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 577584000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6405138000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6405138000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6982722000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6982722000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6982722000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6982722000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) @@ -276,24 +276,24 @@ system.cpu.dcache.demand_accesses::cpu.data 42629968 # system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001327 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001327 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001611 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001611 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324266 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.324266 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17174.836277 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17174.836277 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.538194 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.538194 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45228.924133 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45228.924133 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34998.159443 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34998.159443 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324339 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.324339 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003372 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003372 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004301 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004301 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15735.411104 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15735.411104 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59843.205770 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59843.205770 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48579.512725 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48579.512725 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37975.787636 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37975.787636 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,14 +302,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128193 # number of writebacks -system.cpu.dcache.writebacks::total 128193 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1126 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1126 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1126 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1126 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1126 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1126 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 128175 # number of writebacks +system.cpu.dcache.writebacks::total 128175 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7598 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7598 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7598 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7598 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7598 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7598 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses @@ -320,16 +320,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136140 system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 474518000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 474518000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5582097500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5582097500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1070376500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1070376500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6056615500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6056615500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7126992000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7126992000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 495022500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 495022500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6298106000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6298106000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1201109000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1201109000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6793128500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6793128500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7994237500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7994237500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -340,29 +340,29 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16301.978837 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16301.978837 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52153.538194 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52153.538194 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44864.468941 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44864.468941 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44488.140884 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44488.140884 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44544.256803 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44544.256803 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17006.407173 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17006.407173 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58843.205770 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58843.205770 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50344.077458 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50344.077458 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1733.673242 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1732.356647 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78126162 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4131.910408 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1733.673242 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.846520 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.846520 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356647 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.845877 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.845877 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id @@ -380,12 +380,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 413643000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 413643000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 413643000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 413643000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 413643000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 413643000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 426200500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 426200500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 426200500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 426200500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 426200500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 426200500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 78145070 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 78145070 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 78145070 # number of demand (read+write) accesses @@ -398,12 +398,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21876.613074 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21876.613074 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21876.613074 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21876.613074 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21876.613074 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21876.613074 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22540.749947 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22540.749947 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22540.749947 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22540.749947 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22540.749947 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22540.749947 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,93 +412,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 16890 # number of writebacks +system.cpu.icache.writebacks::total 16890 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 394735000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 394735000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 394735000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 394735000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 394735000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 394735000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 407292500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 407292500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 407292500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 407292500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 407292500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 407292500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20876.613074 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20876.613074 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20876.613074 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20876.613074 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20876.613074 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20876.613074 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.749947 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.749947 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 94651 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30350.483830 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 114091 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 125746 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.907313 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 95333 # number of replacements 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of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.926223 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31095 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1359 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15123 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13873 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948944 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3016794 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3016794 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 128193 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128193 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14958 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 14958 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31426 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 31426 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 14958 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 36178 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 51136 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 14958 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 36178 # number of overall hits -system.cpu.l2cache.overall_hits::total 51136 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 102280 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102280 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3950 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3950 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21540 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 21540 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3950 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 123820 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 127770 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3950 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 123820 # number of overall misses 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(read+write) hits +system.cpu.l2cache.demand_hits::total 51431 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 15265 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 36166 # number of overall hits +system.cpu.l2cache.overall_hits::total 51431 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 102281 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102281 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3643 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3643 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21551 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 21551 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3643 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 123832 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 127475 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3643 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 123832 # number of overall misses +system.cpu.l2cache.overall_misses::total 127475 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6087670500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6087670500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 217265500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 217265500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1284434000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1284434000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 217265500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7372104500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7589370000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 217265500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7372104500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7589370000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 128175 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 128175 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 15790 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 15790 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 18908 # number of ReadCleanReq accesses(hits+misses) @@ -511,30 +517,30 @@ system.cpu.l2cache.demand_accesses::total 178906 # n system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955602 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955602 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.208906 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.208906 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.406676 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.406676 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.208906 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.773885 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.714174 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.208906 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.714174 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52519.099531 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52519.099531 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52651.518987 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52651.518987 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52606.012071 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52606.012071 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52651.518987 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52534.219028 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52537.845347 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52651.518987 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52534.219028 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52537.845347 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955611 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955611 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.192670 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.192670 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.406884 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.406884 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192670 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.773960 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.712525 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192670 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.773960 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.712525 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59519.074901 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59519.074901 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59639.171013 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59639.171013 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59599.740151 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59599.740151 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59639.171013 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59533.113412 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59536.144342 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59639.171013 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59533.113412 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59536.144342 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -543,70 +549,71 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 86115 # number of writebacks -system.cpu.l2cache.writebacks::total 86115 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1102 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1102 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3950 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3950 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21540 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21540 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3950 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 123820 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 127770 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3950 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 127770 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4348853500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4348853500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 168473500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 168473500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 917733500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 917733500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168473500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5266587000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5435060500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168473500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5266587000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5435060500 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 86150 # number of writebacks +system.cpu.l2cache.writebacks::total 86150 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 104 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 104 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102281 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3643 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3643 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21551 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21551 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3643 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123832 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 127475 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3643 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123832 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 127475 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5064860500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5064860500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 180835500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 180835500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1068924000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1068924000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180835500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6133784500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6314620000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180835500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6133784500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6314620000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955602 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955602 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.208906 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.208906 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.406676 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.208906 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.714174 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.208906 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.714174 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42519.099531 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42519.099531 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42651.518987 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42651.518987 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42606.012071 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42606.012071 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42651.518987 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42534.219028 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42537.845347 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42651.518987 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42534.219028 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42537.845347 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955611 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955611 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.192670 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.406884 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.406884 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773960 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.712525 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773960 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.712525 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49519.074901 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49519.074901 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49639.171013 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49639.171013 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49599.740151 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49599.740151 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3112 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3082 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3119 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3089 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 214308 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 49439 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 214325 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 15790 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 34314 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution @@ -614,51 +621,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53606 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473302 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 526908 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18444224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 19654336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 94651 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 446349 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.023656 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.152418 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2220672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18443072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 20663744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 95333 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 274239 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.025051 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.156979 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 435820 97.64% 97.64% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 10499 2.35% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 267399 97.51% 97.51% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 6810 2.48% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 446349 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 304042000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 274239 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 320914000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 25490 # Transaction distribution -system.membus.trans_dist::Writeback 86115 # Transaction distribution -system.membus.trans_dist::CleanEvict 6526 # Transaction distribution -system.membus.trans_dist::ReadExReq 102280 # Transaction distribution -system.membus.trans_dist::ReadExResp 102280 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 25490 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 348181 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 348181 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13688640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13688640 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 25194 # Transaction distribution +system.membus.trans_dist::WritebackDirty 86150 # Transaction distribution +system.membus.trans_dist::CleanEvict 6168 # Transaction distribution +system.membus.trans_dist::ReadExReq 102281 # Transaction distribution +system.membus.trans_dist::ReadExResp 102281 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 25194 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 347268 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 347268 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13672000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13672000 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 220592 # Request fanout histogram +system.membus.snoop_fanout::samples 219817 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 220592 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 219817 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 220592 # Request fanout histogram -system.membus.reqLayer0.occupancy 568748288 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 219817 # Request fanout histogram +system.membus.reqLayer0.occupancy 568080092 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 641607492 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 637375000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 9438e6b22..db3a55da9 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202233 # Number of seconds simulated -sim_ticks 202232960500 # Number of ticks simulated -final_tick 202232960500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.203116 # Number of seconds simulated +sim_ticks 203115876500 # Number of ticks simulated +final_tick 203115876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1135828 # Simulator instruction rate (inst/s) -host_op_rate 1150535 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1709104516 # Simulator tick rate (ticks/s) -host_mem_usage 304720 # Number of bytes of host memory used -host_seconds 118.33 # Real time elapsed on the host +host_inst_rate 1134042 # Simulator instruction rate (inst/s) +host_op_rate 1148726 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1713866597 # Simulator tick rate (ticks/s) +host_mem_usage 305064 # Number of bytes of host memory used +host_seconds 118.51 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 575680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7827008 # Number of bytes read from this memory -system.physmem.bytes_read::total 8402688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 575680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 575680 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5453120 # Number of bytes written to this memory -system.physmem.bytes_written::total 5453120 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8995 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 122297 # Number of read requests responded to by this memory -system.physmem.num_reads::total 131292 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 85205 # Number of write requests responded to by this memory -system.physmem.num_writes::total 85205 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2846618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 38702929 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 41549548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2846618 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2846618 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 26964546 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 26964546 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 26964546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2846618 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 38702929 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 68514094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 525056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7828288 # Number of bytes read from this memory +system.physmem.bytes_read::total 8353344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 525056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 525056 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5457280 # Number of bytes written to this memory +system.physmem.bytes_written::total 5457280 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8204 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 122317 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130521 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 85270 # Number of write requests responded to by this memory +system.physmem.num_writes::total 85270 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2585007 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38540995 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 41126002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2585007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2585007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 26867816 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26867816 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 26867816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2585007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 38540995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 67993818 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 404465921 # number of cpu cycles simulated +system.cpu.numCycles 406231753 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 134398962 # Number of instructions committed @@ -57,7 +57,7 @@ system.cpu.num_mem_refs 58160248 # nu system.cpu.num_load_insts 37275867 # Number of load instructions system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 404465920.998000 # Number of busy cycles +system.cpu.num_busy_cycles 406231752.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 12719095 # Number of branches fetched @@ -97,18 +97,18 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 136293798 # Class of executed instruction system.cpu.dcache.tags.replacements 146582 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.647896 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4087.268920 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 769043500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.647896 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 822359500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.268920 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997868 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997868 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 530 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3529 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3586 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses @@ -132,16 +132,16 @@ system.cpu.dcache.demand_misses::cpu.data 150663 # n system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses system.cpu.dcache.overall_misses::total 150663 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475184000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1475184000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5620115500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5620115500 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7095299500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7095299500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7095299500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7095299500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1623254000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1623254000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6329554500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6329554500 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 441000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 441000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7952808500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7952808500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7952808500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7952808500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) @@ -162,16 +162,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32422.338953 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32422.338953 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53441.439086 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53441.439086 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47093.841886 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47093.841886 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47093.841886 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47093.841886 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35676.696191 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35676.696191 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60187.464341 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60187.464341 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 29400 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 29400 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52785.411813 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52785.411813 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52785.411813 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52785.411813 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -180,8 +180,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 123896 # number of writebacks -system.cpu.dcache.writebacks::total 123896 # number of writebacks +system.cpu.dcache.writebacks::writebacks 123865 # number of writebacks +system.cpu.dcache.writebacks::total 123865 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses @@ -192,16 +192,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 150663 system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1429685000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1429685000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5514951500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5514951500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 390000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 390000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6944636500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6944636500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6944636500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6944636500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1577755000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1577755000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6224390500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6224390500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 426000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 426000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7802145500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7802145500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7802145500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7802145500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses @@ -212,29 +212,29 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31422.338953 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31422.338953 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52441.439086 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52441.439086 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 26000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 26000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46093.841886 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 46093.841886 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46093.841886 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 46093.841886 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34676.696191 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34676.696191 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.464341 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.464341 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28400 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28400 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.411813 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.411813 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.411813 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.411813 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 184976 # number of replacements -system.cpu.icache.tags.tagsinuse 2004.814767 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 2004.181257 # Cycle average of tags in use system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 143963003500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 2004.814767 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.978913 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.978913 # Average percentage of cache occupancy +system.cpu.icache.tags.warmup_cycle 144582729500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 2004.181257 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.978604 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.978604 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id @@ -253,12 +253,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2809868000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2809868000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2809868000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2809868000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2809868000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2809868000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2835239000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2835239000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2835239000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2835239000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2835239000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2835239000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses @@ -271,12 +271,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15024.103858 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15024.103858 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15024.103858 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15024.103858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15024.103858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15024.103858 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15159.760245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15159.760245 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15159.760245 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15159.760245 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15159.760245 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15159.760245 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -285,93 +285,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 184976 # number of writebacks +system.cpu.icache.writebacks::total 184976 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2622844000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2622844000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2622844000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2622844000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2622844000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2622844000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2648215000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2648215000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2648215000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2648215000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2648215000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2648215000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14024.103858 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14024.103858 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14024.103858 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14024.103858 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14024.103858 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14024.103858 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14159.760245 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14159.760245 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 98298 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30848.444719 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 433066 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129294 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.349467 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 99021 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30843.659201 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 433831 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 130064 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.335519 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 25953.828709 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3594.810369 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1299.805642 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.792048 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.109705 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.039667 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.941420 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 30996 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 531 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12218 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17557 # Occupied blocks per task id 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per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 557 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.947357 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 5588795 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 5588795 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 123865 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 123865 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 184923 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 184923 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 3915 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3915 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 178820 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 178820 # number of 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+system.cpu.l2cache.ReadCleanReq_miss_latency::total 488461500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1252774500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1252774500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 488461500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7278665000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7767126500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 488461500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7278665000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7767126500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 123865 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 123865 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 184923 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 184923 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187024 # number of ReadCleanReq accesses(hits+misses) @@ -384,30 +390,30 @@ system.cpu.l2cache.demand_accesses::total 337702 # n system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 150678 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 337702 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962730 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.962730 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.048095 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.048095 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.462384 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.462384 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.048095 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.811645 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.388781 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.048095 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.811645 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.388781 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52503.115772 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52503.115772 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52539.688716 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52539.688716 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52504.087841 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52504.087841 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52539.688716 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52503.282991 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52505.777199 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52539.688716 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52503.282991 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52505.777199 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962778 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.962778 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043866 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043866 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.462713 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.462713 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043866 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.811777 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.386498 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043866 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.811777 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.386498 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59506.739809 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59506.739809 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59539.431984 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59539.431984 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.747399 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.747399 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59506.568997 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59508.634626 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59506.568997 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59508.634626 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -416,70 +422,71 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 85205 # number of writebacks -system.cpu.l2cache.writebacks::total 85205 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1630 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1630 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101259 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101259 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8995 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8995 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21038 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21038 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 8995 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 122297 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 131292 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 8995 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 122297 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 131292 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4303823000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4303823000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 382644500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 382644500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 894201000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 894201000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 382644500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5198024000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5580668500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 382644500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5198024000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5580668500 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 85270 # number of writebacks +system.cpu.l2cache.writebacks::total 85270 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101264 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101264 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8204 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8204 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21053 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21053 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8204 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 122317 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 130521 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8204 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 122317 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 130521 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5013250500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5013250500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 406421500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 406421500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1042244500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1042244500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 406421500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6055495000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6461916500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 406421500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6055495000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6461916500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962730 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962730 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.048095 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.048095 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.462384 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.462384 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.048095 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811645 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.388781 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.048095 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811645 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.388781 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42503.115772 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42503.115772 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42539.688716 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42539.688716 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42504.087841 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42504.087841 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42539.688716 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42503.282991 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42505.777199 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42539.688716 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42503.282991 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42505.777199 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962778 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962778 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043866 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.462713 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.462713 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811777 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.386498 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811777 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.386498 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49506.739809 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49506.739809 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49539.431984 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49539.431984 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.747399 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.747399 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49506.568997 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.634626 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.568997 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.634626 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 669260 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 331558 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3540 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3540 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3547 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 209101 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 220689 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 184923 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 36455 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution @@ -487,51 +494,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 45499 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558971 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447925 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 1006896 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11969536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17572736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 29542272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 98298 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 767558 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004784 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.069001 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23804608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 41375360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 99021 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 436723 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008273 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.090579 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 763886 99.52% 99.52% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3672 0.48% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 433110 99.17% 99.17% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3613 0.83% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 767558 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 458526000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 436723 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 643471000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 226017000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 30033 # Transaction distribution -system.membus.trans_dist::Writeback 85205 # Transaction distribution -system.membus.trans_dist::CleanEvict 11182 # Transaction distribution -system.membus.trans_dist::ReadExReq 101259 # Transaction distribution -system.membus.trans_dist::ReadExResp 101259 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30033 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 358971 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 358971 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13855808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13855808 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 29257 # Transaction distribution +system.membus.trans_dist::WritebackDirty 85270 # Transaction distribution +system.membus.trans_dist::CleanEvict 10300 # Transaction distribution +system.membus.trans_dist::ReadExReq 101264 # Transaction distribution +system.membus.trans_dist::ReadExResp 101264 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 29257 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 356612 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 356612 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13810624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13810624 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 227790 # Request fanout histogram +system.membus.snoop_fanout::samples 226091 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 227790 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 226091 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 227790 # Request fanout histogram -system.membus.reqLayer0.occupancy 569073488 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 226091 # Request fanout histogram +system.membus.reqLayer0.occupancy 568572500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 656842488 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 652605000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt index 4b598b938..f452fe4e6 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000043 # Number of seconds simulated -sim_ticks 42571 # Number of ticks simulated -final_tick 42571 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000042 # Number of seconds simulated +sim_ticks 41751 # Number of ticks simulated +final_tick 41751 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 494113 # Simulator tick rate (ticks/s) -host_mem_usage 400400 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 638805 # Simulator tick rate (ticks/s) +host_mem_usage 452164 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 55744 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 55744 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 49920 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 49920 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 871 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 871 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 780 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 780 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 1309436001 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 1309436001 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1172629255 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1172629255 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 2482065256 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 2482065256 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 871 # Number of read requests accepted -system.mem_ctrls.writeReqs 780 # Number of write requests accepted -system.mem_ctrls.readBursts 871 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 780 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 47744 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 8000 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 42368 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 55744 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 49920 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 100 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 55552 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 55552 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 49728 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 49728 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 868 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 868 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 777 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 777 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 1330554957 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1330554957 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1191061292 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1191061292 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 2521616249 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2521616249 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 868 # Number of read requests accepted +system.mem_ctrls.writeReqs 777 # Number of write requests accepted +system.mem_ctrls.readBursts 868 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 777 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 45760 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 9792 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 40448 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 55552 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 49728 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 123 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 231 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 226 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 227 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 62 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 232 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 213 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 219 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 51 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts @@ -51,10 +51,10 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 200 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 201 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 204 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 57 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 196 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 191 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 198 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 47 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts @@ -69,23 +69,23 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 42423 # Total gap between requests +system.mem_ctrls.totGap 41665 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 871 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 868 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 780 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 448 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 298 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 777 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 439 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 276 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -131,24 +131,24 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 26 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 52 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 24 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 51 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 39 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -180,73 +180,71 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 95 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 926.989474 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 854.614613 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 240.168004 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 1 1.05% 1.05% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 4 4.21% 5.26% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 3 3.16% 8.42% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 1 1.05% 9.47% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 2 2.11% 11.58% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 4 4.21% 15.79% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 5 5.26% 21.05% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 75 78.95% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 95 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 41 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 18.146341 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 17.876894 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.581627 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 4 9.76% 9.76% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 21 51.22% 60.98% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 7 17.07% 78.05% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 3 7.32% 85.37% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::22-23 5 12.20% 97.56% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 2.44% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 41 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 41 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.146341 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.139853 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.477545 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 37 90.24% 90.24% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 2 4.88% 95.12% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 2 4.88% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 41 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 9366 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 23540 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3730 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 12.55 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 89 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 943.460674 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 892.281841 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 207.277759 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 1 1.12% 1.12% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 1 1.12% 2.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 4 4.49% 6.74% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 3 3.37% 10.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 4 4.49% 14.61% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 6 6.74% 21.35% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 70 78.65% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 89 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 39 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 18.128205 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 17.885323 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 3.442608 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 4 10.26% 10.26% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 17 43.59% 53.85% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 12 30.77% 84.62% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 2 5.13% 89.74% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::22-23 3 7.69% 97.44% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::34-35 1 2.56% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 39 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 39 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.205128 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.194457 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.614709 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 35 89.74% 89.74% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 4 10.26% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 39 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 8953 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 22538 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3575 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 12.52 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 31.55 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 1121.51 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 995.23 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 1309.44 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1172.63 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 31.52 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 1096.02 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 968.79 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1330.55 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1191.06 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 16.54 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 8.76 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 7.78 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.67 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.64 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 654 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 656 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 87.67 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 96.47 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 25.70 # Average gap between requests -system.mem_ctrls.pageHitRate 91.87 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 672840 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 373800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 8523840 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 6189696 # Energy for write commands per rank (pJ) +system.mem_ctrls.busUtil 16.13 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 8.56 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 7.57 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.65 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.68 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 630 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 624 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 88.11 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 95.41 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 25.33 # Average gap between requests +system.mem_ctrls.pageHitRate 91.60 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 642600 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 357000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 8311680 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 6034176 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 26706780 # Energy for active background per rank (pJ) +system.mem_ctrls_0.actBackEnergy 26710200 # Energy for active background per rank (pJ) system.mem_ctrls_0.preBackEnergy 87000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 45096756 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 1150.721000 # Core power per rank (mW) +system.mem_ctrls_0.totalEnergy 44685456 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 1140.080520 # Core power per rank (mW) system.mem_ctrls_0.memoryStateTime::IDLE 19 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 37885 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 37890 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) @@ -263,50 +261,50 @@ system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.delayHist::bucket_size 8 # delay histogram for all message -system.ruby.delayHist::max_bucket 79 # delay histogram for all message -system.ruby.delayHist::samples 6521 # delay histogram for all message -system.ruby.delayHist::mean 2.641926 # delay histogram for all message -system.ruby.delayHist::stdev 5.394341 # delay histogram for all message -system.ruby.delayHist | 5055 77.52% 77.52% | 1100 16.87% 94.39% | 315 4.83% 99.22% | 46 0.71% 99.92% | 4 0.06% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 6521 # delay histogram for all message +system.ruby.delayHist::bucket_size 4 # delay histogram for all message +system.ruby.delayHist::max_bucket 39 # delay histogram for all message +system.ruby.delayHist::samples 6487 # delay histogram for all message +system.ruby.delayHist::mean 2.607369 # delay histogram for all message +system.ruby.delayHist::stdev 5.331776 # delay histogram for all message +system.ruby.delayHist | 4997 77.03% 77.03% | 72 1.11% 78.14% | 1050 16.19% 94.33% | 14 0.22% 94.54% | 300 4.62% 99.17% | 2 0.03% 99.20% | 2 0.03% 99.23% | 47 0.72% 99.95% | 0 0.00% 99.95% | 3 0.05% 100.00% # delay histogram for all message +system.ruby.delayHist::total 6487 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 999 -system.ruby.outstanding_req_hist::mean 15.687688 -system.ruby.outstanding_req_hist::gmean 15.581968 -system.ruby.outstanding_req_hist::stdev 1.209746 -system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 2 0.20% 0.70% | 4 0.40% 1.10% | 2 0.20% 1.30% | 5 0.50% 1.80% | 167 16.72% 18.52% | 814 81.48% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 999 +system.ruby.outstanding_req_hist::samples 988 +system.ruby.outstanding_req_hist::mean 15.694332 +system.ruby.outstanding_req_hist::gmean 15.587555 +system.ruby.outstanding_req_hist::stdev 1.214439 +system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.51% | 2 0.20% 0.71% | 4 0.40% 1.11% | 2 0.20% 1.32% | 5 0.51% 1.82% | 157 15.89% 17.71% | 813 82.29% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 988 system.ruby.latency_hist::bucket_size 128 system.ruby.latency_hist::max_bucket 1279 -system.ruby.latency_hist::samples 985 -system.ruby.latency_hist::mean 675.252792 -system.ruby.latency_hist::gmean 398.347794 -system.ruby.latency_hist::stdev 287.376789 -system.ruby.latency_hist | 120 12.18% 12.18% | 34 3.45% 15.63% | 4 0.41% 16.04% | 4 0.41% 16.45% | 24 2.44% 18.88% | 308 31.27% 50.15% | 411 41.73% 91.88% | 38 3.86% 95.74% | 28 2.84% 98.58% | 14 1.42% 100.00% -system.ruby.latency_hist::total 985 +system.ruby.latency_hist::samples 973 +system.ruby.latency_hist::mean 670.474820 +system.ruby.latency_hist::gmean 404.512965 +system.ruby.latency_hist::stdev 282.511489 +system.ruby.latency_hist | 123 12.64% 12.64% | 25 2.57% 15.21% | 6 0.62% 15.83% | 4 0.41% 16.24% | 32 3.29% 19.53% | 325 33.40% 52.93% | 378 38.85% 91.78% | 43 4.42% 96.20% | 29 2.98% 99.18% | 8 0.82% 100.00% +system.ruby.latency_hist::total 973 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 73 +system.ruby.hit_latency_hist::samples 67 system.ruby.hit_latency_hist::mean 1 system.ruby.hit_latency_hist::gmean 1 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 73 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 73 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 67 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 67 system.ruby.miss_latency_hist::bucket_size 128 system.ruby.miss_latency_hist::max_bucket 1279 -system.ruby.miss_latency_hist::samples 912 -system.ruby.miss_latency_hist::mean 729.222588 -system.ruby.miss_latency_hist::gmean 643.276159 -system.ruby.miss_latency_hist::stdev 223.288971 -system.ruby.miss_latency_hist | 47 5.15% 5.15% | 34 3.73% 8.88% | 4 0.44% 9.32% | 4 0.44% 9.76% | 24 2.63% 12.39% | 308 33.77% 46.16% | 411 45.07% 91.23% | 38 4.17% 95.39% | 28 3.07% 98.46% | 14 1.54% 100.00% -system.ruby.miss_latency_hist::total 912 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 71 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 862 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 933 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 2 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 52 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 54 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 906 +system.ruby.miss_latency_hist::mean 719.983444 +system.ruby.miss_latency_hist::gmean 630.548999 +system.ruby.miss_latency_hist::stdev 223.799725 +system.ruby.miss_latency_hist | 56 6.18% 6.18% | 25 2.76% 8.94% | 6 0.66% 9.60% | 4 0.44% 10.04% | 32 3.53% 13.58% | 325 35.87% 49.45% | 378 41.72% 91.17% | 43 4.75% 95.92% | 29 3.20% 99.12% | 8 0.88% 100.00% +system.ruby.miss_latency_hist::total 906 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 66 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 852 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 918 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 1 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 56 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 57 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -316,348 +314,342 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 6 # Number of times a store aliased with a pending load -system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 76 # Number of times a store aliased with a pending store +system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 1 # Number of times a store aliased with a pending load +system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 88 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 7 # Number of times a load aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 2 # Number of times a load aliased with a pending load -system.ruby.l2_cntrl0.L2cache.demand_hits 41 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 872 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 913 # Number of cache demand accesses +system.ruby.l2_cntrl0.L2cache.demand_hits 38 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 868 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 906 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 11.614127 -system.ruby.network.routers0.msg_count.Control::0 914 -system.ruby.network.routers0.msg_count.Request_Control::2 250 -system.ruby.network.routers0.msg_count.Response_Data::1 911 -system.ruby.network.routers0.msg_count.Response_Control::1 848 -system.ruby.network.routers0.msg_count.Response_Control::2 859 -system.ruby.network.routers0.msg_count.Writeback_Data::0 761 -system.ruby.network.routers0.msg_count.Writeback_Data::1 202 -system.ruby.network.routers0.msg_count.Writeback_Control::0 40 -system.ruby.network.routers0.msg_bytes.Control::0 7312 -system.ruby.network.routers0.msg_bytes.Request_Control::2 2000 -system.ruby.network.routers0.msg_bytes.Response_Data::1 65592 -system.ruby.network.routers0.msg_bytes.Response_Control::1 6784 -system.ruby.network.routers0.msg_bytes.Response_Control::2 6872 -system.ruby.network.routers0.msg_bytes.Writeback_Data::0 54792 -system.ruby.network.routers0.msg_bytes.Writeback_Data::1 14544 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 320 -system.ruby.network.routers1.percent_links_utilized 21.410115 -system.ruby.network.routers1.msg_count.Control::0 1785 -system.ruby.network.routers1.msg_count.Request_Control::2 250 -system.ruby.network.routers1.msg_count.Response_Data::1 2562 -system.ruby.network.routers1.msg_count.Response_Control::1 1803 -system.ruby.network.routers1.msg_count.Response_Control::2 859 -system.ruby.network.routers1.msg_count.Writeback_Data::0 761 -system.ruby.network.routers1.msg_count.Writeback_Data::1 202 -system.ruby.network.routers1.msg_count.Writeback_Control::0 40 -system.ruby.network.routers1.msg_bytes.Control::0 14280 -system.ruby.network.routers1.msg_bytes.Request_Control::2 2000 -system.ruby.network.routers1.msg_bytes.Response_Data::1 184464 -system.ruby.network.routers1.msg_bytes.Response_Control::1 14424 -system.ruby.network.routers1.msg_bytes.Response_Control::2 6872 -system.ruby.network.routers1.msg_bytes.Writeback_Data::0 54792 -system.ruby.network.routers1.msg_bytes.Writeback_Data::1 14544 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 320 -system.ruby.network.routers2.percent_links_utilized 9.797750 -system.ruby.network.routers2.msg_count.Control::0 871 -system.ruby.network.routers2.msg_count.Response_Data::1 1651 -system.ruby.network.routers2.msg_count.Response_Control::1 954 -system.ruby.network.routers2.msg_bytes.Control::0 6968 -system.ruby.network.routers2.msg_bytes.Response_Data::1 118872 -system.ruby.network.routers2.msg_bytes.Response_Control::1 7632 -system.ruby.network.routers3.percent_links_utilized 14.274976 -system.ruby.network.routers3.msg_count.Control::0 1785 -system.ruby.network.routers3.msg_count.Request_Control::2 250 -system.ruby.network.routers3.msg_count.Response_Data::1 2562 -system.ruby.network.routers3.msg_count.Response_Control::1 1803 -system.ruby.network.routers3.msg_count.Response_Control::2 859 -system.ruby.network.routers3.msg_count.Writeback_Data::0 761 -system.ruby.network.routers3.msg_count.Writeback_Data::1 202 -system.ruby.network.routers3.msg_count.Writeback_Control::0 40 -system.ruby.network.routers3.msg_bytes.Control::0 14280 -system.ruby.network.routers3.msg_bytes.Request_Control::2 2000 -system.ruby.network.routers3.msg_bytes.Response_Data::1 184464 -system.ruby.network.routers3.msg_bytes.Response_Control::1 14424 -system.ruby.network.routers3.msg_bytes.Response_Control::2 6872 -system.ruby.network.routers3.msg_bytes.Writeback_Data::0 54792 -system.ruby.network.routers3.msg_bytes.Writeback_Data::1 14544 -system.ruby.network.routers3.msg_bytes.Writeback_Control::0 320 -system.ruby.network.msg_count.Control 5355 -system.ruby.network.msg_count.Request_Control 750 -system.ruby.network.msg_count.Response_Data 7686 -system.ruby.network.msg_count.Response_Control 7985 -system.ruby.network.msg_count.Writeback_Data 2889 -system.ruby.network.msg_count.Writeback_Control 120 -system.ruby.network.msg_byte.Control 42840 -system.ruby.network.msg_byte.Request_Control 6000 -system.ruby.network.msg_byte.Response_Data 553392 -system.ruby.network.msg_byte.Response_Control 63880 -system.ruby.network.msg_byte.Writeback_Data 208008 -system.ruby.network.msg_byte.Writeback_Control 960 -system.ruby.network.routers0.throttle0.link_utilization 10.863029 -system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 250 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 911 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 800 -system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 2000 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 65592 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 6400 -system.ruby.network.routers0.throttle1.link_utilization 12.365225 -system.ruby.network.routers0.throttle1.msg_count.Control::0 914 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 48 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 859 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 761 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 202 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 40 -system.ruby.network.routers0.throttle1.msg_bytes.Control::0 7312 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 384 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6872 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 54792 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 14544 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 320 -system.ruby.network.routers1.throttle0.link_utilization 22.584623 -system.ruby.network.routers1.throttle0.msg_count.Control::0 913 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 871 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 915 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 859 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 761 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 202 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 40 -system.ruby.network.routers1.throttle0.msg_bytes.Control::0 7304 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 62712 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 7320 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6872 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 54792 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 14544 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 320 -system.ruby.network.routers1.throttle1.link_utilization 20.235606 -system.ruby.network.routers1.throttle1.msg_count.Control::0 872 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 250 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1691 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 888 -system.ruby.network.routers1.throttle1.msg_bytes.Control::0 6976 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 2000 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 121752 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 7104 -system.ruby.network.routers2.throttle0.link_utilization 9.370229 -system.ruby.network.routers2.throttle0.msg_count.Control::0 871 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 780 +system.ruby.network.routers0.percent_links_utilized 11.787742 +system.ruby.network.routers0.msg_count.Control::0 908 +system.ruby.network.routers0.msg_count.Request_Control::2 264 +system.ruby.network.routers0.msg_count.Response_Data::1 906 +system.ruby.network.routers0.msg_count.Response_Control::1 831 +system.ruby.network.routers0.msg_count.Response_Control::2 850 +system.ruby.network.routers0.msg_count.Writeback_Data::0 745 +system.ruby.network.routers0.msg_count.Writeback_Data::1 215 +system.ruby.network.routers0.msg_count.Writeback_Control::0 39 +system.ruby.network.routers0.msg_bytes.Control::0 7264 +system.ruby.network.routers0.msg_bytes.Request_Control::2 2112 +system.ruby.network.routers0.msg_bytes.Response_Data::1 65232 +system.ruby.network.routers0.msg_bytes.Response_Control::1 6648 +system.ruby.network.routers0.msg_bytes.Response_Control::2 6800 +system.ruby.network.routers0.msg_bytes.Writeback_Data::0 53640 +system.ruby.network.routers0.msg_bytes.Writeback_Data::1 15480 +system.ruby.network.routers0.msg_bytes.Writeback_Control::0 312 +system.ruby.network.routers1.percent_links_utilized 21.738401 +system.ruby.network.routers1.msg_count.Control::0 1774 +system.ruby.network.routers1.msg_count.Request_Control::2 264 +system.ruby.network.routers1.msg_count.Response_Data::1 2551 +system.ruby.network.routers1.msg_count.Response_Control::1 1782 +system.ruby.network.routers1.msg_count.Response_Control::2 850 +system.ruby.network.routers1.msg_count.Writeback_Data::0 745 +system.ruby.network.routers1.msg_count.Writeback_Data::1 215 +system.ruby.network.routers1.msg_count.Writeback_Control::0 38 +system.ruby.network.routers1.msg_bytes.Control::0 14192 +system.ruby.network.routers1.msg_bytes.Request_Control::2 2112 +system.ruby.network.routers1.msg_bytes.Response_Data::1 183672 +system.ruby.network.routers1.msg_bytes.Response_Control::1 14256 +system.ruby.network.routers1.msg_bytes.Response_Control::2 6800 +system.ruby.network.routers1.msg_bytes.Writeback_Data::0 53640 +system.ruby.network.routers1.msg_bytes.Writeback_Data::1 15480 +system.ruby.network.routers1.msg_bytes.Writeback_Control::0 304 +system.ruby.network.routers2.percent_links_utilized 9.954253 +system.ruby.network.routers2.msg_count.Control::0 868 +system.ruby.network.routers2.msg_count.Response_Data::1 1645 +system.ruby.network.routers2.msg_count.Response_Control::1 951 +system.ruby.network.routers2.msg_bytes.Control::0 6944 +system.ruby.network.routers2.msg_bytes.Response_Data::1 118440 +system.ruby.network.routers2.msg_bytes.Response_Control::1 7608 +system.ruby.network.routers3.percent_links_utilized 14.493864 +system.ruby.network.routers3.msg_count.Control::0 1775 +system.ruby.network.routers3.msg_count.Request_Control::2 264 +system.ruby.network.routers3.msg_count.Response_Data::1 2551 +system.ruby.network.routers3.msg_count.Response_Control::1 1782 +system.ruby.network.routers3.msg_count.Response_Control::2 850 +system.ruby.network.routers3.msg_count.Writeback_Data::0 745 +system.ruby.network.routers3.msg_count.Writeback_Data::1 215 +system.ruby.network.routers3.msg_count.Writeback_Control::0 38 +system.ruby.network.routers3.msg_bytes.Control::0 14200 +system.ruby.network.routers3.msg_bytes.Request_Control::2 2112 +system.ruby.network.routers3.msg_bytes.Response_Data::1 183672 +system.ruby.network.routers3.msg_bytes.Response_Control::1 14256 +system.ruby.network.routers3.msg_bytes.Response_Control::2 6800 +system.ruby.network.routers3.msg_bytes.Writeback_Data::0 53640 +system.ruby.network.routers3.msg_bytes.Writeback_Data::1 15480 +system.ruby.network.routers3.msg_bytes.Writeback_Control::0 304 +system.ruby.network.msg_count.Control 5325 +system.ruby.network.msg_count.Request_Control 792 +system.ruby.network.msg_count.Response_Data 7653 +system.ruby.network.msg_count.Response_Control 7896 +system.ruby.network.msg_count.Writeback_Data 2880 +system.ruby.network.msg_count.Writeback_Control 115 +system.ruby.network.msg_byte.Control 42600 +system.ruby.network.msg_byte.Request_Control 6336 +system.ruby.network.msg_byte.Response_Data 551016 +system.ruby.network.msg_byte.Response_Control 63168 +system.ruby.network.msg_byte.Writeback_Data 207360 +system.ruby.network.msg_byte.Writeback_Control 920 +system.ruby.network.routers0.throttle0.link_utilization 11.017700 +system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 264 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 906 +system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 782 +system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 2112 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 65232 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 6256 +system.ruby.network.routers0.throttle1.link_utilization 12.557783 +system.ruby.network.routers0.throttle1.msg_count.Control::0 908 +system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 49 +system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 850 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 745 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 215 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 39 +system.ruby.network.routers0.throttle1.msg_bytes.Control::0 7264 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 392 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6800 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 53640 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 15480 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 312 +system.ruby.network.routers1.throttle0.link_utilization 22.940768 +system.ruby.network.routers1.throttle0.msg_count.Control::0 906 +system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 868 +system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 913 +system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 850 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 745 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 215 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 38 +system.ruby.network.routers1.throttle0.msg_bytes.Control::0 7248 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 62496 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 7304 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6800 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 53640 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 15480 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 304 +system.ruby.network.routers1.throttle1.link_utilization 20.536035 +system.ruby.network.routers1.throttle1.msg_count.Control::0 868 +system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 264 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1683 +system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 869 +system.ruby.network.routers1.throttle1.msg_bytes.Control::0 6944 +system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 2112 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 121176 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 6952 +system.ruby.network.routers2.throttle0.link_utilization 9.518335 +system.ruby.network.routers2.throttle0.msg_count.Control::0 868 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 777 system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 87 -system.ruby.network.routers2.throttle0.msg_bytes.Control::0 6968 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 56160 +system.ruby.network.routers2.throttle0.msg_bytes.Control::0 6944 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 55944 system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 696 -system.ruby.network.routers2.throttle1.link_utilization 10.225271 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 871 -system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 867 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 62712 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 6936 -system.ruby.network.routers3.throttle0.link_utilization 10.864203 -system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 250 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 911 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 801 -system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 2000 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 65592 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 6408 -system.ruby.network.routers3.throttle1.link_utilization 22.589321 -system.ruby.network.routers3.throttle1.msg_count.Control::0 913 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 871 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 915 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 859 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 761 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 202 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 40 -system.ruby.network.routers3.throttle1.msg_bytes.Control::0 7304 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 62712 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 7320 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6872 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 54792 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 14544 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 320 -system.ruby.network.routers3.throttle2.link_utilization 9.371403 -system.ruby.network.routers3.throttle2.msg_count.Control::0 872 -system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 780 +system.ruby.network.routers2.throttle1.link_utilization 10.390170 +system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 868 +system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 864 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 62496 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 6912 +system.ruby.network.routers3.throttle0.link_utilization 11.017700 +system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 264 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 906 +system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 782 +system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 2112 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 65232 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 6256 +system.ruby.network.routers3.throttle1.link_utilization 22.945558 +system.ruby.network.routers3.throttle1.msg_count.Control::0 907 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 868 +system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 913 +system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 850 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 745 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 215 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 38 +system.ruby.network.routers3.throttle1.msg_bytes.Control::0 7256 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 62496 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 7304 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6800 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 53640 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 15480 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 304 +system.ruby.network.routers3.throttle2.link_utilization 9.518335 +system.ruby.network.routers3.throttle2.msg_count.Control::0 868 +system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 777 system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 87 -system.ruby.network.routers3.throttle2.msg_bytes.Control::0 6976 -system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 56160 +system.ruby.network.routers3.throttle2.msg_bytes.Control::0 6944 +system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 55944 system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 696 -system.ruby.delayVCHist.vnet_0::bucket_size 8 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::max_bucket 79 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 2572 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 5.637636 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 7.136996 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 1408 54.74% 54.74% | 798 31.03% 85.77% | 315 12.25% 98.02% | 46 1.79% 99.81% | 4 0.16% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 2572 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 2539 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 5.571485 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 7.083143 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 1391 54.79% 54.79% | 17 0.67% 55.45% | 768 30.25% 85.70% | 9 0.35% 86.06% | 300 11.82% 97.87% | 2 0.08% 97.95% | 2 0.08% 98.03% | 47 1.85% 99.88% | 0 0.00% 99.88% | 3 0.12% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 2539 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 3699 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.736415 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 2.355735 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 3354 90.67% 90.67% | 15 0.41% 91.08% | 8 0.22% 91.29% | 20 0.54% 91.84% | 242 6.54% 98.38% | 57 1.54% 99.92% | 3 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 3699 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 3684 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.750271 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 2.345078 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 3317 90.04% 90.04% | 25 0.68% 90.72% | 16 0.43% 91.15% | 39 1.06% 92.21% | 232 6.30% 98.51% | 50 1.36% 99.86% | 5 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 3684 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 250 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.016000 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.178526 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 248 99.20% 99.20% | 0 0.00% 99.20% | 2 0.80% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 250 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 264 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.015152 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.173746 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 262 99.24% 99.24% | 0 0.00% 99.24% | 2 0.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 264 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 128 system.ruby.LD.latency_hist::max_bucket 1279 -system.ruby.LD.latency_hist::samples 46 -system.ruby.LD.latency_hist::mean 731.913043 -system.ruby.LD.latency_hist::gmean 507.661226 -system.ruby.LD.latency_hist::stdev 273.908162 -system.ruby.LD.latency_hist | 4 8.70% 8.70% | 1 2.17% 10.87% | 0 0.00% 10.87% | 0 0.00% 10.87% | 3 6.52% 17.39% | 12 26.09% 43.48% | 21 45.65% 89.13% | 0 0.00% 89.13% | 4 8.70% 97.83% | 1 2.17% 100.00% -system.ruby.LD.latency_hist::total 46 +system.ruby.LD.latency_hist::samples 43 +system.ruby.LD.latency_hist::mean 744.930233 +system.ruby.LD.latency_hist::gmean 498.811687 +system.ruby.LD.latency_hist::stdev 228.289227 +system.ruby.LD.latency_hist | 3 6.98% 6.98% | 0 0.00% 6.98% | 0 0.00% 6.98% | 0 0.00% 6.98% | 1 2.33% 9.30% | 15 34.88% 44.19% | 20 46.51% 90.70% | 1 2.33% 93.02% | 3 6.98% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 43 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 2 +system.ruby.LD.hit_latency_hist::samples 3 system.ruby.LD.hit_latency_hist::mean 1 system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 2 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 3 system.ruby.LD.miss_latency_hist::bucket_size 128 system.ruby.LD.miss_latency_hist::max_bucket 1279 -system.ruby.LD.miss_latency_hist::samples 44 -system.ruby.LD.miss_latency_hist::mean 765.136364 -system.ruby.LD.miss_latency_hist::gmean 673.836653 -system.ruby.LD.miss_latency_hist::stdev 229.211042 -system.ruby.LD.miss_latency_hist | 2 4.55% 4.55% | 1 2.27% 6.82% | 0 0.00% 6.82% | 0 0.00% 6.82% | 3 6.82% 13.64% | 12 27.27% 40.91% | 21 47.73% 88.64% | 0 0.00% 88.64% | 4 9.09% 97.73% | 1 2.27% 100.00% -system.ruby.LD.miss_latency_hist::total 44 +system.ruby.LD.miss_latency_hist::samples 40 +system.ruby.LD.miss_latency_hist::mean 800.725000 +system.ruby.LD.miss_latency_hist::gmean 794.843938 +system.ruby.LD.miss_latency_hist::stdev 101.785594 +system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.50% 2.50% | 15 37.50% 40.00% | 20 50.00% 90.00% | 1 2.50% 92.50% | 3 7.50% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 40 system.ruby.ST.latency_hist::bucket_size 128 system.ruby.ST.latency_hist::max_bucket 1279 -system.ruby.ST.latency_hist::samples 885 -system.ruby.ST.latency_hist::mean 706.693785 -system.ruby.ST.latency_hist::gmean 432.638212 -system.ruby.ST.latency_hist::stdev 259.501541 -system.ruby.ST.latency_hist | 89 10.06% 10.06% | 6 0.68% 10.73% | 4 0.45% 11.19% | 4 0.45% 11.64% | 21 2.37% 14.01% | 296 33.45% 47.46% | 390 44.07% 91.53% | 38 4.29% 95.82% | 24 2.71% 98.53% | 13 1.47% 100.00% -system.ruby.ST.latency_hist::total 885 +system.ruby.ST.latency_hist::samples 873 +system.ruby.ST.latency_hist::mean 703.712486 +system.ruby.ST.latency_hist::gmean 443.583948 +system.ruby.ST.latency_hist::stdev 252.870649 +system.ruby.ST.latency_hist | 83 9.51% 9.51% | 7 0.80% 10.31% | 4 0.46% 10.77% | 4 0.46% 11.23% | 31 3.55% 14.78% | 310 35.51% 50.29% | 358 41.01% 91.29% | 42 4.81% 96.11% | 26 2.98% 99.08% | 8 0.92% 100.00% +system.ruby.ST.latency_hist::total 873 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 69 +system.ruby.ST.hit_latency_hist::samples 63 system.ruby.ST.hit_latency_hist::mean 1 system.ruby.ST.hit_latency_hist::gmean 1 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 69 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 69 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 63 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 63 system.ruby.ST.miss_latency_hist::bucket_size 128 system.ruby.ST.miss_latency_hist::max_bucket 1279 -system.ruby.ST.miss_latency_hist::samples 816 -system.ruby.ST.miss_latency_hist::mean 766.366422 -system.ruby.ST.miss_latency_hist::gmean 722.823883 -system.ruby.ST.miss_latency_hist::stdev 165.272036 -system.ruby.ST.miss_latency_hist | 20 2.45% 2.45% | 6 0.74% 3.19% | 4 0.49% 3.68% | 4 0.49% 4.17% | 21 2.57% 6.74% | 296 36.27% 43.01% | 390 47.79% 90.81% | 38 4.66% 95.47% | 24 2.94% 98.41% | 13 1.59% 100.00% -system.ruby.ST.miss_latency_hist::total 816 -system.ruby.IFETCH.latency_hist::bucket_size 32 -system.ruby.IFETCH.latency_hist::max_bucket 319 -system.ruby.IFETCH.latency_hist::samples 54 -system.ruby.IFETCH.latency_hist::mean 111.703704 -system.ruby.IFETCH.latency_hist::gmean 83.715657 -system.ruby.IFETCH.latency_hist::stdev 59.263922 -system.ruby.IFETCH.latency_hist | 3 5.56% 5.56% | 10 18.52% 24.07% | 8 14.81% 38.89% | 6 11.11% 50.00% | 20 37.04% 87.04% | 1 1.85% 88.89% | 4 7.41% 96.30% | 2 3.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 54 +system.ruby.ST.miss_latency_hist::samples 810 +system.ruby.ST.miss_latency_hist::mean 758.367901 +system.ruby.ST.miss_latency_hist::gmean 712.609684 +system.ruby.ST.miss_latency_hist::stdev 165.763918 +system.ruby.ST.miss_latency_hist | 20 2.47% 2.47% | 7 0.86% 3.33% | 4 0.49% 3.83% | 4 0.49% 4.32% | 31 3.83% 8.15% | 310 38.27% 46.42% | 358 44.20% 90.62% | 42 5.19% 95.80% | 26 3.21% 99.01% | 8 0.99% 100.00% +system.ruby.ST.miss_latency_hist::total 810 +system.ruby.IFETCH.latency_hist::bucket_size 64 +system.ruby.IFETCH.latency_hist::max_bucket 639 +system.ruby.IFETCH.latency_hist::samples 57 +system.ruby.IFETCH.latency_hist::mean 105.245614 +system.ruby.IFETCH.latency_hist::gmean 84.136461 +system.ruby.IFETCH.latency_hist::stdev 62.237816 +system.ruby.IFETCH.latency_hist | 15 26.32% 26.32% | 22 38.60% 64.91% | 16 28.07% 92.98% | 2 3.51% 96.49% | 1 1.75% 98.25% | 1 1.75% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 57 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 2 +system.ruby.IFETCH.hit_latency_hist::samples 1 system.ruby.IFETCH.hit_latency_hist::mean 1 system.ruby.IFETCH.hit_latency_hist::gmean 1 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 2 -system.ruby.IFETCH.miss_latency_hist::bucket_size 32 -system.ruby.IFETCH.miss_latency_hist::max_bucket 319 -system.ruby.IFETCH.miss_latency_hist::samples 52 -system.ruby.IFETCH.miss_latency_hist::mean 115.961538 -system.ruby.IFETCH.miss_latency_hist::gmean 99.256920 -system.ruby.IFETCH.miss_latency_hist::stdev 56.132533 -system.ruby.IFETCH.miss_latency_hist | 1 1.92% 1.92% | 10 19.23% 21.15% | 8 15.38% 36.54% | 6 11.54% 48.08% | 20 38.46% 86.54% | 1 1.92% 88.46% | 4 7.69% 96.15% | 2 3.85% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 52 -system.ruby.Directory_Controller.Fetch 871 0.00% 0.00% -system.ruby.Directory_Controller.Data 780 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 871 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 780 0.00% 0.00% +system.ruby.IFETCH.hit_latency_hist::stdev nan +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 1 +system.ruby.IFETCH.miss_latency_hist::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist::samples 56 +system.ruby.IFETCH.miss_latency_hist::mean 107.107143 +system.ruby.IFETCH.miss_latency_hist::gmean 91.066566 +system.ruby.IFETCH.miss_latency_hist::stdev 61.178926 +system.ruby.IFETCH.miss_latency_hist | 14 25.00% 25.00% | 22 39.29% 64.29% | 16 28.57% 92.86% | 2 3.57% 96.43% | 1 1.79% 98.21% | 1 1.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 56 +system.ruby.Directory_Controller.Fetch 868 0.00% 0.00% +system.ruby.Directory_Controller.Data 777 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 868 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 777 0.00% 0.00% system.ruby.Directory_Controller.CleanReplacement 87 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 871 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 780 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 868 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 777 0.00% 0.00% system.ruby.Directory_Controller.M.CleanReplacement 87 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 871 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 780 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 47 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 61 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 886 0.00% 0.00% -system.ruby.L1Cache_Controller.Inv 250 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 12148 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_Exclusive 43 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_all_Acks 868 0.00% 0.00% -system.ruby.L1Cache_Controller.Ack_all 1 0.00% 0.00% -system.ruby.L1Cache_Controller.WB_Ack 799 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Load 45 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Ifetch 52 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Store 816 0.00% 0.00% -system.ruby.L1Cache_Controller.I.L1_Replacement 100 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Ifetch 2 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Store 1 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Inv 41 0.00% 0.00% -system.ruby.L1Cache_Controller.S.L1_Replacement 7 0.00% 0.00% -system.ruby.L1Cache_Controller.E.Inv 3 0.00% 0.00% -system.ruby.L1Cache_Controller.E.L1_Replacement 40 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 2 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 69 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Inv 54 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_Replacement 761 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Inv 4 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement 627 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive 43 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 868 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 777 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 43 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 65 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 875 0.00% 0.00% +system.ruby.L1Cache_Controller.Inv 264 0.00% 0.00% +system.ruby.L1Cache_Controller.L1_Replacement 12024 0.00% 0.00% +system.ruby.L1Cache_Controller.Data_Exclusive 40 0.00% 0.00% +system.ruby.L1Cache_Controller.Data_all_Acks 866 0.00% 0.00% +system.ruby.L1Cache_Controller.WB_Ack 782 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Load 40 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Ifetch 56 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Store 812 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Inv 1 0.00% 0.00% +system.ruby.L1Cache_Controller.I.L1_Replacement 112 0.00% 0.00% +system.ruby.L1Cache_Controller.S.Ifetch 1 0.00% 0.00% +system.ruby.L1Cache_Controller.S.Inv 40 0.00% 0.00% +system.ruby.L1Cache_Controller.S.L1_Replacement 9 0.00% 0.00% +system.ruby.L1Cache_Controller.E.Inv 1 0.00% 0.00% +system.ruby.L1Cache_Controller.E.L1_Replacement 39 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 3 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 63 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Inv 64 0.00% 0.00% +system.ruby.L1Cache_Controller.M.L1_Replacement 745 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Inv 7 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement 555 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive 40 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data_all_Acks 49 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement 10613 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks 815 0.00% 0.00% -system.ruby.L1Cache_Controller.SM.Ack_all 1 0.00% 0.00% -system.ruby.L1Cache_Controller.IS_I.Data_all_Acks 4 0.00% 0.00% -system.ruby.L1Cache_Controller.M_I.Ifetch 7 0.00% 0.00% -system.ruby.L1Cache_Controller.M_I.Inv 148 0.00% 0.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack 652 0.00% 0.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack 147 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GET_INSTR 52 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 45 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 815 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_UPGRADE 1 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 653 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX_old 261 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 587 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 531 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 871 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 867 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 194 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 8 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 48 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 859 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 45 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 43 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 784 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_PUTX_old 139 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 1 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 6 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_UPGRADE 1 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 45 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GET_INSTR 7 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 25 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 587 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 31 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 653 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 205 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 8 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 867 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 114 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 194 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 8 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 3 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 45 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 4 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 42 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 98 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 45 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 129 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 784 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 7 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 19 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 852 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement 10564 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks 810 0.00% 0.00% +system.ruby.L1Cache_Controller.IS_I.Data_all_Acks 7 0.00% 0.00% +system.ruby.L1Cache_Controller.M_I.Ifetch 8 0.00% 0.00% +system.ruby.L1Cache_Controller.M_I.Inv 151 0.00% 0.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack 631 0.00% 0.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack 151 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GET_INSTR 56 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 40 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 810 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 632 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX_old 267 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 574 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 530 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 868 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 864 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 203 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 12 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 49 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 850 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 48 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 40 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 780 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_PUTX_old 135 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 8 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 48 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GET_INSTR 8 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 22 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 574 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 26 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 632 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 216 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 16 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 864 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 116 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data 203 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 12 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.Ack_all 1 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 48 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 9 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 40 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 93 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 48 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 123 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 780 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 8 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 15 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 842 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt index 0b73fc8b0..184c2afec 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000053 # Number of seconds simulated -sim_ticks 52651 # Number of ticks simulated -final_tick 52651 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000054 # Number of seconds simulated +sim_ticks 53711 # Number of ticks simulated +final_tick 53711 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 248880 # Simulator tick rate (ticks/s) -host_mem_usage 445380 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_tick_rate 508906 # Simulator tick rate (ticks/s) +host_mem_usage 451636 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 53248 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 53248 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 47552 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 47552 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 832 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 832 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 743 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 743 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 1011338816 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 1011338816 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 903154736 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 903154736 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1914493552 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1914493552 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 833 # Number of read requests accepted -system.mem_ctrls.writeReqs 743 # Number of write requests accepted -system.mem_ctrls.readBursts 833 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 743 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 44416 # Total number of bytes read from DRAM +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54528 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 54528 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 48448 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 48448 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 852 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 852 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 757 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 757 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 1015211037 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1015211037 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 902012623 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 902012623 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1917223660 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1917223660 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 852 # Number of read requests accepted +system.mem_ctrls.writeReqs 757 # Number of write requests accepted +system.mem_ctrls.readBursts 852 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 757 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 45632 # Total number of bytes read from DRAM system.mem_ctrls.bytesReadWrQ 8896 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 39488 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 53312 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 47552 # Total written bytes from the system interface side +system.mem_ctrls.bytesWritten 40448 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 54528 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 48448 # Total written bytes from the system interface side system.mem_ctrls.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 97 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.mergedWrBursts 94 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 203 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 228 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 210 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 53 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 212 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 231 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 224 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 46 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts @@ -51,10 +51,10 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 174 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 209 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 187 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 47 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 190 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 201 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 199 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 42 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts @@ -69,24 +69,24 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 52632 # Total gap between requests +system.mem_ctrls.totGap 53660 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 833 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 852 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 743 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 568 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 125 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 757 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 567 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 143 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 3 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -131,26 +131,26 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 24 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 26 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 34 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 23 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 24 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 38 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 37 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 37 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 37 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 36 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 38 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 37 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 38 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 37 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 36 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 38 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 37 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 39 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::26 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 36 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 36 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 35 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 35 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 35 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 35 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 37 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 38 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 37 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 37 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 36 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 36 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -180,70 +180,73 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 91 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 905.846154 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 828.873073 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 255.986324 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 1 1.10% 1.10% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 3 3.30% 4.40% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 4 4.40% 8.79% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 2 2.20% 10.99% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 5 5.49% 16.48% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 2 2.20% 18.68% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 5 5.49% 24.18% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 69 75.82% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 91 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 35 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 19.285714 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 19.012099 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.839205 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 10 28.57% 28.57% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 15 42.86% 71.43% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 6 17.14% 88.57% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::22-23 2 5.71% 94.29% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::24-25 1 2.86% 97.14% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::38-39 1 2.86% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 35 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 35 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 17.628571 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 17.590452 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.165325 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 10 28.57% 28.57% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 2 5.71% 34.29% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 14 40.00% 74.29% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 9 25.71% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 35 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 5779 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 18965 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3470 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 8.33 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 94 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 889.191489 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 796.949082 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 278.173972 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 2 2.13% 2.13% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 4 4.26% 6.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 5 5.32% 11.70% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 3 3.19% 14.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 1 1.06% 15.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 2 2.13% 18.09% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 2 2.13% 20.21% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 5.32% 25.53% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 70 74.47% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 94 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 36 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 19.277778 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 18.954063 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 4.046947 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 3 8.33% 8.33% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 9 25.00% 33.33% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 11 30.56% 63.89% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 5 13.89% 77.78% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::22-23 6 16.67% 94.44% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::24-25 1 2.78% 97.22% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::38-39 1 2.78% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 36 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 36 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 17.555556 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 17.508645 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.297127 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 13 36.11% 36.11% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 1 2.78% 38.89% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 12 33.33% 72.22% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 9 25.00% 97.22% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 1 2.78% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 36 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 5835 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 19382 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3565 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 8.18 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 27.33 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 843.59 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 750.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 1012.55 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 903.15 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 27.18 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 849.58 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 753.07 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1015.21 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 902.01 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 12.45 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 6.59 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 5.86 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.32 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 24.38 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 607 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 610 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 87.46 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 94.43 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 33.40 # Average gap between requests -system.mem_ctrls.pageHitRate 90.82 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 627480 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 348600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 7637760 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 5681664 # Energy for write commands per rank (pJ) +system.mem_ctrls.busUtil 12.52 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 6.64 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 5.88 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.35 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 24.46 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 622 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 625 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 87.24 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 94.27 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 33.35 # Average gap between requests +system.mem_ctrls.pageHitRate 90.62 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 650160 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 361200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7700160 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 5816448 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) system.mem_ctrls_0.actBackEnergy 32013252 # Energy for active background per rank (pJ) system.mem_ctrls_0.preBackEnergy 103800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 49463916 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 1052.961427 # Core power per rank (mW) +system.mem_ctrls_0.totalEnergy 49696380 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 1057.909997 # Core power per rank (mW) system.mem_ctrls_0.memoryStateTime::IDLE 19 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states @@ -266,360 +269,354 @@ system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 965 -system.ruby.outstanding_req_hist::mean 15.764767 -system.ruby.outstanding_req_hist::gmean 15.657041 -system.ruby.outstanding_req_hist::stdev 1.204074 -system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.21% 0.31% | 2 0.21% 0.52% | 2 0.21% 0.73% | 4 0.41% 1.14% | 2 0.21% 1.35% | 3 0.31% 1.66% | 91 9.43% 11.09% | 858 88.91% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 965 +system.ruby.outstanding_req_hist::samples 972 +system.ruby.outstanding_req_hist::mean 15.762346 +system.ruby.outstanding_req_hist::gmean 15.655254 +system.ruby.outstanding_req_hist::stdev 1.201656 +system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.21% 0.31% | 2 0.21% 0.51% | 2 0.21% 0.72% | 4 0.41% 1.13% | 2 0.21% 1.34% | 3 0.31% 1.65% | 94 9.67% 11.32% | 862 88.68% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 972 system.ruby.latency_hist::bucket_size 256 system.ruby.latency_hist::max_bucket 2559 -system.ruby.latency_hist::samples 950 -system.ruby.latency_hist::mean 871.068421 -system.ruby.latency_hist::gmean 461.645451 -system.ruby.latency_hist::stdev 364.947641 -system.ruby.latency_hist | 141 14.84% 14.84% | 6 0.63% 15.47% | 4 0.42% 15.89% | 461 48.53% 64.42% | 326 34.32% 98.74% | 12 1.26% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 950 +system.ruby.latency_hist::samples 957 +system.ruby.latency_hist::mean 881.794148 +system.ruby.latency_hist::gmean 495.949804 +system.ruby.latency_hist::stdev 359.464211 +system.ruby.latency_hist | 135 14.11% 14.11% | 6 0.63% 14.73% | 4 0.42% 15.15% | 442 46.19% 61.34% | 349 36.47% 97.81% | 21 2.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 957 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 86 +system.ruby.hit_latency_hist::samples 75 system.ruby.hit_latency_hist::mean 1 system.ruby.hit_latency_hist::gmean 1 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 86 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 86 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 75 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 75 system.ruby.miss_latency_hist::bucket_size 256 system.ruby.miss_latency_hist::max_bucket 2559 -system.ruby.miss_latency_hist::samples 864 -system.ruby.miss_latency_hist::mean 957.672454 -system.ruby.miss_latency_hist::gmean 850.170322 -system.ruby.miss_latency_hist::stdev 252.014806 -system.ruby.miss_latency_hist | 55 6.37% 6.37% | 6 0.69% 7.06% | 4 0.46% 7.52% | 461 53.36% 60.88% | 326 37.73% 98.61% | 12 1.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 864 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 84 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 819 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 903 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 2 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 46 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 48 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 5 # Number of times a store aliased with a pending load -system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 84 # Number of times a store aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store -system.ruby.l2_cntrl0.L2cache.demand_hits 32 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 833 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 865 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 882 +system.ruby.miss_latency_hist::mean 956.691610 +system.ruby.miss_latency_hist::gmean 840.701090 +system.ruby.miss_latency_hist::stdev 261.829138 +system.ruby.miss_latency_hist | 60 6.80% 6.80% | 6 0.68% 7.48% | 4 0.45% 7.94% | 442 50.11% 58.05% | 349 39.57% 97.62% | 21 2.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 882 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 75 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 832 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 907 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 50 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 50 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 3 # Number of times a store aliased with a pending load +system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 76 # Number of times a store aliased with a pending store +system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 3 # Number of times a load aliased with a pending store +system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 852 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 882 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 9.000779 -system.ruby.network.routers0.msg_count.Request_Control::0 865 -system.ruby.network.routers0.msg_count.Response_Data::2 832 -system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 32 -system.ruby.network.routers0.msg_count.Writeback_Data::2 859 -system.ruby.network.routers0.msg_count.Writeback_Control::0 1720 -system.ruby.network.routers0.msg_count.Unblock_Control::2 864 -system.ruby.network.routers0.msg_bytes.Request_Control::0 6920 -system.ruby.network.routers0.msg_bytes.Response_Data::2 59904 -system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 2304 -system.ruby.network.routers0.msg_bytes.Writeback_Data::2 61848 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 13760 -system.ruby.network.routers0.msg_bytes.Unblock_Control::2 6912 -system.ruby.network.routers1.percent_links_utilized 17.230442 -system.ruby.network.routers1.msg_count.Request_Control::0 865 -system.ruby.network.routers1.msg_count.Request_Control::1 833 -system.ruby.network.routers1.msg_count.Response_Data::2 1664 -system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 32 -system.ruby.network.routers1.msg_count.Writeback_Data::2 1603 -system.ruby.network.routers1.msg_count.Writeback_Control::0 1720 -system.ruby.network.routers1.msg_count.Writeback_Control::1 1488 -system.ruby.network.routers1.msg_count.Unblock_Control::2 1694 -system.ruby.network.routers1.msg_bytes.Request_Control::0 6920 -system.ruby.network.routers1.msg_bytes.Request_Control::1 6664 -system.ruby.network.routers1.msg_bytes.Response_Data::2 119808 -system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 2304 -system.ruby.network.routers1.msg_bytes.Writeback_Data::2 115416 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 13760 -system.ruby.network.routers1.msg_bytes.Writeback_Control::1 11904 -system.ruby.network.routers1.msg_bytes.Unblock_Control::2 13552 -system.ruby.network.routers2.percent_links_utilized 8.227289 -system.ruby.network.routers2.msg_count.Request_Control::1 833 -system.ruby.network.routers2.msg_count.Response_Data::2 832 -system.ruby.network.routers2.msg_count.Writeback_Data::2 743 -system.ruby.network.routers2.msg_count.Writeback_Control::1 1488 -system.ruby.network.routers2.msg_count.Unblock_Control::2 831 -system.ruby.network.routers2.msg_bytes.Request_Control::1 6664 -system.ruby.network.routers2.msg_bytes.Response_Data::2 59904 -system.ruby.network.routers2.msg_bytes.Writeback_Data::2 53496 -system.ruby.network.routers2.msg_bytes.Writeback_Control::1 11904 -system.ruby.network.routers2.msg_bytes.Unblock_Control::2 6648 -system.ruby.network.routers3.percent_links_utilized 11.486012 -system.ruby.network.routers3.msg_count.Request_Control::0 865 -system.ruby.network.routers3.msg_count.Request_Control::1 833 -system.ruby.network.routers3.msg_count.Response_Data::2 1664 -system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 32 -system.ruby.network.routers3.msg_count.Writeback_Data::2 1603 -system.ruby.network.routers3.msg_count.Writeback_Control::0 1720 -system.ruby.network.routers3.msg_count.Writeback_Control::1 1488 -system.ruby.network.routers3.msg_count.Unblock_Control::2 1695 -system.ruby.network.routers3.msg_bytes.Request_Control::0 6920 -system.ruby.network.routers3.msg_bytes.Request_Control::1 6664 -system.ruby.network.routers3.msg_bytes.Response_Data::2 119808 -system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 2304 -system.ruby.network.routers3.msg_bytes.Writeback_Data::2 115416 -system.ruby.network.routers3.msg_bytes.Writeback_Control::0 13760 -system.ruby.network.routers3.msg_bytes.Writeback_Control::1 11904 -system.ruby.network.routers3.msg_bytes.Unblock_Control::2 13560 -system.ruby.network.msg_count.Request_Control 5094 -system.ruby.network.msg_count.Response_Data 4992 -system.ruby.network.msg_count.ResponseL2hit_Data 96 -system.ruby.network.msg_count.Writeback_Data 4808 -system.ruby.network.msg_count.Writeback_Control 9624 -system.ruby.network.msg_count.Unblock_Control 5084 -system.ruby.network.msg_byte.Request_Control 40752 -system.ruby.network.msg_byte.Response_Data 359424 -system.ruby.network.msg_byte.ResponseL2hit_Data 6912 -system.ruby.network.msg_byte.Writeback_Data 346176 -system.ruby.network.msg_byte.Writeback_Control 76992 -system.ruby.network.msg_byte.Unblock_Control 40672 -system.ruby.network.routers0.throttle0.link_utilization 8.201174 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 832 -system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 32 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 860 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 59904 -system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 2304 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 6880 -system.ruby.network.routers0.throttle1.link_utilization 9.800384 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 865 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 859 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 860 -system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 864 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 6920 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 61848 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 6880 -system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 6912 -system.ruby.network.routers1.throttle0.link_utilization 17.616949 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 865 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 832 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 859 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 860 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 744 -system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 863 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 6920 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 59904 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 61848 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 6880 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 5952 -system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 6904 -system.ruby.network.routers1.throttle1.link_utilization 16.843935 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 833 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 832 -system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 32 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 744 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 860 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 744 -system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 831 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 6664 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 59904 -system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 2304 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-system.ruby.network.routers2.throttle1.link_utilization 7.817515 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 832 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 744 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 59904 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 5952 -system.ruby.network.routers3.throttle0.link_utilization 8.201174 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 832 -system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 32 -system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 860 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 59904 -system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 2304 -system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 6880 -system.ruby.network.routers3.throttle1.link_utilization 17.617899 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317.419654 -system.ruby.LD.latency_hist | 5 9.62% 9.62% | 0 0.00% 9.62% | 0 0.00% 9.62% | 32 61.54% 71.15% | 14 26.92% 98.08% | 1 1.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 52 +system.ruby.LD.latency_hist::samples 50 +system.ruby.LD.latency_hist::mean 914.500000 +system.ruby.LD.latency_hist::gmean 544.079764 +system.ruby.LD.latency_hist::stdev 318.769653 +system.ruby.LD.latency_hist | 5 10.00% 10.00% | 0 0.00% 10.00% | 0 0.00% 10.00% | 30 60.00% 70.00% | 13 26.00% 96.00% | 2 4.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 50 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 5 +system.ruby.LD.hit_latency_hist::samples 4 system.ruby.LD.hit_latency_hist::mean 1 system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 5 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 5 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 4 system.ruby.LD.miss_latency_hist::bucket_size 256 system.ruby.LD.miss_latency_hist::max_bucket 2559 -system.ruby.LD.miss_latency_hist::samples 47 -system.ruby.LD.miss_latency_hist::mean 1019.638298 -system.ruby.LD.miss_latency_hist::gmean 1015.343067 -system.ruby.LD.miss_latency_hist::stdev 98.825148 -system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 32 68.09% 68.09% | 14 29.79% 97.87% | 1 2.13% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 47 +system.ruby.LD.miss_latency_hist::samples 46 +system.ruby.LD.miss_latency_hist::mean 993.934783 +system.ruby.LD.miss_latency_hist::gmean 940.906082 +system.ruby.LD.miss_latency_hist::stdev 173.263243 +system.ruby.LD.miss_latency_hist | 1 2.17% 2.17% | 0 0.00% 2.17% | 0 0.00% 2.17% | 30 65.22% 67.39% | 13 28.26% 95.65% | 2 4.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 46 system.ruby.ST.latency_hist::bucket_size 256 system.ruby.ST.latency_hist::max_bucket 2559 -system.ruby.ST.latency_hist::samples 850 -system.ruby.ST.latency_hist::mean 913.334118 -system.ruby.ST.latency_hist::gmean 517.508162 -system.ruby.ST.latency_hist::stdev 322.997582 -system.ruby.ST.latency_hist | 88 10.35% 10.35% | 6 0.71% 11.06% | 4 0.47% 11.53% | 429 50.47% 62.00% | 312 36.71% 98.71% | 11 1.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 850 +system.ruby.ST.latency_hist::samples 857 +system.ruby.ST.latency_hist::mean 927.439907 +system.ruby.ST.latency_hist::gmean 556.916459 +system.ruby.ST.latency_hist::stdev 312.242258 +system.ruby.ST.latency_hist | 80 9.33% 9.33% | 6 0.70% 10.04% | 4 0.47% 10.50% | 412 48.07% 58.58% | 336 39.21% 97.78% | 19 2.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 857 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 79 +system.ruby.ST.hit_latency_hist::samples 71 system.ruby.ST.hit_latency_hist::mean 1 system.ruby.ST.hit_latency_hist::gmean 1 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 79 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 79 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 71 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 71 system.ruby.ST.miss_latency_hist::bucket_size 256 system.ruby.ST.miss_latency_hist::max_bucket 2559 -system.ruby.ST.miss_latency_hist::samples 771 -system.ruby.ST.miss_latency_hist::mean 1006.815824 -system.ruby.ST.miss_latency_hist::gmean 981.740975 -system.ruby.ST.miss_latency_hist::stdev 144.511842 -system.ruby.ST.miss_latency_hist | 9 1.17% 1.17% | 6 0.78% 1.95% | 4 0.52% 2.46% | 429 55.64% 58.11% | 312 40.47% 98.57% | 11 1.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 771 +system.ruby.ST.miss_latency_hist::samples 786 +system.ruby.ST.miss_latency_hist::mean 1011.125954 +system.ruby.ST.miss_latency_hist::gmean 985.869507 +system.ruby.ST.miss_latency_hist::stdev 147.214582 +system.ruby.ST.miss_latency_hist | 9 1.15% 1.15% | 6 0.76% 1.91% | 4 0.51% 2.42% | 412 52.42% 54.83% | 336 42.75% 97.58% | 19 2.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 786 system.ruby.IFETCH.latency_hist::bucket_size 32 system.ruby.IFETCH.latency_hist::max_bucket 319 -system.ruby.IFETCH.latency_hist::samples 48 -system.ruby.IFETCH.latency_hist::mean 67.770833 -system.ruby.IFETCH.latency_hist::gmean 53.478769 -system.ruby.IFETCH.latency_hist::stdev 34.601217 -system.ruby.IFETCH.latency_hist | 5 10.42% 10.42% | 12 25.00% 35.42% | 27 56.25% 91.67% | 0 0.00% 91.67% | 3 6.25% 97.92% | 1 2.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 48 -system.ruby.IFETCH.hit_latency_hist::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 2 -system.ruby.IFETCH.hit_latency_hist::mean 1 -system.ruby.IFETCH.hit_latency_hist::gmean 1 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 2 +system.ruby.IFETCH.latency_hist::samples 50 +system.ruby.IFETCH.latency_hist::mean 66.720000 +system.ruby.IFETCH.latency_hist::gmean 61.968921 +system.ruby.IFETCH.latency_hist::stdev 27.740812 +system.ruby.IFETCH.latency_hist | 1 2.00% 2.00% | 19 38.00% 40.00% | 28 56.00% 96.00% | 0 0.00% 96.00% | 1 2.00% 98.00% | 0 0.00% 98.00% | 1 2.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 50 system.ruby.IFETCH.miss_latency_hist::bucket_size 32 system.ruby.IFETCH.miss_latency_hist::max_bucket 319 -system.ruby.IFETCH.miss_latency_hist::samples 46 -system.ruby.IFETCH.miss_latency_hist::mean 70.673913 -system.ruby.IFETCH.miss_latency_hist::gmean 63.579883 -system.ruby.IFETCH.miss_latency_hist::stdev 32.306212 -system.ruby.IFETCH.miss_latency_hist | 3 6.52% 6.52% | 12 26.09% 32.61% | 27 58.70% 91.30% | 0 0.00% 91.30% | 3 6.52% 97.83% | 1 2.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 46 -system.ruby.Directory_Controller.GETX 749 0.00% 0.00% -system.ruby.Directory_Controller.GETS 84 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 744 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 78 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 5 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 748 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 743 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 832 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 743 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 687 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 79 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 743 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 62 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 5 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 744 0.00% 0.00% -system.ruby.Directory_Controller.IS.Unblock 78 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 79 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 5 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 5 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 748 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 748 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 743 0.00% 0.00% +system.ruby.IFETCH.miss_latency_hist::samples 50 +system.ruby.IFETCH.miss_latency_hist::mean 66.720000 +system.ruby.IFETCH.miss_latency_hist::gmean 61.968921 +system.ruby.IFETCH.miss_latency_hist::stdev 27.740812 +system.ruby.IFETCH.miss_latency_hist | 1 2.00% 2.00% | 19 38.00% 40.00% | 28 56.00% 96.00% | 0 0.00% 96.00% | 1 2.00% 98.00% | 0 0.00% 98.00% | 1 2.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 50 +system.ruby.Directory_Controller.GETX 763 0.00% 0.00% +system.ruby.Directory_Controller.GETS 89 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 758 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 84 0.00% 0.00% +system.ruby.Directory_Controller.Last_Unblock 4 0.00% 0.00% +system.ruby.Directory_Controller.Exclusive_Unblock 763 0.00% 0.00% +system.ruby.Directory_Controller.Dirty_Writeback 757 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 852 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 757 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 700 0.00% 0.00% +system.ruby.Directory_Controller.I.GETS 85 0.00% 0.00% +system.ruby.Directory_Controller.I.Memory_Ack 757 0.00% 0.00% +system.ruby.Directory_Controller.S.GETX 63 0.00% 0.00% +system.ruby.Directory_Controller.S.GETS 4 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 758 0.00% 0.00% +system.ruby.Directory_Controller.IS.Unblock 84 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Data 85 0.00% 0.00% +system.ruby.Directory_Controller.SS.Last_Unblock 4 0.00% 0.00% +system.ruby.Directory_Controller.SS.Memory_Data 4 0.00% 0.00% +system.ruby.Directory_Controller.MM.Exclusive_Unblock 763 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Data 763 0.00% 0.00% +system.ruby.Directory_Controller.MI.Dirty_Writeback 757 0.00% 0.00% system.ruby.L1Cache_Controller.Load 52 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 60 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 859 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 77732 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 84 0.00% 0.00% -system.ruby.L1Cache_Controller.Exclusive_Data 780 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack_Data 860 0.00% 0.00% -system.ruby.L1Cache_Controller.All_acks 771 0.00% 0.00% -system.ruby.L1Cache_Controller.Use_Timeout 780 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 47 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 46 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 772 0.00% 0.00% -system.ruby.L1Cache_Controller.S.L1_Replacement 81 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 1 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_Replacement 8 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Ifetch 1 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.L1_Replacement 5 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Use_Timeout 9 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Load 5 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Store 67 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement 771 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Store 12 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement 30528 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Use_Timeout 771 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement 43624 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data 771 0.00% 0.00% -system.ruby.L1Cache_Controller.OM.L1_Replacement 28 0.00% 0.00% -system.ruby.L1Cache_Controller.OM.All_acks 771 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement 2687 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 84 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data 9 0.00% 0.00% -system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 81 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Ifetch 12 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% +system.ruby.L1Cache_Controller.L1_Replacement 79286 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 89 0.00% 0.00% +system.ruby.L1Cache_Controller.Exclusive_Data 793 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack_Data 877 0.00% 0.00% +system.ruby.L1Cache_Controller.All_acks 786 0.00% 0.00% +system.ruby.L1Cache_Controller.Use_Timeout 792 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 46 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 50 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 786 0.00% 0.00% +system.ruby.L1Cache_Controller.S.L1_Replacement 87 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 1 0.00% 0.00% +system.ruby.L1Cache_Controller.M.L1_Replacement 6 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.L1_Replacement 4 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.Use_Timeout 7 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Load 3 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Store 59 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.L1_Replacement 784 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.Load 1 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.Store 11 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.L1_Replacement 31474 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.Use_Timeout 785 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement 44509 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Exclusive_Data 786 0.00% 0.00% +system.ruby.L1Cache_Controller.OM.L1_Replacement 57 0.00% 0.00% +system.ruby.L1Cache_Controller.OM.All_acks 786 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement 2365 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 89 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Exclusive_Data 7 0.00% 0.00% +system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 87 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Load 2 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Ifetch 10 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Store 8 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 779 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 93 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 772 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 779 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTS_only 81 0.00% 0.00% -system.ruby.L2Cache_Controller.All_Acks 748 0.00% 0.00% -system.ruby.L2Cache_Controller.Data 832 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBCLEANDATA 81 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 778 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Ack 744 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 83 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 780 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 824 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 84 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 749 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 81 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_PUTX 779 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 80 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 9 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 790 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 96 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 786 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 790 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTS_only 87 0.00% 0.00% +system.ruby.L2Cache_Controller.All_Acks 763 0.00% 0.00% +system.ruby.L2Cache_Controller.Data 852 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_WBCLEANDATA 87 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 790 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_Ack 758 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 88 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 793 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 844 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 89 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 763 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 87 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_PUTX 790 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L2_Replacement 86 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 7 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GETX 23 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 744 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 81 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 778 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Data 84 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Unblock 83 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.Data 748 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.All_Acks 748 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 748 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 758 0.00% 0.00% +system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 87 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 790 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.Data 89 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.Unblock 88 0.00% 0.00% +system.ruby.L2Cache_Controller.IGM.Data 763 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.All_Acks 763 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 763 0.00% 0.00% system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 23 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 9 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.Writeback_Ack 744 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 7 0.00% 0.00% +system.ruby.L2Cache_Controller.MI.Writeback_Ack 758 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt index 904ef14f6..4c7e247ea 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000053 # Number of seconds simulated -sim_ticks 53281 # Number of ticks simulated -final_tick 53281 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 53241 # Number of ticks simulated +final_tick 53241 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 569800 # Simulator tick rate (ticks/s) -host_mem_usage 444292 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 858034 # Simulator tick rate (ticks/s) +host_mem_usage 452700 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 53952 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 53952 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 49600 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 49600 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 843 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 843 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 775 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 775 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 1012593607 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 1012593607 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 930913459 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 930913459 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1943507066 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1943507066 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 843 # Number of read requests accepted -system.mem_ctrls.writeReqs 775 # Number of write requests accepted -system.mem_ctrls.readBursts 843 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 775 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 44736 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 9216 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 41664 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 53952 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 49600 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 104 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54016 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 54016 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 49216 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 49216 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 844 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 844 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 769 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 769 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 1014556451 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1014556451 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 924400368 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 924400368 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1938956819 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1938956819 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 845 # Number of read requests accepted +system.mem_ctrls.writeReqs 769 # Number of write requests accepted +system.mem_ctrls.readBursts 845 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 769 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 44800 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 9280 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 41856 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 54080 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 49216 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 145 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 91 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 206 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 226 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 220 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 47 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 211 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 230 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 216 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 43 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts @@ -51,10 +51,10 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 188 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 209 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 208 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 46 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 195 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 213 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 203 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 43 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts @@ -69,24 +69,24 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 53211 # Total gap between requests +system.mem_ctrls.totGap 53206 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 843 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 845 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 775 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 613 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 85 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 769 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 596 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 104 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -132,24 +132,24 @@ system.mem_ctrls.wrQLenPdf::12 1 # Wh system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 25 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 46 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 45 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 51 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 44 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 45 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 44 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 41 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::27 40 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 40 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::29 40 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 40 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::31 40 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -180,70 +180,71 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 93 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 913.892473 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 847.990264 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 239.348094 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 1 1.08% 1.08% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 2 2.15% 3.23% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 5 5.38% 8.60% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 3 3.23% 11.83% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 3 3.23% 15.05% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 5 5.38% 20.43% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 4 4.30% 24.73% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 70 75.27% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 93 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 91 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 926.241758 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 851.755825 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 236.278712 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 2 2.20% 2.20% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 3 3.30% 5.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 1 1.10% 6.59% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 3 3.30% 9.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 3 3.30% 13.19% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 4 4.40% 17.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 3 3.30% 20.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 72 79.12% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 91 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 40 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 17.375000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 17.123338 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.613986 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 8 20.00% 20.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 19 47.50% 67.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 10 25.00% 92.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 1 2.50% 95.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 17.325000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 17.063768 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 3.661214 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 9 22.50% 22.50% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 19 47.50% 70.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 8 20.00% 90.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 2 5.00% 95.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::22-23 1 2.50% 97.50% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::36-37 1 2.50% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 40 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 40 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.275000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.254222 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.876693 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 36 90.00% 90.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 2 5.00% 95.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 1 2.50% 97.50% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.350000 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.325620 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.948683 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 34 85.00% 85.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 2 5.00% 90.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 1 2.50% 92.50% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 2 5.00% 97.50% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::20 1 2.50% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 40 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 7735 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 21016 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3495 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 11.07 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 7789 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 21089 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3500 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 11.13 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 30.07 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 839.62 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 781.97 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 1012.59 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 930.91 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 30.13 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 841.46 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 786.16 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1015.76 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 924.40 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 12.67 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 6.56 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 6.11 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.22 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.26 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 608 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 646 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 86.98 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 96.27 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 32.89 # Average gap between requests -system.mem_ctrls.pageHitRate 91.53 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 635040 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 352800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 7650240 # Energy for read commands per rank (pJ) +system.mem_ctrls.busUtil 12.72 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 6.57 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 6.14 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.26 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.08 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 611 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 649 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 87.29 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 95.72 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 32.97 # Average gap between requests +system.mem_ctrls.pageHitRate 91.44 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 627480 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 348600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7712640 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 5920128 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) system.mem_ctrls_0.actBackEnergy 32011200 # Energy for active background per rank (pJ) system.mem_ctrls_0.preBackEnergy 105600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 49726368 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 1058.548365 # Core power per rank (mW) +system.mem_ctrls_0.totalEnergy 49777008 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 1059.626362 # Core power per rank (mW) system.mem_ctrls_0.memoryStateTime::IDLE 22 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states @@ -266,418 +267,444 @@ system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 1025 -system.ruby.outstanding_req_hist::mean 15.802927 -system.ruby.outstanding_req_hist::gmean 15.701371 -system.ruby.outstanding_req_hist::stdev 1.166002 -system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.29% | 2 0.20% 0.49% | 2 0.20% 0.68% | 4 0.39% 1.07% | 2 0.20% 1.27% | 3 0.29% 1.56% | 65 6.34% 7.90% | 944 92.10% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 1025 +system.ruby.outstanding_req_hist::samples 1000 +system.ruby.outstanding_req_hist::mean 15.805000 +system.ruby.outstanding_req_hist::gmean 15.701069 +system.ruby.outstanding_req_hist::stdev 1.178288 +system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 2 0.20% 0.70% | 4 0.40% 1.10% | 2 0.20% 1.30% | 3 0.30% 1.60% | 58 5.80% 7.40% | 926 92.60% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 1000 system.ruby.latency_hist::bucket_size 256 system.ruby.latency_hist::max_bucket 2559 -system.ruby.latency_hist::samples 1010 -system.ruby.latency_hist::mean 826.408911 -system.ruby.latency_hist::gmean 360.645319 -system.ruby.latency_hist::stdev 428.892759 -system.ruby.latency_hist | 216 21.39% 21.39% | 6 0.59% 21.98% | 5 0.50% 22.48% | 328 32.48% 54.95% | 410 40.59% 95.54% | 45 4.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 1010 +system.ruby.latency_hist::samples 985 +system.ruby.latency_hist::mean 848.757360 +system.ruby.latency_hist::gmean 399.302244 +system.ruby.latency_hist::stdev 414.190992 +system.ruby.latency_hist | 190 19.29% 19.29% | 6 0.61% 19.90% | 5 0.51% 20.41% | 342 34.72% 55.13% | 403 40.91% 96.04% | 39 3.96% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 985 system.ruby.hit_latency_hist::bucket_size 256 system.ruby.hit_latency_hist::max_bucket 2559 -system.ruby.hit_latency_hist::samples 168 -system.ruby.hit_latency_hist::mean 146.386905 -system.ruby.hit_latency_hist::gmean 5.716522 -system.ruby.hit_latency_hist::stdev 347.347225 -system.ruby.hit_latency_hist | 146 86.90% 86.90% | 0 0.00% 86.90% | 0 0.00% 86.90% | 13 7.74% 94.64% | 7 4.17% 98.81% | 2 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 168 +system.ruby.hit_latency_hist::samples 141 +system.ruby.hit_latency_hist::mean 184.574468 +system.ruby.hit_latency_hist::gmean 5.430666 +system.ruby.hit_latency_hist::stdev 386.473899 +system.ruby.hit_latency_hist | 116 82.27% 82.27% | 0 0.00% 82.27% | 0 0.00% 82.27% | 19 13.48% 95.74% | 4 2.84% 98.58% | 2 1.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 141 system.ruby.miss_latency_hist::bucket_size 256 system.ruby.miss_latency_hist::max_bucket 2559 -system.ruby.miss_latency_hist::samples 842 -system.ruby.miss_latency_hist::mean 962.090261 -system.ruby.miss_latency_hist::gmean 824.546033 -system.ruby.miss_latency_hist::stdev 293.137943 -system.ruby.miss_latency_hist | 70 8.31% 8.31% | 6 0.71% 9.03% | 5 0.59% 9.62% | 315 37.41% 47.03% | 403 47.86% 94.89% | 43 5.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 842 -system.ruby.Directory.incomplete_times 842 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 108 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 847 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 955 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 56 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 56 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 7 # Number of times a store aliased with a pending load -system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 85 # Number of times a store aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 7 # Number of times a load aliased with a pending store -system.ruby.l2_cntrl0.L2cache.demand_hits 60 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 843 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 903 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 844 +system.ruby.miss_latency_hist::mean 959.716825 +system.ruby.miss_latency_hist::gmean 818.679034 +system.ruby.miss_latency_hist::stdev 298.884250 +system.ruby.miss_latency_hist | 74 8.77% 8.77% | 6 0.71% 9.48% | 5 0.59% 10.07% | 323 38.27% 48.34% | 399 47.27% 95.62% | 37 4.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 844 +system.ruby.Directory.incomplete_times 844 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 97 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 841 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 938 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 1 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 47 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 48 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 4 # Number of times a store aliased with a pending load +system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 84 # Number of times a store aliased with a pending store +system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 5 # Number of times a load aliased with a pending store +system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load +system.ruby.l2_cntrl0.L2cache.demand_hits 42 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 846 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 888 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 8.199921 -system.ruby.network.routers0.msg_count.Request_Control::1 903 -system.ruby.network.routers0.msg_count.Response_Data::4 842 -system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 60 -system.ruby.network.routers0.msg_count.Writeback_Data::4 932 -system.ruby.network.routers0.msg_count.Persistent_Control::3 68 -system.ruby.network.routers0.msg_bytes.Request_Control::1 7224 -system.ruby.network.routers0.msg_bytes.Response_Data::4 60624 -system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 4320 -system.ruby.network.routers0.msg_bytes.Writeback_Data::4 67104 -system.ruby.network.routers0.msg_bytes.Persistent_Control::3 544 -system.ruby.network.routers1.percent_links_utilized 8.182560 -system.ruby.network.routers1.msg_count.Request_Control::1 903 -system.ruby.network.routers1.msg_count.Request_Control::2 843 -system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 60 -system.ruby.network.routers1.msg_count.Writeback_Data::4 1673 -system.ruby.network.routers1.msg_count.Writeback_Control::4 62 -system.ruby.network.routers1.msg_count.Persistent_Control::3 34 -system.ruby.network.routers1.msg_bytes.Request_Control::1 7224 -system.ruby.network.routers1.msg_bytes.Request_Control::2 6744 -system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 4320 -system.ruby.network.routers1.msg_bytes.Writeback_Data::4 120456 -system.ruby.network.routers1.msg_bytes.Writeback_Control::4 496 -system.ruby.network.routers1.msg_bytes.Persistent_Control::3 272 -system.ruby.network.routers2.percent_links_utilized 7.271823 -system.ruby.network.routers2.msg_count.Request_Control::2 843 -system.ruby.network.routers2.msg_count.Response_Data::4 843 -system.ruby.network.routers2.msg_count.Writeback_Data::4 775 -system.ruby.network.routers2.msg_count.Writeback_Control::4 62 -system.ruby.network.routers2.msg_count.Persistent_Control::3 34 -system.ruby.network.routers2.msg_bytes.Request_Control::2 6744 -system.ruby.network.routers2.msg_bytes.Response_Data::4 60696 -system.ruby.network.routers2.msg_bytes.Writeback_Data::4 55800 -system.ruby.network.routers2.msg_bytes.Writeback_Control::4 496 -system.ruby.network.routers2.msg_bytes.Persistent_Control::3 272 -system.ruby.network.routers3.percent_links_utilized 7.884612 -system.ruby.network.routers3.msg_count.Request_Control::1 903 -system.ruby.network.routers3.msg_count.Request_Control::2 843 -system.ruby.network.routers3.msg_count.Response_Data::4 843 -system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4 60 -system.ruby.network.routers3.msg_count.Writeback_Data::4 1690 -system.ruby.network.routers3.msg_count.Writeback_Control::4 62 -system.ruby.network.routers3.msg_count.Persistent_Control::3 68 -system.ruby.network.routers3.msg_bytes.Request_Control::1 7224 -system.ruby.network.routers3.msg_bytes.Request_Control::2 6744 -system.ruby.network.routers3.msg_bytes.Response_Data::4 60696 -system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4 4320 -system.ruby.network.routers3.msg_bytes.Writeback_Data::4 121680 -system.ruby.network.routers3.msg_bytes.Writeback_Control::4 496 -system.ruby.network.routers3.msg_bytes.Persistent_Control::3 544 -system.ruby.network.msg_count.Request_Control 5238 -system.ruby.network.msg_count.Response_Data 2528 -system.ruby.network.msg_count.ResponseL2hit_Data 180 -system.ruby.network.msg_count.Writeback_Data 5070 -system.ruby.network.msg_count.Writeback_Control 186 -system.ruby.network.msg_count.Persistent_Control 204 -system.ruby.network.msg_byte.Request_Control 41904 -system.ruby.network.msg_byte.Response_Data 182016 -system.ruby.network.msg_byte.ResponseL2hit_Data 12960 -system.ruby.network.msg_byte.Writeback_Data 365040 -system.ruby.network.msg_byte.Writeback_Control 1488 -system.ruby.network.msg_byte.Persistent_Control 1632 -system.ruby.network.routers0.throttle0.link_utilization 7.792647 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 842 -system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 60 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Data::4 17 -system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3 34 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 60624 -system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 4320 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Data::4 1224 -system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 272 -system.ruby.network.routers0.throttle1.link_utilization 8.607196 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 903 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 915 -system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 34 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 7224 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 65880 -system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 272 -system.ruby.network.routers1.throttle0.link_utilization 8.463617 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 903 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 898 -system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 34 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 7224 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 64656 -system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 272 -system.ruby.network.routers1.throttle1.link_utilization 7.901503 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 843 -system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 60 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::4 775 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4 62 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 6744 -system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 4320 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 55800 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 496 -system.ruby.network.routers2.throttle0.link_utilization 7.426662 -system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 843 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 775 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 62 -system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 34 -system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 6744 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 55800 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 496 -system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 272 -system.ruby.network.routers2.throttle1.link_utilization 7.116984 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 843 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 60696 -system.ruby.network.routers3.throttle0.link_utilization 7.763555 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 843 -system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 60 -system.ruby.network.routers3.throttle0.msg_count.Writeback_Data::4 17 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 60696 -system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 4320 -system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Data::4 1224 -system.ruby.network.routers3.throttle1.link_utilization 8.463617 -system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 903 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 898 -system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 34 -system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 7224 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 64656 -system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 272 -system.ruby.network.routers3.throttle2.link_utilization 7.426662 -system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 843 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 775 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 62 -system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3 34 -system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 6744 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 55800 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 496 -system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 272 +system.ruby.network.routers0.percent_links_utilized 8.048309 +system.ruby.network.routers0.msg_count.Request_Control::1 888 +system.ruby.network.routers0.msg_count.Response_Data::4 844 +system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 43 +system.ruby.network.routers0.msg_count.Response_Control::4 1 +system.ruby.network.routers0.msg_count.Writeback_Data::4 912 +system.ruby.network.routers0.msg_count.Persistent_Control::3 60 +system.ruby.network.routers0.msg_bytes.Request_Control::1 7104 +system.ruby.network.routers0.msg_bytes.Response_Data::4 60768 +system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 3096 +system.ruby.network.routers0.msg_bytes.Response_Control::4 8 +system.ruby.network.routers0.msg_bytes.Writeback_Data::4 65664 +system.ruby.network.routers0.msg_bytes.Persistent_Control::3 480 +system.ruby.network.routers1.percent_links_utilized 8.019665 +system.ruby.network.routers1.msg_count.Request_Control::1 888 +system.ruby.network.routers1.msg_count.Request_Control::2 846 +system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 43 +system.ruby.network.routers1.msg_count.Response_Control::4 1 +system.ruby.network.routers1.msg_count.Writeback_Data::4 1651 +system.ruby.network.routers1.msg_count.Writeback_Control::4 68 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+system.ruby.network.routers0.throttle1.link_utilization 8.443681 +system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 888 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 897 +system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 30 +system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 7104 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 64584 +system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 240 +system.ruby.network.routers1.throttle0.link_utilization 8.316899 +system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 888 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 882 +system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 30 +system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 7104 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 63504 +system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 240 +system.ruby.network.routers1.throttle1.link_utilization 7.722432 +system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 846 +system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 43 +system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 1 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::4 769 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4 68 +system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 6768 +system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 3096 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 8 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 55368 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 544 +system.ruby.network.routers2.throttle0.link_utilization 7.386225 +system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 846 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 769 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 68 +system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 30 +system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 6768 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 55368 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 544 +system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 240 +system.ruby.network.routers2.throttle1.link_utilization 7.133600 +system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 844 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 60768 +system.ruby.network.routers3.throttle0.link_utilization 7.624763 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 844 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444.059442 -system.ruby.LD.latency_hist | 9 20.45% 20.45% | 0 0.00% 20.45% | 0 0.00% 20.45% | 10 22.73% 43.18% | 21 47.73% 90.91% | 4 9.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 44 +system.ruby.LD.latency_hist::samples 52 +system.ruby.LD.latency_hist::mean 846.192308 +system.ruby.LD.latency_hist::gmean 310.504022 +system.ruby.LD.latency_hist::stdev 441.024789 +system.ruby.LD.latency_hist | 11 21.15% 21.15% | 0 0.00% 21.15% | 0 0.00% 21.15% | 14 26.92% 48.08% | 26 50.00% 98.08% | 1 1.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 52 system.ruby.LD.hit_latency_hist::bucket_size 128 system.ruby.LD.hit_latency_hist::max_bucket 1279 -system.ruby.LD.hit_latency_hist::samples 9 -system.ruby.LD.hit_latency_hist::mean 107.666667 -system.ruby.LD.hit_latency_hist::gmean 3.425245 -system.ruby.LD.hit_latency_hist::stdev 293.965984 -system.ruby.LD.hit_latency_hist | 8 88.89% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 9 +system.ruby.LD.hit_latency_hist::samples 11 +system.ruby.LD.hit_latency_hist::mean 90.636364 +system.ruby.LD.hit_latency_hist::gmean 3.663774 +system.ruby.LD.hit_latency_hist::stdev 267.870220 +system.ruby.LD.hit_latency_hist | 10 90.91% 90.91% | 0 0.00% 90.91% | 0 0.00% 90.91% | 0 0.00% 90.91% | 0 0.00% 90.91% | 0 0.00% 90.91% | 0 0.00% 90.91% | 1 9.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 11 system.ruby.LD.miss_latency_hist::bucket_size 256 system.ruby.LD.miss_latency_hist::max_bucket 2559 -system.ruby.LD.miss_latency_hist::samples 35 -system.ruby.LD.miss_latency_hist::mean 1049.485714 -system.ruby.LD.miss_latency_hist::gmean 979.673055 -system.ruby.LD.miss_latency_hist::stdev 205.620349 -system.ruby.LD.miss_latency_hist | 1 2.86% 2.86% | 0 0.00% 2.86% | 0 0.00% 2.86% | 9 25.71% 28.57% | 21 60.00% 88.57% | 4 11.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 35 +system.ruby.LD.miss_latency_hist::samples 41 +system.ruby.LD.miss_latency_hist::mean 1048.902439 +system.ruby.LD.miss_latency_hist::gmean 1021.815979 +system.ruby.LD.miss_latency_hist::stdev 175.914866 +system.ruby.LD.miss_latency_hist | 1 2.44% 2.44% | 0 0.00% 2.44% | 0 0.00% 2.44% | 13 31.71% 34.15% | 26 63.41% 97.56% | 1 2.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 41 system.ruby.ST.latency_hist::bucket_size 256 system.ruby.ST.latency_hist::max_bucket 2559 -system.ruby.ST.latency_hist::samples 910 -system.ruby.ST.latency_hist::mean 872.319780 -system.ruby.ST.latency_hist::gmean 409.364189 -system.ruby.ST.latency_hist::stdev 395.158653 -system.ruby.ST.latency_hist | 151 16.59% 16.59% | 6 0.66% 17.25% | 5 0.55% 17.80% | 318 34.95% 52.75% | 389 42.75% 95.49% | 41 4.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 910 +system.ruby.ST.latency_hist::samples 885 +system.ruby.ST.latency_hist::mean 891.871186 +system.ruby.ST.latency_hist::gmean 453.694429 +system.ruby.ST.latency_hist::stdev 379.187013 +system.ruby.ST.latency_hist | 131 14.80% 14.80% | 6 0.68% 15.48% | 5 0.56% 16.05% | 328 37.06% 53.11% | 377 42.60% 95.71% | 38 4.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 885 system.ruby.ST.hit_latency_hist::bucket_size 256 system.ruby.ST.hit_latency_hist::max_bucket 2559 -system.ruby.ST.hit_latency_hist::samples 148 -system.ruby.ST.hit_latency_hist::mean 157.141892 -system.ruby.ST.hit_latency_hist::gmean 5.215153 -system.ruby.ST.hit_latency_hist::stdev 362.176321 -system.ruby.ST.hit_latency_hist | 127 85.81% 85.81% | 0 0.00% 85.81% | 0 0.00% 85.81% | 12 8.11% 93.92% | 7 4.73% 98.65% | 2 1.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 148 +system.ruby.ST.hit_latency_hist::samples 125 +system.ruby.ST.hit_latency_hist::mean 199.480000 +system.ruby.ST.hit_latency_hist::gmean 5.441959 +system.ruby.ST.hit_latency_hist::stdev 400.907933 +system.ruby.ST.hit_latency_hist | 101 80.80% 80.80% | 0 0.00% 80.80% | 0 0.00% 80.80% | 18 14.40% 95.20% | 4 3.20% 98.40% | 2 1.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 125 system.ruby.ST.miss_latency_hist::bucket_size 256 system.ruby.ST.miss_latency_hist::max_bucket 2559 -system.ruby.ST.miss_latency_hist::samples 762 -system.ruby.ST.miss_latency_hist::mean 1011.225722 -system.ruby.ST.miss_latency_hist::gmean 955.294030 -system.ruby.ST.miss_latency_hist::stdev 205.881979 -system.ruby.ST.miss_latency_hist | 24 3.15% 3.15% | 6 0.79% 3.94% | 5 0.66% 4.59% | 306 40.16% 44.75% | 382 50.13% 94.88% | 39 5.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 762 +system.ruby.ST.miss_latency_hist::samples 760 +system.ruby.ST.miss_latency_hist::mean 1005.751316 +system.ruby.ST.miss_latency_hist::gmean 939.114914 +system.ruby.ST.miss_latency_hist::stdev 221.956577 +system.ruby.ST.miss_latency_hist | 30 3.95% 3.95% | 6 0.79% 4.74% | 5 0.66% 5.39% | 310 40.79% 46.18% | 373 49.08% 95.26% | 36 4.74% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 760 system.ruby.IFETCH.latency_hist::bucket_size 16 system.ruby.IFETCH.latency_hist::max_bucket 159 -system.ruby.IFETCH.latency_hist::samples 56 -system.ruby.IFETCH.latency_hist::mean 56.446429 -system.ruby.IFETCH.latency_hist::gmean 52.074649 -system.ruby.IFETCH.latency_hist::stdev 22.043692 -system.ruby.IFETCH.latency_hist | 0 0.00% 0.00% | 9 16.07% 16.07% | 16 28.57% 44.64% | 1 1.79% 46.43% | 28 50.00% 96.43% | 1 1.79% 98.21% | 0 0.00% 98.21% | 0 0.00% 98.21% | 0 0.00% 98.21% | 1 1.79% 100.00% -system.ruby.IFETCH.latency_hist::total 56 -system.ruby.IFETCH.hit_latency_hist::bucket_size 8 -system.ruby.IFETCH.hit_latency_hist::max_bucket 79 -system.ruby.IFETCH.hit_latency_hist::samples 11 -system.ruby.IFETCH.hit_latency_hist::mean 33.363636 -system.ruby.IFETCH.hit_latency_hist::gmean 29.887638 -system.ruby.IFETCH.hit_latency_hist::stdev 19.673702 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9 81.82% 81.82% | 0 0.00% 81.82% | 0 0.00% 81.82% | 0 0.00% 81.82% | 0 0.00% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 11 +system.ruby.IFETCH.latency_hist::samples 48 +system.ruby.IFETCH.latency_hist::mean 56.625000 +system.ruby.IFETCH.latency_hist::gmean 49.781061 +system.ruby.IFETCH.latency_hist::stdev 21.417457 +system.ruby.IFETCH.latency_hist | 1 2.08% 2.08% | 4 8.33% 10.42% | 17 35.42% 45.83% | 1 2.08% 47.92% | 21 43.75% 91.67% | 3 6.25% 97.92% | 0 0.00% 97.92% | 1 2.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 48 +system.ruby.IFETCH.hit_latency_hist::bucket_size 4 +system.ruby.IFETCH.hit_latency_hist::max_bucket 39 +system.ruby.IFETCH.hit_latency_hist::samples 5 +system.ruby.IFETCH.hit_latency_hist::mean 18.600000 +system.ruby.IFETCH.hit_latency_hist::gmean 12.255548 +system.ruby.IFETCH.hit_latency_hist::stdev 9.989995 +system.ruby.IFETCH.hit_latency_hist | 1 20.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 3 60.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 5 system.ruby.IFETCH.miss_latency_hist::bucket_size 16 system.ruby.IFETCH.miss_latency_hist::max_bucket 159 -system.ruby.IFETCH.miss_latency_hist::samples 45 -system.ruby.IFETCH.miss_latency_hist::mean 62.088889 -system.ruby.IFETCH.miss_latency_hist::gmean 59.644500 -system.ruby.IFETCH.miss_latency_hist::stdev 18.806215 -system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 16 35.56% 35.56% | 1 2.22% 37.78% | 26 57.78% 95.56% | 1 2.22% 97.78% | 0 0.00% 97.78% | 0 0.00% 97.78% | 0 0.00% 97.78% | 1 2.22% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 45 +system.ruby.IFETCH.miss_latency_hist::samples 43 +system.ruby.IFETCH.miss_latency_hist::mean 61.046512 +system.ruby.IFETCH.miss_latency_hist::gmean 58.593153 +system.ruby.IFETCH.miss_latency_hist::stdev 17.654021 +system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 17 39.53% 39.53% | 1 2.33% 41.86% | 21 48.84% 90.70% | 3 6.98% 97.67% | 0 0.00% 97.67% | 1 2.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 43 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist::samples 108 +system.ruby.L1Cache.hit_mach_latency_hist::samples 98 system.ruby.L1Cache.hit_mach_latency_hist::mean 1 system.ruby.L1Cache.hit_mach_latency_hist::gmean 1 -system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 108 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 108 +system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 98 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist::total 98 system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 256 system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 2559 -system.ruby.L2Cache.hit_mach_latency_hist::samples 60 -system.ruby.L2Cache.hit_mach_latency_hist::mean 408.083333 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 131.816321 -system.ruby.L2Cache.hit_mach_latency_hist::stdev 482.869786 -system.ruby.L2Cache.hit_mach_latency_hist | 38 63.33% 63.33% | 0 0.00% 63.33% | 0 0.00% 63.33% | 13 21.67% 85.00% | 7 11.67% 96.67% | 2 3.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 60 +system.ruby.L2Cache.hit_mach_latency_hist::samples 43 +system.ruby.L2Cache.hit_mach_latency_hist::mean 602.953488 +system.ruby.L2Cache.hit_mach_latency_hist::gmean 256.823422 +system.ruby.L2Cache.hit_mach_latency_hist::stdev 489.931188 +system.ruby.L2Cache.hit_mach_latency_hist | 18 41.86% 41.86% | 0 0.00% 41.86% | 0 0.00% 41.86% | 19 44.19% 86.05% | 4 9.30% 95.35% | 2 4.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 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+system.ruby.Directory.miss_mach_latency_hist | 74 8.77% 8.77% | 6 0.71% 9.48% | 5 0.59% 10.07% | 323 38.27% 48.34% | 399 47.27% 95.62% | 37 4.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 844 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 7 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 8 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 7 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 8 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 128 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 1279 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 2 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 481 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 254.748896 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 576.999133 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 2 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 3 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| 0 0.00% 2.86% | 9 25.71% 28.57% | 21 60.00% 88.57% | 4 11.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 35 +system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 41 +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1048.902439 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 1021.815979 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 175.914866 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 1 2.44% 2.44% | 0 0.00% 2.44% | 0 0.00% 2.44% | 13 31.71% 34.15% | 26 63.41% 97.56% | 1 2.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::total 41 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 101 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100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 760 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::samples 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::mean 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::gmean 1 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::stdev nan +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::total 1 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::bucket_size 4 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::max_bucket 39 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples 4 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0.00% | 0 0.00% 0.00% | 16 35.56% 35.56% | 1 2.22% 37.78% | 26 57.78% 95.56% | 1 2.22% 97.78% | 0 0.00% 97.78% | 0 0.00% 97.78% | 0 0.00% 97.78% | 1 2.22% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 45 -system.ruby.Directory_Controller.GETX 763 0.00% 0.00% -system.ruby.Directory_Controller.GETS 81 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 17 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 17 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 2 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 773 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 60 0.00% 0.00% -system.ruby.Directory_Controller.Ack_All_Tokens 2 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 843 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 775 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 763 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 80 0.00% 0.00% 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0.00% 0.00% system.ruby.L2Cache_Controller.Persistent_GETS 2 0.00% 0.00% -system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 17 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 80 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 763 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 2 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 823 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 17 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L2_Replacement 1 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 45 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 2 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L2_Replacement 2 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 11 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 13 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 47 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 816 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 17 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Persistent_GETX 15 0.00% 0.00% +system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 15 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 84 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 760 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 1 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 825 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 15 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 36 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L1_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.O.L1_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.O.L2_Replacement 1 0.00% 0.00% +system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 5 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 7 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 35 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 821 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 15 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Persistent_GETX 13 0.00% 0.00% system.ruby.L2Cache_Controller.I_L.Persistent_GETS 2 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index d67071da5..f22219b78 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 28761 # Number of ticks simulated -final_tick 28761 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000030 # Number of seconds simulated +sim_ticks 29631 # Number of ticks simulated +final_tick 29631 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 479465 # Simulator tick rate (ticks/s) -host_mem_usage 400116 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 551942 # Simulator tick rate (ticks/s) +host_mem_usage 451596 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 53504 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 53504 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 48384 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 48384 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 836 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 836 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 756 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 756 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 1860296930 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 1860296930 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1682278085 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1682278085 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 3542575015 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 3542575015 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 836 # Number of read requests accepted -system.mem_ctrls.writeReqs 756 # Number of write requests accepted -system.mem_ctrls.readBursts 836 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 756 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 44608 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 8896 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 40960 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 53504 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 48384 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 95 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 55872 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 55872 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 49984 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 49984 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 873 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 873 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 781 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 781 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 1885592791 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1885592791 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1686881982 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1686881982 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 3572474773 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 3572474773 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 873 # Number of read requests accepted +system.mem_ctrls.writeReqs 781 # Number of write requests accepted +system.mem_ctrls.readBursts 873 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 781 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 45696 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 10176 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 41088 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 55872 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 49984 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 113 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 214 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 207 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 220 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 56 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 201 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 228 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 232 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 53 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts @@ -51,10 +51,10 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 192 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 190 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 209 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 49 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 181 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 200 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 216 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 45 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts @@ -69,24 +69,24 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 28720 # Total gap between requests +system.mem_ctrls.totGap 29604 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 836 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 873 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 756 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 403 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 275 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 19 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 781 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 412 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 289 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 13 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -131,23 +131,23 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 22 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 37 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 26 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 38 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 41 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 53 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 52 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 42 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 40 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::29 40 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 41 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 40 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see @@ -180,71 +180,70 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 86 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 974.139535 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 941.546343 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 159.630983 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 1 1.16% 1.16% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 1 1.16% 2.33% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 1 1.16% 3.49% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 4 4.65% 8.14% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 2 2.33% 10.47% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 2 2.33% 12.79% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 75 87.21% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 86 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 89 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 957.842697 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 925.208115 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 187.944921 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 4 4.49% 4.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 1 1.12% 5.62% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 1 1.12% 6.74% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 5 5.62% 12.36% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1 1.12% 13.48% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 77 86.52% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 89 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 40 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 17.425000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 17.145937 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.802074 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 11 27.50% 27.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 12 30.00% 57.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 12 30.00% 87.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 4 10.00% 97.50% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 17.575000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 17.282559 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 3.868926 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 10 25.00% 25.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 14 35.00% 60.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 10 25.00% 85.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 4 10.00% 95.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::22-23 1 2.50% 97.50% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::38-39 1 2.50% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 40 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 39 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.102564 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.098366 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.383534 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 36 92.31% 92.31% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 2 5.13% 97.44% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 1 2.56% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 39 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 8301 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 21544 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3485 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 11.91 # Average queueing delay per DRAM burst +system.mem_ctrls.wrPerTurnAround::samples 40 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.050000 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.048573 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.220721 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 38 95.00% 95.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 2 5.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 40 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 8764 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 22330 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3570 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 12.27 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 30.91 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 1550.99 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 1424.15 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 1860.30 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1682.28 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 31.27 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 1542.17 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1386.66 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1885.59 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1686.88 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 23.24 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 12.12 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 11.13 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 22.88 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 12.05 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 10.83 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.73 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 24.75 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 613 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 635 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 87.95 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 96.07 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 18.04 # Average gap between requests -system.mem_ctrls.pageHitRate 91.90 # Row buffer hit rate, read and write combined +system.mem_ctrls.avgWrQLen 24.84 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 626 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 637 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 87.68 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 95.36 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 17.90 # Average gap between requests +system.mem_ctrls.pageHitRate 91.39 # Row buffer hit rate, read and write combined system.mem_ctrls_0.actEnergy 551880 # Energy for activate commands per rank (pJ) system.mem_ctrls_0.preEnergy 306600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 7101120 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 5515776 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7026240 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 5318784 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 16132140 # Energy for active background per rank (pJ) +system.mem_ctrls_0.actBackEnergy 16099308 # Energy for active background per rank (pJ) system.mem_ctrls_0.preBackEnergy 48600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 31181796 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 1317.577791 # Core power per rank (mW) +system.mem_ctrls_0.totalEnergy 30877092 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 1307.354221 # Core power per rank (mW) system.mem_ctrls_0.memoryStateTime::IDLE 11 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 780 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 22889 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 22841 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) @@ -263,315 +262,314 @@ system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 984 -system.ruby.outstanding_req_hist::mean 15.553862 -system.ruby.outstanding_req_hist::gmean 15.439623 -system.ruby.outstanding_req_hist::stdev 1.290526 -system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.51% | 3 0.30% 0.81% | 3 0.30% 1.12% | 6 0.61% 1.73% | 3 0.30% 2.03% | 263 26.73% 28.76% | 701 71.24% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 984 +system.ruby.outstanding_req_hist::samples 1005 +system.ruby.outstanding_req_hist::mean 15.587065 +system.ruby.outstanding_req_hist::gmean 15.474770 +system.ruby.outstanding_req_hist::stdev 1.278707 +system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 3 0.30% 0.80% | 3 0.30% 1.09% | 6 0.60% 1.69% | 5 0.50% 2.19% | 239 23.78% 25.97% | 744 74.03% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 1005 system.ruby.latency_hist::bucket_size 128 system.ruby.latency_hist::max_bucket 1279 -system.ruby.latency_hist::samples 970 -system.ruby.latency_hist::mean 458.965979 -system.ruby.latency_hist::gmean 231.018404 -system.ruby.latency_hist::stdev 243.305475 -system.ruby.latency_hist | 203 20.93% 20.93% | 13 1.34% 22.27% | 7 0.72% 22.99% | 124 12.78% 35.77% | 515 53.09% 88.87% | 65 6.70% 95.57% | 20 2.06% 97.63% | 23 2.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 970 +system.ruby.latency_hist::samples 990 +system.ruby.latency_hist::mean 463.933333 +system.ruby.latency_hist::gmean 252.592392 +system.ruby.latency_hist::stdev 232.151200 +system.ruby.latency_hist | 190 19.19% 19.19% | 9 0.91% 20.10% | 5 0.51% 20.61% | 142 14.34% 34.95% | 561 56.67% 91.62% | 42 4.24% 95.86% | 16 1.62% 97.47% | 25 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 990 system.ruby.hit_latency_hist::bucket_size 128 system.ruby.hit_latency_hist::max_bucket 1279 -system.ruby.hit_latency_hist::samples 136 -system.ruby.hit_latency_hist::mean 88.500000 -system.ruby.hit_latency_hist::gmean 4.693318 -system.ruby.hit_latency_hist::stdev 196.910696 -system.ruby.hit_latency_hist | 115 84.56% 84.56% | 1 0.74% 85.29% | 0 0.00% 85.29% | 7 5.15% 90.44% | 11 8.09% 98.53% | 1 0.74% 99.26% | 1 0.74% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 136 +system.ruby.hit_latency_hist::samples 120 +system.ruby.hit_latency_hist::mean 90.158333 +system.ruby.hit_latency_hist::gmean 4.686569 +system.ruby.hit_latency_hist::stdev 196.031167 +system.ruby.hit_latency_hist | 101 84.17% 84.17% | 0 0.00% 84.17% | 0 0.00% 84.17% | 8 6.67% 90.83% | 9 7.50% 98.33% | 2 1.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 120 system.ruby.miss_latency_hist::bucket_size 128 system.ruby.miss_latency_hist::max_bucket 1279 -system.ruby.miss_latency_hist::samples 834 -system.ruby.miss_latency_hist::mean 519.377698 -system.ruby.miss_latency_hist::gmean 436.101337 -system.ruby.miss_latency_hist::stdev 191.094943 -system.ruby.miss_latency_hist | 88 10.55% 10.55% | 12 1.44% 11.99% | 7 0.84% 12.83% | 117 14.03% 26.86% | 504 60.43% 87.29% | 64 7.67% 94.96% | 19 2.28% 97.24% | 23 2.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 834 -system.ruby.Directory.incomplete_times 834 +system.ruby.miss_latency_hist::samples 870 +system.ruby.miss_latency_hist::mean 515.488506 +system.ruby.miss_latency_hist::gmean 437.780939 +system.ruby.miss_latency_hist::stdev 184.718401 +system.ruby.miss_latency_hist | 89 10.23% 10.23% | 9 1.03% 11.26% | 5 0.57% 11.84% | 134 15.40% 27.24% | 552 63.45% 90.69% | 40 4.60% 95.29% | 16 1.84% 97.13% | 25 2.87% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 870 +system.ruby.Directory.incomplete_times 870 system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Dcache.demand_hits 87 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 832 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 919 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Dcache.demand_hits 77 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 864 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 941 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 49 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 50 # Number of cache demand accesses -system.ruby.l1_cntrl0.L2cache.demand_hits 45 # Number of cache demand hits -system.ruby.l1_cntrl0.L2cache.demand_misses 836 # Number of cache demand misses -system.ruby.l1_cntrl0.L2cache.demand_accesses 881 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_misses 48 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 49 # Number of cache demand accesses +system.ruby.l1_cntrl0.L2cache.demand_hits 39 # Number of cache demand hits +system.ruby.l1_cntrl0.L2cache.demand_misses 873 # Number of cache demand misses +system.ruby.l1_cntrl0.L2cache.demand_accesses 912 # Number of cache demand accesses system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 2 # Number of times a store aliased with a pending load -system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 77 # Number of times a store aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 5 # Number of times a load aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 2 # Number of times a load aliased with a pending load +system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 82 # Number of times a store aliased with a pending store +system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 7 # Number of times a load aliased with a pending store system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 15.412364 -system.ruby.network.routers0.msg_count.Request_Control::2 838 -system.ruby.network.routers0.msg_count.Response_Data::4 836 -system.ruby.network.routers0.msg_count.Writeback_Data::5 756 -system.ruby.network.routers0.msg_count.Writeback_Control::2 830 -system.ruby.network.routers0.msg_count.Writeback_Control::3 830 -system.ruby.network.routers0.msg_count.Writeback_Control::5 73 -system.ruby.network.routers0.msg_count.Unblock_Control::5 832 -system.ruby.network.routers0.msg_bytes.Request_Control::2 6704 -system.ruby.network.routers0.msg_bytes.Response_Data::4 60192 -system.ruby.network.routers0.msg_bytes.Writeback_Data::5 54432 -system.ruby.network.routers0.msg_bytes.Writeback_Control::2 6640 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 6640 -system.ruby.network.routers0.msg_bytes.Writeback_Control::5 584 -system.ruby.network.routers0.msg_bytes.Unblock_Control::5 6656 -system.ruby.network.routers1.percent_links_utilized 15.410625 -system.ruby.network.routers1.msg_count.Request_Control::2 837 -system.ruby.network.routers1.msg_count.Response_Data::4 836 -system.ruby.network.routers1.msg_count.Writeback_Data::5 756 -system.ruby.network.routers1.msg_count.Writeback_Control::2 829 -system.ruby.network.routers1.msg_count.Writeback_Control::3 830 -system.ruby.network.routers1.msg_count.Writeback_Control::5 73 -system.ruby.network.routers1.msg_count.Unblock_Control::5 832 -system.ruby.network.routers1.msg_bytes.Request_Control::2 6696 -system.ruby.network.routers1.msg_bytes.Response_Data::4 60192 -system.ruby.network.routers1.msg_bytes.Writeback_Data::5 54432 -system.ruby.network.routers1.msg_bytes.Writeback_Control::2 6632 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 6640 -system.ruby.network.routers1.msg_bytes.Writeback_Control::5 584 -system.ruby.network.routers1.msg_bytes.Unblock_Control::5 6656 -system.ruby.network.routers2.percent_links_utilized 15.410625 -system.ruby.network.routers2.msg_count.Request_Control::2 837 -system.ruby.network.routers2.msg_count.Response_Data::4 836 -system.ruby.network.routers2.msg_count.Writeback_Data::5 756 -system.ruby.network.routers2.msg_count.Writeback_Control::2 829 -system.ruby.network.routers2.msg_count.Writeback_Control::3 830 -system.ruby.network.routers2.msg_count.Writeback_Control::5 73 -system.ruby.network.routers2.msg_count.Unblock_Control::5 832 -system.ruby.network.routers2.msg_bytes.Request_Control::2 6696 -system.ruby.network.routers2.msg_bytes.Response_Data::4 60192 -system.ruby.network.routers2.msg_bytes.Writeback_Data::5 54432 -system.ruby.network.routers2.msg_bytes.Writeback_Control::2 6632 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 6640 -system.ruby.network.routers2.msg_bytes.Writeback_Control::5 584 -system.ruby.network.routers2.msg_bytes.Unblock_Control::5 6656 -system.ruby.network.msg_count.Request_Control 2512 -system.ruby.network.msg_count.Response_Data 2508 -system.ruby.network.msg_count.Writeback_Data 2268 -system.ruby.network.msg_count.Writeback_Control 5197 -system.ruby.network.msg_count.Unblock_Control 2496 -system.ruby.network.msg_byte.Request_Control 20096 -system.ruby.network.msg_byte.Response_Data 180576 -system.ruby.network.msg_byte.Writeback_Data 163296 -system.ruby.network.msg_byte.Writeback_Control 41576 -system.ruby.network.msg_byte.Unblock_Control 19968 -system.ruby.network.routers0.throttle0.link_utilization 14.523139 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 836 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 830 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 60192 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 6640 -system.ruby.network.routers0.throttle1.link_utilization 16.301589 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 838 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 756 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 830 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 73 -system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 832 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 6704 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 54432 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 6640 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 584 -system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 6656 -system.ruby.network.routers1.throttle0.link_utilization 16.298112 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 837 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 756 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 829 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5 73 -system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5 832 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 6696 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 54432 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 6632 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 584 -system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 6656 -system.ruby.network.routers1.throttle1.link_utilization 14.523139 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 836 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 830 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 60192 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 6640 -system.ruby.network.routers2.throttle0.link_utilization 14.523139 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 836 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 830 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 60192 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 6640 -system.ruby.network.routers2.throttle1.link_utilization 16.298112 -system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 837 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 756 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 829 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 73 -system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 832 -system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 6696 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 54432 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 6632 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 584 -system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 6656 +system.ruby.network.routers0.percent_links_utilized 15.551281 +system.ruby.network.routers0.msg_count.Request_Control::2 874 +system.ruby.network.routers0.msg_count.Response_Data::4 872 +system.ruby.network.routers0.msg_count.Writeback_Data::5 781 +system.ruby.network.routers0.msg_count.Writeback_Control::2 865 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-system.ruby.LD.latency_hist::gmean 175.856196 -system.ruby.LD.latency_hist::stdev 273.498848 -system.ruby.LD.latency_hist | 13 26.00% 26.00% | 1 2.00% 28.00% | 0 0.00% 28.00% | 6 12.00% 40.00% | 23 46.00% 86.00% | 3 6.00% 92.00% | 3 6.00% 98.00% | 1 2.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 50 -system.ruby.LD.hit_latency_hist::bucket_size 4 -system.ruby.LD.hit_latency_hist::max_bucket 39 -system.ruby.LD.hit_latency_hist::samples 8 -system.ruby.LD.hit_latency_hist::mean 4.375000 -system.ruby.LD.hit_latency_hist::gmean 1.516683 -system.ruby.LD.hit_latency_hist::stdev 9.545942 -system.ruby.LD.hit_latency_hist | 7 87.50% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 8 +system.ruby.LD.latency_hist::samples 52 +system.ruby.LD.latency_hist::mean 503.461538 +system.ruby.LD.latency_hist::gmean 317.197338 +system.ruby.LD.latency_hist::stdev 193.436970 +system.ruby.LD.latency_hist | 6 11.54% 11.54% | 0 0.00% 11.54% | 0 0.00% 11.54% | 8 15.38% 26.92% | 34 65.38% 92.31% | 2 3.85% 96.15% | 2 3.85% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 52 +system.ruby.LD.hit_latency_hist::bucket_size 8 +system.ruby.LD.hit_latency_hist::max_bucket 79 +system.ruby.LD.hit_latency_hist::samples 5 +system.ruby.LD.hit_latency_hist::mean 15.200000 +system.ruby.LD.hit_latency_hist::gmean 2.352158 +system.ruby.LD.hit_latency_hist::stdev 31.752165 +system.ruby.LD.hit_latency_hist | 4 80.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% +system.ruby.LD.hit_latency_hist::total 5 system.ruby.LD.miss_latency_hist::bucket_size 128 system.ruby.LD.miss_latency_hist::max_bucket 1279 -system.ruby.LD.miss_latency_hist::samples 42 -system.ruby.LD.miss_latency_hist::mean 525.142857 -system.ruby.LD.miss_latency_hist::gmean 434.861152 -system.ruby.LD.miss_latency_hist::stdev 211.970036 -system.ruby.LD.miss_latency_hist | 5 11.90% 11.90% | 1 2.38% 14.29% | 0 0.00% 14.29% | 6 14.29% 28.57% | 23 54.76% 83.33% | 3 7.14% 90.48% | 3 7.14% 97.62% | 1 2.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 42 +system.ruby.LD.miss_latency_hist::samples 47 +system.ruby.LD.miss_latency_hist::mean 555.404255 +system.ruby.LD.miss_latency_hist::gmean 534.454462 +system.ruby.LD.miss_latency_hist::stdev 112.817024 +system.ruby.LD.miss_latency_hist | 1 2.13% 2.13% | 0 0.00% 2.13% | 0 0.00% 2.13% | 8 17.02% 19.15% | 34 72.34% 91.49% | 2 4.26% 95.74% | 2 4.26% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 47 system.ruby.ST.latency_hist::bucket_size 128 system.ruby.ST.latency_hist::max_bucket 1279 -system.ruby.ST.latency_hist::samples 867 -system.ruby.ST.latency_hist::mean 483.565167 -system.ruby.ST.latency_hist::gmean 261.040314 -system.ruby.ST.latency_hist::stdev 226.674934 -system.ruby.ST.latency_hist | 141 16.26% 16.26% | 11 1.27% 17.53% | 6 0.69% 18.22% | 118 13.61% 31.83% | 491 56.63% 88.47% | 61 7.04% 95.50% | 17 1.96% 97.46% | 22 2.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 867 +system.ruby.ST.latency_hist::samples 887 +system.ruby.ST.latency_hist::mean 483.905299 +system.ruby.ST.latency_hist::gmean 275.171473 +system.ruby.ST.latency_hist::stdev 219.222904 +system.ruby.ST.latency_hist | 137 15.45% 15.45% | 7 0.79% 16.23% | 5 0.56% 16.80% | 134 15.11% 31.91% | 526 59.30% 91.21% | 39 4.40% 95.60% | 14 1.58% 97.18% | 25 2.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 887 system.ruby.ST.hit_latency_hist::bucket_size 128 system.ruby.ST.hit_latency_hist::max_bucket 1279 -system.ruby.ST.hit_latency_hist::samples 116 -system.ruby.ST.hit_latency_hist::mean 91.603448 -system.ruby.ST.hit_latency_hist::gmean 4.370982 -system.ruby.ST.hit_latency_hist::stdev 198.852092 -system.ruby.ST.hit_latency_hist | 97 83.62% 83.62% | 1 0.86% 84.48% | 0 0.00% 84.48% | 7 6.03% 90.52% | 10 8.62% 99.14% | 0 0.00% 99.14% | 1 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 116 +system.ruby.ST.hit_latency_hist::samples 105 +system.ruby.ST.hit_latency_hist::mean 89.133333 +system.ruby.ST.hit_latency_hist::gmean 4.172115 +system.ruby.ST.hit_latency_hist::stdev 193.552272 +system.ruby.ST.hit_latency_hist | 88 83.81% 83.81% | 0 0.00% 83.81% | 0 0.00% 83.81% | 8 7.62% 91.43% | 8 7.62% 99.05% | 1 0.95% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 105 system.ruby.ST.miss_latency_hist::bucket_size 128 system.ruby.ST.miss_latency_hist::max_bucket 1279 -system.ruby.ST.miss_latency_hist::samples 751 -system.ruby.ST.miss_latency_hist::mean 544.107856 -system.ruby.ST.miss_latency_hist::gmean 490.964033 -system.ruby.ST.miss_latency_hist::stdev 160.726610 -system.ruby.ST.miss_latency_hist | 44 5.86% 5.86% | 10 1.33% 7.19% | 6 0.80% 7.99% | 111 14.78% 22.77% | 481 64.05% 86.82% | 61 8.12% 94.94% | 16 2.13% 97.07% | 22 2.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 751 +system.ruby.ST.miss_latency_hist::samples 782 +system.ruby.ST.miss_latency_hist::mean 536.911765 +system.ruby.ST.miss_latency_hist::gmean 482.920590 +system.ruby.ST.miss_latency_hist::stdev 160.516950 +system.ruby.ST.miss_latency_hist | 49 6.27% 6.27% | 7 0.90% 7.16% | 5 0.64% 7.80% | 126 16.11% 23.91% | 518 66.24% 90.15% | 38 4.86% 95.01% | 14 1.79% 96.80% | 25 3.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 782 system.ruby.IFETCH.latency_hist::bucket_size 32 system.ruby.IFETCH.latency_hist::max_bucket 319 -system.ruby.IFETCH.latency_hist::samples 50 -system.ruby.IFETCH.latency_hist::mean 51.380000 -system.ruby.IFETCH.latency_hist::gmean 36.237672 -system.ruby.IFETCH.latency_hist::stdev 50.797674 -system.ruby.IFETCH.latency_hist | 22 44.00% 44.00% | 18 36.00% 80.00% | 6 12.00% 92.00% | 2 4.00% 96.00% | 0 0.00% 96.00% | 1 2.00% 98.00% | 0 0.00% 98.00% | 0 0.00% 98.00% | 0 0.00% 98.00% | 1 2.00% 100.00% -system.ruby.IFETCH.latency_hist::total 50 +system.ruby.IFETCH.latency_hist::samples 48 +system.ruby.IFETCH.latency_hist::mean 53.604167 +system.ruby.IFETCH.latency_hist::gmean 40.463792 +system.ruby.IFETCH.latency_hist::stdev 35.834572 +system.ruby.IFETCH.latency_hist | 19 39.58% 39.58% | 18 37.50% 77.08% | 5 10.42% 87.50% | 4 8.33% 95.83% | 1 2.08% 97.92% | 1 2.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 48 system.ruby.IFETCH.hit_latency_hist::bucket_size 2 system.ruby.IFETCH.hit_latency_hist::max_bucket 19 -system.ruby.IFETCH.hit_latency_hist::samples 9 -system.ruby.IFETCH.hit_latency_hist::mean 9.888889 -system.ruby.IFETCH.hit_latency_hist::gmean 8.427182 -system.ruby.IFETCH.hit_latency_hist::stdev 3.333333 -system.ruby.IFETCH.hit_latency_hist | 1 11.11% 11.11% | 0 0.00% 11.11% | 0 0.00% 11.11% | 0 0.00% 11.11% | 0 0.00% 11.11% | 8 88.89% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 9 +system.ruby.IFETCH.hit_latency_hist::samples 7 +system.ruby.IFETCH.hit_latency_hist::mean 9.571429 +system.ruby.IFETCH.hit_latency_hist::gmean 7.809483 +system.ruby.IFETCH.hit_latency_hist::stdev 3.779645 +system.ruby.IFETCH.hit_latency_hist | 1 14.29% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 6 85.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 7 system.ruby.IFETCH.miss_latency_hist::bucket_size 32 system.ruby.IFETCH.miss_latency_hist::max_bucket 319 system.ruby.IFETCH.miss_latency_hist::samples 41 -system.ruby.IFETCH.miss_latency_hist::mean 60.487805 -system.ruby.IFETCH.miss_latency_hist::gmean 49.913314 -system.ruby.IFETCH.miss_latency_hist::stdev 51.830552 -system.ruby.IFETCH.miss_latency_hist | 13 31.71% 31.71% | 18 43.90% 75.61% | 6 14.63% 90.24% | 2 4.88% 95.12% | 0 0.00% 95.12% | 1 2.44% 97.56% | 0 0.00% 97.56% | 0 0.00% 97.56% | 0 0.00% 97.56% | 1 2.44% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 61.121951 +system.ruby.IFETCH.miss_latency_hist::gmean 53.585201 +system.ruby.IFETCH.miss_latency_hist::stdev 33.308554 +system.ruby.IFETCH.miss_latency_hist | 12 29.27% 29.27% | 18 43.90% 73.17% | 5 12.20% 85.37% | 4 9.76% 95.12% | 1 2.44% 97.56% | 1 2.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 41 system.ruby.FLUSH.latency_hist::bucket_size 128 system.ruby.FLUSH.latency_hist::max_bucket 1279 system.ruby.FLUSH.latency_hist::samples 3 -system.ruby.FLUSH.latency_hist::mean 428.666667 -system.ruby.FLUSH.latency_hist::gmean 258.188343 -system.ruby.FLUSH.latency_hist::stdev 336.080843 +system.ruby.FLUSH.latency_hist::mean 439 +system.ruby.FLUSH.latency_hist::gmean 262.927467 +system.ruby.FLUSH.latency_hist::stdev 342.057013 system.ruby.FLUSH.latency_hist | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.FLUSH.latency_hist::total 3 system.ruby.FLUSH.hit_latency_hist::bucket_size 128 system.ruby.FLUSH.hit_latency_hist::max_bucket 1279 system.ruby.FLUSH.hit_latency_hist::samples 3 -system.ruby.FLUSH.hit_latency_hist::mean 428.666667 -system.ruby.FLUSH.hit_latency_hist::gmean 258.188343 -system.ruby.FLUSH.hit_latency_hist::stdev 336.080843 +system.ruby.FLUSH.hit_latency_hist::mean 439 +system.ruby.FLUSH.hit_latency_hist::gmean 262.927467 +system.ruby.FLUSH.hit_latency_hist::stdev 342.057013 system.ruby.FLUSH.hit_latency_hist | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.FLUSH.hit_latency_hist::total 3 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 128 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 1279 -system.ruby.L1Cache.hit_mach_latency_hist::samples 91 -system.ruby.L1Cache.hit_mach_latency_hist::mean 15.098901 -system.ruby.L1Cache.hit_mach_latency_hist::gmean 1.200921 -system.ruby.L1Cache.hit_mach_latency_hist::stdev 91.682308 -system.ruby.L1Cache.hit_mach_latency_hist | 89 97.80% 97.80% | 0 0.00% 97.80% | 0 0.00% 97.80% | 0 0.00% 97.80% | 1 1.10% 98.90% | 1 1.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 91 +system.ruby.L1Cache.hit_mach_latency_hist::samples 81 +system.ruby.L1Cache.hit_mach_latency_hist::mean 17.222222 +system.ruby.L1Cache.hit_mach_latency_hist::gmean 1.229203 +system.ruby.L1Cache.hit_mach_latency_hist::stdev 99.261145 +system.ruby.L1Cache.hit_mach_latency_hist | 79 97.53% 97.53% | 0 0.00% 97.53% | 0 0.00% 97.53% | 0 0.00% 97.53% | 1 1.23% 98.77% | 1 1.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist::total 81 system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 128 system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 1279 -system.ruby.L2Cache.hit_mach_latency_hist::samples 45 -system.ruby.L2Cache.hit_mach_latency_hist::mean 236.933333 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 73.886639 -system.ruby.L2Cache.hit_mach_latency_hist::stdev 260.951702 -system.ruby.L2Cache.hit_mach_latency_hist | 26 57.78% 57.78% | 1 2.22% 60.00% | 0 0.00% 60.00% | 7 15.56% 75.56% | 10 22.22% 97.78% | 0 0.00% 97.78% | 1 2.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 45 +system.ruby.L2Cache.hit_mach_latency_hist::samples 39 +system.ruby.L2Cache.hit_mach_latency_hist::mean 241.641026 +system.ruby.L2Cache.hit_mach_latency_hist::gmean 75.514116 +system.ruby.L2Cache.hit_mach_latency_hist::stdev 254.377929 +system.ruby.L2Cache.hit_mach_latency_hist | 22 56.41% 56.41% | 0 0.00% 56.41% | 0 0.00% 56.41% | 8 20.51% 76.92% | 8 20.51% 97.44% | 1 2.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist::total 39 system.ruby.Directory.miss_mach_latency_hist::bucket_size 128 system.ruby.Directory.miss_mach_latency_hist::max_bucket 1279 -system.ruby.Directory.miss_mach_latency_hist::samples 834 -system.ruby.Directory.miss_mach_latency_hist::mean 519.377698 -system.ruby.Directory.miss_mach_latency_hist::gmean 436.101337 -system.ruby.Directory.miss_mach_latency_hist::stdev 191.094943 -system.ruby.Directory.miss_mach_latency_hist | 88 10.55% 10.55% | 12 1.44% 11.99% | 7 0.84% 12.83% | 117 14.03% 26.86% | 504 60.43% 87.29% | 64 7.67% 94.96% | 19 2.28% 97.24% | 23 2.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 834 +system.ruby.Directory.miss_mach_latency_hist::samples 870 +system.ruby.Directory.miss_mach_latency_hist::mean 515.488506 +system.ruby.Directory.miss_mach_latency_hist::gmean 437.780939 +system.ruby.Directory.miss_mach_latency_hist::stdev 184.718401 +system.ruby.Directory.miss_mach_latency_hist | 89 10.23% 10.23% | 9 1.03% 11.26% | 5 0.57% 11.84% | 134 15.40% 27.24% | 552 63.45% 90.69% | 40 4.60% 95.29% | 16 1.84% 97.13% | 25 2.87% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 870 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 7 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 4 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 7 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 4 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 39 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 4 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 8 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 79 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 1 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 28 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 28.000000 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 72 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 72 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev nan -system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 1 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 128 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 1279 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 42 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 525.142857 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 434.861152 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 211.970036 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 5 11.90% 11.90% | 1 2.38% 14.29% | 0 0.00% 14.29% | 6 14.29% 28.57% | 23 54.76% 83.33% | 3 7.14% 90.48% | 3 7.14% 97.62% | 1 2.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 42 +system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 47 +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 555.404255 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 534.454462 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 112.817024 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 1 2.13% 2.13% | 0 0.00% 2.13% | 0 0.00% 2.13% | 8 17.02% 19.15% | 34 72.34% 91.49% | 2 4.26% 95.74% | 2 4.26% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::total 47 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 80 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 73 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 80 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 80 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 73 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 73 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 128 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 1279 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 36 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 292.944444 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 115.901207 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 263.560993 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 17 47.22% 47.22% | 1 2.78% 50.00% | 0 0.00% 50.00% | 7 19.44% 69.44% | 10 27.78% 97.22% | 0 0.00% 97.22% | 1 2.78% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 36 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 32 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 290.187500 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 108.528557 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 256.247290 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 15 46.88% 46.88% | 0 0.00% 46.88% | 0 0.00% 46.88% | 8 25.00% 71.88% | 8 25.00% 96.88% | 1 3.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 32 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 128 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 1279 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 751 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 544.107856 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 490.964033 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 160.726610 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 44 5.86% 5.86% | 10 1.33% 7.19% | 6 0.80% 7.99% | 111 14.78% 22.77% | 481 64.05% 86.82% | 61 8.12% 94.94% | 16 2.13% 97.07% | 22 2.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 751 +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 782 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 536.911765 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 482.920590 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 160.516950 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 49 6.27% 6.27% | 7 0.90% 7.16% | 5 0.64% 7.80% | 126 16.11% 23.91% | 518 66.24% 90.15% | 38 4.86% 95.01% | 14 1.79% 96.80% | 25 3.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 782 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::samples 1 @@ -582,102 +580,103 @@ system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist | 0 0.00% system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::total 1 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::bucket_size 2 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::max_bucket 19 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples 8 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples 6 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 11 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 11.000000 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 8 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 6 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 32 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 41 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 60.487805 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 49.913314 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 51.830552 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 13 31.71% 31.71% | 18 43.90% 75.61% | 6 14.63% 90.24% | 2 4.88% 95.12% | 0 0.00% 95.12% | 1 2.44% 97.56% | 0 0.00% 97.56% | 0 0.00% 97.56% | 0 0.00% 97.56% | 1 2.44% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 61.121951 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 53.585201 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 33.308554 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 12 29.27% 29.27% | 18 43.90% 73.17% | 5 12.20% 85.37% | 4 9.76% 95.12% | 1 2.44% 97.56% | 1 2.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 41 system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::bucket_size 128 system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::max_bucket 1279 system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::samples 3 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::mean 428.666667 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::gmean 258.188343 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::stdev 336.080843 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::mean 439 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::gmean 262.927467 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::stdev 342.057013 system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::total 3 -system.ruby.Directory_Controller.GETX 751 0.00% 0.00% -system.ruby.Directory_Controller.GETS 84 0.00% 0.00% -system.ruby.Directory_Controller.PUT 1063 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 832 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 73 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 756 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 836 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 756 0.00% 0.00% +system.ruby.Directory_Controller.GETX 782 0.00% 0.00% +system.ruby.Directory_Controller.GETS 93 0.00% 0.00% +system.ruby.Directory_Controller.PUT 1119 0.00% 0.00% +system.ruby.Directory_Controller.UnblockM 869 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Clean 84 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 781 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 873 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 781 0.00% 0.00% system.ruby.Directory_Controller.GETF 3 0.00% 0.00% system.ruby.Directory_Controller.PUTF 3 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 826 0.00% 0.00% +system.ruby.Directory_Controller.NO.PUT 862 0.00% 0.00% system.ruby.Directory_Controller.NO.GETF 1 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 751 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 83 0.00% 0.00% +system.ruby.Directory_Controller.E.GETX 782 0.00% 0.00% +system.ruby.Directory_Controller.E.GETS 89 0.00% 0.00% system.ruby.Directory_Controller.E.GETF 2 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.PUT 237 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 832 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 834 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 73 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 756 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 756 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.PUT 257 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockM 869 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.Memory_Data 871 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETS 3 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 84 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 781 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.GETS 1 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.Memory_Ack 781 0.00% 0.00% system.ruby.Directory_Controller.NO_F.PUTF 3 0.00% 0.00% system.ruby.Directory_Controller.NO_F_W.Memory_Data 2 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 51 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 53 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 50 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 901 0.00% 0.00% -system.ruby.L1Cache_Controller.L2_Replacement 828 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_to_L2 17754 0.00% 0.00% -system.ruby.L1Cache_Controller.Trigger_L2_to_L1D 38 0.00% 0.00% -system.ruby.L1Cache_Controller.Trigger_L2_to_L1I 8 0.00% 0.00% -system.ruby.L1Cache_Controller.Complete_L2_to_L1 46 0.00% 0.00% -system.ruby.L1Cache_Controller.Exclusive_Data 836 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 829 0.00% 0.00% -system.ruby.L1Cache_Controller.All_acks_no_sharers 836 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 916 0.00% 0.00% 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0.00% 0.00% -system.ruby.L1Cache_Controller.M.L2_Replacement 72 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_to_L2 82 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D 9 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Load 7 0.00% 0.00% +system.ruby.L1Cache_Controller.M.L2_Replacement 82 0.00% 0.00% +system.ruby.L1Cache_Controller.M.L1_to_L2 88 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D 5 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Load 4 0.00% 0.00% system.ruby.L1Cache_Controller.MM.Ifetch 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Store 80 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L2_Replacement 756 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L1_to_L2 794 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Store 73 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.L2_Replacement 783 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.L1_to_L2 819 0.00% 0.00% system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D 29 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1I 8 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1I 6 0.00% 0.00% system.ruby.L1Cache_Controller.MR.Load 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MR.Store 8 0.00% 0.00% -system.ruby.L1Cache_Controller.MR.L1_to_L2 114 0.00% 0.00% -system.ruby.L1Cache_Controller.MMR.Ifetch 8 0.00% 0.00% +system.ruby.L1Cache_Controller.MR.Store 4 0.00% 0.00% +system.ruby.L1Cache_Controller.MR.L1_to_L2 53 0.00% 0.00% +system.ruby.L1Cache_Controller.MMR.Ifetch 6 0.00% 0.00% system.ruby.L1Cache_Controller.MMR.Store 28 0.00% 0.00% -system.ruby.L1Cache_Controller.MMR.L1_to_L2 14 0.00% 0.00% system.ruby.L1Cache_Controller.MMR.Flush_line 1 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.L1_to_L2 10325 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data 751 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.L1_to_L2 256 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 83 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.L1_to_L2 5274 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers 751 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.L1_to_L2 580 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data 83 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.L1_to_L2 10628 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Exclusive_Data 782 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.L1_to_L2 348 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 88 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.L1_to_L2 5413 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers 782 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.L1_to_L2 644 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Exclusive_Data 88 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Ifetch 1 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Store 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 826 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 862 0.00% 0.00% system.ruby.L1Cache_Controller.MT.Load 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MT.Store 8 0.00% 0.00% -system.ruby.L1Cache_Controller.MT.L1_to_L2 117 0.00% 0.00% -system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 9 0.00% 0.00% +system.ruby.L1Cache_Controller.MT.Store 3 0.00% 0.00% +system.ruby.L1Cache_Controller.MT.L1_to_L2 56 0.00% 0.00% +system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 5 0.00% 0.00% system.ruby.L1Cache_Controller.MMT.Store 23 0.00% 0.00% -system.ruby.L1Cache_Controller.MMT.L1_to_L2 198 0.00% 0.00% -system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 37 0.00% 0.00% +system.ruby.L1Cache_Controller.MMT.L1_to_L2 159 0.00% 0.00% +system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 35 0.00% 0.00% system.ruby.L1Cache_Controller.MI_F.Writeback_Ack 3 0.00% 0.00% system.ruby.L1Cache_Controller.MM_F.Block_Ack 1 0.00% 0.00% system.ruby.L1Cache_Controller.IM_F.Exclusive_Data 2 0.00% 0.00% diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt index e85a7a6f9..e6e71a4ae 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 8340026204 # Simulator tick rate (ticks/s) -host_mem_usage 263964 # Number of bytes of host memory used -host_seconds 11.99 # Real time elapsed on the host +host_tick_rate 8352384426 # Simulator tick rate (ticks/s) +host_mem_usage 264628 # Number of bytes of host memory used +host_seconds 11.97 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu 106649408 # Number of bytes read from this memory @@ -285,7 +285,7 @@ system.membus.pkt_size_system.monitor-master::system.physmem.port 213329664 system.membus.pkt_size::total 213329664 # Cumulative packet size per connected master and slave (bytes) system.membus.reqLayer0.occupancy 11679751447 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 11.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 11025639931 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 11025969759 # Layer occupancy (ticks) system.membus.respLayer0.utilization 11.0 # Layer utilization (%) system.monitor.readBurstLengthHist::samples 1666397 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets @@ -392,21 +392,21 @@ system.monitor.writeBandwidthHist::total 100 # Hi system.monitor.averageWriteBandwidth 1066802560 0.00% 0.00% # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 106680256 # Number of bytes written system.monitor.readLatencyHist::samples 1666397 # Read request-response latency -system.monitor.readLatencyHist::mean 80828.076592 # Read request-response latency -system.monitor.readLatencyHist::gmean 75646.741335 # Read request-response latency -system.monitor.readLatencyHist::stdev 40157.798719 # Read request-response latency +system.monitor.readLatencyHist::mean 80828.757102 # Read request-response latency +system.monitor.readLatencyHist::gmean 75647.211665 # Read request-response latency +system.monitor.readLatencyHist::stdev 40158.670662 # Read request-response latency system.monitor.readLatencyHist::0-32767 22 0.00% 0.00% # Read request-response latency -system.monitor.readLatencyHist::32768-65535 453129 27.19% 27.19% # Read request-response latency -system.monitor.readLatencyHist::65536-98303 1001108 60.08% 87.27% # Read request-response latency +system.monitor.readLatencyHist::32768-65535 453126 27.19% 27.19% # Read request-response latency +system.monitor.readLatencyHist::65536-98303 1001111 60.08% 87.27% # Read request-response latency system.monitor.readLatencyHist::98304-131071 83302 5.00% 92.27% # Read request-response latency system.monitor.readLatencyHist::131072-163839 62543 3.75% 96.02% # Read request-response latency system.monitor.readLatencyHist::163840-196607 26583 1.60% 97.62% # Read request-response latency system.monitor.readLatencyHist::196608-229375 8788 0.53% 98.14% # Read request-response latency -system.monitor.readLatencyHist::229376-262143 7679 0.46% 98.61% # Read request-response latency +system.monitor.readLatencyHist::229376-262143 7677 0.46% 98.61% # Read request-response latency system.monitor.readLatencyHist::262144-294911 7849 0.47% 99.08% # Read request-response latency -system.monitor.readLatencyHist::294912-327679 7873 0.47% 99.55% # Read request-response latency +system.monitor.readLatencyHist::294912-327679 7874 0.47% 99.55% # Read request-response latency system.monitor.readLatencyHist::327680-360447 4044 0.24% 99.79% # Read request-response latency -system.monitor.readLatencyHist::360448-393215 1554 0.09% 99.88% # Read request-response latency +system.monitor.readLatencyHist::360448-393215 1555 0.09% 99.88% # Read request-response latency system.monitor.readLatencyHist::393216-425983 891 0.05% 99.94% # Read request-response latency system.monitor.readLatencyHist::425984-458751 671 0.04% 99.98% # Read request-response latency system.monitor.readLatencyHist::458752-491519 316 0.02% 100.00% # Read request-response latency @@ -417,9 +417,9 @@ system.monitor.readLatencyHist::589824-622591 0 0.00% 100.00% system.monitor.readLatencyHist::622592-655359 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::total 1666397 # Read request-response latency system.monitor.writeLatencyHist::samples 1666878 # Write request-response latency -system.monitor.writeLatencyHist::mean 19578.682028 # Write request-response latency -system.monitor.writeLatencyHist::gmean 19571.486505 # Write request-response latency -system.monitor.writeLatencyHist::stdev 552.701557 # Write request-response latency +system.monitor.writeLatencyHist::mean 19652.383883 # Write request-response latency +system.monitor.writeLatencyHist::gmean 19632.845881 # Write request-response latency +system.monitor.writeLatencyHist::stdev 964.266043 # Write request-response latency system.monitor.writeLatencyHist::0-2047 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::2048-4095 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::4096-6143 0 0.00% 0.00% # Write request-response latency @@ -429,13 +429,13 @@ system.monitor.writeLatencyHist::10240-12287 0 0.00% 0.00% system.monitor.writeLatencyHist::12288-14335 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::14336-16383 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::16384-18431 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::18432-20479 1622054 97.31% 97.31% # Write request-response latency -system.monitor.writeLatencyHist::20480-22527 29447 1.77% 99.08% # Write request-response latency -system.monitor.writeLatencyHist::22528-24575 12825 0.77% 99.85% # Write request-response latency -system.monitor.writeLatencyHist::24576-26623 2552 0.15% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::26624-28671 0 0.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::28672-30719 0 0.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::30720-32767 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::18432-20479 1607382 96.43% 96.43% # Write request-response latency +system.monitor.writeLatencyHist::20480-22527 29447 1.77% 98.20% # Write request-response latency +system.monitor.writeLatencyHist::22528-24575 12825 0.77% 98.97% # Write request-response latency +system.monitor.writeLatencyHist::24576-26623 7107 0.43% 99.39% # Write request-response latency +system.monitor.writeLatencyHist::26624-28671 4858 0.29% 99.68% # Write request-response latency +system.monitor.writeLatencyHist::28672-30719 4531 0.27% 99.96% # Write request-response latency +system.monitor.writeLatencyHist::30720-32767 728 0.04% 100.00% # Write request-response latency system.monitor.writeLatencyHist::32768-34815 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::34816-36863 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::36864-38911 0 0.00% 100.00% # Write request-response latency diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt index 0520a1aac..a95826599 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 16305869412 # Simulator tick rate (ticks/s) -host_mem_usage 265756 # Number of bytes of host memory used -host_seconds 6.13 # Real time elapsed on the host +host_tick_rate 16291006908 # Simulator tick rate (ticks/s) +host_mem_usage 266948 # Number of bytes of host memory used +host_seconds 6.14 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory @@ -143,8 +143,8 @@ system.monitor.writeBandwidthHist::total 100 # Hi system.monitor.averageWriteBandwidth 8533120 0.00% 0.00% # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 853312 # Number of bytes written system.monitor.readLatencyHist::samples 1 # Read request-response latency -system.monitor.readLatencyHist::mean 32000 # Read request-response latency -system.monitor.readLatencyHist::gmean 32000.000000 # Read request-response latency +system.monitor.readLatencyHist::mean 35000 # Read request-response latency +system.monitor.readLatencyHist::gmean 35000.000000 # Read request-response latency system.monitor.readLatencyHist::stdev nan # Read request-response latency system.monitor.readLatencyHist::0-2047 0 0.00% 0.00% # Read request-response latency system.monitor.readLatencyHist::2048-4095 0 0.00% 0.00% # Read request-response latency @@ -161,15 +161,15 @@ system.monitor.readLatencyHist::22528-24575 0 0.00% 0.00% # system.monitor.readLatencyHist::24576-26623 0 0.00% 0.00% # Read request-response latency system.monitor.readLatencyHist::26624-28671 0 0.00% 0.00% # Read request-response latency system.monitor.readLatencyHist::28672-30719 0 0.00% 0.00% # Read request-response latency -system.monitor.readLatencyHist::30720-32767 1 100.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::32768-34815 0 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::34816-36863 0 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::30720-32767 0 0.00% 0.00% # Read request-response latency +system.monitor.readLatencyHist::32768-34815 0 0.00% 0.00% # Read request-response latency +system.monitor.readLatencyHist::34816-36863 1 100.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::36864-38911 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::38912-40959 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::total 1 # Read request-response latency system.monitor.writeLatencyHist::samples 13333 # Write request-response latency -system.monitor.writeLatencyHist::mean 32000.024601 # Write request-response latency -system.monitor.writeLatencyHist::gmean 32000.024475 # Write request-response latency +system.monitor.writeLatencyHist::mean 39000.024601 # Write request-response latency +system.monitor.writeLatencyHist::gmean 39000.024498 # Write request-response latency system.monitor.writeLatencyHist::stdev 2.840599 # Write request-response latency system.monitor.writeLatencyHist::0-2047 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::2048-4095 0 0.00% 0.00% # Write request-response latency @@ -186,11 +186,11 @@ system.monitor.writeLatencyHist::22528-24575 0 0.00% 0.00% system.monitor.writeLatencyHist::24576-26623 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::26624-28671 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::28672-30719 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::30720-32767 13333 100.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::32768-34815 0 0.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::34816-36863 0 0.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::36864-38911 0 0.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::38912-40959 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::30720-32767 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::32768-34815 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::34816-36863 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::36864-38911 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::38912-40959 13333 100.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::total 13333 # Write request-response latency system.monitor.ittReadRead::samples 0 # Read-to-read inter transaction time system.monitor.ittReadRead::mean nan # Read-to-read inter transaction time diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 6c0305fad..eda01d75f 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.118729 # Number of seconds simulated -sim_ticks 118729316500 # Number of ticks simulated -final_tick 118729316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.118763 # Number of seconds simulated +sim_ticks 118762761500 # Number of ticks simulated +final_tick 118762761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1432938 # Simulator instruction rate (inst/s) -host_op_rate 1432938 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1851208744 # Simulator tick rate (ticks/s) -host_mem_usage 301400 # Number of bytes of host memory used -host_seconds 64.14 # Real time elapsed on the host +host_inst_rate 1561278 # Simulator instruction rate (inst/s) +host_op_rate 1561278 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2017578166 # Simulator tick rate (ticks/s) +host_mem_usage 301004 # Number of bytes of host memory used +host_seconds 58.86 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 167744 # Nu system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1412827 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1155704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2568532 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1412827 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1412827 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1412429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1155379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2567808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1412429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1412429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1412429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1155379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2567808 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 237458633 # number of cpu cycles simulated +system.cpu.numCycles 237525523 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903056 # Number of instructions committed @@ -82,7 +82,7 @@ system.cpu.num_mem_refs 26497334 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_store_insts 6501126 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 237458633 # Number of busy cycles +system.cpu.num_busy_cycles 237525523 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 10240685 # Number of branches fetched @@ -122,19 +122,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91903089 # Class of executed instruction system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1442.043368 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1441.946319 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043368 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.946319 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352038 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352038 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 487 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 491 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses @@ -155,14 +155,14 @@ system.cpu.dcache.demand_misses::cpu.data 2223 # n system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses system.cpu.dcache.overall_misses::total 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26856500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26856500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 107103000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 107103000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 133959500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 133959500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 133959500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 133959500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -179,14 +179,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56540 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56540 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61271.739130 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61271.739130 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60260.683761 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60260.683761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60260.683761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60260.683761 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -205,14 +205,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23424000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23424000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 93300000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 93300000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 116724000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 116724000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116724000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 116724000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26381500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26381500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 105355000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 105355000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 131736500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 131736500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 131736500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 131736500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -221,24 +221,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52507.422402 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52507.422402 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55540 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55540 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60271.739130 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60271.739130 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 6681 # number of replacements -system.cpu.icache.tags.tagsinuse 1418.052751 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1417.953327 # Cycle average of tags in use system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052751 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1417.953327 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.692360 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.692360 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id @@ -260,12 +260,12 @@ system.cpu.icache.demand_misses::cpu.inst 8510 # n system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses system.cpu.icache.overall_misses::total 8510 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 220712500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 220712500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 220712500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 220712500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 220712500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 239145000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 239145000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 239145000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 239145000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 239145000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 239145000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses @@ -278,12 +278,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.663925 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25935.663925 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.663925 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25935.663925 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.663925 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25935.663925 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28101.645123 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28101.645123 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28101.645123 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28101.645123 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28101.645123 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28101.645123 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -292,55 +292,59 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 6681 # number of writebacks +system.cpu.icache.writebacks::total 6681 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 8510 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 8510 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 212202500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 212202500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 212202500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 212202500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 212202500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 212202500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 230635000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 230635000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 230635000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 230635000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 230635000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 230635000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24935.663925 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24935.663925 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24935.663925 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24935.663925 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24935.663925 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24935.663925 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27101.645123 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27101.645123 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2074.070486 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2073.923151 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 12687 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.080733 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.795177 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.017940 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257369 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.795341 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1704.894227 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 351.233582 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.063296 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052029 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.010719 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.063291 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 3109 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 703 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2096 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.094879 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 145425 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 145425 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 6681 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 6681 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5889 # number of ReadCleanReq hits @@ -365,20 +369,22 @@ system.cpu.l2cache.demand_misses::total 4765 # nu system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4765 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90405000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 90405000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137603000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 137603000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22155000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 22155000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 137603000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 112560000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 250163000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 137603000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 112560000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 250163000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 102460000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 102460000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155964000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 155964000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 25110500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 25110500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 155964000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 127570500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 283534500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 155964000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 127570500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 283534500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 6681 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 6681 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8510 # number of ReadCleanReq accesses(hits+misses) @@ -403,18 +409,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.443958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52500.190767 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52500.190767 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.104932 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.104932 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.580720 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.580720 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59505.532240 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59505.532240 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59503.554502 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59503.554502 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59505.532240 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.166045 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59503.567681 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59505.532240 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.166045 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59503.567681 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -435,18 +441,18 @@ system.cpu.l2cache.demand_mshr_misses::total 4765 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73185000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73185000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 111393000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 111393000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17935000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17935000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111393000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 91120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 202513000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111393000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 91120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 202513000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 85240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 85240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129754000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129754000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 20890500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 20890500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129754000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 106130500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 235884500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129754000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 106130500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 235884500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadCleanReq accesses @@ -459,18 +465,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42500.190767 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42500.190767 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.190767 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.104932 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.190767 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.104932 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.580720 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.580720 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49505.532240 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49505.532240 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49503.554502 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49503.554502 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49505.532240 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.166045 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.567681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49505.532240 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.166045 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.567681 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 17571 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 6838 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -479,8 +485,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6731 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6681 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 8510 # Transaction distribution @@ -488,22 +495,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 475 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23701 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4603 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 28304 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 544640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 972224 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 693760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1121344 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 17571 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 10733 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 17571 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10733 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 17571 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 8892500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 10733 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15573500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -528,9 +535,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 4765 # Request fanout histogram -system.membus.reqLayer0.occupancy 4765500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4782000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 23825500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 23825000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 879b8d2d0..0ec96492a 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.230174 # Number of seconds simulated -sim_ticks 230173520500 # Number of ticks simulated -final_tick 230173520500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.230198 # Number of seconds simulated +sim_ticks 230197694500 # Number of ticks simulated +final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1035845 # Simulator instruction rate (inst/s) -host_op_rate 1092042 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1387457275 # Simulator tick rate (ticks/s) -host_mem_usage 319880 # Number of bytes of host memory used -host_seconds 165.90 # Real time elapsed on the host +host_inst_rate 1005681 # Simulator instruction rate (inst/s) +host_op_rate 1060242 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1347195966 # Simulator tick rate (ticks/s) +host_mem_usage 319496 # Number of bytes of host memory used +host_seconds 170.87 # Real time elapsed on the host sim_insts 171842484 # Number of instructions simulated sim_ops 181165371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 110656 # Nu system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 480750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 479360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 960110 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 480750 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 480750 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 480750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 960110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 480700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 479310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 960010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 480700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 480700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 480700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 479310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 960010 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 460347041 # number of cpu cycles simulated +system.cpu.numCycles 460395389 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 171842484 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 40540779 # nu system.cpu.num_load_insts 27896144 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 460347040.998000 # Number of busy cycles +system.cpu.num_busy_cycles 460395388.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 40300312 # Number of branches fetched @@ -208,14 +208,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650743 # Class of executed instruction system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.619059 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1363.571253 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619059 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.571253 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332903 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332903 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id @@ -249,14 +249,14 @@ system.cpu.dcache.demand_misses::cpu.data 1788 # n system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses system.cpu.dcache.overall_misses::total 1789 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35518000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35518000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 95712500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 95712500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 95712500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 95712500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 39940000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39940000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 67838500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 67838500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 107778500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 107778500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 107778500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 107778500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) @@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51625 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51625 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53530.480984 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53530.480984 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53500.558971 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53500.558971 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58052.325581 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58052.325581 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61671.363636 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61671.363636 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60278.803132 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60278.803132 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60245.108999 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60245.108999 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -309,16 +309,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1788 system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34830000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34830000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59094500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 59094500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 93924500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 93924500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93978500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 93978500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39252000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 39252000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 66738500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 66738500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 105990500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 105990500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 106051500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 106051500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -329,26 +329,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50625 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50625 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53722.272727 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53722.272727 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52530.480984 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52530.480984 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52531.302404 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52531.302404 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57052.325581 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57052.325581 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60671.363636 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60671.363636 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1506 # number of replacements -system.cpu.icache.tags.tagsinuse 1147.992416 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1147.958164 # Cycle average of tags in use system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 62227.794821 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992416 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1147.958164 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.560526 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.560526 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id @@ -370,12 +370,12 @@ system.cpu.icache.demand_misses::cpu.inst 3051 # n system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses system.cpu.icache.overall_misses::total 3051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 112484000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 112484000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 112484000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 112484000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 112484000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 112484000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 124592000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 124592000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 124592000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 124592000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 124592000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 124592000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 189860053 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 189860053 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 189860053 # number of demand (read+write) accesses @@ -388,12 +388,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36867.912160 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36867.912160 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36867.912160 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36867.912160 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36867.912160 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36867.912160 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40836.447067 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 40836.447067 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 40836.447067 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 40836.447067 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -402,44 +402,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 1506 # number of writebacks +system.cpu.icache.writebacks::total 1506 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 109433000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 109433000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 109433000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 109433000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 109433000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 109433000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 121541000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 121541000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 121541000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 121541000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 121541000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 121541000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35867.912160 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35867.912160 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35867.912160 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35867.912160 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35867.912160 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35867.912160 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39836.447067 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39836.447067 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1675.663068 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 1675.610098 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.201351 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036560 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588729 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 3.037805 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.001518 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 503.570775 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035675 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.051137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.051136 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 2369 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id @@ -449,8 +451,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 54045 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 54045 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1448 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1448 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1322 # number of ReadCleanReq hits @@ -475,20 +479,22 @@ system.cpu.l2cache.demand_misses::total 3453 # nu system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses system.cpu.l2cache.overall_misses::total 3453 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57360500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 57360500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 90862500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 90862500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33203000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 33203000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 90862500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 90563500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 181426000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 90862500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 90563500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 181426000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65004500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 65004500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 102968000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 102968000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37629500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 37629500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 102968000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 102634000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 205602000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 102968000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 102634000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 205602000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1448 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1448 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1100 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3051 # number of ReadCleanReq accesses(hits+misses) @@ -513,18 +519,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.713430 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52527.930403 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52527.930403 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52552.053210 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52552.053210 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52536.392405 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52536.392405 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52541.558065 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52541.558065 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59527.930403 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59527.930403 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59553.499132 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59553.499132 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59540.348101 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59540.348101 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59553.499132 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59543.006082 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59553.499132 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59543.006082 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -545,18 +551,18 @@ system.cpu.l2cache.demand_mshr_misses::total 3453 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 46440500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 46440500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 73572500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 73572500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 26883000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 26883000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 73572500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 73323500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 146896000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 73572500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 73323500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 146896000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54084500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54084500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85678000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85678000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31309500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31309500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85678000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85394000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 171072000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85678000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85394000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 171072000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadCleanReq accesses @@ -569,18 +575,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42527.930403 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42527.930403 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42552.053210 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42552.053210 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42536.392405 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42536.392405 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42552.053210 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42531.032483 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42541.558065 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42552.053210 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42531.032483 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42541.558065 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49527.930403 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49527.930403 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49553.499132 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49553.499132 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49540.348101 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49540.348101 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -589,8 +595,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1466 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1448 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 # Transaction distribution @@ -598,22 +605,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7550 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3612 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 11162 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 287936 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 403456 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6386 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.035390 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.184778 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 4840 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.033471 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.179882 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6160 96.46% 96.46% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 226 3.54% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4678 96.65% 96.65% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 162 3.35% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6386 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3209000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4840 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4715000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -638,9 +645,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3453 # Request fanout histogram -system.membus.reqLayer0.occupancy 3596500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3601500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 17408500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 17265000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index b410464ce..ab4d1300a 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.270563 # Number of seconds simulated -sim_ticks 270563083500 # Number of ticks simulated -final_tick 270563083500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.270600 # Number of seconds simulated +sim_ticks 270599529500 # Number of ticks simulated +final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1207450 # Simulator instruction rate (inst/s) -host_op_rate 1207451 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1688810940 # Simulator tick rate (ticks/s) -host_mem_usage 300136 # Number of bytes of host memory used -host_seconds 160.21 # Real time elapsed on the host +host_inst_rate 1167307 # Simulator instruction rate (inst/s) +host_op_rate 1167308 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1632884817 # Simulator tick rate (ticks/s) +host_mem_usage 300512 # Number of bytes of host memory used +host_seconds 165.72 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 230208 # Nu system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 850848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 372793 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1223641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 850848 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 850848 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 850733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 372743 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1223476 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 850733 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 850733 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 401 # Number of system calls -system.cpu.numCycles 541126167 # number of cpu cycles simulated +system.cpu.numCycles 541199059 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 193444518 # Number of instructions committed @@ -50,7 +50,7 @@ system.cpu.num_mem_refs 76733958 # nu system.cpu.num_load_insts 57735091 # Number of load instructions system.cpu.num_store_insts 18998867 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 541126166.998000 # Number of busy cycles +system.cpu.num_busy_cycles 541199058.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 15132745 # Number of branches fetched @@ -90,14 +90,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 193445773 # Class of executed instruction system.cpu.dcache.tags.replacements 2 # number of replacements -system.cpu.dcache.tags.tagsinuse 1237.203935 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203935 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1237.159344 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.302041 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.302041 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id @@ -127,16 +127,16 @@ system.cpu.dcache.demand_misses::cpu.data 1575 # n system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses system.cpu.dcache.overall_misses::total 1575 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 30877500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 30877500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 66775000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 66775000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 62000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 62000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 97652500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 97652500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 97652500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 97652500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) @@ -157,16 +157,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62003.012048 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62003.012048 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000.928505 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62000.928505 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 62000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 62000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62001.587302 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62001.587302 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -187,16 +187,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1575 system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26892000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26892000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58158000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 58158000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 54000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 54000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 85050000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 85050000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 85050000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 85050000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30379500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30379500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65698000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 65698000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 61000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 61000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 96077500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 96077500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 96077500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 96077500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses @@ -207,26 +207,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 54000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 54000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61003.012048 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61003.012048 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000.928505 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000.928505 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 61000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 61000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10362 # number of replacements -system.cpu.icache.tags.tagsinuse 1591.579162 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579162 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1591.528232 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.777113 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.777113 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id @@ -248,12 +248,12 @@ system.cpu.icache.demand_misses::cpu.inst 12288 # n system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses system.cpu.icache.overall_misses::total 12288 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 310819500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 310819500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 310819500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 310819500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 310819500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 310819500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 336231000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 336231000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 336231000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 336231000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 336231000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 336231000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses @@ -266,12 +266,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.555664 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25294.555664 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.555664 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25294.555664 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.555664 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25294.555664 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27362.548828 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27362.548828 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27362.548828 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27362.548828 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -280,44 +280,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 10362 # number of writebacks +system.cpu.icache.writebacks::total 10362 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 298531500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 298531500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 298531500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 298531500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 298531500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 298531500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323943000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 323943000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323943000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 323943000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323943000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 323943000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24294.555664 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24294.555664 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24294.555664 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24294.555664 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24294.555664 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24294.555664 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26362.548828 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26362.548828 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2678.340828 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282891 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057483 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.203530 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 403.042121 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069434 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.081734 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id @@ -327,8 +329,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 10362 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8691 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 8691 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits @@ -347,20 +351,22 @@ system.cpu.l2cache.demand_misses::total 5173 # nu system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses system.cpu.l2cache.overall_misses::total 5173 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56595000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 56595000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 188843000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 188843000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 26145000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 26145000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 188843000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 82740000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 271583000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 188843000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 82740000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 271583000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 2 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64142000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 64142000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 214049500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 214049500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29632000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 29632000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 214049500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 93774000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 307823500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 214049500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 93774000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 307823500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 10362 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 10362 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12288 # number of ReadCleanReq accesses(hits+misses) @@ -385,18 +391,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.373125 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52500.139005 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52500.139005 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.096656 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.096656 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.927644 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.927644 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59507.784265 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59507.784265 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59502.008032 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59502.008032 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59505.799343 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59505.799343 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -417,18 +423,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5173 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 45815000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 45815000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 152873000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 152873000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 21165000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 21165000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 152873000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 66980000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 219853000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 152873000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 66980000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 219853000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53362000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53362000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 178079500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 178079500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24652000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24652000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178079500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78014000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 256093500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178079500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78014000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 256093500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses @@ -441,18 +447,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42500.139005 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42500.139005 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.139005 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.096656 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.139005 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.096656 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.927644 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.927644 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49507.784265 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49507.784265 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49502.008032 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49502.008032 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -461,8 +467,8 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 10362 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution @@ -470,22 +476,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 38092 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1449600 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1550592 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 24228 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000041 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.006425 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 13864 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000072 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.008493 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 24227 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 13863 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 24228 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12116000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 13864 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 22478000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -510,9 +516,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5173 # Request fanout histogram -system.membus.reqLayer0.occupancy 5173500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 5203000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 25865500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25865000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 00e1fc087..d9abd5a16 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.250954 # Number of seconds simulated -sim_ticks 250953958500 # Number of ticks simulated -final_tick 250953958500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.250987 # Number of seconds simulated +sim_ticks 250987138500 # Number of ticks simulated +final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 759533 # Simulator instruction rate (inst/s) -host_op_rate 1273047 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1443220819 # Simulator tick rate (ticks/s) -host_mem_usage 343748 # Number of bytes of host memory used -host_seconds 173.88 # Real time elapsed on the host +host_inst_rate 735776 # Simulator instruction rate (inst/s) +host_op_rate 1233228 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1398263201 # Simulator tick rate (ticks/s) +host_mem_usage 343356 # Number of bytes of host memory used +host_seconds 179.50 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,18 +21,18 @@ system.physmem.bytes_inst_read::total 181760 # Nu system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 724276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 483276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1207552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 724276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 724276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 724181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 483212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1207393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 724181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 724181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 724181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 483212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1207393 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 501907917 # number of cpu cycles simulated +system.cpu.numCycles 501974277 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 132071193 # Number of instructions committed @@ -53,7 +53,7 @@ system.cpu.num_mem_refs 77165304 # nu system.cpu.num_load_insts 56649587 # Number of load instructions system.cpu.num_store_insts 20515717 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 501907916.998000 # Number of busy cycles +system.cpu.num_busy_cycles 501974276.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 12326938 # Number of branches fetched @@ -93,19 +93,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 221363385 # Class of executed instruction system.cpu.dcache.tags.replacements 41 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.457562 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1363.414730 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457562 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.414730 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332865 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332865 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 471 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 472 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses @@ -126,14 +126,14 @@ system.cpu.dcache.demand_misses::cpu.data 1905 # n system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses system.cpu.dcache.overall_misses::total 1905 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 86664000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 104356500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 19933500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 19933500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 97691000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 97691000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 117624500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117624500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117624500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117624500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) @@ -150,14 +150,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54780.314961 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60958.715596 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60958.715596 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61908.111534 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61908.111534 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61745.144357 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61745.144357 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -176,14 +176,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1905 system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17365500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17365500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85086000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85086000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 102451500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 102451500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 102451500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 102451500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19606500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 19606500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96113000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 96113000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115719500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 115719500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115719500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 115719500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses @@ -192,29 +192,29 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53105.504587 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53105.504587 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53920.152091 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53920.152091 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53780.314961 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53780.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53780.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53780.314961 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59958.715596 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59958.715596 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60908.111534 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60908.111534 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2836 # number of replacements -system.cpu.icache.tags.tagsinuse 1455.296634 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296634 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1455.245085 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.710569 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.710569 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 394 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 415 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses @@ -231,12 +231,12 @@ system.cpu.icache.demand_misses::cpu.inst 4694 # n system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses system.cpu.icache.overall_misses::total 4694 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 180320500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 180320500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 180320500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 180320500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 180320500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 180320500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 200232500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 200232500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 200232500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 200232500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 200232500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 200232500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses @@ -249,12 +249,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38415.104389 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 38415.104389 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 38415.104389 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 38415.104389 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 38415.104389 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 38415.104389 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42657.115467 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42657.115467 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42657.115467 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42657.115467 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -263,55 +263,59 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 2836 # number of writebacks +system.cpu.icache.writebacks::total 2836 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175626500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 175626500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175626500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 175626500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175626500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 175626500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195538500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 195538500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195538500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 195538500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195538500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 195538500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37415.104389 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37415.104389 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37415.104389 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37415.104389 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37415.104389 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37415.104389 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41657.115467 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41657.115467 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2058.178654 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978552 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178359 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 0.021821 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.911143 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 228.172589 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055844 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.062808 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 513 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 516 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 532 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 80550 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 80550 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 7 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 7 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 2836 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 # number of ReadCleanReq hits @@ -336,20 +340,22 @@ system.cpu.l2cache.demand_misses::total 4735 # nu system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses system.cpu.l2cache.overall_misses::total 4735 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 82687500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 82687500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 149117500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 149117500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 16801500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 16801500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 149117500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 99489000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 248606500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 149117500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 99489000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 248606500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 7 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 7 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 93713500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 93713500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 169013000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 169013000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19042000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 19042000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 169013000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112755500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 281768500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 169013000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112755500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 281768500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 7 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 7 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 2836 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 2836 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4694 # number of ReadCleanReq accesses(hits+misses) @@ -374,18 +380,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.717533 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52506.161972 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52506.161972 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52504.687500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52504.687500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52504.012672 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52504.012672 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.634921 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.634921 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.619718 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.619718 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59506.250000 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59506.250000 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59507.602957 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59507.602957 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -406,18 +412,18 @@ system.cpu.l2cache.demand_mshr_misses::total 4735 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 66937500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 66937500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 120717500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 120717500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13601500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13601500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 120717500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 80539000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 201256500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 120717500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 80539000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 201256500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77963500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77963500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140613000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140613000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15842000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15842000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140613000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 93805500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 234418500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140613000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 93805500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 234418500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadCleanReq accesses @@ -430,18 +436,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42506.161972 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42506.161972 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42504.687500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42504.687500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42506.161972 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.791557 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42504.012672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42506.161972 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.791557 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42504.012672 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.634921 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.634921 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.619718 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.619718 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49506.250000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49506.250000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -450,8 +456,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2870 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution @@ -459,22 +466,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12224 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3851 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 16075 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481920 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 604288 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9476 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000106 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010273 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 6599 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000152 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.012310 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 9475 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6598 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9476 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4745000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6599 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7581000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -501,9 +508,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 4735 # Request fanout histogram -system.membus.reqLayer0.occupancy 4754000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4771000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 23694000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 23675000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |