diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:21 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:21 -0400 |
| commit | d52adc4eb68c2733f9af4ac68834583c0a555f9d (patch) | |
| tree | 2ee5c3d271af63a3ef527c54950f57f406a05d90 /tests/quick | |
| parent | 88554790c34f6fef4ba6285927fb9742b90ab258 (diff) | |
| download | gem5-d52adc4eb68c2733f9af4ac68834583c0a555f9d.tar.xz | |
Stats: Update stats for cache timings in cycles
This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
Diffstat (limited to 'tests/quick')
16 files changed, 7531 insertions, 7567 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 98f92d27e..b9451bcf6 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,170 +1,170 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.870336 # Number of seconds simulated -sim_ticks 1870335522500 # Number of ticks simulated -final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.870325 # Number of seconds simulated +sim_ticks 1870325497500 # Number of ticks simulated +final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3051606 # Simulator instruction rate (inst/s) -host_op_rate 3051604 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90374561583 # Simulator tick rate (ticks/s) -host_mem_usage 305448 # Number of bytes of host memory used -host_seconds 20.70 # Real time elapsed on the host -sim_insts 63154034 # Number of instructions simulated -sim_ops 63154034 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory +host_inst_rate 2529303 # Simulator instruction rate (inst/s) +host_op_rate 2529302 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 74909435310 # Simulator tick rate (ticks/s) +host_mem_usage 298360 # Number of bytes of host memory used +host_seconds 24.97 # Real time elapsed on the host +sim_insts 63151114 # Number of instructions simulated +sim_ops 63151114 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 760896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66666560 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory -system.physmem.bytes_read::total 70883520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 761216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7861504 # Number of bytes written to this memory -system.physmem.bytes_written::total 7861504 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11894 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1042079 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 111168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 681792 # Number of bytes read from this memory +system.physmem.bytes_read::total 70870016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 760896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 111168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 872064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7852480 # Number of bytes written to this memory +system.physmem.bytes_written::total 7852480 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11889 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1041665 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10448 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1107555 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122836 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122836 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 406994 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35658338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 357514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37898826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 406994 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4203259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4203259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4203259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35658338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42102084 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 1000626 # number of replacements -system.l2c.tagsinuse 65381.922680 # Cycle average of tags in use -system.l2c.total_refs 2464737 # Total number of references to valid blocks. -system.l2c.sampled_refs 1065768 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.312639 # Average number of references to valid blocks. +system.physmem.num_reads::cpu1.inst 1737 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10653 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1107344 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122695 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122695 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 406825 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35644362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1416652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 364531 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37891809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 406825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466263 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4198456 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4198456 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4198456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 406825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35644362 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1416652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 364531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42090265 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 1000406 # number of replacements +system.l2c.tagsinuse 65381.817479 # Cycle average of tags in use +system.l2c.total_refs 2465974 # Total number of references to valid blocks. +system.l2c.sampled_refs 1065550 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.314273 # Average number of references to valid blocks. system.l2c.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 56158.702580 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4894.236968 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4134.601551 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 174.423287 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 19.958294 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 56158.126687 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4894.240577 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4135.004263 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 174.436812 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 20.009142 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.856905 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.063095 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.002662 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.997649 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 873086 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 763077 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 101896 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 36734 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1774793 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 816653 # number of Writeback hits -system.l2c.Writeback_hits::total 816653 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 135 # 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number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 816811 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 816811 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2579 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 612 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3191 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 81 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 112 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 193 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 281716 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 24162 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 305878 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 884613 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1971544 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 104648 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 61969 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3022774 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 884613 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1971544 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 104648 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 61969 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3022774 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.548432 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.016733 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024122 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.346563 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.410392 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.403474 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.409851 # miss rate for ReadExReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.548440 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.016599 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024281 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.346467 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.946491 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939542 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.945158 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.827160 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.919643 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.880829 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.409214 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.408162 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.409130 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.528694 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.016733 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.171622 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.352969 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.528546 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.016599 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.173958 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.352808 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.528694 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.016733 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.171622 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.352969 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.528546 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.016599 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.173958 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.352808 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,34 +173,34 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 81316 # number of writebacks -system.l2c.writebacks::total 81316 # number of writebacks +system.l2c.writebacks::writebacks 81175 # number of writebacks +system.l2c.writebacks::total 81175 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41695 # number of replacements -system.iocache.tagsinuse 0.435437 # Cycle average of tags in use +system.iocache.replacements 41694 # number of replacements +system.iocache.tagsinuse 0.435353 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.435437 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.027215 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.warmup_cycle 1685787105067 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.435353 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.027210 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.027210 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -236,22 +236,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9154530 # DTB read hits +system.cpu0.dtb.read_hits 9148429 # DTB read hits system.cpu0.dtb.read_misses 7079 # DTB read misses system.cpu0.dtb.read_acv 152 # DTB read access violations system.cpu0.dtb.read_accesses 508987 # DTB read accesses -system.cpu0.dtb.write_hits 5936899 # DTB write hits +system.cpu0.dtb.write_hits 5932048 # DTB write hits system.cpu0.dtb.write_misses 726 # DTB write misses system.cpu0.dtb.write_acv 99 # DTB write access violations system.cpu0.dtb.write_accesses 189050 # DTB write accesses -system.cpu0.dtb.data_hits 15091429 # DTB hits +system.cpu0.dtb.data_hits 15080477 # DTB hits system.cpu0.dtb.data_misses 7805 # DTB misses system.cpu0.dtb.data_acv 251 # DTB access violations system.cpu0.dtb.data_accesses 698037 # DTB accesses -system.cpu0.itb.fetch_hits 3855556 # ITB hits +system.cpu0.itb.fetch_hits 3854196 # ITB hits system.cpu0.itb.fetch_misses 3485 # ITB misses system.cpu0.itb.fetch_acv 127 # ITB acv -system.cpu0.itb.fetch_accesses 3859041 # ITB accesses +system.cpu0.itb.fetch_accesses 3857681 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -264,55 +264,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3740670933 # number of cpu cycles simulated +system.cpu0.numCycles 3740650883 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 57222076 # Number of instructions committed -system.cpu0.committedOps 57222076 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses -system.cpu0.num_func_calls 1399585 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls -system.cpu0.num_int_insts 53249924 # number of integer instructions -system.cpu0.num_fp_insts 299810 # number of float instructions -system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written -system.cpu0.num_mem_refs 15135515 # number of memory refs -system.cpu0.num_load_insts 9184477 # Number of load instructions -system.cpu0.num_store_insts 5951038 # Number of store instructions -system.cpu0.num_idle_cycles 3683437089.313678 # Number of idle cycles -system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles -system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles +system.cpu0.committedInsts 57184467 # Number of instructions committed +system.cpu0.committedOps 57184467 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 53214865 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 299670 # Number of float alu accesses +system.cpu0.num_func_calls 1398025 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6803964 # number of instructions that are conditional controls +system.cpu0.num_int_insts 53214865 # number of integer instructions +system.cpu0.num_fp_insts 299670 # number of float instructions +system.cpu0.num_int_register_reads 73271755 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39802131 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 147658 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 150767 # number of times the floating registers were written +system.cpu0.num_mem_refs 15124548 # number of memory refs +system.cpu0.num_load_insts 9178366 # Number of load instructions +system.cpu0.num_store_insts 5946182 # Number of store instructions +system.cpu0.num_idle_cycles 3683454679.572560 # Number of idle cycles +system.cpu0.num_busy_cycles 57196203.427440 # Number of busy cycles +system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6280 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 196965 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 70940 40.60% 40.60% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 101631 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 174730 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 69573 49.24% 49.24% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 69565 49.23% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 141297 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1852985718000 99.07% 99.07% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_ticks::31 17236468500 0.92% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1870325290000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.980730 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684486 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808659 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed @@ -345,37 +345,37 @@ system.cpu0.kern.syscall::144 2 0.88% 99.12% # nu system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 226 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wripir 111 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3760 2.05% 2.12% # number of callpals executed system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal::swpipl 168035 91.68% 93.82% # number of callpals executed -system.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed +system.cpu0.kern.callpal::swpipl 167897 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal::rdps 6134 3.35% 97.17% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 183291 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches +system.cpu0.kern.callpal::total 183136 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7089 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1156 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1157 -system.cpu0.kern.mode_good::user 1158 +system.cpu0.kern.mode_good::kernel 1155 +system.cpu0.kern.mode_good::user 1156 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.162928 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.280291 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1869368290000 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 956999000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3763 # number of times the context was actually changed +system.cpu0.kern.swap_context 3761 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -407,39 +407,39 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 884404 # number of replacements -system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use -system.cpu0.icache.total_refs 56345132 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 884916 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks. +system.cpu0.icache.replacements 883989 # number of replacements +system.cpu0.icache.tagsinuse 511.244895 # Cycle average of tags in use +system.cpu0.icache.total_refs 56307893 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 884501 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 63.660632 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 511.244895 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.998525 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 56345132 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 56345132 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 56345132 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 56345132 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 56345132 # number of overall hits -system.cpu0.icache.overall_hits::total 56345132 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 885000 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 885000 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 885000 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 885000 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 885000 # number of overall misses -system.cpu0.icache.overall_misses::total 885000 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230132 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 57230132 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 56307893 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 56307893 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 56307893 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 56307893 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 56307893 # number of overall hits +system.cpu0.icache.overall_hits::total 56307893 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 884630 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 884630 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 884630 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 884630 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 884630 # number of overall misses +system.cpu0.icache.overall_misses::total 884630 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 57192523 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 57192523 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 57192523 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 57192523 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 57192523 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 57192523 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015468 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.015468 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015468 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.015468 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015468 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.015468 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,63 +449,63 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1978686 # number of replacements -system.cpu0.dcache.tagsinuse 507.129778 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13123753 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1979198 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 6.630844 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1978242 # number of replacements +system.cpu0.dcache.tagsinuse 507.129590 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13113201 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1978754 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 6.626999 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 507.129778 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.990488 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7298337 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7298337 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5462263 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5462263 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12760600 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12760600 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12760600 # number of overall hits -system.cpu0.dcache.overall_hits::total 12760600 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1683332 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1683332 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1969330 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1969330 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1969330 # number of overall misses -system.cpu0.dcache.overall_misses::total 1969330 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14729930 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003811 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003811 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses +system.cpu0.dcache.occ_blocks::cpu0.data 507.129590 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.990487 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.990487 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7292600 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7292600 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5457787 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5457787 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 171977 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 171977 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186443 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 186443 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12750387 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12750387 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12750387 # number of overall hits +system.cpu0.dcache.overall_hits::total 12750387 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1683130 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1683130 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 285798 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 285798 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16152 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16152 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 726 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 726 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1968928 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1968928 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1968928 # number of overall misses +system.cpu0.dcache.overall_misses::total 1968928 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8975730 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8975730 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5743585 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5743585 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188129 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 188129 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187169 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 187169 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14719315 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14719315 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14719315 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14719315 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187520 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.187520 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049760 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049760 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085856 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085856 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003879 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003879 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133765 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.133765 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133765 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.133765 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -514,29 +514,29 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 775641 # number of writebacks -system.cpu0.dcache.writebacks::total 775641 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 775494 # number of writebacks +system.cpu0.dcache.writebacks::total 775494 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1163439 # DTB read hits +system.cpu1.dtb.read_hits 1169160 # DTB read hits system.cpu1.dtb.read_misses 3277 # DTB read misses system.cpu1.dtb.read_acv 58 # DTB read access violations system.cpu1.dtb.read_accesses 220342 # DTB read accesses -system.cpu1.dtb.write_hits 751446 # DTB write hits +system.cpu1.dtb.write_hits 755883 # DTB write hits system.cpu1.dtb.write_misses 415 # DTB write misses system.cpu1.dtb.write_acv 58 # DTB write access violations system.cpu1.dtb.write_accesses 103280 # DTB write accesses -system.cpu1.dtb.data_hits 1914885 # DTB hits +system.cpu1.dtb.data_hits 1925043 # DTB hits system.cpu1.dtb.data_misses 3692 # DTB misses system.cpu1.dtb.data_acv 116 # DTB access violations system.cpu1.dtb.data_accesses 323622 # DTB accesses -system.cpu1.itb.fetch_hits 1468399 # ITB hits +system.cpu1.itb.fetch_hits 1469677 # ITB hits system.cpu1.itb.fetch_misses 1539 # ITB misses system.cpu1.itb.fetch_acv 57 # ITB acv -system.cpu1.itb.fetch_accesses 1469938 # ITB accesses +system.cpu1.itb.fetch_accesses 1471216 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -549,51 +549,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3740248881 # number of cpu cycles simulated +system.cpu1.numCycles 3740237218 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5931958 # Number of instructions committed -system.cpu1.committedOps 5931958 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses -system.cpu1.num_func_calls 182742 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls -system.cpu1.num_int_insts 5550578 # number of integer instructions -system.cpu1.num_fp_insts 28590 # number of float instructions -system.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read -system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written -system.cpu1.num_mem_refs 1926244 # number of memory refs -system.cpu1.num_load_insts 1170888 # Number of load instructions -system.cpu1.num_store_insts 755356 # Number of store instructions -system.cpu1.num_idle_cycles 3734312190.077655 # Number of idle cycles -system.cpu1.num_busy_cycles 5936690.922345 # Number of busy cycles -system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles +system.cpu1.committedInsts 5966647 # Number of instructions committed +system.cpu1.committedOps 5966647 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 5582916 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 28730 # Number of float alu accesses +system.cpu1.num_func_calls 184190 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 581489 # number of instructions that are conditional controls +system.cpu1.num_int_insts 5582916 # number of integer instructions +system.cpu1.num_fp_insts 28730 # number of float instructions +system.cpu1.num_int_register_reads 7700123 # number of times the integer registers were read +system.cpu1.num_int_register_writes 4186358 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 17955 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 17751 # number of times the floating registers were written +system.cpu1.num_mem_refs 1936419 # number of memory refs +system.cpu1.num_load_insts 1176619 # Number of load instructions +system.cpu1.num_store_insts 759800 # Number of store instructions +system.cpu1.num_idle_cycles 3734265828.606121 # Number of idle cycles +system.cpu1.num_busy_cycles 5971389.393879 # Number of busy cycles +system.cpu1.not_idle_fraction 0.001597 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.998403 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.inst.quiesce 2208 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 39691 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 10388 33.53% 33.53% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1907 6.15% 39.68% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 111 0.36% 40.04% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 18579 59.96% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 30985 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 10378 45.79% 45.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1907 8.41% 54.21% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 111 0.49% 54.70% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 10267 45.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 22663 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1859112376500 99.41% 99.41% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_ticks::30 14176500 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 10910041500 0.58% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1870118595500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.999037 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.552613 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.731418 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed @@ -616,67 +616,67 @@ system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed +system.cpu1.kern.callpal::swpctx 472 1.46% 1.50% # number of callpals executed system.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed -system.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed -system.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed +system.cpu1.kern.callpal::swpipl 26358 81.69% 83.25% # number of callpals executed +system.cpu1.kern.callpal::rdps 2589 8.02% 91.28% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.28% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 91.29% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.01% 91.30% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.31% # number of callpals executed +system.cpu1.kern.callpal::rti 2608 8.08% 99.39% # number of callpals executed system.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed system.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 32131 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches +system.cpu1.kern.callpal::total 32267 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1034 # number of protection mode switches system.cpu1.kern.mode_switch::user 580 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 612 +system.cpu1.kern.mode_switch::idle 2048 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 613 system.cpu1.kern.mode_good::user 580 -system.cpu1.kern.mode_good::idle 32 -system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 33 +system.cpu1.kern.mode_switch_good::kernel 0.592843 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::idle 0.016113 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.334790 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 1393260500 0.07% 0.07% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 471 # number of times the context was actually changed -system.cpu1.icache.replacements 103091 # number of replacements -system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use -system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.834231 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 5832136 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5832136 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5832136 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5832136 # number of overall hits -system.cpu1.icache.overall_hits::total 5832136 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 103630 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 103630 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 103630 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 103630 # number of overall misses -system.cpu1.icache.overall_misses::total 103630 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.017459 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.017459 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.017459 # miss rate for overall accesses +system.cpu1.kern.mode_ticks::idle 1867980072500 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 473 # number of times the context was actually changed +system.cpu1.icache.replacements 104103 # number of replacements +system.cpu1.icache.tagsinuse 427.138444 # Cycle average of tags in use +system.cpu1.icache.total_refs 5865807 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 104615 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 56.070420 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1868930362000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 427.138444 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.834255 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.834255 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 5865807 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5865807 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 5865807 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5865807 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 5865807 # number of overall hits +system.cpu1.icache.overall_hits::total 5865807 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 104648 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 104648 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 104648 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 104648 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 104648 # number of overall misses +system.cpu1.icache.overall_misses::total 104648 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5970455 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5970455 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 5970455 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5970455 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5970455 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5970455 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017528 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.017528 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017528 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.017528 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017528 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.017528 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -686,63 +686,63 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 62044 # number of replacements -system.cpu1.dcache.tagsinuse 421.562730 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1836054 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 62382 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 29.432432 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1851115552500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 421.562730 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.823365 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.823365 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1109521 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1109521 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 707457 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 707457 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1816978 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1816978 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1816978 # number of overall hits -system.cpu1.dcache.overall_hits::total 1816978 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 41444 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 41444 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 25848 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 25848 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 67292 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 67292 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 67292 # number of overall misses -system.cpu1.dcache.overall_misses::total 67292 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036008 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036008 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035249 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.035249 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035713 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.035713 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035713 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035713 # miss rate for overall accesses +system.cpu1.dcache.replacements 62444 # number of replacements +system.cpu1.dcache.tagsinuse 421.660465 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1845254 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 62784 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 29.390514 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1851113732500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 421.660465 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.823556 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.823556 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1114890 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1114890 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 711494 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 711494 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15278 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 15278 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15743 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 15743 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1826384 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1826384 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1826384 # number of overall hits +system.cpu1.dcache.overall_hits::total 1826384 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 41651 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 41651 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 26091 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 26091 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1291 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1291 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 751 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 751 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 67742 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 67742 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 67742 # number of overall misses +system.cpu1.dcache.overall_misses::total 67742 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1156541 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1156541 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 737585 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 737585 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16569 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 16569 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16494 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 16494 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1894126 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1894126 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1894126 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1894126 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036013 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036013 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035374 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.035374 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.077917 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.077917 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.045532 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.045532 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035764 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.035764 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035764 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035764 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -751,8 +751,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 41012 # number of writebacks -system.cpu1.dcache.writebacks::total 41012 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 41317 # number of writebacks +system.cpu1.dcache.writebacks::total 41317 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index a50f49017..cf5c30619 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,132 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.829332 # Number of seconds simulated -sim_ticks 1829332258000 # Number of ticks simulated -final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.829331 # Number of seconds simulated +sim_ticks 1829330593000 # Number of ticks simulated +final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2962809 # Simulator instruction rate (inst/s) -host_op_rate 2962806 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90274916526 # Simulator tick rate (ticks/s) -host_mem_usage 302384 # Number of bytes of host memory used -host_seconds 20.26 # Real time elapsed on the host -sim_insts 60038305 # Number of instructions simulated -sim_ops 60038305 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory +host_inst_rate 2569577 # Simulator instruction rate (inst/s) +host_op_rate 2569575 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78294086451 # Simulator tick rate (ticks/s) +host_mem_usage 295292 # Number of bytes of host memory used +host_seconds 23.37 # Real time elapsed on the host +sim_insts 60037737 # Number of instructions simulated +sim_ops 60037737 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66839296 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7411392 # Number of bytes written to this memory -system.physmem.bytes_written::total 7411392 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044366 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 70349440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 857856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 857856 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7411136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7411136 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13404 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044364 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1099214 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115803 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115803 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36537607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1449867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 38456489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 992301 # number of replacements -system.cpu.l2cache.tagsinuse 65424.374305 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2433239 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1057464 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.301014 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.998297 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 811229 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1718026 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187229 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187229 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906797 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998458 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905255 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906797 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998458 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905255 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 117117 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044757 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1058163 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044757 # number of overall misses -system.cpu.l2cache.overall_misses::total 1058163 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1738869 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2659072 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2043215 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2963418 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2043215 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2963418 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.353900 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384815 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384815 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511330 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511330 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks -system.cpu.l2cache.writebacks::total 74291 # number of writebacks -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.physmem.num_reads::total 1099210 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115799 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115799 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 468945 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36537571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1449868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 38456384 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 468945 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 468945 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4051283 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4051283 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4051283 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 468945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36537571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1449868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42507667 # Total bandwidth to/from this memory (bytes/s) system.iocache.replacements 41686 # number of replacements -system.iocache.tagsinuse 1.225570 # Cycle average of tags in use +system.iocache.tagsinuse 1.225558 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.076598 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1685780599067 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.225558 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.076597 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.076597 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -178,22 +98,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9710427 # DTB read hits +system.cpu.dtb.read_hits 9710417 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6352498 # DTB write hits +system.cpu.dtb.write_hits 6352487 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 16062925 # DTB hits +system.cpu.dtb.data_hits 16062904 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974648 # ITB hits +system.cpu.itb.fetch_hits 4974615 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979654 # ITB accesses +system.cpu.itb.fetch_accesses 4979621 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -206,51 +126,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3658664408 # number of cpu cycles simulated +system.cpu.numCycles 3658661078 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60038305 # Number of instructions committed -system.cpu.committedOps 60038305 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses +system.cpu.committedInsts 60037737 # Number of instructions committed +system.cpu.committedOps 60037737 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 55912968 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses -system.cpu.num_func_calls 1484182 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls -system.cpu.num_int_insts 55913521 # number of integer instructions +system.cpu.num_func_calls 1484174 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7110641 # number of instructions that are conditional controls +system.cpu.num_int_insts 55912968 # number of integer instructions system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read -system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written +system.cpu.num_int_register_reads 76953007 # number of times the integer registers were read +system.cpu.num_int_register_writes 41739788 # number of times the integer registers were written system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 16115709 # number of memory refs -system.cpu.num_load_insts 9747513 # Number of load instructions -system.cpu.num_store_insts 6368196 # Number of store instructions -system.cpu.num_idle_cycles 3598608979.180807 # Number of idle cycles -system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles -system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.983585 # Percentage of idle cycles +system.cpu.num_mem_refs 16115688 # number of memory refs +system.cpu.num_load_insts 9747503 # Number of load instructions +system.cpu.num_store_insts 6368185 # Number of store instructions +system.cpu.num_idle_cycles 3598606247.544791 # Number of idle cycles +system.cpu.num_busy_cycles 60054830.455209 # Number of busy cycles +system.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.983586 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 211316 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105620 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182559 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1811925911500 99.05% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 17304126000 0.95% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1829330385500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.695541 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.816366 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -289,7 +209,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal::swpipl 175246 91.19% 93.40% # number of callpals executed system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed @@ -298,20 +218,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192180 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1738 +system.cpu.kern.callpal::total 192177 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5948 # number of protection mode switches +system.cpu.kern.mode_switch::user 1735 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1906 +system.cpu.kern.mode_good::user 1735 system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320444 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081506 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.389735 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 26832734500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 1465059000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1801032591000 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -344,33 +264,33 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 919594 # number of replacements -system.cpu.icache.tagsinuse 511.215243 # Cycle average of tags in use -system.cpu.icache.total_refs 59129922 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks. +system.cpu.icache.replacements 919577 # number of replacements +system.cpu.icache.tagsinuse 511.215229 # Cycle average of tags in use +system.cpu.icache.total_refs 59129371 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 920089 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 64.264839 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.215243 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 511.215229 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.998467 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 59129922 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59129922 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59129922 # number of overall hits -system.cpu.icache.overall_hits::total 59129922 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 920221 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 920221 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 920221 # number of overall misses -system.cpu.icache.overall_misses::total 920221 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 59129371 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59129371 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59129371 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59129371 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59129371 # number of overall hits +system.cpu.icache.overall_hits::total 59129371 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 920204 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 920204 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 920204 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 920204 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 920204 # number of overall misses +system.cpu.icache.overall_misses::total 920204 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 60049575 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60049575 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60049575 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60049575 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60049575 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60049575 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses @@ -386,55 +306,55 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2042702 # number of replacements +system.cpu.dcache.replacements 2042708 # number of replacements system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.total_refs 14038431 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2043214 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 6.870759 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 14038404 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2043220 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 6.870726 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7807780 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807780 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655992 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655992 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655992 # number of overall hits -system.cpu.dcache.overall_hits::total 13655992 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721707 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721707 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 7807768 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807768 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13655967 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655967 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655967 # number of overall hits +system.cpu.dcache.overall_hits::total 13655967 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721710 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721710 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026069 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026069 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026069 # number of overall misses -system.cpu.dcache.overall_misses::total 2026069 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15682061 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses +system.cpu.dcache.demand_misses::cpu.data 2026075 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026075 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026075 # number of overall misses +system.cpu.dcache.overall_misses::total 2026075 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses @@ -450,5 +370,85 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks system.cpu.dcache.writebacks::total 833491 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 992297 # number of replacements +system.cpu.l2cache.tagsinuse 65424.375500 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2433229 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1057460 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.301013 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 56309.097195 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 4867.351144 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 4247.927161 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.998297 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 906782 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 811232 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1718014 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187234 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187234 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906782 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998466 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905248 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 906782 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998466 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905248 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 13404 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 941044 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 117115 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 117115 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13404 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044755 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1058159 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13404 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1044755 # number of overall misses +system.cpu.l2cache.overall_misses::total 1058159 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 920186 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1738872 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2659058 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304349 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304349 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 920186 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2043221 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2963407 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 920186 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2043221 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2963407 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014567 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.353901 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384805 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.384805 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014567 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511327 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014567 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511327 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 74287 # number of writebacks +system.cpu.l2cache.writebacks::total 74287 # number of writebacks +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 181c5df24..ba361e6db 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962058 # Number of seconds simulated -sim_ticks 1962057812000 # Number of ticks simulated -final_tick 1962057812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.955746 # Number of seconds simulated +sim_ticks 1955746240500 # Number of ticks simulated +final_tick 1955746240500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1235183 # Simulator instruction rate (inst/s) -host_op_rate 1235183 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40819911602 # Simulator tick rate (ticks/s) -host_mem_usage 297060 # Number of bytes of host memory used -host_seconds 48.07 # Real time elapsed on the host -sim_insts 59370518 # Number of instructions simulated -sim_ops 59370518 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 834432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24593280 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 29312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 572992 # Number of bytes read from this memory -system.physmem.bytes_read::total 28680832 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 834432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 29312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7715456 # Number of bytes written to this memory -system.physmem.bytes_written::total 7715456 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13038 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 384270 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 458 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8953 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448138 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120554 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120554 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 425284 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12534432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1351039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14939 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 292036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14617730 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 425284 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14939 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3932329 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3932329 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3932329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 425284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12534432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1351039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14939 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 292036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18550059 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 341238 # number of replacements -system.l2c.tagsinuse 65290.171288 # Cycle average of tags in use -system.l2c.total_refs 2492514 # Total number of references to valid blocks. -system.l2c.sampled_refs 406253 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.135374 # Average number of references to valid blocks. -system.l2c.warmup_cycle 7854344000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55481.148199 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4824.640956 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4855.323185 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 116.032373 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 13.026576 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.846575 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.073618 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.074086 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001771 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000199 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996249 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 902430 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 773977 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 86748 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 31919 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1795074 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 820361 # number of Writeback hits -system.l2c.Writeback_hits::total 820361 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 161 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 57 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 218 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 21 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 42 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 172410 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 12341 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 184751 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 902430 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 946387 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 86748 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 44260 # number of demand (read+write) hits -system.l2c.demand_hits::total 1979825 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 902430 # number of overall hits -system.l2c.overall_hits::cpu0.data 946387 # number of overall hits -system.l2c.overall_hits::cpu1.inst 86748 # number of overall hits -system.l2c.overall_hits::cpu1.data 44260 # number of overall hits -system.l2c.overall_hits::total 1979825 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13038 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271462 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 469 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 326 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285295 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2435 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 490 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2925 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 34 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 107 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113176 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8669 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121845 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13038 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 384638 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 469 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8995 # number of demand (read+write) misses -system.l2c.demand_misses::total 407140 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13038 # number of overall misses -system.l2c.overall_misses::cpu0.data 384638 # number of overall misses -system.l2c.overall_misses::cpu1.inst 469 # number of overall misses -system.l2c.overall_misses::cpu1.data 8995 # number of overall misses -system.l2c.overall_misses::total 407140 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 678189500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 14120883000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 24328000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 17368000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 14840768500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1412000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1560000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 2972000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 156000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 208000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 364000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5885512000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 450808000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6336320000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 678189500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 20006395000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 24328000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 468176000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21177088500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 678189500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 20006395000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 24328000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 468176000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21177088500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 915468 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1045439 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 87217 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 32245 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2080369 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 820361 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 820361 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2596 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 547 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3143 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 55 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 94 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 149 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 285586 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 21010 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 306596 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 915468 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1331025 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 87217 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 53255 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2386965 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 915468 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1331025 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 87217 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 53255 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2386965 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014242 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.259663 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.005377 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.010110 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.137137 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.937982 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.895795 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.930640 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.618182 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.776596 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.718121 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.396294 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.412613 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.397412 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014242 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.288979 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005377 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.168904 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.170568 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014242 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.288979 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.005377 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.168904 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.170568 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52016.375211 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.899374 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51872.068230 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 53276.073620 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52019.027673 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 579.876797 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3183.673469 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1016.068376 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4588.235294 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2849.315068 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3401.869159 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52003.180886 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52002.307071 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52003.118716 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52016.375211 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52013.568602 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 51872.068230 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52048.471373 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52014.266591 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52016.375211 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52013.568602 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 51872.068230 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52048.471373 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52014.266591 # average overall miss latency +host_inst_rate 1240365 # Simulator instruction rate (inst/s) +host_op_rate 1240364 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39831169965 # Simulator tick rate (ticks/s) +host_mem_usage 291792 # Number of bytes of host memory used +host_seconds 49.10 # Real time elapsed on the host +sim_insts 60902973 # Number of instructions simulated +sim_ops 60902973 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 830080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24726528 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 35200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 438464 # Number of bytes read from this memory +system.physmem.bytes_read::total 28681152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 830080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 35200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 865280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7699072 # Number of bytes written to this memory +system.physmem.bytes_written::total 7699072 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12970 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386352 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 550 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6851 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448143 # 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number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses +system.iocache.demand_misses::total 41728 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses +system.iocache.overall_misses::total 41728 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21013998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21013998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 11453563806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11453563806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 11474577804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11474577804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 11474577804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11474577804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -385,40 +385,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119325.831461 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119325.831461 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275512.774499 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 275512.774499 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 274846.556530 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 274846.556530 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 274846.556530 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 274846.556530 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 199371000 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119397.715909 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119397.715909 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275644.103918 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 275644.103918 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 274985.089245 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 274985.089245 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 274985.089245 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 274985.089245 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 199825 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 24657 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24712 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8085.776858 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.086152 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11983000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11983000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9287247000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9287247000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9299230000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9299230000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9299230000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9299230000 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11861998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11861998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9292859806 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9292859806 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9304721804 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9304721804 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9304721804 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9304721804 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -427,14 +427,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67320.224719 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67320.224719 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223509.024836 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 223509.024836 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222842.798946 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 222842.798946 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222842.798946 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 222842.798946 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67397.715909 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67397.715909 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223644.103918 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 223644.103918 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222985.089245 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 222985.089245 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222985.089245 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 222985.089245 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -452,22 +452,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8658368 # DTB read hits -system.cpu0.dtb.read_misses 7687 # DTB read misses -system.cpu0.dtb.read_acv 174 # DTB read access violations -system.cpu0.dtb.read_accesses 524201 # DTB read accesses -system.cpu0.dtb.write_hits 6036843 # DTB write hits -system.cpu0.dtb.write_misses 798 # DTB write misses -system.cpu0.dtb.write_acv 115 # DTB write access violations -system.cpu0.dtb.write_accesses 195659 # DTB write accesses -system.cpu0.dtb.data_hits 14695211 # DTB hits -system.cpu0.dtb.data_misses 8485 # DTB misses -system.cpu0.dtb.data_acv 289 # DTB access violations -system.cpu0.dtb.data_accesses 719860 # DTB accesses -system.cpu0.itb.fetch_hits 3948323 # ITB hits -system.cpu0.itb.fetch_misses 3841 # ITB misses -system.cpu0.itb.fetch_acv 143 # ITB acv -system.cpu0.itb.fetch_accesses 3952164 # ITB accesses +system.cpu0.dtb.read_hits 7486542 # DTB read hits +system.cpu0.dtb.read_misses 7443 # DTB read misses +system.cpu0.dtb.read_acv 210 # DTB read access violations +system.cpu0.dtb.read_accesses 490673 # DTB read accesses +system.cpu0.dtb.write_hits 5063820 # DTB write hits +system.cpu0.dtb.write_misses 813 # DTB write misses +system.cpu0.dtb.write_acv 134 # DTB write access violations +system.cpu0.dtb.write_accesses 187452 # DTB write accesses +system.cpu0.dtb.data_hits 12550362 # DTB hits +system.cpu0.dtb.data_misses 8256 # DTB misses +system.cpu0.dtb.data_acv 344 # DTB access violations +system.cpu0.dtb.data_accesses 678125 # DTB accesses +system.cpu0.itb.fetch_hits 3500956 # ITB hits +system.cpu0.itb.fetch_misses 3871 # ITB misses +system.cpu0.itb.fetch_acv 184 # ITB acv +system.cpu0.itb.fetch_accesses 3504827 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -480,118 +480,117 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3924115624 # number of cpu cycles simulated +system.cpu0.numCycles 3910167080 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 54116505 # Number of instructions committed -system.cpu0.committedOps 54116505 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 50087098 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 302903 # Number of float alu accesses -system.cpu0.num_func_calls 1426970 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6243728 # number of instructions that are conditional controls -system.cpu0.num_int_insts 50087098 # number of integer instructions -system.cpu0.num_fp_insts 302903 # number of float instructions -system.cpu0.num_int_register_reads 68610814 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37122288 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 149298 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 152355 # number of times the floating registers were written -system.cpu0.num_mem_refs 14741096 # number of memory refs -system.cpu0.num_load_insts 8689646 # Number of load instructions -system.cpu0.num_store_insts 6051450 # Number of store instructions -system.cpu0.num_idle_cycles 3676817171.998126 # Number of idle cycles -system.cpu0.num_busy_cycles 247298452.001874 # Number of busy cycles -system.cpu0.not_idle_fraction 0.063020 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.936980 # Percentage of idle cycles +system.cpu0.committedInsts 47719039 # Number of instructions committed +system.cpu0.committedOps 47719039 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44257119 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 210954 # Number of float alu accesses +system.cpu0.num_func_calls 1200899 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5607083 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44257119 # number of integer instructions +system.cpu0.num_fp_insts 210954 # number of float instructions +system.cpu0.num_int_register_reads 60839484 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32982631 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102466 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104326 # number of times the floating registers were written +system.cpu0.num_mem_refs 12590587 # number of memory refs +system.cpu0.num_load_insts 7513713 # Number of load instructions +system.cpu0.num_store_insts 5076874 # Number of store instructions +system.cpu0.num_idle_cycles 3701181001.496715 # Number of idle cycles +system.cpu0.num_busy_cycles 208986078.503285 # Number of busy cycles +system.cpu0.not_idle_fraction 0.053447 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.946553 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 202757 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 72604 40.61% 40.61% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1979 1.11% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 104050 58.20% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 178770 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71235 49.27% 49.27% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1979 1.37% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71229 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 144580 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1900688314000 96.87% 96.87% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 102511500 0.01% 96.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 795126500 0.04% 96.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 5572000 0.00% 96.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 60465450000 3.08% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1962056974000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981144 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6789 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 164868 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56806 40.18% 40.18% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1972 1.39% 41.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 420 0.30% 41.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82040 58.03% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141369 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56268 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1972 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 420 0.37% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55848 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114639 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1899887304000 97.18% 97.18% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 92906000 0.00% 97.18% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 760170500 0.04% 97.22% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 309335500 0.02% 97.24% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 54033794000 2.76% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1955083510000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990529 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684565 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808749 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 6 2.68% 2.68% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.48% 11.16% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.34% 12.50% # number of syscalls executed -system.cpu0.kern.syscall::6 30 13.39% 25.89% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.45% 26.34% # number of syscalls executed -system.cpu0.kern.syscall::15 1 0.45% 26.79% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.46% 31.25% # number of syscalls executed -system.cpu0.kern.syscall::19 6 2.68% 33.93% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.79% 35.71% # number of syscalls executed -system.cpu0.kern.syscall::23 2 0.89% 36.61% # number of syscalls executed -system.cpu0.kern.syscall::24 4 1.79% 38.39% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.57% 41.96% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.89% 42.86% # number of syscalls executed -system.cpu0.kern.syscall::45 39 17.41% 60.27% # number of syscalls executed -system.cpu0.kern.syscall::47 4 1.79% 62.05% # number of syscalls executed -system.cpu0.kern.syscall::48 7 3.12% 65.18% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.02% 69.20% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.45% 69.64% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.23% 71.88% # number of syscalls executed -system.cpu0.kern.syscall::71 32 14.29% 86.16% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.34% 87.50% # number of syscalls executed -system.cpu0.kern.syscall::74 9 4.02% 91.52% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.45% 91.96% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.89% 92.86% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.12% 95.98% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.89% 96.87% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.89% 97.77% # number of syscalls executed -system.cpu0.kern.syscall::132 2 0.89% 98.66% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.45% 99.11% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 224 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.680741 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810920 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed +system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed +system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed +system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 91 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3872 2.06% 2.11% # number of callpals executed -system.cpu0.kern.callpal::tbi 44 0.02% 2.13% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal::swpipl 171948 91.52% 93.66% # number of callpals executed -system.cpu0.kern.callpal::rdps 6691 3.56% 97.22% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.00% 97.23% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.23% # number of callpals executed -system.cpu0.kern.callpal::rti 4705 2.50% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 356 0.19% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 149 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 187881 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7233 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1235 # number of protection mode switches +system.cpu0.kern.callpal::wripir 503 0.34% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3070 2.05% 2.39% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.43% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134512 89.86% 92.29% # number of callpals executed +system.cpu0.kern.callpal::rdps 6676 4.46% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 149688 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6889 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1285 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1234 -system.cpu0.kern.mode_good::user 1235 +system.cpu0.kern.mode_good::kernel 1285 +system.cpu0.kern.mode_good::user 1285 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.170607 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186529 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.291568 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958395542000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3661425000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.314412 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1951516113500 99.83% 99.83% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3347061000 0.17% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3873 # number of times the context was actually changed +system.cpu0.kern.swap_context 3071 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -623,51 +622,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 914851 # number of replacements -system.cpu0.icache.tagsinuse 508.781994 # Cycle average of tags in use -system.cpu0.icache.total_refs 53209789 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 915362 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 58.129777 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 36528993000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 508.781994 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.993715 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.993715 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 53209789 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 53209789 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 53209789 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 53209789 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 53209789 # number of overall hits -system.cpu0.icache.overall_hits::total 53209789 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 915491 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 915491 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 915491 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 915491 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 915491 # number of overall misses -system.cpu0.icache.overall_misses::total 915491 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13646549000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13646549000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13646549000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13646549000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13646549000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13646549000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 54125280 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 54125280 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 54125280 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 54125280 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 54125280 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 54125280 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016914 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.016914 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016914 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.016914 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016914 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.016914 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14906.262323 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14906.262323 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14906.262323 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14906.262323 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14906.262323 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14906.262323 # average overall miss latency +system.cpu0.icache.replacements 698187 # number of replacements +system.cpu0.icache.tagsinuse 508.830635 # Cycle average of tags in use +system.cpu0.icache.total_refs 47028847 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 698699 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.309166 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 35739052000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 508.830635 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.993810 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.993810 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 47028847 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47028847 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47028847 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47028847 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47028847 # number of overall hits +system.cpu0.icache.overall_hits::total 47028847 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 698792 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 698792 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 698792 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 698792 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 698792 # number of overall misses +system.cpu0.icache.overall_misses::total 698792 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9694162500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9694162500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9694162500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9694162500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9694162500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9694162500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47727639 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47727639 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47727639 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47727639 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47727639 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47727639 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014641 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014641 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014641 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014641 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014641 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014641 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13872.743964 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13872.743964 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13872.743964 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13872.743964 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13872.743964 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13872.743964 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -676,112 +675,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915491 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 915491 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 915491 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 915491 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 915491 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 915491 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10899382500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10899382500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10899382500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10899382500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10899382500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10899382500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016914 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016914 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016914 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11905.504806 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11905.504806 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11905.504806 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 698792 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 698792 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 698792 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 698792 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 698792 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 698792 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8296578500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8296578500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8296578500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8296578500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8296578500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8296578500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014641 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014641 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014641 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014641 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014641 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014641 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11872.743964 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11872.743964 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11872.743964 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1337819 # number of replacements -system.cpu0.dcache.tagsinuse 506.532892 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13370103 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1338331 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.990132 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 101834000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 506.532892 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.989322 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.989322 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7444463 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7444463 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5554933 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5554933 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 175817 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 175817 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191182 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 191182 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12999396 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12999396 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12999396 # number of overall hits -system.cpu0.dcache.overall_hits::total 12999396 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1037635 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1037635 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 289296 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 289296 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16772 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16772 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 445 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 445 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1326931 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1326931 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1326931 # number of overall misses -system.cpu0.dcache.overall_misses::total 1326931 # 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number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 35076865000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8482098 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8482098 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5844229 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5844229 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 192589 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 192589 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191627 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 191627 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14326327 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14326327 # 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miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.092622 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092622 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092622 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25166.495926 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25166.495926 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30982.896411 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30982.896411 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14228.058669 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14228.058669 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10937.078652 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10937.078652 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26434.580999 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26434.580999 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26434.580999 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 26434.580999 # average overall miss latency +system.cpu0.dcache.replacements 1180402 # number of replacements +system.cpu0.dcache.tagsinuse 505.183019 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11360683 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1180820 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.621012 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 99461000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 505.183019 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.986686 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.986686 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6406782 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6406782 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4655760 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4655760 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140286 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140286 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147915 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 147915 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11062542 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11062542 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11062542 # number of overall hits +system.cpu0.dcache.overall_hits::total 11062542 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 938249 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 938249 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 251643 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 251643 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13638 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13638 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5458 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5458 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1189892 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1189892 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1189892 # number of overall misses +system.cpu0.dcache.overall_misses::total 1189892 # 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number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 31723890000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7345031 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7345031 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4907403 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4907403 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 153924 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 153924 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153373 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153373 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12252434 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12252434 # 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average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23434.532785 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23434.532785 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23434.532785 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23434.532785 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 679069 # number of writebacks +system.cpu0.dcache.writebacks::total 679069 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938249 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 938249 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251643 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251643 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13638 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13638 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5458 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5458 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1189892 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1189892 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1189892 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1189892 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21646065000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21646065000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7698041000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7698041000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 120630000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 120630000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 56880500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 56880500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29344106000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 29344106000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29344106000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 29344106000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465334500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465334500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2275733500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2275733500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3741068000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3741068000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127739 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127739 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051278 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051278 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088602 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088602 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035586 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035586 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097115 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097115 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097115 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097115 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 23070.704046 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 23070.704046 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30591.119165 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30591.119165 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8845.138583 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8845.138583 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 10421.491389 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 10421.491389 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24661.150760 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24661.150760 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24661.150760 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24661.150760 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -857,22 +856,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1027530 # DTB read hits -system.cpu1.dtb.read_misses 2750 # DTB read misses -system.cpu1.dtb.read_acv 36 # DTB read access violations -system.cpu1.dtb.read_accesses 205838 # DTB read accesses -system.cpu1.dtb.write_hits 663193 # DTB write hits -system.cpu1.dtb.write_misses 356 # DTB write misses -system.cpu1.dtb.write_acv 48 # DTB write access violations -system.cpu1.dtb.write_accesses 97040 # DTB write accesses -system.cpu1.dtb.data_hits 1690723 # DTB hits -system.cpu1.dtb.data_misses 3106 # DTB misses -system.cpu1.dtb.data_acv 84 # DTB access violations -system.cpu1.dtb.data_accesses 302878 # DTB accesses -system.cpu1.itb.fetch_hits 1394871 # ITB hits -system.cpu1.itb.fetch_misses 1246 # ITB misses -system.cpu1.itb.fetch_acv 41 # ITB acv -system.cpu1.itb.fetch_accesses 1396117 # ITB accesses +system.cpu1.dtb.read_hits 2425080 # DTB read hits +system.cpu1.dtb.read_misses 2992 # DTB read misses +system.cpu1.dtb.read_acv 0 # DTB read access violations +system.cpu1.dtb.read_accesses 239363 # DTB read accesses +system.cpu1.dtb.write_hits 1761000 # DTB write hits +system.cpu1.dtb.write_misses 341 # DTB write misses +system.cpu1.dtb.write_acv 29 # DTB write access violations +system.cpu1.dtb.write_accesses 105247 # DTB write accesses +system.cpu1.dtb.data_hits 4186080 # DTB hits +system.cpu1.dtb.data_misses 3333 # DTB misses +system.cpu1.dtb.data_acv 29 # DTB access violations +system.cpu1.dtb.data_accesses 344610 # DTB accesses +system.cpu1.itb.fetch_hits 1964871 # ITB hits +system.cpu1.itb.fetch_misses 1216 # ITB misses +system.cpu1.itb.fetch_acv 0 # ITB acv +system.cpu1.itb.fetch_accesses 1966087 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -885,150 +884,141 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3923836552 # number of cpu cycles simulated +system.cpu1.numCycles 3911492481 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5254013 # Number of instructions committed -system.cpu1.committedOps 5254013 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 4921025 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 25430 # Number of float alu accesses -system.cpu1.num_func_calls 157600 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 506865 # number of instructions that are conditional controls -system.cpu1.num_int_insts 4921025 # number of integer instructions -system.cpu1.num_fp_insts 25430 # number of float instructions -system.cpu1.num_int_register_reads 6827399 # number of times the integer registers were read -system.cpu1.num_int_register_writes 3700117 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 16282 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 16129 # number of times the floating registers were written -system.cpu1.num_mem_refs 1700348 # number of memory refs -system.cpu1.num_load_insts 1033584 # Number of load instructions -system.cpu1.num_store_insts 666764 # Number of store instructions -system.cpu1.num_idle_cycles 3903107404.303190 # Number of idle cycles -system.cpu1.num_busy_cycles 20729147.696810 # Number of busy cycles -system.cpu1.not_idle_fraction 0.005283 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.994717 # Percentage of idle cycles +system.cpu1.committedInsts 13183934 # Number of instructions committed +system.cpu1.committedOps 13183934 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12160396 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 172922 # Number of float alu accesses +system.cpu1.num_func_calls 412685 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1307407 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12160396 # number of integer instructions +system.cpu1.num_fp_insts 172922 # number of float instructions +system.cpu1.num_int_register_reads 16740645 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8924669 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90471 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 92344 # number of times the floating registers were written +system.cpu1.num_mem_refs 4209624 # number of memory refs +system.cpu1.num_load_insts 2439377 # Number of load instructions +system.cpu1.num_store_insts 1770247 # Number of store instructions +system.cpu1.num_idle_cycles 3861803254.998025 # Number of idle cycles +system.cpu1.num_busy_cycles 49689226.001975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012703 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987297 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2331 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 35942 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 9143 31.85% 31.85% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1973 6.87% 38.72% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 91 0.32% 39.04% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17499 60.96% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 28706 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 9135 45.13% 45.13% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1973 9.75% 54.87% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 9044 44.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 20243 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1920766593500 97.90% 97.90% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 726074500 0.04% 97.94% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 67017000 0.00% 97.94% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 40358561000 2.06% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1961918246000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999125 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78634 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26575 38.36% 38.36% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1967 2.84% 41.20% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 503 0.73% 41.93% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40225 58.07% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69270 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25736 48.16% 48.16% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1967 3.68% 51.84% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 503 0.94% 52.78% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25233 47.22% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53439 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909053778500 97.61% 97.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 705460500 0.04% 97.65% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 351339000 0.02% 97.67% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 45634904500 2.33% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1955745482500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968429 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.516830 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.705184 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 2 1.96% 1.96% # number of syscalls executed -system.cpu1.kern.syscall::3 11 10.78% 12.75% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.98% 13.73% # number of syscalls executed -system.cpu1.kern.syscall::6 12 11.76% 25.49% # number of syscalls executed -system.cpu1.kern.syscall::17 5 4.90% 30.39% # number of syscalls executed -system.cpu1.kern.syscall::19 4 3.92% 34.31% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.96% 36.27% # number of syscalls executed -system.cpu1.kern.syscall::23 2 1.96% 38.24% # number of syscalls executed -system.cpu1.kern.syscall::24 2 1.96% 40.20% # number of syscalls executed -system.cpu1.kern.syscall::33 3 2.94% 43.14% # number of syscalls executed -system.cpu1.kern.syscall::45 15 14.71% 57.84% # number of syscalls executed -system.cpu1.kern.syscall::47 2 1.96% 59.80% # number of syscalls executed -system.cpu1.kern.syscall::48 3 2.94% 62.75% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.98% 63.73% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.96% 65.69% # number of syscalls executed -system.cpu1.kern.syscall::71 22 21.57% 87.25% # number of syscalls executed -system.cpu1.kern.syscall::74 7 6.86% 94.12% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.98% 95.10% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.96% 97.06% # number of syscalls executed -system.cpu1.kern.syscall::132 2 1.96% 99.02% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.98% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 102 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.627296 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771460 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed +system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed +system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed +system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 365 1.24% 1.27% # number of callpals executed -system.cpu1.kern.callpal::tbi 10 0.03% 1.31% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.33% # number of callpals executed -system.cpu1.kern.callpal::swpipl 24054 81.82% 83.15% # number of callpals executed -system.cpu1.kern.callpal::rdps 2165 7.36% 90.51% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 90.52% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 90.53% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.01% 90.53% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 90.54% # number of callpals executed -system.cpu1.kern.callpal::rti 2587 8.80% 99.34% # number of callpals executed -system.cpu1.kern.callpal::callsys 161 0.55% 99.89% # number of callpals executed -system.cpu1.kern.callpal::imb 31 0.11% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 420 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1995 2.79% 3.38% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed +system.cpu1.kern.callpal::swpipl 63027 88.05% 91.44% # number of callpals executed +system.cpu1.kern.callpal::rdps 2168 3.03% 94.47% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.47% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.47% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.48% # number of callpals executed +system.cpu1.kern.callpal::rti 3772 5.27% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 29399 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 879 # number of protection mode switches -system.cpu1.kern.mode_switch::user 515 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2075 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 531 -system.cpu1.kern.mode_good::user 515 -system.cpu1.kern.mode_good::idle 16 -system.cpu1.kern.mode_switch_good::kernel 0.604096 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 71584 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2065 # number of protection mode switches +system.cpu1.kern.mode_switch::user 464 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2874 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 891 +system.cpu1.kern.mode_good::user 464 +system.cpu1.kern.mode_good::idle 427 +system.cpu1.kern.mode_switch_good::kernel 0.431477 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.007711 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.306140 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4075179000 0.21% 0.21% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1593973000 0.08% 0.29% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1955466537000 99.71% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 366 # number of times the context was actually changed -system.cpu1.icache.replacements 86678 # number of replacements -system.cpu1.icache.tagsinuse 419.761864 # Cycle average of tags in use -system.cpu1.icache.total_refs 5169985 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 87190 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 59.295619 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1958463060000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 419.761864 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.819847 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.819847 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 5169985 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5169985 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5169985 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5169985 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5169985 # number of overall hits -system.cpu1.icache.overall_hits::total 5169985 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 87218 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 87218 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 87218 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 87218 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 87218 # number of overall misses -system.cpu1.icache.overall_misses::total 87218 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1315004000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1315004000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1315004000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1315004000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1315004000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1315004000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5257203 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5257203 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5257203 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5257203 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5257203 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5257203 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016590 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.016590 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016590 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.016590 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016590 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.016590 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15077.208833 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15077.208833 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15077.208833 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15077.208833 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15077.208833 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15077.208833 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.148573 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.329817 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17893399500 0.91% 0.91% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1709951500 0.09% 1.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1936142128000 99.00% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1996 # number of times the context was actually changed +system.cpu1.icache.replacements 316204 # number of replacements +system.cpu1.icache.tagsinuse 447.456269 # Cycle average of tags in use +system.cpu1.icache.total_refs 12870545 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 316716 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 40.637495 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1953875803000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 447.456269 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.873938 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.873938 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 12870545 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12870545 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12870545 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12870545 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12870545 # number of overall hits +system.cpu1.icache.overall_hits::total 12870545 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 316752 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 316752 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 316752 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 316752 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 316752 # number of overall misses +system.cpu1.icache.overall_misses::total 316752 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4179857000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4179857000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4179857000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4179857000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4179857000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4179857000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13187297 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13187297 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13187297 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13187297 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13187297 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13187297 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024019 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024019 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024019 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024019 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024019 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024019 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13195.992448 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13195.992448 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13195.992448 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13195.992448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13195.992448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13195.992448 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1037,112 +1027,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 87218 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 87218 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 87218 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 87218 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 87218 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 87218 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1053316500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1053316500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1053316500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1053316500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1053316500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1053316500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016590 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.016590 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.016590 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12076.824738 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12076.824738 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12076.824738 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316752 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 316752 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 316752 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 316752 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 316752 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 316752 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3546353000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3546353000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3546353000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3546353000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3546353000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3546353000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024019 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024019 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024019 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11195.992448 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11195.992448 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11195.992448 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 53530 # number of replacements -system.cpu1.dcache.tagsinuse 416.811223 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1627239 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 53938 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 30.168694 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1941569871000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 416.811223 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.814084 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.814084 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 982758 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 982758 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 626472 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 626472 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 11310 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 11310 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11707 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 11707 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1609230 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1609230 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1609230 # number of overall hits -system.cpu1.dcache.overall_hits::total 1609230 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 35626 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 35626 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 22614 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 22614 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1003 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1003 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 544 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 544 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 58240 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 58240 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 58240 # number of overall misses -system.cpu1.dcache.overall_misses::total 58240 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 484494000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 484494000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 694414000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 694414000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 12192000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 12192000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 7087000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 7087000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 1178908000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 1178908000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 1178908000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 1178908000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1018384 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1018384 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 649086 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 649086 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 12313 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 12313 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 12251 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 12251 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1667470 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1667470 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1667470 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1667470 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034983 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.034983 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034840 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034840 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081459 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081459 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044405 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044405 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034927 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.034927 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034927 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.034927 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13599.449840 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13599.449840 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30707.260989 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 30707.260989 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12155.533400 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12155.533400 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13027.573529 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13027.573529 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20242.239011 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20242.239011 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20242.239011 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20242.239011 # average overall miss latency +system.cpu1.dcache.replacements 166318 # number of replacements +system.cpu1.dcache.tagsinuse 487.121043 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4017452 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 166830 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 24.081113 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 63885131000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 487.121043 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.951408 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.951408 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2260833 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2260833 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1643465 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1643465 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48243 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 48243 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50839 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50839 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3904298 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3904298 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3904298 # number of overall hits +system.cpu1.dcache.overall_hits::total 3904298 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 118301 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 118301 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 62725 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 62725 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8915 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8915 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5846 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5846 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 181026 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 181026 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 181026 # number of overall misses +system.cpu1.dcache.overall_misses::total 181026 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1440550500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1440550500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1113565500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1113565500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81445500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 81445500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 69062000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 69062000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2554116000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2554116000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2554116000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2554116000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2379134 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2379134 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1706190 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1706190 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57158 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 57158 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56685 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 56685 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4085324 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4085324 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4085324 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4085324 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049724 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049724 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036763 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.036763 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155971 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155971 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103131 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103131 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044311 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044311 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044311 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044311 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12176.993432 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12176.993432 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17753.136708 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17753.136708 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9135.782389 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9135.782389 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11813.547725 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11813.547725 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14109.111398 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14109.111398 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14109.111398 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14109.111398 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1151,62 +1141,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 35195 # number of writebacks -system.cpu1.dcache.writebacks::total 35195 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35626 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 35626 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 22614 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 22614 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1003 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1003 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 544 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 544 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 58240 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 58240 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 58240 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 58240 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 377607005 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 377607005 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 626568004 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 626568004 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9183000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 9183000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5455000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5455000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1004175009 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1004175009 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1004175009 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1004175009 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20565000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20565000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 534647000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 534647000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555212000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555212000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.034983 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.034983 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034840 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034840 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.081459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.044405 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.044405 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034927 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.034927 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034927 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034927 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10599.197356 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10599.197356 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27707.084284 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27707.084284 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9155.533400 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9155.533400 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10027.573529 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10027.573529 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17242.015951 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17242.015951 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17242.015951 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17242.015951 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 114265 # number of writebacks +system.cpu1.dcache.writebacks::total 114265 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118301 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 118301 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62725 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 62725 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8915 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8915 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5846 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5846 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 181026 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 181026 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 181026 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 181026 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1203948500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1203948500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 988115500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 988115500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63615500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 63615500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57370000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57370000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2192064000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2192064000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2192064000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2192064000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19387500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19387500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713392500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713392500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732780000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732780000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049724 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049724 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036763 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036763 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155971 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155971 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103131 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103131 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044311 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044311 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044311 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044311 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10176.993432 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10176.993432 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15753.136708 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15753.136708 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7135.782389 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7135.782389 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9813.547725 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9813.547725 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12109.111398 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12109.111398 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12109.111398 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12109.111398 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 23658f386..369a1e336 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.914421 # Nu sim_ticks 1914420945000 # Number of ticks simulated final_tick 1914420945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1284205 # Simulator instruction rate (inst/s) -host_op_rate 1284205 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43773036105 # Simulator tick rate (ticks/s) -host_mem_usage 295308 # Number of bytes of host memory used -host_seconds 43.74 # Real time elapsed on the host +host_inst_rate 1299276 # Simulator instruction rate (inst/s) +host_op_rate 1299275 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44286723014 # Simulator tick rate (ticks/s) +host_mem_usage 288696 # Number of bytes of host memory used +host_seconds 43.23 # Real time elapsed on the host sim_insts 56164879 # Number of instructions simulated sim_ops 56164879 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory @@ -87,11 +87,11 @@ system.iocache.demand_avg_miss_latency::tsunami.ide 274768.790989 system.iocache.demand_avg_miss_latency::total 274768.790989 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency system.iocache.overall_avg_miss_latency::total 274768.790989 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 199052000 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 199052 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 24614 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8086.942391 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.086942 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -105,14 +105,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9283200000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9283200000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9294876000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9294876000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9294876000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9294876000 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11676998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9283350806 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9283350806 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9295027804 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9295027804 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9295027804 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9295027804 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -121,14 +121,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223411.628802 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 223411.628802 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222765.152786 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 222765.152786 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222765.152786 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 222765.152786 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67497.098266 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67497.098266 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223415.258134 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 223415.258134 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222768.790989 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 222768.790989 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222768.790989 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 222768.790989 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -649,14 +649,14 @@ system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10884274000 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11416158000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675219000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675219000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675219500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675219500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 531884000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559493000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16091377000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559493500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16091377500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 531884000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559493000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16091377000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559493500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16091377500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1332180000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1332180000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892328500 # number of WriteReq MSHR uncacheable cycles @@ -681,14 +681,14 @@ system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40020.127220 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40020.185094 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.350739 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.350739 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.355018 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.355018 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40016.287365 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40016.455328 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40016.288651 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40016.456571 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40016.287365 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40016.455328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40016.288651 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40016.456571 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 0ffcacbe4..0a013f420 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,75 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.207291 # Number of seconds simulated -sim_ticks 1207290627000 # Number of ticks simulated -final_tick 1207290627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.203695 # Number of seconds simulated +sim_ticks 1203694548000 # Number of ticks simulated +final_tick 1203694548000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 648322 # Simulator instruction rate (inst/s) -host_op_rate 826248 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12731770448 # Simulator tick rate (ticks/s) -host_mem_usage 380152 # Number of bytes of host memory used -host_seconds 94.83 # Real time elapsed on the host -sim_insts 61477134 # Number of instructions simulated -sim_ops 78349023 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 52642784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 394084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4718772 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 323100 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4791152 # Number of bytes read from this memory -system.physmem.bytes_read::total 62870404 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 394084 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 323100 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4105920 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7133264 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 6580348 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12376 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5130 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74888 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6746553 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64155 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 820991 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43604069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 106 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 326420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3908563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 267624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3968516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52075617 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 326420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 267624 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 594044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3400938 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14081 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2493471 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5908490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3400938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43604069 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 326420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3922645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 212 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 267624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6461987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57984106 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 610810 # Simulator instruction rate (inst/s) +host_op_rate 778429 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11963163223 # Simulator tick rate (ticks/s) +host_mem_usage 383784 # Number of bytes of host memory used +host_seconds 100.62 # Real time elapsed on the host +sim_insts 61457649 # Number of instructions simulated +sim_ops 78322983 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -88,251 +29,292 @@ system.realview.nvmem.bw_inst_read::total 56 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 69267 # number of replacements -system.l2c.tagsinuse 52917.687101 # Cycle average of tags in use -system.l2c.total_refs 1645693 # Total number of references to valid blocks. -system.l2c.sampled_refs 134464 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.238912 # Average number of references to valid blocks. +system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 354404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4259252 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 364636 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5307760 # Number of bytes read from this memory +system.physmem.bytes_read::total 62191012 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 354404 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 364636 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 719040 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4163840 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory +system.physmem.bytes_written::total 7191184 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11756 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 66623 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5779 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82960 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6655189 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 65060 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory +system.physmem.num_writes::total 821896 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43120999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 294430 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3538482 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 302931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4409557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51666772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 294430 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 302931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 597361 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3459216 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14123 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2500920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5974260 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3459216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43120999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 294430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3552606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 302931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6910477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57641032 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 70187 # number of replacements +system.l2c.tagsinuse 53228.642974 # Cycle average of tags in use +system.l2c.total_refs 1643789 # Total number of references to valid blocks. +system.l2c.sampled_refs 135350 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.144728 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40124.661917 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000403 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001466 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3720.854167 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4213.259554 # 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average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40027.940056 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40072.547403 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40075.805801 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40082.908163 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40098.493304 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40089.647683 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.634446 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40074.226804 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.233397 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40006.444124 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40041.816422 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40024.782668 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40009.498417 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40089.798466 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40070.196166 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40047.606680 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40029.842942 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.831745 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40003.051908 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40020.615979 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40009.585810 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40010.813699 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40147.319169 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40087.526994 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40010.696679 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40143.499941 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40085.138012 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40010.696679 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40143.499941 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40085.138012 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -528,27 +498,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7076084 # DTB read hits -system.cpu0.dtb.read_misses 3743 # DTB read misses -system.cpu0.dtb.write_hits 5660386 # DTB write hits -system.cpu0.dtb.write_misses 804 # DTB write misses +system.cpu0.dtb.read_hits 4800541 # DTB read hits +system.cpu0.dtb.read_misses 2116 # DTB read misses +system.cpu0.dtb.write_hits 4101169 # DTB write hits +system.cpu0.dtb.write_misses 405 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1539 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7079827 # DTB read accesses -system.cpu0.dtb.write_accesses 5661190 # DTB write accesses +system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 4802657 # DTB read accesses +system.cpu0.dtb.write_accesses 4101574 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12736470 # DTB hits -system.cpu0.dtb.misses 4547 # DTB misses -system.cpu0.dtb.accesses 12741017 # DTB accesses -system.cpu0.itb.inst_hits 29574655 # ITB inst hits -system.cpu0.itb.inst_misses 2205 # ITB inst misses +system.cpu0.dtb.hits 8901710 # DTB hits +system.cpu0.dtb.misses 2521 # DTB misses +system.cpu0.dtb.accesses 8904231 # DTB accesses +system.cpu0.itb.inst_hits 19425295 # ITB inst hits +system.cpu0.itb.inst_misses 1350 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -557,86 +527,86 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29576860 # ITB inst accesses -system.cpu0.itb.hits 29574655 # DTB hits -system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29576860 # DTB accesses -system.cpu0.numCycles 2414581254 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 19426645 # ITB inst accesses +system.cpu0.itb.hits 19425295 # DTB hits +system.cpu0.itb.misses 1350 # DTB misses +system.cpu0.itb.accesses 19426645 # DTB accesses +system.cpu0.numCycles 2405961611 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28876799 # Number of instructions committed -system.cpu0.committedOps 37228975 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33114839 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241592 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4373527 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33114839 # number of integer instructions -system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 190147140 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36238708 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13404188 # number of memory refs -system.cpu0.num_load_insts 7413537 # Number of load instructions -system.cpu0.num_store_insts 5990651 # Number of store instructions -system.cpu0.num_idle_cycles 2267023582.330122 # Number of idle cycles -system.cpu0.num_busy_cycles 147557671.669878 # Number of busy cycles -system.cpu0.not_idle_fraction 0.061111 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.938889 # Percentage of idle cycles +system.cpu0.committedInsts 19048182 # Number of instructions committed +system.cpu0.committedOps 25051772 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 22684080 # 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Number of idle cycles +system.cpu0.num_busy_cycles 104459206.176251 # Number of busy cycles +system.cpu0.not_idle_fraction 0.043417 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.956583 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46683 # number of quiesce instructions executed -system.cpu0.icache.replacements 408135 # number of replacements -system.cpu0.icache.tagsinuse 509.469782 # Cycle average of tags in use -system.cpu0.icache.total_refs 29165991 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 408647 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 71.372091 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 75845657000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.469782 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995058 # 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number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6096279000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6096279000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6096279000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6096279000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6096279000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6096279000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29574638 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29574638 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29574638 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29574638 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29574638 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29574638 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013817 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013817 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013817 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013817 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013817 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013817 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.203241 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.203241 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14918.203241 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14918.203241 # average overall miss latency +system.cpu0.kern.inst.quiesce 34020 # number of quiesce instructions executed +system.cpu0.icache.replacements 283184 # number of replacements +system.cpu0.icache.tagsinuse 509.502628 # Cycle average of tags in use +system.cpu0.icache.total_refs 19141582 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 283696 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.472160 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 75588601000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.502628 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995122 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995122 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 19141582 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 19141582 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 19141582 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 19141582 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 19141582 # number of overall hits +system.cpu0.icache.overall_hits::total 19141582 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 283696 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 283696 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 283696 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 283696 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 283696 # number of overall misses +system.cpu0.icache.overall_misses::total 283696 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 3929923500 # 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number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014604 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014604 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014604 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014604 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014604 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014604 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13852.586924 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13852.586924 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13852.586924 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13852.586924 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13852.586924 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13852.586924 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -645,120 +615,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408647 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 408647 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 408647 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 408647 # 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miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062733 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061308 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061308 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030743 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.030743 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030743 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.030743 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13596.209913 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13596.209913 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35907.261581 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35907.261581 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 8916.687817 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8916.687817 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8618.227881 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8618.227881 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23502.313804 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 23502.313804 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23502.313804 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23502.313804 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -767,66 +737,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306480 # number of writebacks -system.cpu0.dcache.writebacks::total 306480 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228053 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 228053 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141722 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141722 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9325 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9325 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369775 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369775 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369775 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369775 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758303642 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758303642 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493366071 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493366071 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72896006 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72896006 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52131016 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52131016 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1001 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1001 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251669713 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7251669713 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251669713 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7251669713 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559876000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559876000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253192500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253192500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813068500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813068500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033372 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033372 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025782 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025782 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059295 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059295 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047646 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047646 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029988 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029988 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12095.011432 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12095.011432 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.494355 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.494355 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.266059 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.266059 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6961.011617 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6961.011617 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 204960 # number of writebacks +system.cpu0.dcache.writebacks::total 204960 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 146461 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 146461 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 116958 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 116958 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7880 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7880 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7695 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7695 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 263419 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 263419 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 263419 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 263419 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1698392500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1698392500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3965725500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3965725500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54503500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 54503500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50946500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50946500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5664118000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5664118000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5664118000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5664118000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12130688000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12130688000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1193496500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1193496500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13324184500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13324184500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031847 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031847 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029464 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029464 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062733 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062733 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.061292 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.061292 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030743 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030743 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11596.209913 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11596.209913 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33907.261581 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33907.261581 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 6916.687817 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6916.687817 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6620.727745 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6620.727745 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21502.313804 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21502.313804 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21502.313804 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21502.313804 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -836,27 +806,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8318170 # DTB read hits -system.cpu1.dtb.read_misses 3663 # DTB read misses -system.cpu1.dtb.write_hits 5832653 # DTB write hits -system.cpu1.dtb.write_misses 1435 # DTB write misses +system.cpu1.dtb.read_hits 10590618 # DTB read hits +system.cpu1.dtb.read_misses 5230 # DTB read misses +system.cpu1.dtb.write_hits 7384755 # DTB write hits +system.cpu1.dtb.write_misses 1835 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1968 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2257 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8321833 # DTB read accesses -system.cpu1.dtb.write_accesses 5834088 # DTB write accesses +system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10595848 # DTB read accesses +system.cpu1.dtb.write_accesses 7386590 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14150823 # DTB hits -system.cpu1.dtb.misses 5098 # DTB misses -system.cpu1.dtb.accesses 14155921 # DTB accesses -system.cpu1.itb.inst_hits 33211066 # ITB inst hits -system.cpu1.itb.inst_misses 2171 # ITB inst misses +system.cpu1.dtb.hits 17975373 # DTB hits +system.cpu1.dtb.misses 7065 # DTB misses +system.cpu1.dtb.accesses 17982438 # DTB accesses +system.cpu1.itb.inst_hits 43340388 # ITB inst hits +system.cpu1.itb.inst_misses 3017 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -865,86 +835,86 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33213237 # ITB inst accesses -system.cpu1.itb.hits 33211066 # DTB hits -system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33213237 # DTB accesses -system.cpu1.numCycles 2413083038 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 43343405 # ITB inst accesses +system.cpu1.itb.hits 43340388 # DTB hits +system.cpu1.itb.misses 3017 # DTB misses +system.cpu1.itb.accesses 43343405 # DTB accesses +system.cpu1.numCycles 2407389096 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32600335 # Number of instructions committed -system.cpu1.committedOps 41120048 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37342001 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 963082 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3735102 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37342001 # number of integer instructions -system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 213831809 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39482622 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14689113 # number of memory refs -system.cpu1.num_load_insts 8640454 # Number of load instructions -system.cpu1.num_store_insts 6048659 # Number of store instructions -system.cpu1.num_idle_cycles 1863361359.722463 # Number of idle cycles -system.cpu1.num_busy_cycles 549721678.277537 # Number of busy cycles -system.cpu1.not_idle_fraction 0.227809 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.772191 # Percentage of idle cycles +system.cpu1.committedInsts 42409467 # Number of instructions committed +system.cpu1.committedOps 53271211 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 47739499 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses +system.cpu1.num_func_calls 1335008 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5483103 # number of instructions that are conditional controls +system.cpu1.num_int_insts 47739499 # number of integer instructions +system.cpu1.num_fp_insts 5457 # number of float instructions +system.cpu1.num_int_register_reads 274842107 # number of times the integer registers were read +system.cpu1.num_int_register_writes 51975033 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written +system.cpu1.num_mem_refs 18684058 # number of memory refs +system.cpu1.num_load_insts 11000639 # Number of load instructions +system.cpu1.num_store_insts 7683419 # Number of store instructions +system.cpu1.num_idle_cycles 1827105047.254482 # Number of idle cycles +system.cpu1.num_busy_cycles 580284048.745518 # Number of busy cycles +system.cpu1.not_idle_fraction 0.241043 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.758957 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43948 # number of quiesce instructions executed -system.cpu1.icache.replacements 455071 # number of replacements -system.cpu1.icache.tagsinuse 479.019014 # Cycle average of tags in use -system.cpu1.icache.total_refs 32755479 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 455583 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 71.897940 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 94151388000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 479.019014 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935584 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935584 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 32755479 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32755479 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32755479 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32755479 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32755479 # number of overall hits -system.cpu1.icache.overall_hits::total 32755479 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 455583 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 455583 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 455583 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 455583 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 455583 # number of overall misses -system.cpu1.icache.overall_misses::total 455583 # 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average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14768.439560 # average overall miss latency +system.cpu1.kern.inst.quiesce 56706 # number of quiesce instructions executed +system.cpu1.icache.replacements 582628 # number of replacements +system.cpu1.icache.tagsinuse 479.068937 # Cycle average of tags in use +system.cpu1.icache.total_refs 42757244 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 583140 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 73.322434 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 92849627500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 479.068937 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.935682 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.935682 # 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Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 39.022077 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 84382221000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 473.304740 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.924423 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.924423 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 9101949 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9101949 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6323711 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6323711 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 111853 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 111853 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 114473 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 114473 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 15425660 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 15425660 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 15425660 # number of overall hits +system.cpu1.dcache.overall_hits::total 15425660 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 253200 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 253200 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 178129 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 178129 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13100 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13100 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10404 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10404 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 431329 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 431329 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 431329 # number of overall misses +system.cpu1.dcache.overall_misses::total 431329 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3278248500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3278248500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5660664500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 5660664500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 115759000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 115759000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 63020500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 63020500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8938913000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8938913000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8938913000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8938913000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9355149 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9355149 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6501840 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6501840 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 124953 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 124953 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 124877 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 124877 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 15856989 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 15856989 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 15856989 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 15856989 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027065 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.027065 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027397 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027397 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104839 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104839 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083314 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083314 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027201 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027201 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027201 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.027201 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12947.268957 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12947.268957 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31778.455501 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 31778.455501 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8836.564885 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8836.564885 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6057.333718 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6057.333718 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20724.117785 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20724.117785 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20724.117785 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20724.117785 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1075,62 +1045,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 266100 # number of writebacks -system.cpu1.dcache.writebacks::total 266100 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170988 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170988 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150171 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150171 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11121 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11121 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10070 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10070 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 321159 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 321159 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 321159 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 321159 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860790612 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860790612 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686951190 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686951190 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72983005 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72983005 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57622011 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57622011 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547741802 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6547741802 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547741802 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6547741802 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686201000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686201000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932204000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932204000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618405000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618405000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024002 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024002 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030142 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030142 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119518 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119518 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108316 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108316 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026529 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026529 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10882.580134 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10882.580134 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.760999 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.760999 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6562.629710 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6562.629710 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.146077 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.146077 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 366483 # number of writebacks +system.cpu1.dcache.writebacks::total 366483 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 253200 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 253200 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 178129 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 178129 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13100 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13100 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10399 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10399 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 431329 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 431329 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 431329 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 431329 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2771848500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2771848500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5304406500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5304406500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89559000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89559000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 42226500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 42226500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8076255000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8076255000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8076255000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8076255000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170163530000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170163530000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40377042500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40377042500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210540572500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210540572500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027065 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027065 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027397 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027397 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104839 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104839 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083274 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083274 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027201 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027201 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027201 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027201 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.268957 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.268957 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29778.455501 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29778.455501 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6836.564885 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6836.564885 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4060.630830 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4060.630830 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18724.117785 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18724.117785 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18724.117785 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18724.117785 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1152,10 +1126,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574279130811 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 574279130811 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574279130811 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 574279130811 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 567076826640 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 567076826640 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 567076826640 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 567076826640 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 07e356a30..e07e69ea6 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,28 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.624688 # Number of seconds simulated -sim_ticks 2624688029000 # Number of ticks simulated -final_tick 2624688029000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2624688000000 # Number of ticks simulated +final_tick 2624688000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 388710 # Simulator instruction rate (inst/s) -host_op_rate 494628 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16947208284 # Simulator tick rate (ticks/s) -host_mem_usage 385844 # Number of bytes of host memory used -host_seconds 154.87 # Real time elapsed on the host +host_inst_rate 509092 # Simulator instruction rate (inst/s) +host_op_rate 647812 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22195691402 # Simulator tick rate (ticks/s) +host_mem_usage 379628 # Number of bytes of host memory used +host_seconds 118.25 # Real time elapsed on the host sim_insts 60201138 # Number of instructions simulated sim_ops 76605123 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory @@ -60,7 +48,19 @@ system.physmem.bw_total::cpu.dtb.walker 122 # To system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 268917 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4596999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53608355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53608356 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -109,7 +109,7 @@ system.cpu.itb.inst_accesses 61499578 # IT system.cpu.itb.hits 61495107 # DTB hits system.cpu.itb.misses 4471 # DTB misses system.cpu.itb.accesses 61499578 # DTB accesses -system.cpu.numCycles 5249376058 # number of cpu cycles simulated +system.cpu.numCycles 5249376000 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 60201138 # Number of instructions committed @@ -121,14 +121,14 @@ system.cpu.num_conditional_control_insts 7948064 # nu system.cpu.num_int_insts 68872510 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions system.cpu.num_int_register_reads 394780312 # number of times the integer registers were read -system.cpu.num_int_register_writes 74180713 # number of times the integer registers were written +system.cpu.num_int_register_writes 74180711 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written system.cpu.num_mem_refs 27395681 # number of memory refs system.cpu.num_load_insts 15660705 # Number of load instructions system.cpu.num_store_insts 11734976 # Number of store instructions -system.cpu.num_idle_cycles 4573668194.612258 # Number of idle cycles -system.cpu.num_busy_cycles 675707863.387743 # Number of busy cycles +system.cpu.num_idle_cycles 4573668198.612257 # Number of idle cycles +system.cpu.num_busy_cycles 675707801.387743 # Number of busy cycles system.cpu.not_idle_fraction 0.128722 # Percentage of non-idle cycles system.cpu.idle_fraction 0.871278 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed @@ -154,12 +154,12 @@ system.cpu.icache.demand_misses::cpu.inst 856390 # n system.cpu.icache.demand_misses::total 856390 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 856390 # number of overall misses system.cpu.icache.overall_misses::total 856390 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11565472500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11565472500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11565472500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11565472500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11565472500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11565472500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11565531500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11565531500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11565531500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11565531500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11565531500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11565531500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 61495107 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 61495107 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 61495107 # number of demand (read+write) accesses @@ -172,12 +172,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.913065 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13504.913065 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.913065 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13504.913065 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.913065 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13504.913065 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.981959 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13504.981959 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.981959 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13504.981959 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.981959 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13504.981959 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -192,12 +192,12 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 856390 system.cpu.icache.demand_mshr_misses::total 856390 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 856390 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 856390 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9852692500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9852692500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9852692500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9852692500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9852692500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9852692500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9852751500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9852751500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9852751500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9852751500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9852751500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9852751500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 353004500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 353004500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 353004500 # number of overall MSHR uncacheable cycles @@ -208,58 +208,58 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926 system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11504.913065 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11504.913065 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11504.913065 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11504.913065 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11504.913065 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11504.913065 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11504.981959 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11504.981959 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11504.981959 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11504.981959 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11504.981959 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11504.981959 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 627202 # number of replacements +system.cpu.dcache.replacements 627203 # number of replacements system.cpu.dcache.tagsinuse 511.878516 # Cycle average of tags in use -system.cpu.dcache.total_refs 23656924 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627714 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.687425 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 23656923 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 627715 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.687363 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 653137000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.878516 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999763 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999763 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13196261 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13196261 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 13196260 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13196260 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 9973783 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 9973783 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 236291 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 236291 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247690 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247690 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23170044 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23170044 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23170044 # number of overall hits -system.cpu.dcache.overall_hits::total 23170044 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368703 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368703 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 23170043 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23170043 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23170043 # number of overall hits +system.cpu.dcache.overall_hits::total 23170043 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368704 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368704 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 250510 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 250510 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 11400 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 11400 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 619213 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 619213 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 619213 # number of overall misses -system.cpu.dcache.overall_misses::total 619213 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201080500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5201080500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8976707500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8976707500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 619214 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 619214 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 619214 # number of overall misses +system.cpu.dcache.overall_misses::total 619214 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201105500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5201105500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8977284500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8977284500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154794000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 154794000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14177788000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14177788000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14177788000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14177788000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14178390000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14178390000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14178390000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14178390000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 13564964 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13564964 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10224293 # number of WriteReq accesses(hits+misses) @@ -282,16 +282,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.026029 system.cpu.dcache.demand_miss_rate::total 0.026029 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.026029 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.026029 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14106.423056 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14106.423056 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35833.729192 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35833.729192 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14106.452602 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14106.452602 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35836.032494 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35836.032494 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13578.421053 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13578.421053 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22896.463737 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22896.463737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22896.463737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22896.463737 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22897.398961 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22897.398961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22897.398961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22897.398961 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,32 +302,32 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 595968 # number of writebacks system.cpu.dcache.writebacks::total 595968 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368703 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368703 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368704 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368704 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11400 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 11400 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619213 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619213 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619213 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619213 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463674500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463674500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8475687500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8475687500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 619214 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619214 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619214 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619214 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463697500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463697500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8476264500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8476264500 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131994000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131994000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12939362000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12939362000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12939362000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12939362000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182162796000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182162796000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41387867000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41387867000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223550663000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 223550663000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12939962000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12939962000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12939962000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12939962000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182162296000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182162296000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41387676000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41387676000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223549972000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 223549972000 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027181 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027181 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024501 # mshr miss rate for WriteReq accesses @@ -338,16 +338,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026029 system.cpu.dcache.demand_mshr_miss_rate::total 0.026029 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026029 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.026029 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12106.423056 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12106.423056 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33833.729192 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33833.729192 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12106.452602 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12106.452602 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33836.032494 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33836.032494 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11578.421053 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11578.421053 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20896.463737 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20896.463737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20896.463737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20896.463737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20897.398961 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20897.398961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20897.398961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20897.398961 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -356,16 +356,16 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 61913 # number of replacements -system.cpu.l2cache.tagsinuse 50867.983375 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1683054 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 50867.983864 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1683055 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 127295 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.221682 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2574063802000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 37864.330216 # Average occupied blocks per requestor +system.cpu.l2cache.avg_refs 13.221690 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2574063892000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 37864.330390 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001416 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 6985.667758 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6014.098399 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 6985.667850 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6014.098622 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.577764 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -375,8 +375,8 @@ system.cpu.l2cache.occ_percent::total 0.776184 # Av system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8765 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3551 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 844136 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 370245 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226697 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 370246 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1226698 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 595968 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 595968 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits @@ -386,13 +386,13 @@ system.cpu.l2cache.ReadExReq_hits::total 114435 # nu system.cpu.l2cache.demand_hits::cpu.dtb.walker 8765 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3551 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 844136 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 484680 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1341132 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 484681 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1341133 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 8765 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3551 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 844136 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 484680 # number of overall hits -system.cpu.l2cache.overall_hits::total 1341132 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 484681 # number of overall hits +system.cpu.l2cache.overall_hits::total 1341133 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 10615 # number of ReadReq misses @@ -414,28 +414,28 @@ system.cpu.l2cache.overall_misses::cpu.data 143034 # system.cpu.l2cache.overall_misses::total 153657 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 261500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 156000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553303500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 513115500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1066836500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553362500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 513127500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1066907500 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6933900000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6933900000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6934471000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6934471000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 261500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 156000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 553303500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7447015500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8000736500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 553362500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7447598500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8001378500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 261500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 156000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 553303500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7447015500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8000736500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 553362500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7447598500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8001378500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8770 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3554 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 854751 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 380103 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1247178 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 380104 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1247179 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 595968 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 595968 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2899 # number of UpgradeReq accesses(hits+misses) @@ -445,13 +445,13 @@ system.cpu.l2cache.ReadExReq_accesses::total 247611 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8770 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3554 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 854751 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 627714 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1494789 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 627715 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1494790 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8770 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3554 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 854751 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 627714 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1494789 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 627715 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1494790 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000570 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000844 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012419 # miss rate for ReadReq accesses @@ -473,23 +473,23 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.227865 system.cpu.l2cache.overall_miss_rate::total 0.102795 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52300 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52124.682054 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52050.669507 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52089.082564 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52130.240226 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52051.886792 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52092.549192 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 361.990950 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 361.990950 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52065.687511 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52065.687511 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52069.975071 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52069.975071 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52124.682054 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52064.652460 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52068.805847 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52130.240226 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52068.728414 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52072.983984 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52124.682054 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52064.652460 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52068.805847 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52130.240226 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52068.728414 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52072.983984 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -521,31 +521,31 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 143034 system.cpu.l2cache.overall_mshr_misses::total 153657 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 200000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425853000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 394738000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 820911000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 115017000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 115017000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5335717000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5335717000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425912000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 394750500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 820982500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 115023000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 115023000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5336288000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5336288000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 200000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425853000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5730455000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6156628000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425912000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5731038500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6157270500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 200000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425853000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5730455000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6156628000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425912000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5731038500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6157270500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166763732500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167028572500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31856780000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31856780000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166763232500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167028072500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31856015000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31856015000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198620512500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198885352500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198619247500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198884087500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for ReadReq accesses @@ -567,23 +567,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227865 system.cpu.l2cache.overall_mshr_miss_rate::total 0.102795 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.040509 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40042.402110 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40081.587813 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40033.762617 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40033.762617 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40065.154382 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40065.154382 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40123.598681 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40043.670116 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40085.078854 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40035.851027 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40035.851027 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40069.441941 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40069.441941 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40123.598681 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40067.665730 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40071.526191 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40123.598681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40067.665730 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40071.526191 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -607,10 +607,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1358750753218 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1358750753218 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1359273920420 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1359273920420 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1359273920420 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1359273920420 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 5a613cfa1..551274795 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,184 +1,76 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.112043 # Number of seconds simulated -sim_ticks 5112043255000 # Number of ticks simulated -final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.112041 # Number of seconds simulated +sim_ticks 5112040968500 # Number of ticks simulated +final_tick 5112040968500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1011485 # Simulator instruction rate (inst/s) -host_op_rate 2071087 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25877843451 # Simulator tick rate (ticks/s) -host_mem_usage 397304 # Number of bytes of host memory used -host_seconds 197.55 # Real time elapsed on the host -sim_insts 199813914 # Number of instructions simulated -sim_ops 409133298 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2464768 # Number of bytes read from this memory +host_inst_rate 923075 # Simulator instruction rate (inst/s) +host_op_rate 1890063 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23616389220 # Simulator tick rate (ticks/s) +host_mem_usage 353316 # Number of bytes of host memory used +host_seconds 216.46 # Real time elapsed on the host +sim_insts 199810236 # Number of instructions simulated +sim_ops 409125915 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10600192 # Number of bytes read from this memory -system.physmem.bytes_read::total 13919232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10600128 # Number of bytes read from this memory +system.physmem.bytes_read::total 13919040 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9292800 # Number of bytes written to this memory -system.physmem.bytes_written::total 9292800 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38512 # Number of read requests responded to by this memory +system.physmem.bytes_written::writebacks 9292608 # Number of bytes written to this memory +system.physmem.bytes_written::total 9292608 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38510 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165628 # Number of read requests responded to by this memory -system.physmem.num_reads::total 217488 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 145200 # Number of write requests responded to by this memory -system.physmem.num_writes::total 145200 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 482149 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.data 165627 # Number of read requests responded to by this memory +system.physmem.num_reads::total 217485 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 145197 # Number of write requests responded to by this memory +system.physmem.num_writes::total 145197 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 482124 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2073572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2722831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2073561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2722795 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1817825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1817825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1817825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 482149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 1817788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1817788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1817788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 482124 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2073572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 106561 # number of replacements -system.cpu.l2cache.tagsinuse 64822.143261 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3456533 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 170680 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 20.251541 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2434.983596 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 10405.560614 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989107 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2062630 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1538130 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1538130 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 179208 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 777957 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1454603 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2241838 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 777957 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1454603 # number of overall hits -system.cpu.l2cache.overall_hits::total 2241838 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 32184 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 45533 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 134377 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 166561 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 179910 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 166561 # number of overall misses -system.cpu.l2cache.overall_misses::total 179910 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1538130 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1538130 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2421748 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2421748 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.074289 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.074289 # miss rate for overall accesses -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98533 # number of writebacks -system.cpu.l2cache.writebacks::total 98533 # number of writebacks -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47570 # number of replacements -system.iocache.tagsinuse 0.042409 # Cycle average of tags in use +system.physmem.bw_total::cpu.data 2073561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4540583 # Total bandwidth to/from this memory (bytes/s) +system.iocache.replacements 47569 # number of replacements +system.iocache.tagsinuse 0.042402 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47585 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.002651 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.002651 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses -system.iocache.ReadReq_misses::total 905 # number of ReadReq misses +system.iocache.warmup_cycle 4994776680059 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.042402 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.002650 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.002650 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses +system.iocache.ReadReq_misses::total 904 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses -system.iocache.demand_misses::total 47625 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses -system.iocache.overall_misses::total 47625 # number of overall misses -system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses +system.iocache.demand_misses::total 47624 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses +system.iocache.overall_misses::total 47624 # number of overall misses +system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -200,7 +92,7 @@ system.iocache.writebacks::total 46667 # nu system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -210,57 +102,57 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10224086531 # number of cpu cycles simulated +system.cpu.numCycles 10224081960 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 199813914 # Number of instructions committed -system.cpu.committedOps 409133298 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374297264 # Number of integer alu accesses +system.cpu.committedInsts 199810236 # Number of instructions committed +system.cpu.committedOps 409125915 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374289906 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39954974 # number of instructions that are conditional controls -system.cpu.num_int_insts 374297264 # number of integer instructions +system.cpu.num_conditional_control_insts 39954535 # number of instructions that are conditional controls +system.cpu.num_int_insts 374289906 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 915470380 # number of times the integer registers were read -system.cpu.num_int_register_writes 480331069 # number of times the integer registers were written +system.cpu.num_int_register_reads 915450684 # number of times the integer registers were read +system.cpu.num_int_register_writes 480322735 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 35626517 # number of memory refs -system.cpu.num_load_insts 27217782 # Number of load instructions -system.cpu.num_store_insts 8408735 # Number of store instructions -system.cpu.num_idle_cycles 9770605318.086651 # Number of idle cycles -system.cpu.num_busy_cycles 453481212.913350 # Number of busy cycles -system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.955646 # Percentage of idle cycles +system.cpu.num_mem_refs 35624588 # number of memory refs +system.cpu.num_load_insts 27216588 # Number of load instructions +system.cpu.num_store_insts 8408000 # Number of store instructions +system.cpu.num_idle_cycles 9770609605.299961 # Number of idle cycles +system.cpu.num_busy_cycles 453472354.700038 # Number of busy cycles +system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.955647 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 790793 # number of replacements +system.cpu.icache.replacements 790732 # number of replacements system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use -system.cpu.icache.total_refs 243365779 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791305 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 307.549907 # Average number of references to valid blocks. +system.cpu.icache.total_refs 243360722 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 791244 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 307.567226 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 148763110500 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 243365779 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243365779 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243365779 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243365779 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243365779 # number of overall hits -system.cpu.icache.overall_hits::total 243365779 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791312 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791312 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791312 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791312 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791312 # number of overall misses -system.cpu.icache.overall_misses::total 791312 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 243360722 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243360722 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243360722 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243360722 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243360722 # number of overall hits +system.cpu.icache.overall_hits::total 243360722 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791251 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791251 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791251 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791251 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791251 # number of overall misses +system.cpu.icache.overall_misses::total 791251 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 244151973 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244151973 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244151973 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244151973 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244151973 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244151973 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses @@ -277,14 +169,14 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.replacements 3335 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.026444 # Cycle average of tags in use +system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cycle average of tags in use system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks. system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5102048603500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026444 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.189153 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.warmup_cycle 5102019603000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8031 # number of ReadReq hits system.cpu.itb_walker_cache.ReadReq_hits::total 8031 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits @@ -324,39 +216,39 @@ system.cpu.itb_walker_cache.cache_copies 0 # nu system.cpu.itb_walker_cache.writebacks::writebacks 593 # number of writebacks system.cpu.itb_walker_cache.writebacks::total 593 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7598 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.013733 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13014 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7612 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.709669 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5101231664000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013733 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313358 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.313358 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13016 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13016 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13016 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13016 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13016 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13016 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8792 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8792 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8792 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8792 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8792 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8792 # number of overall misses +system.cpu.dtb_walker_cache.replacements 7597 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5101206381500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13017 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13017 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13017 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13017 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13017 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13017 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8791 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8791 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8791 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8791 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8791 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8791 # number of overall misses system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403155 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403155 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403155 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403155 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403155 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403155 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403109 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403109 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403109 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403109 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403109 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403109 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -368,39 +260,39 @@ system.cpu.dtb_walker_cache.cache_copies 0 # nu system.cpu.dtb_walker_cache.writebacks::writebacks 2556 # number of writebacks system.cpu.dtb_walker_cache.writebacks::total 2556 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1621273 # number of replacements +system.cpu.dcache.replacements 1621135 # number of replacements system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use -system.cpu.dcache.total_refs 20142222 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1621785 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.419786 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 20140429 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1621647 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.419737 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8082936 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8082936 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20139960 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20139960 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20139960 # number of overall hits -system.cpu.dcache.overall_hits::total 20139960 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308205 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308205 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315852 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315852 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses -system.cpu.dcache.overall_misses::total 1624057 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13365229 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13365229 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21764017 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21764017 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21764017 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21764017 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12055941 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12055941 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8082226 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8082226 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20138167 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20138167 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20138167 # number of overall hits +system.cpu.dcache.overall_hits::total 20138167 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308091 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308091 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315828 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315828 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1623919 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1623919 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1623919 # number of overall misses +system.cpu.dcache.overall_misses::total 1623919 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 13364032 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13364032 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8398054 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8398054 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21762086 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21762086 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21762086 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21762086 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses @@ -417,8 +309,116 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1534981 # number of writebacks -system.cpu.dcache.writebacks::total 1534981 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1534848 # number of writebacks +system.cpu.dcache.writebacks::total 1534848 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 106558 # number of replacements +system.cpu.l2cache.tagsinuse 64822.149249 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 51981.453140 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2434.994085 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 10405.564956 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.989108 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 777896 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1275281 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2062455 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1537997 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1537997 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 179183 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 179183 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 777896 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1454464 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2241638 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 777896 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1454464 # number of overall hits +system.cpu.l2cache.overall_hits::total 2241638 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 32182 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 45531 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 134378 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 134378 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 166560 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 179909 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 166560 # number of overall misses +system.cpu.l2cache.overall_misses::total 179909 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 791238 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1307463 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2107986 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1537997 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1537997 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 313561 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 313561 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 791238 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1621024 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2421547 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 791238 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1621024 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2421547 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016862 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024614 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428555 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.428555 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016862 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102750 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.074295 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016862 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102750 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.074295 # miss rate for overall accesses +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 98530 # number of writebacks +system.cpu.l2cache.writebacks::total 98530 # number of writebacks +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 358803d5d..b8216d15c 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.187896 # Nu sim_ticks 5187896410000 # Number of ticks simulated final_tick 5187896410000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 834857 # Simulator instruction rate (inst/s) -host_op_rate 1609393 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33766110220 # Simulator tick rate (ticks/s) -host_mem_usage 354356 # Number of bytes of host memory used -host_seconds 153.64 # Real time elapsed on the host +host_inst_rate 812782 # Simulator instruction rate (inst/s) +host_op_rate 1566838 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32873266023 # Simulator tick rate (ticks/s) +host_mem_usage 347504 # Number of bytes of host memory used +host_seconds 157.82 # Real time elapsed on the host sim_insts 128269216 # Number of instructions simulated sim_ops 247270559 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2867328 # Number of bytes read from this memory @@ -59,14 +59,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47558 system.iocache.demand_misses::total 47558 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses system.iocache.overall_misses::total 47558 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130045932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 130045932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130086932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 130086932 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10696163160 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 10696163160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10826209092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10826209092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10826209092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10826209092 # number of overall miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10826250092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10826250092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10826250092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10826250092 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -83,19 +83,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155186.076372 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 155186.076372 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155235.002387 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 155235.002387 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 228941.848459 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 228941.848459 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 227642.228269 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 227642.228269 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 90077012 # number of cycles access was blocked +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227643.090374 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 227643.090374 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227643.090374 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 227643.090374 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 90078 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 11025 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8170.250522 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.170340 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -109,14 +109,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47558 system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86439000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 86439000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8266468944 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8266468944 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8352907944 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8352907944 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86510932 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 86510932 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8266723160 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8266723160 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8353234092 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8353234092 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8353234092 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8353234092 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -125,14 +125,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103149.164678 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 103149.164678 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176936.407192 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176936.407192 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103235.002387 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 103235.002387 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176941.848459 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 176941.848459 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175643.090374 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 175643.090374 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175643.090374 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 175643.090374 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -437,14 +437,14 @@ system.cpu.dcache.demand_misses::cpu.data 1621067 # n system.cpu.dcache.demand_misses::total 1621067 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1621067 # number of overall misses system.cpu.dcache.overall_misses::total 1621067 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18175236500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18175236500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18175237000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18175237000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 8903442500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 8903442500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27078679000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27078679000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27078679000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27078679000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27078679500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27078679500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27078679500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27078679500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 13298830 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13298830 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 8353033 # number of WriteReq accesses(hits+misses) @@ -461,14 +461,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.074870 system.cpu.dcache.demand_miss_rate::total 0.074870 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074870 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.074870 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13913.843616 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13913.843616 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13913.843999 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13913.843999 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28283.123727 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 28283.123727 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16704.231842 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16704.231842 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16704.231842 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16704.231842 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16704.232151 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16704.232151 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16704.232151 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16704.232151 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -487,20 +487,20 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1621067 system.cpu.dcache.demand_mshr_misses::total 1621067 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1621067 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1621067 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15562696500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15562696500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15562697000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15562697000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8273848500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 8273848500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23836545000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23836545000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23836545000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23836545000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23836545500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23836545500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23836545500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23836545500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94146954000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94146954000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469435000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469435000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96616389000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96616389000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469434500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469434500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96616388500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96616388500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098224 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098224 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037687 # mshr miss rate for WriteReq accesses @@ -509,14 +509,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074870 system.cpu.dcache.demand_mshr_miss_rate::total 0.074870 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074870 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074870 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11913.843616 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11913.843616 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11913.843999 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11913.843999 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26283.123727 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26283.123727 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14704.231842 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14704.231842 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14704.231842 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14704.231842 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14704.232151 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14704.232151 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14704.232151 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14704.232151 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -672,21 +672,21 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 12922 system.cpu.l2cache.overall_mshr_misses::cpu.data 141498 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 154425 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 517329000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1144074500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1661603500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 517329500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1144100000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1661629500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 54186500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 54186500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4533030500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4533030500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 517329000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5677105000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6194634000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 517329500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5677130500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6194660000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 517329000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5677105000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6194634000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 517329500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5677130500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6194660000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86587561000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86587561000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305699000 # number of WriteReq MSHR uncacheable cycles @@ -710,21 +710,21 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016282 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087447 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.063788 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40034.746943 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40515.422480 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40364.472246 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40034.785637 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40516.325519 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40365.103850 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40287.360595 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40287.360595 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40023.225322 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40023.225322 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40034.785637 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40121.630694 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40114.359722 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40034.785637 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40121.630694 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40114.359722 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index ba49bebdd..062194e2a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 21628500 # Number of ticks simulated final_tick 21628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48865 # Simulator instruction rate (inst/s) -host_op_rate 48859 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 165354272 # Simulator tick rate (ticks/s) -host_mem_usage 218640 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 34038 # Simulator instruction rate (inst/s) +host_op_rate 34033 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 115179622 # Simulator tick rate (ticks/s) +host_mem_usage 212112 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory @@ -270,11 +270,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 56590.517241 system.cpu.dcache.overall_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 56590.517241 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1690000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3380 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 37 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 45675.675676 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 91.351351 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 1d71c4fe2..04aaa0ff5 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 20184000 # Number of ticks simulated final_tick 20184000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50290 # Simulator instruction rate (inst/s) -host_op_rate 50282 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174536927 # Simulator tick rate (ticks/s) -host_mem_usage 219492 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 91753 # Simulator instruction rate (inst/s) +host_op_rate 91718 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 318298211 # Simulator tick rate (ticks/s) +host_mem_usage 212944 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -160,11 +160,11 @@ system.cpu.icache.demand_avg_miss_latency::total 56098.837209 system.cpu.icache.overall_avg_miss_latency::cpu.inst 56098.837209 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 56098.837209 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 58 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 58 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits @@ -256,11 +256,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 57663.385827 system.cpu.dcache.overall_avg_miss_latency::cpu.data 57663.385827 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 57663.385827 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1194500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2389 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51934.782609 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 103.869565 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 9881f90a7..a6445a723 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18570500 # Number of ticks simulated final_tick 18570500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42410 # Simulator instruction rate (inst/s) -host_op_rate 42404 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 147804999 # Simulator tick rate (ticks/s) -host_mem_usage 221464 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 78205 # Simulator instruction rate (inst/s) +host_op_rate 78177 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 272440141 # Simulator tick rate (ticks/s) +host_mem_usage 214124 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -142,11 +142,11 @@ system.cpu.icache.demand_avg_miss_latency::total 55220 system.cpu.icache.overall_avg_miss_latency::cpu.inst 55220 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 55220 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 109000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 218 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 36333.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 72.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59 # number of ReadReq MSHR hits @@ -238,11 +238,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 55992.711370 system.cpu.dcache.overall_avg_miss_latency::cpu.data 55992.711370 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 55992.711370 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2307000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4614 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51266.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 102.533333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 2a32b08b0..c19d33801 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000015 # Nu sim_ticks 14818500 # Number of ticks simulated final_tick 14818500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71701 # Simulator instruction rate (inst/s) -host_op_rate 71694 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 83350191 # Simulator tick rate (ticks/s) -host_mem_usage 220256 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 95139 # Simulator instruction rate (inst/s) +host_op_rate 95123 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 110579898 # Simulator tick rate (ticks/s) +host_mem_usage 213740 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory @@ -736,11 +736,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 40780.102041 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 38918.400000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44057.746479 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 40780.102041 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 49000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 4083.333333 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8.166667 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index e278da8a8..c5840e3c9 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu sim_ticks 25317500 # Number of ticks simulated final_tick 25317500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 47783 # Simulator instruction rate (inst/s) -host_op_rate 47781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79779918 # Simulator tick rate (ticks/s) -host_mem_usage 220364 # Number of bytes of host memory used -host_seconds 0.32 # Real time elapsed on the host +host_inst_rate 84248 # Simulator instruction rate (inst/s) +host_op_rate 84237 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140641450 # Simulator tick rate (ticks/s) +host_mem_usage 214032 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -142,11 +142,11 @@ system.cpu.icache.demand_avg_miss_latency::total 54837.398374 system.cpu.icache.overall_avg_miss_latency::cpu.inst 54837.398374 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 54837.398374 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 65500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 131 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 32750 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 65.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits @@ -242,11 +242,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 56182.451253 system.cpu.dcache.overall_avg_miss_latency::cpu.data 56182.451253 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 56182.451253 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4519 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 100.422222 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 482a9e980..ff9862a27 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,953 +1,953 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000114 # Number of seconds simulated -sim_ticks 113910500 # Number of ticks simulated -final_tick 113910500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000110 # Number of seconds simulated +sim_ticks 109894000 # Number of ticks simulated +final_tick 109894000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141669 # Simulator instruction rate (inst/s) -host_op_rate 141669 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14682125 # Simulator tick rate (ticks/s) -host_mem_usage 244464 # Number of bytes of host memory used -host_seconds 7.76 # Real time elapsed on the host -sim_insts 1099129 # Number of instructions simulated -sim_ops 1099129 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 23168 # Number of bytes read from this memory +host_inst_rate 161995 # Simulator instruction rate (inst/s) +host_op_rate 161994 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16590549 # Simulator tick rate (ticks/s) +host_mem_usage 228988 # Number of bytes of host memory used +host_seconds 6.62 # Real time elapsed on the host +sim_insts 1073027 # Number of instructions simulated +sim_ops 1073027 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5632 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 23168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 29248 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 362 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 42880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 29184 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 84 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 88 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 671 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 203387747 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 94389894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 47194947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11236892 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 2809223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7303980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 3371068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7303980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 376997731 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 203387747 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 47194947 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 2809223 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 3371068 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 256762985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 203387747 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 94389894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 47194947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11236892 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 2809223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7303980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 3371068 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7303980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 376997731 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 670 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 209656578 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 97839736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 51249386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11647588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 2329518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7570932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 2329518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7570932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 390194187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 209656578 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 51249386 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 2329518 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 2329518 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 265564999 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 209656578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 97839736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 51249386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11647588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 2329518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7570932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 2329518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7570932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 390194187 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 227822 # number of cpu cycles simulated +system.cpu0.numCycles 219789 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 88179 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 85929 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 1290 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 85894 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 83486 # Number of BTB hits +system.cpu0.BPredUnit.lookups 85747 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 83485 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 1265 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 83551 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 81101 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 517 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.usedRAS 507 # Number of times the RAS was used to get a target. system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 17727 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 523680 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 88179 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 84003 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 172095 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 4009 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 15408 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 17217 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 509162 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 85747 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 81608 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 167267 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3854 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13783 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1281 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 6036 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 519 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 209087 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.504603 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.209881 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1302 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 6029 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 502 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 202015 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.520417 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.209670 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 36992 17.69% 17.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 85294 40.79% 58.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 585 0.28% 58.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1000 0.48% 59.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 484 0.23% 59.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 81297 38.88% 98.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 665 0.32% 98.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 355 0.17% 98.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2415 1.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34748 17.20% 17.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 82895 41.03% 58.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 589 0.29% 58.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 956 0.47% 59.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 519 0.26% 59.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 78871 39.04% 98.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 675 0.33% 98.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 356 0.18% 98.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2406 1.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 209087 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.387052 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.298637 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18268 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 16880 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 171017 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 351 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2571 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 520658 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2571 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18993 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2288 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13870 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 170679 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 686 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 517484 # Number of instructions processed by rename -system.cpu0.rename.LSQFullEvents 297 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 353459 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1032335 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 1032335 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 339779 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13680 # Number of HB maps that are undone due to squashing +system.cpu0.fetch.rateDist::total 202015 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.390133 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.316595 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17805 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 15234 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 166234 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 301 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2441 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 506087 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2441 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18480 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 1523 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13039 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 165885 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 647 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 502881 # Number of instructions processed by rename +system.cpu0.rename.LSQFullEvents 252 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 343651 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1003098 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 1003098 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 330631 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13020 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 904 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 933 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4009 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 165974 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 83785 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 81138 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 80830 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 432592 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 951 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 429324 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 270 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11361 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11323 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 392 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 209087 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.053327 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.097112 # Number of insts issued each cycle +system.cpu0.rename.tempSerializingInsts 932 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3938 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 161147 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 81377 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 78673 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 78441 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 420405 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 949 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 417702 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 122 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10651 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 9804 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 390 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 202015 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.067678 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.086169 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 36280 17.35% 17.35% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5325 2.55% 19.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 82668 39.54% 59.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 82134 39.28% 98.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1638 0.78% 99.50% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 661 0.32% 99.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 275 0.13% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 94 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 12 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33785 16.72% 16.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5274 2.61% 19.33% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 80485 39.84% 59.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 79928 39.57% 98.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1527 0.76% 99.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 645 0.32% 99.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 270 0.13% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 14 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 209087 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 202015 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 52 18.77% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 113 40.79% 59.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 40.43% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 46 19.74% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 73 31.33% 51.07% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 114 48.93% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 180924 42.14% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.14% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 165296 38.50% 80.64% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 83104 19.36% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 176241 42.19% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 160662 38.46% 80.66% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 80799 19.34% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 429324 # Type of FU issued -system.cpu0.iq.rate 1.884471 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 277 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000645 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1068282 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 444960 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 427393 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 417702 # Type of FU issued +system.cpu0.iq.rate 1.900468 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 233 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000558 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1037774 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 432063 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 415867 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 429601 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 417935 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 80458 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 78173 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2495 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 56 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1539 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2242 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 58 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 20 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2571 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1789 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 88 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 515149 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 291 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 165974 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 83785 # Number of dispatched store instructions +system.cpu0.iew.iewSquashCycles 2441 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1114 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 500579 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 311 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 161147 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 81377 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 838 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 95 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 56 # Number of memory order violations +system.cpu0.iew.memOrderViolationEvents 58 # Number of memory order violations system.cpu0.iew.predictedTakenIncorrect 383 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1496 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 428216 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 164977 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1108 # Number of squashed instructions skipped in execute +system.cpu0.iew.predictedNotTakenIncorrect 1089 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1472 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 416616 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 160343 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1086 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 81606 # number of nop insts executed -system.cpu0.iew.exec_refs 247935 # number of memory reference insts executed -system.cpu0.iew.exec_branches 85106 # Number of branches executed -system.cpu0.iew.exec_stores 82958 # Number of stores executed -system.cpu0.iew.exec_rate 1.879608 # Inst execution rate -system.cpu0.iew.wb_sent 427739 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 427393 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 253334 # num instructions producing a value -system.cpu0.iew.wb_consumers 255736 # num instructions consuming a value +system.cpu0.iew.exec_nop 79225 # number of nop insts executed +system.cpu0.iew.exec_refs 241004 # number of memory reference insts executed +system.cpu0.iew.exec_branches 82800 # Number of branches executed +system.cpu0.iew.exec_stores 80661 # Number of stores executed +system.cpu0.iew.exec_rate 1.895527 # Inst execution rate +system.cpu0.iew.wb_sent 416200 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 415867 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 246464 # num instructions producing a value +system.cpu0.iew.wb_consumers 248856 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.875995 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.990608 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.892119 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.990388 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 13085 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12251 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1290 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 206533 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.430701 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.136521 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1265 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 199591 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.446493 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.132962 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 36757 17.80% 17.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 84830 41.07% 58.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2489 1.21% 60.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 701 0.34% 60.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 579 0.28% 60.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 80093 38.78% 99.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 561 0.27% 99.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 222 0.11% 99.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 301 0.15% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34293 17.18% 17.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 82677 41.42% 58.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2432 1.22% 59.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 705 0.35% 60.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 565 0.28% 60.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 77961 39.06% 99.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 418 0.21% 99.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 251 0.13% 99.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 289 0.14% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 206533 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 502020 # Number of instructions committed -system.cpu0.commit.committedOps 502020 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 199591 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 488298 # Number of instructions committed +system.cpu0.commit.committedOps 488298 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 245725 # Number of memory references committed -system.cpu0.commit.loads 163479 # Number of loads committed +system.cpu0.commit.refs 238864 # Number of memory references committed +system.cpu0.commit.loads 158905 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 84133 # Number of branches committed +system.cpu0.commit.branches 81846 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 338110 # Number of committed integer instructions. +system.cpu0.commit.int_insts 328962 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 301 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 289 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 720176 # The number of ROB reads -system.cpu0.rob.rob_writes 1032801 # The number of ROB writes -system.cpu0.timesIdled 336 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 18735 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 421071 # Number of Instructions Simulated -system.cpu0.committedOps 421071 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 421071 # Number of Instructions Simulated -system.cpu0.cpi 0.541054 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.541054 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.848246 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.848246 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 766308 # number of integer regfile reads -system.cpu0.int_regfile_writes 345106 # number of integer regfile writes +system.cpu0.rob.rob_reads 698690 # The number of ROB reads +system.cpu0.rob.rob_writes 1003556 # The number of ROB writes +system.cpu0.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 17774 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 409636 # Number of Instructions Simulated +system.cpu0.committedOps 409636 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 409636 # Number of Instructions Simulated +system.cpu0.cpi 0.536547 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.536547 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.863769 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.863769 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 745424 # number of integer regfile reads +system.cpu0.int_regfile_writes 335847 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 249733 # number of misc regfile reads +system.cpu0.misc_regfile_reads 242810 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 302 # number of replacements -system.cpu0.icache.tagsinuse 247.706871 # Cycle average of tags in use -system.cpu0.icache.total_refs 5276 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 594 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.882155 # Average number of references to valid blocks. +system.cpu0.icache.replacements 299 # number of replacements +system.cpu0.icache.tagsinuse 247.576197 # Cycle average of tags in use +system.cpu0.icache.total_refs 5285 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 591 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.942470 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 247.706871 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.483802 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.483802 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5276 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5276 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5276 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5276 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5276 # number of overall hits -system.cpu0.icache.overall_hits::total 5276 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 760 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 760 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 760 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 760 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 760 # number of overall misses -system.cpu0.icache.overall_misses::total 760 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 29374500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 29374500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 29374500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 29374500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 29374500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 29374500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6036 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6036 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6036 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6036 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6036 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6036 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125911 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.125911 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125911 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.125911 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125911 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.125911 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38650.657895 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38650.657895 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38650.657895 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38650.657895 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38650.657895 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38650.657895 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 13500 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 247.576197 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.483547 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.483547 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5285 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5285 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5285 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5285 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5285 # number of overall hits +system.cpu0.icache.overall_hits::total 5285 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 744 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 744 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 744 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 744 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 744 # number of overall misses +system.cpu0.icache.overall_misses::total 744 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 28183000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 28183000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 28183000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 28183000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 28183000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 28183000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6029 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6029 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6029 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6029 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6029 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6029 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123404 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.123404 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123404 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.123404 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123404 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.123404 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 37880.376344 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 37880.376344 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 37880.376344 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 37880.376344 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 37880.376344 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 37880.376344 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13500 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.500000 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 165 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 165 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 165 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 165 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 595 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 595 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 595 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 595 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 595 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 595 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22317000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 22317000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22317000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 22317000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22317000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 22317000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.098575 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.098575 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.098575 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.098575 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.098575 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.098575 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37507.563025 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37507.563025 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37507.563025 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 37507.563025 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37507.563025 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 37507.563025 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 152 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 152 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 152 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 152 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 152 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 152 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 592 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 592 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 592 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 592 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 592 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 592 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22043000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 22043000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22043000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 22043000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22043000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 22043000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.098192 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.098192 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.098192 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.098192 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.098192 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.098192 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37234.797297 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37234.797297 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37234.797297 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 37234.797297 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37234.797297 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 37234.797297 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 144.389455 # Cycle average of tags in use -system.cpu0.dcache.total_refs 165484 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 144.284283 # Cycle average of tags in use +system.cpu0.dcache.total_refs 160925 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 973.435294 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 946.617647 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 144.389455 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.282011 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.282011 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 83924 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 83924 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 81641 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 81641 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 17 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 17 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 165565 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 165565 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 165565 # number of overall hits -system.cpu0.dcache.overall_hits::total 165565 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 532 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 532 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 563 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 563 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 25 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 25 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1095 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1095 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1095 # number of overall misses -system.cpu0.dcache.overall_misses::total 1095 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16935000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 16935000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 28694494 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 28694494 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 516500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 516500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 45629494 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 45629494 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 45629494 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 45629494 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 84456 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 84456 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 82204 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 82204 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.occ_blocks::cpu0.data 144.284283 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.281805 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.281805 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 81643 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 81643 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 79364 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 79364 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 161007 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 161007 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 161007 # number of overall hits +system.cpu0.dcache.overall_hits::total 161007 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 465 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 465 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 553 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 553 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1018 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1018 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1018 # number of overall misses +system.cpu0.dcache.overall_misses::total 1018 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 14129000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 14129000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26395982 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 26395982 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 370000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 370000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 40524982 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 40524982 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 40524982 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 40524982 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 82108 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 82108 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 79917 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 79917 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 166660 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 166660 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 166660 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 166660 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006299 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006299 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006849 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006849 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.595238 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.595238 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006570 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006570 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006570 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006570 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31832.706767 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31832.706767 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50967.129663 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50967.129663 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 20660 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 20660 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41670.770776 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 41670.770776 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41670.770776 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 41670.770776 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 112000 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 162025 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 162025 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 162025 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 162025 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005663 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.005663 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006920 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006920 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006283 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006283 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006283 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006283 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30384.946237 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 30384.946237 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 47732.336347 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 47732.336347 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 17619.047619 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 17619.047619 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39808.430255 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39808.430255 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39808.430255 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39808.430255 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 319 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 24 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6222.222222 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.291667 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 351 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 351 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 394 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 394 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 745 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 745 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 745 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 745 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 181 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 169 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 169 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 25 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 25 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 350 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 350 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5844010 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5844010 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6652500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6652500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 438500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 438500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12496510 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12496510 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12496510 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12496510 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002143 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002143 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002056 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002056 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.595238 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.595238 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002100 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002100 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002100 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002100 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32287.348066 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32287.348066 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39363.905325 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39363.905325 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17540 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17540 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35704.314286 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35704.314286 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35704.314286 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35704.314286 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 276 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 381 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 381 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 657 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 657 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 657 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 657 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 172 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 172 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5343500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5343500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6330000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6330000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 328000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 328000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11673500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11673500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11673500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11673500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002302 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002302 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002152 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002228 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002228 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002228 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002228 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28272.486772 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28272.486772 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36802.325581 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36802.325581 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 15619.047619 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 15619.047619 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32336.565097 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32336.565097 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32336.565097 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32336.565097 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 191317 # number of cpu cycles simulated +system.cpu1.numCycles 184127 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 53059 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 50011 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 1521 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 46382 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 45427 # Number of BTB hits +system.cpu1.BPredUnit.lookups 48566 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 45425 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 1525 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 41634 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 40784 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 803 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.usedRAS 857 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 31318 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 294530 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 53059 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 46230 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 104588 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4407 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 38684 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6733 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1070 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 21833 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 319 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 185209 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.590257 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.119058 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 32363 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 265611 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 48566 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 41641 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 96301 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4375 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 40077 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.NoActiveThreadStallCycles 6455 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 1055 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 23564 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 345 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 179027 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.483637 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.076927 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 80621 43.53% 43.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 53529 28.90% 72.43% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 6903 3.73% 76.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3276 1.77% 77.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 732 0.40% 78.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 34514 18.64% 96.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1160 0.63% 97.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 883 0.48% 98.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3591 1.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 82726 46.21% 46.21% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 49826 27.83% 74.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7772 4.34% 78.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3158 1.76% 80.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 709 0.40% 80.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 29207 16.31% 96.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1125 0.63% 97.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 886 0.49% 97.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3618 2.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 185209 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.277336 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.539487 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 37437 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 34588 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 97784 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 5856 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2811 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 290465 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2811 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 38251 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18737 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 14962 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 92242 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 11473 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 288015 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 15 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 60 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 201252 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 549512 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 549512 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 185544 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15708 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1231 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1359 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 14237 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 80834 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 37999 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 38862 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 32764 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 237666 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 7151 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 239902 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12973 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 11962 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 719 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 185209 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.295304 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.311031 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 179027 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.263764 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.442542 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 39330 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 35122 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 88807 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 6541 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2772 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 261671 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2772 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 40116 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 20114 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 14157 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 82544 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 12869 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 259082 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 41 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 180494 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 488461 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 488461 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 165372 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15122 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1240 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1383 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 15783 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 71004 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 32715 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 34344 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 27479 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 212625 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 7991 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 216005 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 69 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12464 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 11017 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 740 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 179027 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.206550 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.298788 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 78322 42.29% 42.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 24974 13.48% 55.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 38132 20.59% 76.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 38761 20.93% 97.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3339 1.80% 99.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1231 0.66% 99.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 341 0.18% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 48 0.03% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 80193 44.79% 44.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 27393 15.30% 60.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 32961 18.41% 78.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 33539 18.73% 97.24% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3241 1.81% 99.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1264 0.71% 99.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 324 0.18% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 185209 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 179027 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 21 6.44% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 95 29.14% 35.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 64.42% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 20 6.78% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 65 22.03% 28.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 116849 48.71% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.71% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 85748 35.74% 84.45% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 37305 15.55% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 107139 49.60% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.60% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 76812 35.56% 85.16% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 32054 14.84% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 239902 # Type of FU issued -system.cpu1.iq.rate 1.253950 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 326 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001359 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 665467 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 257831 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 237819 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 216005 # Type of FU issued +system.cpu1.iq.rate 1.173131 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 295 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001366 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 611401 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 233118 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 214044 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 240228 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 216300 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 32613 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 27354 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2758 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1567 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2609 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1525 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2811 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2340 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 107 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 284663 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 80834 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 37999 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1126 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 105 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2772 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1710 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 255983 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 380 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 71004 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 32715 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1159 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 52 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 509 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1185 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1694 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 238552 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 79712 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1350 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 484 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1213 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1697 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 214708 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 69981 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1297 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 39846 # number of nop insts executed -system.cpu1.iew.exec_refs 116931 # number of memory reference insts executed -system.cpu1.iew.exec_branches 49232 # Number of branches executed -system.cpu1.iew.exec_stores 37219 # Number of stores executed -system.cpu1.iew.exec_rate 1.246894 # Inst execution rate -system.cpu1.iew.wb_sent 238105 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 237819 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 133762 # num instructions producing a value -system.cpu1.iew.wb_consumers 138617 # num instructions consuming a value +system.cpu1.iew.exec_nop 35367 # number of nop insts executed +system.cpu1.iew.exec_refs 101954 # number of memory reference insts executed +system.cpu1.iew.exec_branches 44806 # Number of branches executed +system.cpu1.iew.exec_stores 31973 # Number of stores executed +system.cpu1.iew.exec_rate 1.166086 # Inst execution rate +system.cpu1.iew.wb_sent 214321 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 214044 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 118861 # num instructions producing a value +system.cpu1.iew.wb_consumers 123754 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.243063 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.964975 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.162480 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.960462 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 14936 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 6432 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1521 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 175666 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.535334 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.989786 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 14492 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 7251 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1525 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 169801 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.422188 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.937267 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 78046 44.43% 44.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 47129 26.83% 71.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6230 3.55% 74.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 7351 4.18% 78.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1552 0.88% 79.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 32915 18.74% 98.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 634 0.36% 98.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 995 0.57% 99.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 814 0.46% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 80979 47.69% 47.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 42780 25.19% 72.88% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6215 3.66% 76.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 8147 4.80% 81.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1520 0.90% 82.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 27830 16.39% 98.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 515 0.30% 98.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1002 0.59% 99.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 813 0.48% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 175666 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 269706 # Number of instructions committed -system.cpu1.commit.committedOps 269706 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 169801 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 241489 # Number of instructions committed +system.cpu1.commit.committedOps 241489 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 114508 # Number of memory references committed -system.cpu1.commit.loads 78076 # Number of loads committed -system.cpu1.commit.membars 5720 # Number of memory barriers committed -system.cpu1.commit.branches 48115 # Number of branches committed +system.cpu1.commit.refs 99585 # Number of memory references committed +system.cpu1.commit.loads 68395 # Number of loads committed +system.cpu1.commit.membars 6536 # Number of memory barriers committed +system.cpu1.commit.branches 43685 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 184747 # Number of committed integer instructions. +system.cpu1.commit.int_insts 165393 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 814 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 813 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 458907 # The number of ROB reads -system.cpu1.rob.rob_writes 572109 # The number of ROB writes -system.cpu1.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 6108 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 36503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 225079 # Number of Instructions Simulated -system.cpu1.committedOps 225079 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 225079 # Number of Instructions Simulated -system.cpu1.cpi 0.849999 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.849999 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.176472 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.176472 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 410678 # number of integer regfile reads -system.cpu1.int_regfile_writes 191757 # number of integer regfile writes +system.cpu1.rob.rob_reads 424382 # The number of ROB reads +system.cpu1.rob.rob_writes 514748 # The number of ROB writes +system.cpu1.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 5100 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 35660 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 200479 # Number of Instructions Simulated +system.cpu1.committedOps 200479 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 200479 # Number of Instructions Simulated +system.cpu1.cpi 0.918435 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.918435 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.088808 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.088808 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 365766 # number of integer regfile reads +system.cpu1.int_regfile_writes 171568 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 118640 # number of misc regfile reads +system.cpu1.misc_regfile_reads 103658 # number of misc regfile reads system.cpu1.misc_regfile_writes 646 # number of misc regfile writes -system.cpu1.icache.replacements 322 # number of replacements -system.cpu1.icache.tagsinuse 90.918932 # Cycle average of tags in use -system.cpu1.icache.total_refs 21316 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 436 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 48.889908 # Average number of references to valid blocks. +system.cpu1.icache.replacements 321 # number of replacements +system.cpu1.icache.tagsinuse 92.890627 # Cycle average of tags in use +system.cpu1.icache.total_refs 23041 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 438 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 52.605023 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 90.918932 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.177576 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.177576 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 21316 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 21316 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 21316 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 21316 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 21316 # number of overall hits -system.cpu1.icache.overall_hits::total 21316 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 517 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 517 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 517 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 517 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 517 # number of overall misses -system.cpu1.icache.overall_misses::total 517 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11871000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 11871000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 11871000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 11871000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 11871000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 11871000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 21833 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 21833 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 21833 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 21833 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 21833 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 21833 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023680 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023680 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023680 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023680 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023680 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023680 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22961.315280 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 22961.315280 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22961.315280 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 22961.315280 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22961.315280 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 22961.315280 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 32000 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 92.890627 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.181427 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.181427 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 23041 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 23041 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 23041 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 23041 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 23041 # number of overall hits +system.cpu1.icache.overall_hits::total 23041 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 523 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 523 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 523 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 523 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 523 # number of overall misses +system.cpu1.icache.overall_misses::total 523 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10934000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 10934000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 10934000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 10934000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 10934000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 10934000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 23564 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 23564 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 23564 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 23564 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 23564 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 23564 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022195 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.022195 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022195 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.022195 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022195 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.022195 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20906.309751 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 20906.309751 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20906.309751 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 20906.309751 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20906.309751 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 20906.309751 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 66 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 32000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 66 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 81 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 81 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 81 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 81 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 436 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 436 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 436 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 436 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8857500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8857500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8857500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8857500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8857500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8857500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019970 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019970 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019970 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.019970 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019970 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.019970 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20315.366972 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 20315.366972 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 20315.366972 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 20315.366972 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 20315.366972 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 20315.366972 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 85 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 85 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 85 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 85 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 85 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 438 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 438 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 438 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 438 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 438 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 438 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8718000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8718000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8718000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8718000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8718000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8718000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018588 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018588 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018588 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.018588 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018588 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.018588 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19904.109589 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19904.109589 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19904.109589 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 19904.109589 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19904.109589 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 19904.109589 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.526466 # Cycle average of tags in use -system.cpu1.dcache.total_refs 42609 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 27.499718 # Cycle average of tags in use +system.cpu1.dcache.total_refs 37345 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1521.750000 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 1333.750000 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.526466 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.053763 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.053763 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 46637 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 46637 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 36226 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 36226 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 82863 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 82863 # 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miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.009473 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003850 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003850 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.787879 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.787879 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007022 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.007022 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007022 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.007022 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 28554.932735 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 28554.932735 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25532.142857 # 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miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004499 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004499 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.753623 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.753623 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007297 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.007297 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007297 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.007297 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 24870.603015 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 24870.603015 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22417.857143 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22417.857143 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 19384.615385 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 19384.615385 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24232.342007 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24232.342007 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24232.342007 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24232.342007 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -956,364 +956,364 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # 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number of SwapReq MSHR misses system.cpu1.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3164503 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3164503 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1890000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1890000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 1168500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 1168500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5054503 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5054503 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5054503 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5054503 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003398 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003398 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002915 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002915 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.787879 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.787879 # 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average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19001.890977 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19001.890977 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19001.890977 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19001.890977 # average overall mshr miss latency +system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2446500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2446500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1653500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1653500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 904000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 904000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4100000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4100000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4100000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4100000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003755 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003755 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003310 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003310 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.753623 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.753623 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003567 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003567 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003567 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003567 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15290.625000 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15290.625000 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16053.398058 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16053.398058 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 17384.615385 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 17384.615385 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15589.353612 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15589.353612 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15589.353612 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15589.353612 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 191010 # number of cpu cycles simulated +system.cpu2.numCycles 183836 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 57179 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 53988 # Number of conditional branches predicted -system.cpu2.BPredUnit.condIncorrect 1553 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 50487 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 49441 # Number of BTB hits +system.cpu2.BPredUnit.lookups 53962 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 50907 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 1502 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 47302 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 46374 # Number of BTB hits system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.usedRAS 815 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.usedRAS 814 # Number of times the RAS was used to get a target. system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.fetch.icacheStallCycles 29527 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 320031 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 57179 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 50256 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 111848 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 4474 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 35937 # Number of cycles fetch has spent blocked +system.cpu2.fetch.icacheStallCycles 29545 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 300535 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 53962 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 47188 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 106111 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 4305 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 35885 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6751 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1077 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 20539 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 333 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 187993 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.702356 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.156955 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.NoActiveThreadStallCycles 6446 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 1035 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 21240 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 181756 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.653508 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.139245 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 76145 40.50% 40.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 56782 30.20% 70.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 6165 3.28% 73.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3347 1.78% 75.77% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 731 0.39% 76.16% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 39077 20.79% 96.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1243 0.66% 97.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 913 0.49% 98.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3590 1.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 75645 41.62% 41.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 54116 29.77% 71.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 6682 3.68% 75.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3224 1.77% 76.84% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 665 0.37% 77.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 35775 19.68% 96.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1232 0.68% 97.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 880 0.48% 98.05% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3537 1.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 187993 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.299351 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.675467 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 35252 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 32290 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 105597 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5255 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2848 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 315625 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2848 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 36036 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 16472 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 14955 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 100655 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 10276 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 313299 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 22 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 57 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 219155 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 602465 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 602465 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 203359 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 15796 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1243 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1365 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 12944 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 89370 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 42679 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 42734 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 37374 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 259618 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6531 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 261379 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 134 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13068 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11786 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 697 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 187993 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.390366 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.314588 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 181756 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.293533 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.634799 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 35633 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 31817 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 99530 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5601 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2729 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 296271 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2729 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 36405 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 17349 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13658 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 94174 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 10995 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 293755 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 37 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 205188 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 562117 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 562117 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 190142 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 15046 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1228 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1359 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 13734 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 82915 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 39246 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 39773 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 34011 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 242760 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6943 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 245051 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 12414 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11373 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 664 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 181756 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.348242 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.310708 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 73641 39.17% 39.17% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 23139 12.31% 51.48% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 42800 22.77% 74.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 43353 23.06% 97.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3352 1.78% 99.09% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1252 0.67% 99.76% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 341 0.18% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 62 0.03% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 73115 40.23% 40.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 24368 13.41% 53.63% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 39333 21.64% 75.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 39995 22.00% 97.28% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3268 1.80% 99.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1268 0.70% 99.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 298 0.16% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 187993 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 181756 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 21 6.71% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 82 26.20% 32.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 67.09% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 20 6.83% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 63 21.50% 28.33% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 71.67% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 125670 48.08% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.08% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 93767 35.87% 83.95% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 41942 16.05% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 118754 48.46% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.46% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 87780 35.82% 84.28% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 38517 15.72% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 261379 # Type of FU issued -system.cpu2.iq.rate 1.368405 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 313 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001197 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 711198 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 279252 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 259224 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 245051 # Type of FU issued +system.cpu2.iq.rate 1.332987 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 293 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001196 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 672224 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 262158 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 243059 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 261692 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 245344 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 37218 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 33799 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2690 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1641 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2624 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1621 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2848 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 1926 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 75 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 309970 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 424 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 89370 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 42679 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1173 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 72 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2729 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 1758 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 290501 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 383 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 82915 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 39246 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1163 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 35 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 514 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1208 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1722 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 259980 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 88335 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1399 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 513 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1158 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1671 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 243729 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 81914 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1322 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 43821 # number of nop insts executed -system.cpu2.iew.exec_refs 130189 # number of memory reference insts executed -system.cpu2.iew.exec_branches 53302 # Number of branches executed -system.cpu2.iew.exec_stores 41854 # Number of stores executed -system.cpu2.iew.exec_rate 1.361081 # Inst execution rate -system.cpu2.iew.wb_sent 259524 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 259224 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 147020 # num instructions producing a value -system.cpu2.iew.wb_consumers 151915 # num instructions consuming a value +system.cpu2.iew.exec_nop 40798 # number of nop insts executed +system.cpu2.iew.exec_refs 120340 # number of memory reference insts executed +system.cpu2.iew.exec_branches 50195 # Number of branches executed +system.cpu2.iew.exec_stores 38426 # Number of stores executed +system.cpu2.iew.exec_rate 1.325796 # Inst execution rate +system.cpu2.iew.wb_sent 243343 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 243059 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 137174 # num instructions producing a value +system.cpu2.iew.wb_consumers 142058 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.357123 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.967778 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.322151 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.965620 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 15032 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5834 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1553 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 178395 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.653241 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.030877 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 14265 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 6279 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1502 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 172582 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.600480 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.009191 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 72759 40.79% 40.79% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 51159 28.68% 69.46% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6241 3.50% 72.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6697 3.75% 76.72% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1549 0.87% 77.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 37557 21.05% 98.64% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 629 0.35% 98.99% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 989 0.55% 99.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 815 0.46% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 72897 42.24% 42.24% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 48196 27.93% 70.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6187 3.58% 73.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 7136 4.13% 77.89% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1545 0.90% 78.78% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 34295 19.87% 98.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 518 0.30% 98.95% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 991 0.57% 99.53% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 817 0.47% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 178395 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 294930 # Number of instructions committed -system.cpu2.commit.committedOps 294930 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 172582 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 276214 # Number of instructions committed +system.cpu2.commit.committedOps 276214 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 127718 # Number of memory references committed -system.cpu2.commit.loads 86680 # Number of loads committed -system.cpu2.commit.membars 5119 # Number of memory barriers committed -system.cpu2.commit.branches 52122 # Number of branches committed +system.cpu2.commit.refs 117916 # Number of memory references committed +system.cpu2.commit.loads 80291 # Number of loads committed +system.cpu2.commit.membars 5562 # Number of memory barriers committed +system.cpu2.commit.branches 49152 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 201960 # Number of committed integer instructions. +system.cpu2.commit.int_insts 189186 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 815 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 817 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 486955 # The number of ROB reads -system.cpu2.rob.rob_writes 622786 # The number of ROB writes -system.cpu2.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3017 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 36810 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 246900 # Number of Instructions Simulated -system.cpu2.committedOps 246900 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 246900 # Number of Instructions Simulated -system.cpu2.cpi 0.773633 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.773633 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.292602 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.292602 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 450556 # number of integer regfile reads -system.cpu2.int_regfile_writes 209704 # number of integer regfile writes +system.cpu2.rob.rob_reads 461657 # The number of ROB reads +system.cpu2.rob.rob_writes 583698 # The number of ROB writes +system.cpu2.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 2080 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 35951 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 230713 # Number of Instructions Simulated +system.cpu2.committedOps 230713 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 230713 # Number of Instructions Simulated +system.cpu2.cpi 0.796817 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.796817 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.254994 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.254994 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 420543 # number of integer regfile reads +system.cpu2.int_regfile_writes 196056 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 131893 # number of misc regfile reads +system.cpu2.misc_regfile_reads 121964 # number of misc regfile reads system.cpu2.misc_regfile_writes 646 # number of misc regfile writes -system.cpu2.icache.replacements 322 # number of replacements -system.cpu2.icache.tagsinuse 84.177245 # Cycle average of tags in use -system.cpu2.icache.total_refs 20042 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 438 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 45.757991 # Average number of references to valid blocks. +system.cpu2.icache.replacements 323 # number of replacements +system.cpu2.icache.tagsinuse 86.140818 # Cycle average of tags in use +system.cpu2.icache.total_refs 20746 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 436 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 47.582569 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 84.177245 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.164409 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.164409 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 20042 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 20042 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 20042 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 20042 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 20042 # number of overall hits -system.cpu2.icache.overall_hits::total 20042 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 497 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 497 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 497 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 497 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 497 # number of overall misses -system.cpu2.icache.overall_misses::total 497 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7614500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 7614500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 7614500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 7614500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 7614500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 7614500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 20539 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 20539 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 20539 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 20539 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 20539 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 20539 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024198 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.024198 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024198 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.024198 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024198 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.024198 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15320.925553 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 15320.925553 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15320.925553 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 15320.925553 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15320.925553 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 15320.925553 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 86.140818 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.168244 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.168244 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 20746 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 20746 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 20746 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 20746 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 20746 # number of overall hits +system.cpu2.icache.overall_hits::total 20746 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 494 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 494 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 494 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 494 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 494 # number of overall misses +system.cpu2.icache.overall_misses::total 494 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6486500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 6486500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 6486500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 6486500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 6486500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 6486500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 21240 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 21240 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 21240 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 21240 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 21240 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 21240 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.023258 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.023258 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.023258 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.023258 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.023258 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.023258 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13130.566802 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 13130.566802 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13130.566802 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 13130.566802 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13130.566802 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 13130.566802 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1322,106 +1322,106 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 438 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 438 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5672000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 5672000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5672000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 5672000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5672000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 5672000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021325 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021325 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021325 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.021325 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021325 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.021325 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12949.771689 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12949.771689 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12949.771689 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12949.771689 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12949.771689 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12949.771689 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 58 # 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Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1686.285714 # Average number of references to valid blocks. +system.cpu2.dcache.tagsinuse 26.073093 # Cycle average of tags in use +system.cpu2.dcache.total_refs 43891 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1513.482759 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 24.875323 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.048585 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.048585 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 50709 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 50709 # 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number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 141 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 141 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 59 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 59 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 546 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 546 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 546 # number of overall misses +system.cpu2.dcache.overall_misses::total 546 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 9305500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 9305500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2828000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2828000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 998500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 998500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 12133500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 12133500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 12133500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 12133500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 48097 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 48097 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 37554 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 37554 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 85651 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 85651 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 85651 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 85651 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.008420 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.008420 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003755 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.003755 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.830986 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.830986 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006375 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.006375 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006375 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.006375 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 22976.543210 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 22976.543210 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20056.737589 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 20056.737589 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 16923.728814 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 16923.728814 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22222.527473 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 22222.527473 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22222.527473 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 22222.527473 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1430,364 +1430,364 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 234 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 234 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 35 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 269 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 269 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 269 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 269 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 155 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 259 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 259 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2539505 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2539505 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1736500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1736500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 1057000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1057000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4276005 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 4276005 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4276005 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 4276005 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003033 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003033 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002539 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002539 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.826087 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002813 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.002813 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002813 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.002813 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16383.903226 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16383.903226 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16697.115385 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16697.115385 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18543.859649 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18543.859649 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16509.671815 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16509.671815 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16509.671815 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16509.671815 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 239 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 239 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 273 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 273 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 273 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 273 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 166 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 107 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 59 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 273 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 273 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 273 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2062000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2062000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1458000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1458000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 880500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 880500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3520000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3520000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3520000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3520000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003451 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003451 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002849 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002849 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.830986 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.830986 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003187 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003187 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003187 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003187 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12421.686747 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 12421.686747 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13626.168224 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13626.168224 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 14923.728814 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 14923.728814 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12893.772894 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12893.772894 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12893.772894 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12893.772894 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 190730 # number of cpu cycles simulated +system.cpu3.numCycles 183564 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.BPredUnit.lookups 50135 # Number of BP lookups -system.cpu3.BPredUnit.condPredicted 46886 # Number of conditional branches predicted -system.cpu3.BPredUnit.condIncorrect 1563 # Number of conditional branches incorrect -system.cpu3.BPredUnit.BTBLookups 43380 # Number of BTB lookups -system.cpu3.BPredUnit.BTBHits 42368 # Number of BTB hits +system.cpu3.BPredUnit.lookups 54292 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 51137 # Number of conditional branches predicted +system.cpu3.BPredUnit.condIncorrect 1552 # Number of conditional branches incorrect +system.cpu3.BPredUnit.BTBLookups 47375 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 46456 # Number of BTB hits system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.usedRAS 844 # Number of times the RAS was used to get a target. +system.cpu3.BPredUnit.usedRAS 865 # Number of times the RAS was used to get a target. system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.fetch.icacheStallCycles 33373 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 273510 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 50135 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 43212 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 99693 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 4441 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 43703 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 29332 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 302436 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 54292 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 47321 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 106466 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 4424 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 35508 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6715 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1058 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 24485 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 321 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 187356 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.459841 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.059659 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 6464 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 1083 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 21183 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 181653 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.664911 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.146175 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 87663 46.79% 46.79% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 51707 27.60% 74.39% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 8154 4.35% 78.74% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3276 1.75% 80.49% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 745 0.40% 80.89% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 30183 16.11% 97.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1182 0.63% 97.63% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 888 0.47% 98.10% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3558 1.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 75187 41.39% 41.39% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 54224 29.85% 71.24% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 6571 3.62% 74.86% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3185 1.75% 76.61% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 729 0.40% 77.01% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 36075 19.86% 96.87% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1175 0.65% 97.52% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 882 0.49% 98.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3625 2.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 187356 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.262858 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.434017 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 40875 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 38262 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 91696 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 6999 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2809 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 269218 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2809 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 41677 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 21676 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 15745 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 84975 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 13759 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 266737 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 40 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 184789 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 501822 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 501822 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 169578 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 15211 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1292 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1426 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 16516 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 73298 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 33720 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 35666 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 28418 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 218299 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 8477 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 222114 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 12726 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11163 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 773 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 187356 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.185518 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.293170 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 181653 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.295766 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.647578 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 35528 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 31409 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 99893 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 5564 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2795 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 298258 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2795 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 36311 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 17134 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 13439 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 94588 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 10922 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 295479 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 43 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 206753 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 566043 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 566043 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 191392 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 15361 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1256 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1388 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 13950 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 83468 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 39555 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 39943 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 34309 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 244369 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 6827 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 246724 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 12382 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 11033 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 652 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 181653 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.358216 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.312562 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 85320 45.54% 45.54% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 28690 15.31% 60.85% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 33902 18.09% 78.95% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 34456 18.39% 97.34% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3309 1.77% 99.10% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1236 0.66% 99.76% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 327 0.17% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 62 0.03% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 72528 39.93% 39.93% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 24126 13.28% 53.21% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 39707 21.86% 75.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 40305 22.19% 97.25% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3272 1.80% 99.06% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1282 0.71% 99.76% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 320 0.18% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 60 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 187356 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 181653 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 22 7.17% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 75 24.43% 31.60% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 68.40% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 22 7.41% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 65 21.89% 29.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 70.71% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 109540 49.32% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.32% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 79567 35.82% 85.14% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 33007 14.86% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 119576 48.47% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.47% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 88284 35.78% 84.25% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 38864 15.75% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 222114 # Type of FU issued -system.cpu3.iq.rate 1.164547 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 307 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001382 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 632004 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 239536 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 220090 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 246724 # Type of FU issued +system.cpu3.iq.rate 1.344076 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 297 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001204 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 675462 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 263617 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 244690 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 222421 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 247021 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 28294 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 34138 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2578 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1587 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2601 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1592 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2809 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 1854 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 263586 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 366 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 73298 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 33720 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1219 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 53 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2795 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 1688 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 292203 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 375 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 83468 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 39555 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1173 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 48 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 509 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1217 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1726 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 220807 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 72290 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1307 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 498 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1226 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1724 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 245374 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 82515 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1350 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 36810 # number of nop insts executed -system.cpu3.iew.exec_refs 105220 # number of memory reference insts executed -system.cpu3.iew.exec_branches 46242 # Number of branches executed -system.cpu3.iew.exec_stores 32930 # Number of stores executed -system.cpu3.iew.exec_rate 1.157694 # Inst execution rate -system.cpu3.iew.wb_sent 220376 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 220090 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 122048 # num instructions producing a value -system.cpu3.iew.wb_consumers 126919 # num instructions consuming a value +system.cpu3.iew.exec_nop 41007 # number of nop insts executed +system.cpu3.iew.exec_refs 121290 # number of memory reference insts executed +system.cpu3.iew.exec_branches 50490 # Number of branches executed +system.cpu3.iew.exec_stores 38775 # Number of stores executed +system.cpu3.iew.exec_rate 1.336722 # Inst execution rate +system.cpu3.iew.wb_sent 244974 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 244690 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 138171 # num instructions producing a value +system.cpu3.iew.wb_consumers 143054 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.153935 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.961621 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.332996 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.965866 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 14631 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7704 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1563 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 177833 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.399791 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.928963 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 14351 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 6175 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1552 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 172395 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.611613 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.012919 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 86250 48.50% 48.50% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 44177 24.84% 73.34% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6214 3.49% 76.84% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8561 4.81% 81.65% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1535 0.86% 82.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 28697 16.14% 98.65% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 590 0.33% 98.98% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 996 0.56% 99.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 813 0.46% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 72191 41.88% 41.88% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 48466 28.11% 69.99% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6229 3.61% 73.60% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 7040 4.08% 77.69% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1522 0.88% 78.57% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 34600 20.07% 98.64% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 541 0.31% 98.95% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 992 0.58% 99.53% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 814 0.47% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 177833 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 248929 # Number of instructions committed -system.cpu3.commit.committedOps 248929 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 172395 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 277834 # Number of instructions committed +system.cpu3.commit.committedOps 277834 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 102853 # Number of memory references committed -system.cpu3.commit.loads 70720 # Number of loads committed -system.cpu3.commit.membars 6986 # Number of memory barriers committed -system.cpu3.commit.branches 45078 # Number of branches committed +system.cpu3.commit.refs 118830 # Number of memory references committed +system.cpu3.commit.loads 80867 # Number of loads committed +system.cpu3.commit.membars 5460 # Number of memory barriers committed +system.cpu3.commit.branches 49386 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 170050 # Number of committed integer instructions. +system.cpu3.commit.int_insts 190336 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 813 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 814 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 439993 # The number of ROB reads -system.cpu3.rob.rob_writes 529937 # The number of ROB writes -system.cpu3.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 3374 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 37090 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 206079 # Number of Instructions Simulated -system.cpu3.committedOps 206079 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 206079 # Number of Instructions Simulated -system.cpu3.cpi 0.925519 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.925519 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.080475 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.080475 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 375615 # number of integer regfile reads -system.cpu3.int_regfile_writes 175714 # number of integer regfile writes +system.cpu3.rob.rob_reads 463179 # The number of ROB reads +system.cpu3.rob.rob_writes 587180 # The number of ROB writes +system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1911 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 36223 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 232199 # Number of Instructions Simulated +system.cpu3.committedOps 232199 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 232199 # Number of Instructions Simulated +system.cpu3.cpi 0.790546 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.790546 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.264948 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.264948 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 423588 # number of integer regfile reads +system.cpu3.int_regfile_writes 197545 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 106918 # number of misc regfile reads +system.cpu3.misc_regfile_reads 122942 # number of misc regfile reads system.cpu3.misc_regfile_writes 646 # number of misc regfile writes -system.cpu3.icache.replacements 323 # number of replacements -system.cpu3.icache.tagsinuse 88.249587 # Cycle average of tags in use -system.cpu3.icache.total_refs 23982 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 439 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 54.628702 # Average number of references to valid blocks. +system.cpu3.icache.replacements 321 # number of replacements +system.cpu3.icache.tagsinuse 83.581511 # Cycle average of tags in use +system.cpu3.icache.total_refs 20679 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 436 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 47.428899 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 88.249587 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.172362 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.172362 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 23982 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 23982 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 23982 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 23982 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 23982 # number of overall hits -system.cpu3.icache.overall_hits::total 23982 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 503 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 503 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 503 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 503 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 503 # number of overall misses -system.cpu3.icache.overall_misses::total 503 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7707000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 7707000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 7707000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 7707000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 7707000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 7707000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 24485 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 24485 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 24485 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 24485 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 24485 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 24485 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020543 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.020543 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020543 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.020543 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020543 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.020543 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15322.067594 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 15322.067594 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15322.067594 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 15322.067594 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15322.067594 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 15322.067594 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 83.581511 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.163245 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.163245 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 20679 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 20679 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 20679 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 20679 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 20679 # number of overall hits +system.cpu3.icache.overall_hits::total 20679 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 504 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 504 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 504 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 504 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 504 # number of overall misses +system.cpu3.icache.overall_misses::total 504 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6381500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6381500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6381500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6381500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6381500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6381500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 21183 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 21183 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 21183 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 21183 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 21183 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 21183 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023793 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.023793 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023793 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.023793 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023793 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.023793 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 12661.706349 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 12661.706349 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 12661.706349 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 12661.706349 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 12661.706349 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 12661.706349 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1796,106 +1796,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 64 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 64 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 64 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 64 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 439 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 439 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 439 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 439 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 439 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 439 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5684000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5684000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5684000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5684000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5684000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5684000 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017929 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017929 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017929 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.017929 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017929 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.017929 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12947.608200 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12947.608200 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12947.608200 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12947.608200 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12947.608200 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12947.608200 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 68 # 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number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5023500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5023500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5023500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5023500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5023500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020583 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020583 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020583 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.020583 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020583 # 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mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003014 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003014 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 12680.645161 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 12680.645161 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13923.809524 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13923.809524 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 14964.285714 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 14964.285714 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13182.692308 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13182.692308 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13182.692308 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13182.692308 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 436.337885 # Cycle average of tags in use -system.l2c.total_refs 1474 # Total number of references to valid blocks. -system.l2c.sampled_refs 537 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.744879 # Average number of references to valid blocks. +system.l2c.tagsinuse 435.526886 # Cycle average of tags in use +system.l2c.total_refs 1471 # Total number of references to valid blocks. +system.l2c.sampled_refs 536 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.744403 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.838584 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 294.109117 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 59.534191 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 68.191567 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 5.703860 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 2.346215 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.730565 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 4.110047 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.773739 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.836552 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 292.896606 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 59.494044 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 70.004577 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 5.700111 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 3.075204 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.772877 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 2.016825 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.730090 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004488 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.004469 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.000908 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001041 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.001068 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.000087 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000063 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.006658 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 233 # number of ReadReq hits +system.l2c.occ_percent::cpu2.inst 0.000047 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.000012 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000031 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.006646 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 232 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 350 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 348 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 428 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 427 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 431 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 432 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1474 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1471 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 233 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40720.238095 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 42576.923077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 41749.253731 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40963.888889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 43630.952381 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40681.818182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44175 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42807.692308 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42923.076923 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42423.076923 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 41641.579732 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42576.923077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 41749.253731 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 1523ab302..df50fe29d 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000269 # Number of seconds simulated -sim_ticks 268898000 # Number of ticks simulated -final_tick 268898000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000262 # Number of seconds simulated +sim_ticks 261623500 # Number of ticks simulated +final_tick 261623500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1131883 # Simulator instruction rate (inst/s) -host_op_rate 1131850 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 454173870 # Simulator tick rate (ticks/s) -host_mem_usage 240368 # Number of bytes of host memory used -host_seconds 0.59 # Real time elapsed on the host -sim_insts 670104 # Number of instructions simulated -sim_ops 670104 # Number of ops (including micro ops) simulated +host_inst_rate 776063 # Simulator instruction rate (inst/s) +host_op_rate 776047 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 307506962 # Simulator tick rate (ticks/s) +host_mem_usage 231300 # Number of bytes of host memory used +host_seconds 0.85 # Real time elapsed on the host +sim_insts 660239 # Number of instructions simulated +sim_ops 660239 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 3392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 1408 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 3392 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 53 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 22 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 67832412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 39271397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14042499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5236186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 476017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3570127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1904068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3808135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 136140842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 67832412 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14042499 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 476017 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1904068 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 84254996 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 67832412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 39271397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14042499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 5236186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 476017 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3570127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1904068 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3808135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 136140842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69718508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40363347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 1712384 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3669395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 2201637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 3914021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 12965196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 5381780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139926268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69718508 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 1712384 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 2201637 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 12965196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86597725 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69718508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40363347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 1712384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3669395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 2201637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 3914021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 12965196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 5381780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 139926268 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 537796 # number of cpu cycles simulated +system.cpu0.numCycles 523247 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 160914 # Number of instructions committed -system.cpu0.committedOps 160914 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 110768 # Number of integer alu accesses +system.cpu0.committedInsts 158010 # Number of instructions committed +system.cpu0.committedOps 158010 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108832 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 26422 # number of instructions that are conditional controls -system.cpu0.num_int_insts 110768 # number of integer instructions +system.cpu0.num_conditional_control_insts 25938 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108832 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 320462 # number of times the integer registers were read -system.cpu0.num_int_register_writes 112374 # number of times the integer registers were written +system.cpu0.num_int_register_reads 314654 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110438 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 75191 # number of memory refs -system.cpu0.num_load_insts 49787 # Number of load instructions -system.cpu0.num_store_insts 25404 # Number of store instructions +system.cpu0.num_mem_refs 73739 # number of memory refs +system.cpu0.num_load_insts 48819 # Number of load instructions +system.cpu0.num_store_insts 24920 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 537796 # Number of busy cycles +system.cpu0.num_busy_cycles 523247 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 212.263647 # Cycle average of tags in use -system.cpu0.icache.total_refs 160510 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 212.464540 # Cycle average of tags in use +system.cpu0.icache.total_refs 157606 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 343.704497 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 337.486081 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 212.263647 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.414577 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.414577 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 160510 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 160510 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 160510 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 160510 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 160510 # number of overall hits -system.cpu0.icache.overall_hits::total 160510 # number of overall hits +system.cpu0.icache.occ_blocks::cpu0.inst 212.464540 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.414970 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.414970 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 157606 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 157606 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 157606 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 157606 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 157606 # number of overall hits +system.cpu0.icache.overall_hits::total 157606 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18554000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18554000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18554000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18554000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18554000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18554000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 160977 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 160977 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 160977 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 160977 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 160977 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 160977 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002901 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002901 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002901 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002901 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002901 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002901 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39730.192719 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 39730.192719 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39730.192719 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 39730.192719 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39730.192719 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 39730.192719 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18144000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18144000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18144000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18144000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18144000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18144000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 158073 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 158073 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 158073 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 158073 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 158073 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 158073 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002954 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002954 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002954 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002954 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002954 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002954 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38852.248394 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38852.248394 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38852.248394 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38852.248394 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -139,44 +139,44 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17153000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17153000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17153000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17153000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17153000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17153000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002901 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002901 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002901 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36730.192719 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36730.192719 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36730.192719 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17210000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17210000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17210000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17210000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17210000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17210000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002954 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002954 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002954 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36852.248394 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 36852.248394 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 36852.248394 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 145.520681 # Cycle average of tags in use -system.cpu0.dcache.total_refs 74667 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 145.601248 # Cycle average of tags in use +system.cpu0.dcache.total_refs 73215 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 447.107784 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 438.413174 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 145.520681 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.284220 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.284220 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 49615 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 49615 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 25170 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 25170 # number of WriteReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 145.601248 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.284377 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.284377 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 48647 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48647 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24686 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24686 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 74785 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 74785 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 74785 # number of overall hits -system.cpu0.dcache.overall_hits::total 74785 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 73333 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73333 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73333 # number of overall hits +system.cpu0.dcache.overall_hits::total 73333 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses @@ -187,46 +187,46 @@ system.cpu0.dcache.demand_misses::cpu0.data 345 # system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses system.cpu0.dcache.overall_misses::total 345 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5171000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5171000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7310000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7310000 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 522000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 522000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 12481000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 12481000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 12481000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 12481000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 49777 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 49777 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 25353 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 25353 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4649500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4649500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7005000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7005000 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 363500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 363500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11654500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11654500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11654500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11654500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48809 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48809 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24869 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24869 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 75130 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 75130 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 75130 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 75130 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003255 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003255 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007218 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007218 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 73678 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73678 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73678 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73678 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003319 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003319 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007359 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007359 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004592 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004592 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004592 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004592 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31919.753086 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31919.753086 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39945.355191 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39945.355191 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 20076.923077 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 20076.923077 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36176.811594 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36176.811594 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36176.811594 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36176.811594 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004683 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004683 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004683 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004683 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28700.617284 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28700.617284 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38278.688525 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38278.688525 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13980.769231 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 13980.769231 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33781.159420 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33781.159420 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33781.159420 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33781.159420 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -247,104 +247,104 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4684001 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4684001 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6761000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6761000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 444000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 444000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11445001 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11445001 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11445001 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11445001 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003255 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003255 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007218 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007218 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4325500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4325500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6639000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6639000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 311500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 311500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10964500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10964500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10964500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10964500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003319 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003319 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007359 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007359 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004592 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004592 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004592 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004592 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28913.586420 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28913.586420 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36945.355191 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36945.355191 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17076.923077 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17076.923077 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33173.915942 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33173.915942 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33173.915942 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33173.915942 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004683 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004683 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004683 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004683 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26700.617284 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26700.617284 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36278.688525 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36278.688525 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11980.769231 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11980.769231 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31781.159420 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31781.159420 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31781.159420 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31781.159420 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 537796 # number of cpu cycles simulated +system.cpu1.numCycles 523247 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 159902 # Number of instructions committed -system.cpu1.committedOps 159902 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 114536 # Number of integer alu accesses +system.cpu1.committedInsts 173283 # Number of instructions committed +system.cpu1.committedOps 173283 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 108736 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 26689 # number of instructions that are conditional controls -system.cpu1.num_int_insts 114536 # number of integer instructions +system.cpu1.num_conditional_control_insts 36284 # number of instructions that are conditional controls +system.cpu1.num_int_insts 108736 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 313629 # number of times the integer registers were read -system.cpu1.num_int_register_writes 121810 # number of times the integer registers were written +system.cpu1.num_int_register_reads 252002 # number of times the integer registers were read +system.cpu1.num_int_register_writes 93825 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 64016 # number of memory refs -system.cpu1.num_load_insts 42937 # Number of load instructions -system.cpu1.num_store_insts 21079 # Number of store instructions -system.cpu1.num_idle_cycles 71578.001734 # Number of idle cycles -system.cpu1.num_busy_cycles 466217.998266 # Number of busy cycles -system.cpu1.not_idle_fraction 0.866905 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.133095 # Percentage of idle cycles +system.cpu1.num_mem_refs 48621 # number of memory refs +system.cpu1.num_load_insts 40031 # Number of load instructions +system.cpu1.num_store_insts 8590 # Number of store instructions +system.cpu1.num_idle_cycles 68750.001737 # Number of idle cycles +system.cpu1.num_busy_cycles 454496.998263 # Number of busy cycles +system.cpu1.not_idle_fraction 0.868609 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.131391 # Percentage of idle cycles system.cpu1.icache.replacements 280 # number of replacements -system.cpu1.icache.tagsinuse 69.905818 # Cycle average of tags in use -system.cpu1.icache.total_refs 159569 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 65.593035 # Cycle average of tags in use +system.cpu1.icache.total_refs 172950 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 435.980874 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 472.540984 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 69.905818 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.136535 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.136535 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 159569 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 159569 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 159569 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 159569 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 159569 # number of overall hits -system.cpu1.icache.overall_hits::total 159569 # number of overall hits +system.cpu1.icache.occ_blocks::cpu1.inst 65.593035 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.128111 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.128111 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 172950 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 172950 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 172950 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 172950 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 172950 # number of overall hits +system.cpu1.icache.overall_hits::total 172950 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7984500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7984500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7984500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7984500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7984500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7984500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 159935 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 159935 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 159935 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 159935 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 159935 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 159935 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002288 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002288 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002288 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002288 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002288 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002288 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21815.573770 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 21815.573770 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21815.573770 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 21815.573770 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21815.573770 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 21815.573770 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5373500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5373500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5373500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5373500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5373500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5373500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 173316 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 173316 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 173316 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 173316 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 173316 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 173316 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002112 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002112 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002112 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002112 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002112 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002112 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14681.693989 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14681.693989 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14681.693989 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14681.693989 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14681.693989 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14681.693989 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # 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number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1665500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 549500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 549500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4627500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4627500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4627500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4627500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004422 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004422 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012328 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.012328 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.774648 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.774648 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005810 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.005810 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005810 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.005810 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16734.463277 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16734.463277 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15861.904762 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15861.904762 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 9990.909091 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 9990.909091 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16409.574468 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16409.574468 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16409.574468 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16409.574468 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 537796 # number of cpu cycles simulated +system.cpu2.numCycles 523246 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 177221 # Number of instructions committed -system.cpu2.committedOps 177221 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 109567 # Number of integer alu accesses +system.cpu2.committedInsts 160665 # Number of instructions committed +system.cpu2.committedOps 160665 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 113639 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 37840 # number of instructions that are conditional controls -system.cpu2.num_int_insts 109567 # number of integer instructions +system.cpu2.num_conditional_control_insts 27518 # number of instructions that are conditional controls +system.cpu2.num_int_insts 113639 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 249142 # number of times the integer registers were read -system.cpu2.num_int_register_writes 92045 # number of times the integer registers were written +system.cpu2.num_int_register_reads 306682 # number of times the integer registers were read +system.cpu2.num_int_register_writes 118721 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 47896 # number of memory refs -system.cpu2.num_load_insts 40447 # Number of load instructions -system.cpu2.num_store_insts 7449 # Number of store instructions -system.cpu2.num_idle_cycles 71854.001733 # Number of idle cycles -system.cpu2.num_busy_cycles 465941.998267 # Number of busy cycles -system.cpu2.not_idle_fraction 0.866392 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.133608 # Percentage of idle cycles +system.cpu2.num_mem_refs 62290 # number of memory refs +system.cpu2.num_load_insts 42488 # Number of load instructions +system.cpu2.num_store_insts 19802 # Number of store instructions +system.cpu2.num_idle_cycles 69015.869837 # Number of idle cycles +system.cpu2.num_busy_cycles 454230.130163 # Number of busy cycles +system.cpu2.not_idle_fraction 0.868101 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.131899 # Percentage of idle cycles system.cpu2.icache.replacements 281 # number of replacements -system.cpu2.icache.tagsinuse 67.534984 # Cycle average of tags in use -system.cpu2.icache.total_refs 176887 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 67.731754 # Cycle average of tags in use +system.cpu2.icache.total_refs 160331 # Total number of references to valid blocks. system.cpu2.icache.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 481.980926 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 436.869210 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 67.534984 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.131904 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.131904 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 176887 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 176887 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 176887 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 176887 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 176887 # number of overall hits -system.cpu2.icache.overall_hits::total 176887 # number of overall hits +system.cpu2.icache.occ_blocks::cpu2.inst 67.731754 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.132289 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.132289 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 160331 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 160331 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 160331 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 160331 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 160331 # number of overall hits +system.cpu2.icache.overall_hits::total 160331 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 367 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 367 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 367 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 367 # number of overall misses system.cpu2.icache.overall_misses::total 367 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5709500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 5709500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 5709500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 5709500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 5709500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 5709500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 177254 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 177254 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 177254 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 177254 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 177254 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 177254 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002070 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002070 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002070 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002070 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002070 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002070 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15557.220708 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 15557.220708 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15557.220708 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 15557.220708 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15557.220708 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 15557.220708 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5321500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 5321500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 5321500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 5321500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 5321500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 5321500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 160698 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 160698 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 160698 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 160698 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 160698 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 160698 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002284 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002284 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002284 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002284 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002284 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002284 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14500 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 14500 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14500 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 14500 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14500 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 14500 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -577,94 +577,94 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 367 system.cpu2.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 367 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4608500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 4608500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4608500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 4608500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4608500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 4608500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002070 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002070 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002070 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002070 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002070 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002070 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12557.220708 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12557.220708 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12557.220708 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12557.220708 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12557.220708 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12557.220708 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4587500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 4587500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4587500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 4587500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4587500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 4587500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002284 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002284 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002284 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12500 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12500 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12500 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12500 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12500 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12500 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 26.638398 # Cycle average of tags in use -system.cpu2.dcache.total_refs 17171 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 26.833050 # Cycle average of tags in use +system.cpu2.dcache.total_refs 41851 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 592.103448 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 1443.137931 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 26.638398 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.052028 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.052028 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 40266 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 40266 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 7273 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 7273 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 18 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 18 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 47539 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 47539 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 47539 # number of overall hits -system.cpu2.dcache.overall_hits::total 47539 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 173 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 173 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 278 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 278 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 278 # number of overall misses -system.cpu2.dcache.overall_misses::total 278 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3995000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 3995000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2318000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2318000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 814000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 814000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 6313000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 6313000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 6313000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 6313000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 40439 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 40439 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 7378 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 7378 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 47817 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 47817 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 47817 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 47817 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.004278 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.004278 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.014231 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.014231 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.739130 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.739130 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005814 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.005814 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005814 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.005814 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23092.485549 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 23092.485549 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22076.190476 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 22076.190476 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 15960.784314 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 15960.784314 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22708.633094 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 22708.633094 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22708.633094 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 22708.633094 # average overall miss latency +system.cpu2.dcache.occ_blocks::cpu2.data 26.833050 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.052408 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.052408 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 42328 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42328 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 19626 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 19626 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 61954 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 61954 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 61954 # number of overall hits +system.cpu2.dcache.overall_hits::total 61954 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 152 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 152 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 106 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 106 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 258 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 258 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 258 # number of overall misses +system.cpu2.dcache.overall_misses::total 258 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 1938000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 1938000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2155000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2155000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 612500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 612500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 4093000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4093000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4093000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4093000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 42480 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 42480 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 19732 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 19732 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 62212 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 62212 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 62212 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 62212 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003578 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003578 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.005372 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.005372 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.852941 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.852941 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004147 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004147 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004147 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004147 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12750 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 12750 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20330.188679 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 20330.188679 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10560.344828 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 10560.344828 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15864.341085 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 15864.341085 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15864.341085 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 15864.341085 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -673,114 +673,114 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 173 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 278 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 278 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 278 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 3476000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 3476000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2003000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2003000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 661000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 661000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 5479000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 5479000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 5479000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 5479000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004278 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004278 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014231 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.014231 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.739130 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.739130 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.005814 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.005814 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.005814 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.005814 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 20092.485549 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 20092.485549 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19076.190476 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19076.190476 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 12960.784314 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 12960.784314 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 19708.633094 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19708.633094 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19708.633094 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19708.633094 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 152 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 258 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 258 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 258 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 258 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1634000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1634000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1943000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1943000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 496500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 496500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3577000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3577000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3577000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3577000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003578 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003578 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.005372 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.005372 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.852941 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.852941 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004147 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004147 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004147 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004147 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10750 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10750 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 18330.188679 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 18330.188679 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8560.344828 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8560.344828 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13864.341085 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13864.341085 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13864.341085 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13864.341085 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 537796 # number of cpu cycles simulated +system.cpu3.numCycles 523246 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 172067 # Number of instructions committed -system.cpu3.committedOps 172067 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 111206 # Number of integer alu accesses +system.cpu3.committedInsts 168281 # Number of instructions committed +system.cpu3.committedOps 168281 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 108796 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 34437 # number of instructions that are conditional controls -system.cpu3.num_int_insts 111206 # number of integer instructions +system.cpu3.num_conditional_control_insts 33752 # number of instructions that are conditional controls +system.cpu3.num_int_insts 108796 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 269314 # number of times the integer registers were read -system.cpu3.num_int_register_writes 101322 # number of times the integer registers were written +system.cpu3.num_int_register_reads 262371 # number of times the integer registers were read +system.cpu3.num_int_register_writes 98980 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 52937 # number of memory refs -system.cpu3.num_load_insts 41268 # Number of load instructions -system.cpu3.num_store_insts 11669 # Number of store instructions -system.cpu3.num_idle_cycles 72130.001732 # Number of idle cycles -system.cpu3.num_busy_cycles 465665.998268 # Number of busy cycles -system.cpu3.not_idle_fraction 0.865879 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.134121 # Percentage of idle cycles +system.cpu3.num_mem_refs 51213 # number of memory refs +system.cpu3.num_load_insts 40064 # Number of load instructions +system.cpu3.num_store_insts 11149 # Number of store instructions +system.cpu3.num_idle_cycles 69253.869381 # Number of idle cycles +system.cpu3.num_busy_cycles 453992.130619 # Number of busy cycles +system.cpu3.not_idle_fraction 0.867646 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.132354 # Percentage of idle cycles system.cpu3.icache.replacements 280 # number of replacements -system.cpu3.icache.tagsinuse 65.345482 # Cycle average of tags in use -system.cpu3.icache.total_refs 171734 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 70.063196 # Cycle average of tags in use +system.cpu3.icache.total_refs 167948 # Total number of references to valid blocks. system.cpu3.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 469.218579 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 458.874317 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 65.345482 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.127628 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.127628 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 171734 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 171734 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 171734 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 171734 # 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number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 751000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 751000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 5419000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 5419000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 5419000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 5419000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004266 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004266 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.009055 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.009055 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830986 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.830986 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005316 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.005316 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005316 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.005316 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 22005.681818 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 22005.681818 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14723.809524 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14723.809524 # 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number of ReadReq accesses(hits+misses) @@ -1069,47 +1069,47 @@ system.l2c.ReadReq_accesses::total 1670 # nu system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 27 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 11 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 88 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 87 # 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miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses @@ -1117,54 +1117,54 @@ system.l2c.ReadExReq_miss_rate::cpu3.data 1 # m system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.640000 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.inst 0.032698 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.021858 # 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Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index e04fdea8a..0a4a4cf1a 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,633 +1,633 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000757 # Number of seconds simulated -sim_ticks 757091500 # Number of ticks simulated -final_tick 757091500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000761 # Number of seconds simulated +sim_ticks 761298000 # Number of ticks simulated +final_tick 761298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 129668365 # Simulator tick rate (ticks/s) -host_mem_usage 347944 # Number of bytes of host memory used -host_seconds 5.84 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 90255 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 89097 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 89397 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 87447 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 92253 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 92127 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 87941 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 90122 # Number of bytes read from this memory -system.physmem.bytes_read::total 718639 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 466688 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5395 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5319 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5314 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5343 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5295 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5581 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5197 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5320 # Number of bytes written to this memory -system.physmem.bytes_written::total 509452 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10977 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11088 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11217 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11361 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11298 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11018 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11057 # Number of read requests responded to by this memory -system.physmem.num_reads::total 89080 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 7292 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5395 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5319 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5314 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5343 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5295 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5581 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5197 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5320 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50056 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 119212803 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 117683265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 118079519 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 115503872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 121851850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 121685424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 116156369 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 119037131 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 949210234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 616422189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 7125955 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 7025571 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 7018967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 7057271 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 6993871 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 7371632 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 6864428 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 7026892 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 672906775 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 616422189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 126338758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 124708836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 125098485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 122561144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 128845721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 129057056 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 123020797 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 126064023 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1622117010 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 15543 # number of replacements -system.l2c.tagsinuse 804.498263 # Cycle average of tags in use -system.l2c.total_refs 151705 # Total number of references to valid blocks. -system.l2c.sampled_refs 16364 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.270655 # Average number of references to valid blocks. +host_tick_rate 219241825 # Simulator tick rate (ticks/s) +host_mem_usage 341324 # Number of bytes of host memory used +host_seconds 3.47 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 89717 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 92471 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 92156 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 88405 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 90559 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 92920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 90802 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 90403 # Number of bytes read from this memory +system.physmem.bytes_read::total 727433 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 479872 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5444 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5306 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5518 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5318 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5329 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5364 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5370 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5377 # Number of bytes written to this memory +system.physmem.bytes_written::total 522898 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11345 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11075 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11201 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11041 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11368 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11335 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11107 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11275 # Number of read requests responded to by this memory +system.physmem.num_reads::total 89747 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 7498 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5444 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5306 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5518 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5318 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5329 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5364 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5370 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5377 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50524 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 117847413 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 121464919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 121051152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 116124041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 118953419 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 122054701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 119272611 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 118748506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 955516762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 630333982 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 7150945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 6969675 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 7248147 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 6985438 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 6999887 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 7045861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 7053742 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 7062937 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 686850616 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 630333982 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 124998358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 128434595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 128299299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 123109479 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 125953306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 129100562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 126326353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 125811443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1642367378 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 15728 # number of replacements +system.l2c.tagsinuse 804.643799 # Cycle average of tags in use +system.l2c.total_refs 152339 # Total number of references to valid blocks. +system.l2c.sampled_refs 16530 # Sample count of references to valid blocks. +system.l2c.avg_refs 9.215910 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 743.034079 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 7.652510 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 7.207345 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 7.804802 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 7.584993 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 7.883519 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 7.822009 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 7.314161 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu7 8.194845 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.725619 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0 0.007473 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1 0.007038 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2 0.007622 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3 0.007407 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu4 0.007699 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu5 0.007639 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu6 0.007143 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu7 0.008003 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.785643 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0 10656 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10576 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10855 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10944 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10856 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10997 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10762 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10884 # number of ReadReq hits -system.l2c.ReadReq_hits::total 86530 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 77152 # number of Writeback hits -system.l2c.Writeback_hits::total 77152 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 335 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 345 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 353 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 387 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 361 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 367 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 340 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 332 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2820 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 2056 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 2082 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 2008 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 2098 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 2081 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 2029 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 2020 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 2069 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 16443 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12712 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12658 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12863 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 13042 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12937 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 13026 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12782 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12953 # number of demand (read+write) hits -system.l2c.demand_hits::total 102973 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12712 # number of overall hits -system.l2c.overall_hits::cpu1 12658 # number of overall hits -system.l2c.overall_hits::cpu2 12863 # number of overall hits -system.l2c.overall_hits::cpu3 13042 # number of overall hits -system.l2c.overall_hits::cpu4 12937 # number of overall hits -system.l2c.overall_hits::cpu5 13026 # number of overall hits -system.l2c.overall_hits::cpu6 12782 # number of overall hits -system.l2c.overall_hits::cpu7 12953 # number of overall hits -system.l2c.overall_hits::total 102973 # number of overall hits -system.l2c.ReadReq_misses::cpu0 825 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 783 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 805 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 784 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 818 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 847 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 802 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 828 # number of ReadReq misses -system.l2c.ReadReq_misses::total 6492 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1871 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1835 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1867 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1892 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1828 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1835 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1851 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1876 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 14855 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4261 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4189 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4229 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4314 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4275 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4251 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4117 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4314 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 33950 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5086 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 4972 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5034 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5098 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5093 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5098 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 4919 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5142 # number of demand (read+write) misses -system.l2c.demand_misses::total 40442 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5086 # number of overall misses -system.l2c.overall_misses::cpu1 4972 # number of overall misses -system.l2c.overall_misses::cpu2 5034 # number of overall misses -system.l2c.overall_misses::cpu3 5098 # number of overall misses -system.l2c.overall_misses::cpu4 5093 # number of overall misses -system.l2c.overall_misses::cpu5 5098 # number of overall misses -system.l2c.overall_misses::cpu6 4919 # number of overall misses -system.l2c.overall_misses::cpu7 5142 # number of overall misses -system.l2c.overall_misses::total 40442 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 68189898 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 66156919 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 68642411 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 68279416 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 69618906 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 72771903 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 69510913 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 75078411 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 558248777 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 55439380 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 51556398 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 53772873 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 56810367 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 54586881 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 52940893 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 52708899 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 53996365 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 431812056 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 243093964 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 240130019 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 242345503 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 242765011 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 244393485 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 241342993 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 234214460 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 244073518 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1932358953 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 311283862 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 306286938 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 310987914 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 311044427 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 314012391 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 314114896 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 303725373 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 319151929 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2490607730 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 311283862 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 306286938 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 310987914 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 311044427 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 314012391 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 314114896 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 303725373 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 319151929 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2490607730 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0 11481 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1 11359 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2 11660 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3 11728 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu4 11674 # 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number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2191 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2208 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 17675 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6317 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6271 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6237 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6412 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6356 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6280 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6137 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6383 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50393 # 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number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1828 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 14842 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4339 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4322 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4349 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4270 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4225 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4246 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4116 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4276 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 34143 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5150 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5172 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5190 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5067 # 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number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 53053446 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 55065452 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 53902466 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 431652155 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 247942331 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 244706822 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 247942337 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 243863836 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 241149827 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 241354363 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 234845330 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 242655342 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1944460188 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 315527812 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 317380789 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 320449810 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 311764322 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 312134794 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 313976345 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 308865301 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 314544815 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2514643988 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 315527812 # 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number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11816 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11805 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11792 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 93855 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 77421 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 77421 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2247 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2119 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2235 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2185 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2252 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2188 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2275 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2226 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 17727 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6435 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6412 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6366 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6389 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6253 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6308 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6228 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6331 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50722 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 18261 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18034 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18176 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17865 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17961 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu5 18124 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17701 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 18095 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 143415 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17798 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17630 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17897 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 18140 # 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number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.071858 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.068932 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.069039 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.066849 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.070070 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.071513 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.069353 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.070697 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.069790 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.848141 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.841743 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.840991 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.830189 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.835085 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.833333 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.844820 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.849638 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.840453 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.674529 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.667996 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.678050 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.672801 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.672593 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.676911 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.670849 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.675858 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.673705 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.285762 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.282019 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.281276 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.281036 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.282474 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.281284 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.277894 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.284167 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.281993 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.285762 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.282019 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.281276 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.281036 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.282474 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.281284 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.277894 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.284167 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.281993 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 82654.421818 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 84491.595147 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 85270.075776 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 87091.091837 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 85108.687042 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 85917.240850 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 86671.961347 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 90674.409420 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 85990.261399 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 29630.881881 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 28096.129700 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 28801.753080 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 30026.621036 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 29861.532276 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28850.622888 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 28475.904376 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 28782.710554 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29068.465567 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 57050.918564 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 57323.948198 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 57305.628517 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 56273.762401 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 57168.066667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 56773.228182 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 56889.594365 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 56577.078813 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 56917.789485 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 61204.062525 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 61602.360821 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 61777.495828 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 61013.030012 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 61655.682505 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 61615.318949 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 61745.349258 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 62067.664138 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 61584.682508 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 61204.062525 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 61602.360821 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 61777.495828 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 61013.030012 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 61655.682505 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 61615.318949 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 61745.349258 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 62067.664138 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 61584.682508 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 323471 # number of cycles access was blocked +system.l2c.overall_accesses::cpu6 18033 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18123 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 144577 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.068578 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.073137 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.071211 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.069449 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.070208 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.073290 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.073528 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.067927 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.070918 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.847352 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.842850 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.842506 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.830664 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.839254 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.846435 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.828132 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.821204 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.837254 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.674281 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.674049 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.683161 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.668336 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.675676 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.673114 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.660886 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.675407 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.673140 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.282022 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.286792 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.285541 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.283627 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.280998 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.282057 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.276382 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.280141 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.282196 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.282022 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.286792 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.285541 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.283627 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.280998 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.282057 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.276382 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.280141 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.282196 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 83335.981504 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 85498.784706 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 86215.782402 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 85195.089084 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 86356.407543 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 83859.101617 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 85276.464286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 89749.654182 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 85664.633413 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 28851.082983 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 28838.723964 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 29108.578864 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 29583.996143 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28934.370899 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 28646.569114 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 29227.946921 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29487.125821 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29083.152877 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 57142.735884 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 56618.885238 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 57011.344447 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 57110.968618 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 57076.882130 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 56842.760951 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 57056.688533 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 56748.209074 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 56950.478517 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 61267.536311 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 61365.195089 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 61743.701349 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 61528.384054 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 61845.610065 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 61419.472809 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 61971.368579 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 61954.858184 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 61634.941739 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 61267.536311 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 61365.195089 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 61743.701349 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 61528.384054 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 61845.610065 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 61419.472809 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 61971.368579 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 61954.858184 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 61634.941739 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 618 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 94 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 3441.180851 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 6.574468 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 7293 # number of writebacks -system.l2c.writebacks::total 7293 # number of writebacks +system.l2c.writebacks::writebacks 7498 # number of writebacks +system.l2c.writebacks::total 7498 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 1 # number of UpgradeReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 11 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu0 2 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu0 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 3 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 31 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 34 # number of ReadExReq MSHR hits system.l2c.demand_mshr_hits::cpu0 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 96 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 19 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 98 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 16 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 96 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 818 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 774 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 794 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 778 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 810 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 838 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 793 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 822 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 6427 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1871 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1835 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1867 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1892 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1828 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1835 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1850 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1876 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 14854 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4256 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4182 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4226 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4311 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4274 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4247 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4111 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4312 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 33919 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5074 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 4956 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5020 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5089 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5084 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5085 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 4904 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5134 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40346 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5074 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 4956 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5020 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5089 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5084 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5085 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 4904 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5134 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40346 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 57681466 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 55801476 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 58516973 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 58678465 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 58920974 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 61933964 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 58878980 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 64759967 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 475172265 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 77326932 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 75430964 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 76820936 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 77936944 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 75295947 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 75638458 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 76288450 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 77210443 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 611949074 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 190865870 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 188480880 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 190796375 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 190236368 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 192397382 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 189567870 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 183778356 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 191626863 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1517749964 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 248547336 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 244282356 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 249313348 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 248914833 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 251318356 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 251501834 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 242657336 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 256386830 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1992922229 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 248547336 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 244282356 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 249313348 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 248914833 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 251318356 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 251501834 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 242657336 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 256386830 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1992922229 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 413458717 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 411792191 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 414319722 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 423127681 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 423239170 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 421136201 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 414540172 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 411527705 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3333141559 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 232000375 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 229604409 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 230860874 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 229140383 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 229719408 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 244869353 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 226374384 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 231941380 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1854510566 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 645459092 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 641396600 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 645180596 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 652268064 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 652958578 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 666005554 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 640914556 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 643469085 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5187652125 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.071248 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.068140 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.068096 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.066337 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.069385 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.070753 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.068575 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.070184 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.069091 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.848141 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.841743 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.840991 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.830189 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.835085 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.833333 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.844363 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.849638 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.840396 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.673738 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.666879 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.677569 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.672333 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.672435 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.676274 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.669871 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.675544 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.673090 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.285088 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.281112 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.280494 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.280540 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.281974 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.280567 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.277046 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.283725 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.281323 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.285088 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.281112 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.280494 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.280540 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.281974 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.280567 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.277046 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.283725 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.281323 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 70515.239609 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 72094.930233 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 73698.958438 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 75422.191517 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 72741.943210 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 73906.878282 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 74248.398487 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 78783.414842 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 73933.758363 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41329.199359 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41106.792371 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41146.725228 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41192.887949 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41190.342998 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41219.868120 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41237 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41156.952559 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41197.594857 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 44846.304041 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 45069.555237 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 45148.219356 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44128.129900 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 45015.765559 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44635.712267 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44704.051569 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44440.367115 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 44746.306318 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 48984.496650 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 49290.225182 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 49664.013546 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 48912.327176 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 49433.193548 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 49459.554376 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 49481.512235 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 49939.000779 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 49395.782209 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 48984.496650 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 49290.225182 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 49664.013546 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 48912.327176 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 49433.193548 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 49459.554376 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 49481.512235 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 49939.000779 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 49395.782209 # average overall mshr miss latency +system.l2c.overall_mshr_hits::cpu1 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 19 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 98 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 804 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 843 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 831 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 788 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 815 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 856 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 857 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 798 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 6592 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1902 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1786 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1883 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1815 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1889 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1852 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1884 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1828 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 14839 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4334 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4318 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4340 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4265 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4222 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4242 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4116 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4272 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34109 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5138 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5161 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5171 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5053 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5037 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5098 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 4973 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5070 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40701 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5138 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5161 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5171 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5053 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5037 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5098 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 4973 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5070 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40701 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 57455481 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 61467468 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 61812473 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 57960486 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 60571467 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 61211482 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 62615971 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 61885973 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 484980801 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 78471422 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 73680432 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 77692433 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 74790419 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 77910437 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 76253912 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 77720922 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 75415430 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 611935407 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 195176331 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 192089822 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 194667337 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 191905836 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 189907827 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 189746863 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 184982830 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 190582842 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1529059688 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 252631812 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 253557290 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 256479810 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 249866322 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 250479294 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 250958345 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 247598801 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 252468815 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2014040489 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 252631812 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 253557290 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 256479810 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 249866322 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 250479294 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 250958345 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 247598801 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 252468815 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2014040489 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 426624598 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 414248119 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 417125081 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 415481622 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 425535608 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 422832619 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 413879620 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 421948093 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3357675360 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 234914484 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 229533990 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 238126486 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 230756493 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 230060497 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 233129489 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 235046492 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 235339481 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1866907412 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 661539082 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 643782109 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 655251567 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 646238115 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 655596105 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 655962108 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 648926112 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 657287574 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5224582772 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.067986 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.072535 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.070364 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.068665 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.069611 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.072444 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.072596 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.067673 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.070236 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.846462 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.842850 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.842506 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.830664 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.838810 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.846435 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.828132 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.821204 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.837085 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.673504 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.673425 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.681747 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.667554 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.675196 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.672479 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.660886 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.674775 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.672470 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.281365 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.286182 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.284496 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.282844 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.280441 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.281284 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.275772 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.279755 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.281518 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.281365 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.286182 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.284496 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.282844 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.280441 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.281284 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.275772 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.279755 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.281518 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 71462.041045 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 72915.145907 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 74383.240674 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 73553.916244 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 74320.818405 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 71508.740654 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 73064.143524 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 77551.344612 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 73571.116657 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41257.319664 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41254.441209 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41259.921933 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41206.842424 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41244.275807 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41173.818575 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41253.143312 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41255.705689 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41238.318418 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 45033.763498 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 44485.831867 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44854.225115 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44995.506682 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44980.536949 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44730.519331 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44942.378523 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44612.088483 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 44828.628456 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 49169.289996 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 49129.488471 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 49599.653839 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 49449.103899 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 49727.872543 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 49226.823264 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 49788.618741 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 49796.610454 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 49483.808481 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 49169.289996 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 49129.488471 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 49599.653839 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 49449.103899 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 49727.872543 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 49226.823264 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 49788.618741 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 49796.610454 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 49483.808481 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -656,114 +656,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.num_reads 98965 # number of read accesses completed -system.cpu0.num_writes 53188 # number of write accesses completed +system.cpu0.num_reads 99935 # number of read accesses completed +system.cpu0.num_writes 53927 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 22322 # number of replacements -system.cpu0.l1c.tagsinuse 389.061969 # Cycle average of tags in use -system.cpu0.l1c.total_refs 13312 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 22723 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.585838 # Average number of references to valid blocks. +system.cpu0.l1c.replacements 22552 # number of replacements +system.cpu0.l1c.tagsinuse 390.299440 # Cycle average of tags in use +system.cpu0.l1c.total_refs 13259 # Total number of references to valid blocks. +system.cpu0.l1c.sampled_refs 22978 # Sample count of references to valid blocks. +system.cpu0.l1c.avg_refs 0.577030 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 389.061969 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.759887 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.759887 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 8733 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8733 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1107 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1107 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9840 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9840 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9840 # number of overall hits -system.cpu0.l1c.overall_hits::total 9840 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 35619 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 35619 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23007 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23007 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 58626 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 58626 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 58626 # number of overall misses -system.cpu0.l1c.overall_misses::total 58626 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 4549553769 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 4549553769 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 3145624806 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 3145624806 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 7695178575 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 7695178575 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 7695178575 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 7695178575 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44352 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44352 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24114 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24114 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 68466 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 68466 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 68466 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 68466 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.803098 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.803098 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954093 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.954093 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.856279 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.856279 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.856279 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.856279 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 127728.284595 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 127728.284595 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 136724.684053 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 136724.684053 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 131258.802835 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 131258.802835 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 131258.802835 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 131258.802835 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 714656307 # number of cycles access was blocked +system.cpu0.l1c.occ_blocks::cpu0 390.299440 # Average occupied blocks per requestor +system.cpu0.l1c.occ_percent::cpu0 0.762304 # Average percentage of cache occupancy +system.cpu0.l1c.occ_percent::total 0.762304 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8650 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8650 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1121 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1121 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9771 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9771 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9771 # number of overall hits +system.cpu0.l1c.overall_hits::total 9771 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36111 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36111 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23070 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23070 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 59181 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 59181 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 59181 # number of overall misses +system.cpu0.l1c.overall_misses::total 59181 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 4619304150 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 4619304150 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 3123415012 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 3123415012 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 7742719162 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 7742719162 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 7742719162 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 7742719162 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44761 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44761 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24191 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24191 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 68952 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 68952 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 68952 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 68952 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.806751 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.806751 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953660 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.953660 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.858293 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.858293 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.858293 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.858293 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 127919.585445 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 127919.585445 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 135388.600433 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 135388.600433 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 130831.164766 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 130831.164766 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 130831.164766 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 130831.164766 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1413270 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 63701 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 64534 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11218.918180 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.899619 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9780 # number of writebacks -system.cpu0.l1c.writebacks::total 9780 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35619 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 35619 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23007 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23007 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 58626 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 58626 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 58626 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 58626 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 4478007425 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 4478007425 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 3099554441 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 3099554441 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 7577561866 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 7577561866 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 7577561866 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 7577561866 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1380411824 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1380411824 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 995386324 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 995386324 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2375798148 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2375798148 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.803098 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.803098 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954093 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954093 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.856279 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.856279 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.856279 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.856279 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 125719.627867 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 125719.627867 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 134722.234146 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 134722.234146 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 129252.581892 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 129252.581892 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 129252.581892 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 129252.581892 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9856 # number of writebacks +system.cpu0.l1c.writebacks::total 9856 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36111 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36111 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23070 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23070 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 59181 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 59181 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 59181 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 59181 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 4547088150 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 4547088150 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 3077287012 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 3077287012 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 7624375162 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 7624375162 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 7624375162 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 7624375162 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1436864073 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1436864073 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 955697316 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 955697316 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2392561389 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2392561389 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.806751 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.806751 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953660 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953660 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858293 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.858293 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858293 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.858293 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 125919.751599 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 125919.751599 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 133389.120590 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 133389.120590 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 128831.468917 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 128831.468917 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 128831.468917 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 128831.468917 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -771,114 +771,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 97331 # number of read accesses completed -system.cpu1.num_writes 52743 # number of write accesses completed +system.cpu1.num_reads 97805 # number of read accesses completed +system.cpu1.num_writes 52541 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 21605 # number of replacements -system.cpu1.l1c.tagsinuse 388.260770 # Cycle average of tags in use -system.cpu1.l1c.total_refs 12987 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 21962 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.591340 # Average number of references to valid blocks. +system.cpu1.l1c.replacements 21861 # number of replacements +system.cpu1.l1c.tagsinuse 389.546383 # Cycle average of tags in use +system.cpu1.l1c.total_refs 12913 # Total number of references to valid blocks. +system.cpu1.l1c.sampled_refs 22254 # Sample count of references to valid blocks. +system.cpu1.l1c.avg_refs 0.580255 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 388.260770 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.758322 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.758322 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 8534 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8534 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1058 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1058 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9592 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9592 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9592 # number of overall hits -system.cpu1.l1c.overall_hits::total 9592 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 35254 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 35254 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 22627 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 22627 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 57881 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 57881 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 57881 # number of overall misses -system.cpu1.l1c.overall_misses::total 57881 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 4617875359 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 4617875359 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 3138675137 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 3138675137 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 7756550496 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 7756550496 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 7756550496 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 7756550496 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 43788 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 43788 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 23685 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 23685 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 67473 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 67473 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 67473 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 67473 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805106 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.805106 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955330 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.955330 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.857839 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.857839 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.857839 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.857839 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 130988.692319 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 130988.692319 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 138713.710921 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 138713.710921 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 134008.577875 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 134008.577875 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 134008.577875 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 134008.577875 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 723339270 # number of cycles access was blocked +system.cpu1.l1c.occ_blocks::cpu1 389.546383 # Average occupied blocks per requestor +system.cpu1.l1c.occ_percent::cpu1 0.760833 # Average percentage of cache occupancy +system.cpu1.l1c.occ_percent::total 0.760833 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8526 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8526 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1045 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1045 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9571 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9571 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9571 # number of overall hits +system.cpu1.l1c.overall_hits::total 9571 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 35398 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 35398 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 22650 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 22650 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 58048 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 58048 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 58048 # number of overall misses +system.cpu1.l1c.overall_misses::total 58048 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 4577570179 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 4577570179 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 3175338798 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 3175338798 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 7752908977 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 7752908977 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 7752908977 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 7752908977 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 43924 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 43924 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 23695 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 23695 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 67619 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 67619 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 67619 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 67619 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805892 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.805892 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955898 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.955898 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.858457 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.858457 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.858457 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.858457 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 129317.198119 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 129317.198119 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 140191.558411 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 140191.558411 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 133560.311759 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 133560.311759 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 133560.311759 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 133560.311759 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1404233 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 62977 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 62944 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11485.768932 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 22.309243 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9483 # number of writebacks -system.cpu1.l1c.writebacks::total 9483 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35254 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 35254 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22627 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 22627 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 57881 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 57881 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 57881 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 57881 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 4547061522 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 4547061522 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 3093362268 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 3093362268 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 7640423790 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 7640423790 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 7640423790 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 7640423790 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1364091847 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1364091847 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 932992416 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 932992416 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2297084263 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2297084263 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805106 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805106 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955330 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955330 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857839 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.857839 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857839 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.857839 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 128980.017076 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 128980.017076 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 136711.109206 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 136711.109206 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 132002.276913 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 132002.276913 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 132002.276913 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 132002.276913 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9603 # number of writebacks +system.cpu1.l1c.writebacks::total 9603 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35398 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 35398 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22650 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 22650 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 58048 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 58048 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 58048 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 58048 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 4506790179 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 4506790179 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 3130040798 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 3130040798 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 7636830977 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 7636830977 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 7636830977 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 7636830977 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1394209419 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1394209419 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 928511940 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 928511940 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2322721359 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2322721359 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805892 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805892 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955898 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955898 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858457 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.858457 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858457 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.858457 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 127317.650121 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 127317.650121 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 138191.646711 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 138191.646711 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 131560.621847 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 131560.621847 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 131560.621847 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 131560.621847 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -886,114 +886,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 98360 # number of read accesses completed -system.cpu2.num_writes 53068 # number of write accesses completed +system.cpu2.num_reads 100000 # number of read accesses completed +system.cpu2.num_writes 54114 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 22096 # number of replacements -system.cpu2.l1c.tagsinuse 389.724593 # Cycle average of tags in use -system.cpu2.l1c.total_refs 13250 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 22502 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.588837 # Average number of references to valid blocks. +system.cpu2.l1c.replacements 22990 # number of replacements +system.cpu2.l1c.tagsinuse 392.060782 # Cycle average of tags in use +system.cpu2.l1c.total_refs 13456 # Total number of references to valid blocks. +system.cpu2.l1c.sampled_refs 23401 # Sample count of references to valid blocks. +system.cpu2.l1c.avg_refs 0.575018 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 389.724593 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.761181 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.761181 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 8687 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8687 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1121 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1121 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9808 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9808 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9808 # number of overall hits -system.cpu2.l1c.overall_hits::total 9808 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 35624 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 35624 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 22874 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 22874 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 58498 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 58498 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 58498 # number of overall misses -system.cpu2.l1c.overall_misses::total 58498 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 4545456138 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 4545456138 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 3151736803 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 3151736803 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 7697192941 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 7697192941 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 7697192941 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 7697192941 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44311 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44311 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 23995 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 23995 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 68306 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 68306 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 68306 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 68306 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.803954 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.803954 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953282 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.953282 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.856411 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.856411 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.856411 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.856411 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 127595.332865 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 127595.332865 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 137786.867317 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 137786.867317 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 131580.446186 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 131580.446186 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 131580.446186 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 131580.446186 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 716129194 # number of cycles access was blocked +system.cpu2.l1c.occ_blocks::cpu2 392.060782 # Average occupied blocks per requestor +system.cpu2.l1c.occ_percent::cpu2 0.765744 # Average percentage of cache occupancy +system.cpu2.l1c.occ_percent::total 0.765744 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8750 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8750 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1243 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1243 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9993 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9993 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9993 # number of overall hits +system.cpu2.l1c.overall_hits::total 9993 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36203 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36203 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23173 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23173 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 59376 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 59376 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 59376 # number of overall misses +system.cpu2.l1c.overall_misses::total 59376 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 4641358719 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 4641358719 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 3127191782 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 3127191782 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 7768550501 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 7768550501 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 7768550501 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 7768550501 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44953 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44953 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24416 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24416 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 69369 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 69369 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 69369 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 69369 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805352 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805352 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.949091 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.949091 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.855944 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.855944 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.855944 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.855944 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 128203.704638 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 128203.704638 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 134949.802874 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 134949.802874 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 130836.541717 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 130836.541717 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 130836.541717 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 130836.541717 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1392289 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 63633 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 64514 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11254.053620 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.581192 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9686 # number of writebacks -system.cpu2.l1c.writebacks::total 9686 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35624 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 35624 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22874 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 22874 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 58498 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 58498 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 58498 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 58498 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 4473878832 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 4473878832 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 3105924454 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 3105924454 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 7579803286 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 7579803286 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 7579803286 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 7579803286 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1379555288 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1379555288 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 954692892 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 954692892 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2334248180 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2334248180 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.803954 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.803954 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953282 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953282 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.856411 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.856411 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.856411 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.856411 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 125586.088929 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 125586.088929 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 135784.054123 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 135784.054123 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 129573.716811 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 129573.716811 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 129573.716811 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 129573.716811 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9991 # number of writebacks +system.cpu2.l1c.writebacks::total 9991 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36203 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36203 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23173 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23173 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 59376 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 59376 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 59376 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 59376 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 4568956719 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 4568956719 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 3080855782 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 3080855782 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 7649812501 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 7649812501 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 7649812501 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 7649812501 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1362583834 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1362583834 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 971805765 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 971805765 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2334389599 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2334389599 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805352 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805352 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.949091 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.949091 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.855944 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.855944 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.855944 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.855944 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 126203.815126 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 126203.815126 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 132950.234411 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 132950.234411 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 128836.777503 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 128836.777503 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 128836.777503 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 128836.777503 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1001,114 +1001,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 100000 # number of read accesses completed -system.cpu3.num_writes 53600 # number of write accesses completed +system.cpu3.num_reads 98308 # number of read accesses completed +system.cpu3.num_writes 52892 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 22673 # number of replacements -system.cpu3.l1c.tagsinuse 391.747074 # Cycle average of tags in use -system.cpu3.l1c.total_refs 13403 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 23070 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.580971 # Average number of references to valid blocks. +system.cpu3.l1c.replacements 21879 # number of replacements +system.cpu3.l1c.tagsinuse 388.243829 # Cycle average of tags in use +system.cpu3.l1c.total_refs 13269 # Total number of references to valid blocks. +system.cpu3.l1c.sampled_refs 22290 # Sample count of references to valid blocks. +system.cpu3.l1c.avg_refs 0.595289 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 391.747074 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.765131 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.765131 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 8720 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8720 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1143 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1143 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9863 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9863 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9863 # number of overall hits -system.cpu3.l1c.overall_hits::total 9863 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36203 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36203 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 22978 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 22978 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 59181 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 59181 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 59181 # number of overall misses -system.cpu3.l1c.overall_misses::total 59181 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 4605371729 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 4605371729 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 3121949330 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 3121949330 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 7727321059 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 7727321059 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 7727321059 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 7727321059 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44923 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44923 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24121 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24121 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 69044 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 69044 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 69044 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 69044 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805890 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.805890 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.952614 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.952614 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.857149 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.857149 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.857149 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.857149 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 127209.671270 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 127209.671270 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 135866.887022 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 135866.887022 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 130570.978169 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 130570.978169 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 130570.978169 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 130570.978169 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 721076565 # number of cycles access was blocked +system.cpu3.l1c.occ_blocks::cpu3 388.243829 # Average occupied blocks per requestor +system.cpu3.l1c.occ_percent::cpu3 0.758289 # Average percentage of cache occupancy +system.cpu3.l1c.occ_percent::total 0.758289 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8771 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8771 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1066 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1066 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9837 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9837 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9837 # number of overall hits +system.cpu3.l1c.overall_hits::total 9837 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 35672 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 35672 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 22858 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 22858 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 58530 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 58530 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 58530 # number of overall misses +system.cpu3.l1c.overall_misses::total 58530 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 4705192371 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 4705192371 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 3092503889 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 3092503889 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 7797696260 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 7797696260 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 7797696260 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 7797696260 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44443 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44443 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 23924 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 23924 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 68367 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 68367 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 68367 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 68367 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.802646 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.802646 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955442 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.955442 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.856115 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.856115 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.856115 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.856115 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 131901.557832 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 131901.557832 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 135291.971695 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 135291.971695 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 133225.632325 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 133225.632325 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 133225.632325 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 133225.632325 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1411864 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 64491 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 63831 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11181.041773 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 22.118782 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9961 # number of writebacks -system.cpu3.l1c.writebacks::total 9961 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36203 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36203 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22978 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 22978 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 59181 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 59181 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 59181 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 59181 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 4532659362 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 4532659362 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 3075925984 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 3075925984 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 7608585346 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 7608585346 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 7608585346 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 7608585346 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1393944138 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1393944138 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 919834390 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 919834390 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2313778528 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2313778528 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805890 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805890 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.952614 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.952614 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.857149 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.857149 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.857149 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.857149 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 125201.208795 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 125201.208795 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 133863.956132 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 133863.956132 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 128564.663422 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 128564.663422 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 128564.663422 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 128564.663422 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9578 # number of writebacks +system.cpu3.l1c.writebacks::total 9578 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35672 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 35672 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22858 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 22858 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 58530 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 58530 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 58530 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 58530 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 4633860371 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 4633860371 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 3046797889 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 3046797889 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 7680658260 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 7680658260 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 7680658260 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 7680658260 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1383140389 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1383140389 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 919277948 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 919277948 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2302418337 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2302418337 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.802646 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.802646 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955442 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955442 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.856115 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.856115 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.856115 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.856115 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 129901.894231 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 129901.894231 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 133292.409178 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 133292.409178 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 131226.008201 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 131226.008201 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 131226.008201 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 131226.008201 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1116,114 +1116,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99186 # number of read accesses completed -system.cpu4.num_writes 53232 # number of write accesses completed +system.cpu4.num_reads 99646 # number of read accesses completed +system.cpu4.num_writes 53184 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 22556 # number of replacements -system.cpu4.l1c.tagsinuse 391.523203 # Cycle average of tags in use -system.cpu4.l1c.total_refs 13363 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 22976 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.581607 # Average number of references to valid blocks. +system.cpu4.l1c.replacements 22486 # number of replacements +system.cpu4.l1c.tagsinuse 389.564427 # Cycle average of tags in use +system.cpu4.l1c.total_refs 13323 # Total number of references to valid blocks. +system.cpu4.l1c.sampled_refs 22871 # Sample count of references to valid blocks. +system.cpu4.l1c.avg_refs 0.582528 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 391.523203 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.764694 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.764694 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 8704 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8704 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1177 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1177 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9881 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9881 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9881 # number of overall hits -system.cpu4.l1c.overall_hits::total 9881 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 35925 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 35925 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 22955 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 22955 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 58880 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 58880 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 58880 # number of overall misses -system.cpu4.l1c.overall_misses::total 58880 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 4605243494 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 4605243494 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 3106119837 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 3106119837 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 7711363331 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 7711363331 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 7711363331 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 7711363331 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44629 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44629 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24132 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24132 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 68761 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 68761 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 68761 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 68761 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804970 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.804970 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.951227 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.951227 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.856299 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.856299 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.856299 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.856299 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 128190.493918 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 128190.493918 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 135313.432237 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 135313.432237 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 130967.447877 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 130967.447877 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 130967.447877 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 130967.447877 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 718630789 # number of cycles access was blocked +system.cpu4.l1c.occ_blocks::cpu4 389.564427 # Average occupied blocks per requestor +system.cpu4.l1c.occ_percent::cpu4 0.760868 # Average percentage of cache occupancy +system.cpu4.l1c.occ_percent::total 0.760868 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8662 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8662 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1144 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1144 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9806 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9806 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9806 # number of overall hits +system.cpu4.l1c.overall_hits::total 9806 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36129 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36129 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 22914 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 22914 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 59043 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 59043 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 59043 # number of overall misses +system.cpu4.l1c.overall_misses::total 59043 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 4597368029 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 4597368029 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 3131496490 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 3131496490 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 7728864519 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 7728864519 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 7728864519 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 7728864519 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44791 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44791 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24058 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24058 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 68849 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 68849 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 68849 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 68849 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.806613 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.806613 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952448 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.952448 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.857572 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.857572 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.857572 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.857572 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 127248.692989 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 127248.692989 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 136663.022170 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 136663.022170 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 130902.300340 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 130902.300340 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 130902.300340 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 130902.300340 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1409065 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 64157 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 64552 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 11201.128310 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 21.828371 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9838 # number of writebacks -system.cpu4.l1c.writebacks::total 9838 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35925 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 35925 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22955 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 22955 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 58880 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 58880 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 58880 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 58880 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 4533093127 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 4533093127 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 3060147977 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 3060147977 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 7593241104 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 7593241104 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 7593241104 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 7593241104 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1402247556 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1402247556 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 894394941 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 894394941 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2296642497 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2296642497 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804970 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804970 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.951227 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.951227 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.856299 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.856299 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.856299 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.856299 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 126182.132971 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 126182.132971 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 133310.737399 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 133310.737399 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 128961.295924 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 128961.295924 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 128961.295924 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 128961.295924 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9768 # number of writebacks +system.cpu4.l1c.writebacks::total 9768 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36129 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36129 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22914 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 22914 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 59043 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 59043 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 59043 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 59043 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 4525124029 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 4525124029 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 3085672490 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 3085672490 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 7610796519 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 7610796519 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 7610796519 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 7610796519 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1426221714 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1426221714 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 886330386 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 886330386 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2312552100 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2312552100 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.806613 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.806613 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952448 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952448 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857572 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.857572 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857572 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.857572 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 125249.080489 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 125249.080489 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 134663.196736 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 134663.196736 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 128902.605203 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 128902.605203 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 128902.605203 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 128902.605203 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1231,114 +1231,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99811 # number of read accesses completed -system.cpu5.num_writes 54122 # number of write accesses completed +system.cpu5.num_reads 99510 # number of read accesses completed +system.cpu5.num_writes 53712 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 22776 # number of replacements -system.cpu5.l1c.tagsinuse 391.477551 # Cycle average of tags in use -system.cpu5.l1c.total_refs 13322 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 23147 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.575539 # Average number of references to valid blocks. +system.cpu5.l1c.replacements 22704 # number of replacements +system.cpu5.l1c.tagsinuse 391.715809 # Cycle average of tags in use +system.cpu5.l1c.total_refs 13238 # Total number of references to valid blocks. +system.cpu5.l1c.sampled_refs 23109 # Sample count of references to valid blocks. +system.cpu5.l1c.avg_refs 0.572850 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 391.477551 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.764605 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.764605 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 8701 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8701 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1178 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1178 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9879 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9879 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9879 # number of overall hits -system.cpu5.l1c.overall_hits::total 9879 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36192 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36192 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23103 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23103 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 59295 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 59295 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 59295 # number of overall misses -system.cpu5.l1c.overall_misses::total 59295 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 4578113743 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 4578113743 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 3131851801 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 3131851801 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 7709965544 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 7709965544 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 7709965544 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 7709965544 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44893 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44893 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24281 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24281 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 69174 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 69174 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 69174 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 69174 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806184 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.806184 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.951485 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.951485 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.857186 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.857186 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.857186 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.857186 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 126495.185207 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 126495.185207 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 135560.394797 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 135560.394797 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 130027.245872 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 130027.245872 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 130027.245872 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 130027.245872 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 718707273 # number of cycles access was blocked +system.cpu5.l1c.occ_blocks::cpu5 391.715809 # Average occupied blocks per requestor +system.cpu5.l1c.occ_percent::cpu5 0.765070 # Average percentage of cache occupancy +system.cpu5.l1c.occ_percent::total 0.765070 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8676 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8676 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1153 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1153 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9829 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9829 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9829 # number of overall hits +system.cpu5.l1c.overall_hits::total 9829 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36073 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36073 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23060 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23060 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 59133 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 59133 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 59133 # number of overall misses +system.cpu5.l1c.overall_misses::total 59133 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 4612203646 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 4612203646 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 3154708419 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 3154708419 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 7766912065 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 7766912065 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 7766912065 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 7766912065 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44749 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44749 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24213 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24213 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 68962 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 68962 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 68962 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 68962 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806119 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.806119 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952381 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.952381 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.857472 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.857472 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.857472 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.857472 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 127857.501344 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 127857.501344 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 136804.354683 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 136804.354683 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 131346.491215 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 131346.491215 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 131346.491215 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 131346.491215 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1402922 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 64475 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 64326 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 11147.068988 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.809564 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 10068 # number of writebacks -system.cpu5.l1c.writebacks::total 10068 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36192 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36192 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23103 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23103 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 59295 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 59295 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 59295 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 59295 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 4505401434 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 4505401434 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 3085574966 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 3085574966 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 7590976400 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 7590976400 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 7590976400 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 7590976400 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1396623229 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1396623229 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 970059681 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 970059681 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2366682910 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2366682910 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806184 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806184 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.951485 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.951485 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.857186 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.857186 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.857186 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.857186 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 124486.113893 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 124486.113893 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 133557.328745 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 133557.328745 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 128020.514377 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 128020.514377 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 128020.514377 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 128020.514377 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9873 # number of writebacks +system.cpu5.l1c.writebacks::total 9873 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36073 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36073 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23060 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23060 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 59133 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 59133 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 59133 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 59133 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 4540061646 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 4540061646 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 3108604419 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 3108604419 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 7648666065 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 7648666065 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 7648666065 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 7648666065 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1397826307 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1397826307 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 952355893 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 952355893 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2350182200 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2350182200 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806119 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806119 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952381 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952381 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.857472 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.857472 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.857472 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.857472 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 125857.612231 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 125857.612231 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 134805.048526 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 134805.048526 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 129346.829435 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 129346.829435 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 129346.829435 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 129346.829435 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1346,114 +1346,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 96701 # number of read accesses completed -system.cpu6.num_writes 52167 # number of write accesses completed +system.cpu6.num_reads 99341 # number of read accesses completed +system.cpu6.num_writes 53460 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 21524 # number of replacements -system.cpu6.l1c.tagsinuse 387.796217 # Cycle average of tags in use -system.cpu6.l1c.total_refs 12859 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 21936 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.586205 # Average number of references to valid blocks. +system.cpu6.l1c.replacements 22728 # number of replacements +system.cpu6.l1c.tagsinuse 391.033952 # Cycle average of tags in use +system.cpu6.l1c.total_refs 13418 # Total number of references to valid blocks. +system.cpu6.l1c.sampled_refs 23126 # Sample count of references to valid blocks. +system.cpu6.l1c.avg_refs 0.580213 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 387.796217 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.757414 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.757414 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 8329 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8329 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1106 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1106 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9435 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9435 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9435 # number of overall hits -system.cpu6.l1c.overall_hits::total 9435 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 35191 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 35191 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 22544 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 22544 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 57735 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 57735 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 57735 # number of overall misses -system.cpu6.l1c.overall_misses::total 57735 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 4508353371 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 4508353371 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 3154254558 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 3154254558 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 7662607929 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 7662607929 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 7662607929 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 7662607929 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 43520 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 43520 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 23650 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 23650 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 67170 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 67170 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 67170 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 67170 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808617 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.808617 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953235 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.953235 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859536 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859536 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859536 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859536 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 128110.976414 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 128110.976414 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 139915.478974 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 139915.478974 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 132720.324396 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 132720.324396 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 132720.324396 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 132720.324396 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 719066693 # number of cycles access was blocked +system.cpu6.l1c.occ_blocks::cpu6 391.033952 # Average occupied blocks per requestor +system.cpu6.l1c.occ_percent::cpu6 0.763738 # Average percentage of cache occupancy +system.cpu6.l1c.occ_percent::total 0.763738 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8762 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8762 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1095 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1095 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9857 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9857 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9857 # number of overall hits +system.cpu6.l1c.overall_hits::total 9857 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 35979 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 35979 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23081 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23081 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 59060 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 59060 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 59060 # number of overall misses +system.cpu6.l1c.overall_misses::total 59060 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 4670056241 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 4670056241 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 3140122564 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 3140122564 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 7810178805 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 7810178805 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 7810178805 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 7810178805 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44741 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44741 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24176 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24176 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 68917 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 68917 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 68917 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 68917 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.804162 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.804162 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954707 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954707 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.856973 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.856973 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.856973 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.856973 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 129799.500848 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 129799.500848 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 136047.942637 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 136047.942637 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 132241.429140 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 132241.429140 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 132241.429140 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 132241.429140 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1402385 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 62816 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 64109 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 11447.190095 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.875010 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9499 # number of writebacks -system.cpu6.l1c.writebacks::total 9499 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35191 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 35191 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 22544 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 22544 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 57735 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 57735 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 57735 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 57735 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 4437636067 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 4437636067 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 3109111203 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 3109111203 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 7546747270 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 7546747270 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 7546747270 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 7546747270 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 1416513847 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 1416513847 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 907986926 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 907986926 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2324500773 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2324500773 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808617 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808617 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953235 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953235 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859536 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859536 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859536 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859536 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 126101.448296 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 126101.448296 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 137913.023554 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 137913.023554 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 130713.557980 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 130713.557980 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 130713.557980 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 130713.557980 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9866 # number of writebacks +system.cpu6.l1c.writebacks::total 9866 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35979 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 35979 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23081 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23081 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 59060 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 59060 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 59060 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 59060 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 4598108241 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 4598108241 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 3093974564 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 3093974564 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 7692082805 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 7692082805 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 7692082805 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 7692082805 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 1335573448 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 1335573448 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 977750934 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 977750934 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2313324382 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2313324382 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.804162 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.804162 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954707 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954707 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.856973 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.856973 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.856973 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.856973 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 127799.778788 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 127799.778788 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 134048.549196 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 134048.549196 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 130241.835506 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 130241.835506 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 130241.835506 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 130241.835506 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1461,114 +1461,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 98233 # number of read accesses completed -system.cpu7.num_writes 53134 # number of write accesses completed +system.cpu7.num_reads 99191 # number of read accesses completed +system.cpu7.num_writes 53936 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 22239 # number of replacements -system.cpu7.l1c.tagsinuse 390.077286 # Cycle average of tags in use -system.cpu7.l1c.total_refs 13228 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 22658 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.583811 # Average number of references to valid blocks. +system.cpu7.l1c.replacements 22510 # number of replacements +system.cpu7.l1c.tagsinuse 390.052988 # Cycle average of tags in use +system.cpu7.l1c.total_refs 13451 # Total number of references to valid blocks. +system.cpu7.l1c.sampled_refs 22924 # Sample count of references to valid blocks. +system.cpu7.l1c.avg_refs 0.586765 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 390.077286 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.761870 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.761870 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 8637 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8637 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1096 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1096 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9733 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9733 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9733 # number of overall hits -system.cpu7.l1c.overall_hits::total 9733 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 35699 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 35699 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 22823 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 22823 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 58522 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 58522 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 58522 # number of overall misses -system.cpu7.l1c.overall_misses::total 58522 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 4580220165 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 4580220165 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 3149286383 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 3149286383 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 7729506548 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 7729506548 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 7729506548 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 7729506548 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44336 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44336 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 23919 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 23919 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 68255 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 68255 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 68255 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 68255 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805192 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.805192 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954179 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954179 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.857402 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.857402 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.857402 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.857402 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 128301.077481 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 128301.077481 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 137987.397932 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 137987.397932 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 132078.646458 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 132078.646458 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 132078.646458 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 132078.646458 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 716139762 # number of cycles access was blocked +system.cpu7.l1c.occ_blocks::cpu7 390.052988 # Average occupied blocks per requestor +system.cpu7.l1c.occ_percent::cpu7 0.761822 # Average percentage of cache occupancy +system.cpu7.l1c.occ_percent::total 0.761822 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8796 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8796 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1169 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1169 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9965 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9965 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9965 # number of overall hits +system.cpu7.l1c.overall_hits::total 9965 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 35920 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 35920 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23167 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23167 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 59087 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 59087 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 59087 # number of overall misses +system.cpu7.l1c.overall_misses::total 59087 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 4583534857 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 4583534857 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 3157115869 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 3157115869 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 7740650726 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 7740650726 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 7740650726 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 7740650726 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44716 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44716 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24336 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24336 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 69052 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 69052 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 69052 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 69052 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.803292 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.803292 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.951964 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.951964 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.855688 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.855688 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.855688 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.855688 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 127603.977088 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 127603.977088 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 136276.422023 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 136276.422023 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 131004.294109 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 131004.294109 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 131004.294109 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 131004.294109 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1403287 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 63505 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 64246 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 11276.903582 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.842403 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9791 # number of writebacks -system.cpu7.l1c.writebacks::total 9791 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35699 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 35699 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22823 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 22823 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 58522 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 58522 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 58522 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 58522 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 4508506825 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 4508506825 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 3103586023 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 3103586023 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 7612092848 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 7612092848 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 7612092848 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 7612092848 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 1364395277 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 1364395277 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 924938405 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 924938405 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2289333682 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2289333682 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805192 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805192 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954179 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954179 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857402 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.857402 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857402 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.857402 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 126292.244181 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 126292.244181 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 135985.016124 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 135985.016124 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 130072.329175 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 130072.329175 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 130072.329175 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 130072.329175 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9883 # number of writebacks +system.cpu7.l1c.writebacks::total 9883 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35920 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 35920 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23167 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23167 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 59087 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 59087 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 59087 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 59087 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 4511708857 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 4511708857 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 3110789869 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 3110789869 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 7622498726 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 7622498726 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 7622498726 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 7622498726 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 1423430289 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 1423430289 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 942416285 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 942416285 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2365846574 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2365846574 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.803292 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.803292 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.951964 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.951964 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.855688 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.855688 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.855688 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.855688 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 125604.366843 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 125604.366843 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 134276.767341 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 134276.767341 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 129004.666441 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 129004.666441 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 129004.666441 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 129004.666441 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency |